WO2024135066A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2024135066A1
WO2024135066A1 PCT/JP2023/037365 JP2023037365W WO2024135066A1 WO 2024135066 A1 WO2024135066 A1 WO 2024135066A1 JP 2023037365 W JP2023037365 W JP 2023037365W WO 2024135066 A1 WO2024135066 A1 WO 2024135066A1
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WO
WIPO (PCT)
Prior art keywords
internal electrode
exposed
dielectric layer
auxiliary
multilayer ceramic
Prior art date
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Ceased
Application number
PCT/JP2023/037365
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English (en)
French (fr)
Japanese (ja)
Inventor
和博 西林
悠子 河崎
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Filing date
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Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2024565622A priority Critical patent/JPWO2024135066A1/ja
Priority to KR1020257008939A priority patent/KR20250051085A/ko
Priority to CN202380068011.0A priority patent/CN119895517A/zh
Publication of WO2024135066A1 publication Critical patent/WO2024135066A1/ja
Priority to US18/905,344 priority patent/US20250029783A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/35—Feed-through capacitors or anti-noise capacitors

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • multi-terminal multilayer ceramic capacitor that includes a laminate in which dielectric layers with internal electrodes exposed on the end faces of the laminate and dielectric layers with internal electrodes exposed on the side faces of the laminate are alternately stacked in multiple layers, end face external electrodes arranged on the end faces, and side face external electrodes arranged on the side faces (see Patent Document 1).
  • the direction in which the internal electrodes extend differs for each layer. This causes the layers to shrink in different directions during sintering, resulting in a large difference in internal stress between layers, particularly in the draw-out areas where the internal electrode draw-out portions are located. This increases the likelihood of peeling between layers.
  • the objective of the present invention is to provide a multilayer ceramic capacitor that can reduce internal stress differences and prevent peeling between layers.
  • the multilayer ceramic capacitor of the present invention comprises a laminate in which a plurality of dielectric layers on which internal electrodes are arranged are laminated, the laminate having two main surfaces provided on both sides of the lamination direction, two side surfaces provided on both sides of a width direction intersecting the lamination direction, and two end surfaces provided on both sides of a length direction intersecting the lamination direction and the width direction, and an end face external electrode provided on the end face and a side face external electrode provided on the side face in the laminate, the internal electrodes comprising an end face exposed internal electrode exposed on the end face and a side face exposed internal electrode exposed on the side face, the end face exposed internal electrode and the side face exposed internal electrode each having an opposing portion facing each other and an extraction portion drawn out from the opposing portion, the dielectric layer has an end face exposed internal electrode and a side face exposed internal electrode, the end face exposed internal electrode and the side face exposed internal electrode each having an opposing portion facing each other and an extraction portion drawn out from the opposing portion,
  • a multilayer ceramic capacitor comprising
  • the present invention provides a multilayer ceramic capacitor that can reduce internal stress differences and prevent peeling between layers.
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the II-II direction in FIG. 1.
  • 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the line III-III in FIG. 1.
  • 2 is a cross-sectional view of the first embodiment taken along an end surface exposed internal electrode 15A of the multilayer ceramic capacitor 1.
  • FIG. 2 is a cross-sectional view of the first embodiment taken along a side surface exposed internal electrode 15B of the multilayer ceramic capacitor 1.
  • FIG. 2A to 2C are diagrams illustrating a manufacturing process of a laminate 2 in a manufacturing method of a multilayer ceramic capacitor 1.
  • 2 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1.
  • 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to a second embodiment taken along the line II-II in FIG. 1.
  • 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to a second embodiment taken along the line III-III in FIG. 1.
  • FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1.
  • Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the II-II direction in Fig. 1.
  • Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the III-III direction in Fig. 1.
  • the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a three-terminal structure, including end surface external electrodes 3 provided on both end surfaces C in the length direction L of the laminate 2, and side surface external electrodes 4 provided on both side surfaces B in the width direction W of the laminate 2.
  • the laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are laminated, and an outer layer portion 12.
  • a pair of outer surfaces on both sides of the stacking direction T are referred to as main surfaces A
  • a pair of outer surfaces extending in the stacking direction T and on both sides of the width direction W are referred to as side surfaces B
  • a pair of outer surfaces extending in the stacking direction T and on both sides of the length direction L are referred to as end surfaces C.
  • the laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. It is preferable that the corners and ridges of the laminate 2 are rounded. The corners are portions where three surfaces of the laminate intersect, and the ridges are portions where two surfaces of the laminate intersect.
  • the inner layer portion 11 includes a plurality of dielectric layers 14 and internal electrodes 15 laminated in a lamination direction T.
  • the dielectric layer 14 is made of a ceramic material.
  • a dielectric ceramic containing BaTiO3 as a main component is used as the ceramic material.
  • the ceramic material may be one containing at least one of the subcomponents such as a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound in addition to the main component.
  • the internal electrodes 15 are preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.
  • the internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrodes 15.
  • FIG. 4 is a cross-sectional view along the end-face exposed internal electrode 15A of the multilayer ceramic capacitor 1.
  • FIG. 5 is a cross-sectional view along the side-face exposed internal electrode 15B of the multilayer ceramic capacitor 1.
  • End surface exposed internal electrode 15A 4 the end surface exposed internal electrode 15A extends between both end faces C in the length direction L of the laminate 2 and is spaced a certain distance from both side faces B in the width direction W.
  • the end surface exposed internal electrode 15A has an end surface facing portion 15Aa located in the center between both end faces C and an end surface drawn portion 15Ab extending from the end surface facing portion 15Aa to both end faces C.
  • the end surface drawn portions 15Ab extend to both end faces C, respectively, are exposed at the end faces C of the laminate 2, and are connected to the end surface external electrodes 3 provided on both side faces in the width direction W of the laminate 2.
  • the side surface exposed internal electrode 15B is slightly smaller than the laminate 2 and is spaced a certain distance from both end faces C in the length direction L.
  • the side surface exposed internal electrode 15B has a side surface facing portion 15Ba located in the center between both side faces B, and a side surface drawn portion 15Bb extending from the side surface facing portion 15Ba to both side faces B.
  • the side surface drawn portion 15Bb extends to both side faces B, is exposed at the side face B of the laminate 2, and is connected to the side surface external electrodes 4 provided on both side faces in the width direction W of the laminate 2.
  • the end face facing portion 15Aa and the side face facing portion 15Ba face each other and form a capacitor portion.
  • the facing portion 15a Unless it is necessary to distinguish between the end face facing portion 15Aa and the side face facing portion 15Ba, they will be collectively referred to as the facing portion 15a.
  • the drawn-out portion 15b Unless it is necessary to distinguish between the end face drawn-out portion 15Ab and the side face drawn-out portion 15Bb, they will be collectively referred to as the drawn-out portion 15b.
  • the region in the laminate 2 where the facing portion 15a is arranged will be referred to as the facing region, and the region where the end face drawn-out portion 15Ab or the side face drawn-out portion 15Bb is arranged will be referred to as the drawn-out region.
  • the dielectric layer 14 is formed by alternately stacking multiple layers of a first dielectric layer 14A having an end-surface-exposed internal electrode 15A exposed on end face C, and a second dielectric layer 14B having a side-surface-exposed internal electrode 15B exposed on part of side face B.
  • the outer layer portion 12 is a dielectric layer of a constant thickness disposed on the main surface A side of the inner layer portion 11.
  • the outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.
  • End surface external electrode 3 End surface external electrodes 3 are disposed on both end surfaces C of the laminate 2. End surface drawn portions 15Ab of end surface exposed internal electrodes 15A are connected to the end surface external electrodes 3. The end surface external electrodes 3 cover not only the end surfaces C but also parts of the main surfaces A and side surfaces B on the end surface C side.
  • Side surface external electrodes 4 are disposed on both side surfaces B of the laminate 2. Side surface drawn portions 15Bb of side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 cover not only the side surface B but also a portion of the main surface A on the side surface B side.
  • the end face external electrode 3 and the side face external electrode 4 include an underlying electrode layer 31 and a plating layer 32 disposed on the underlying electrode layer 31.
  • the plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the underlying electrode layer 31 and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321.
  • a side surface-exposed auxiliary internal electrode 16A is arranged as an auxiliary internal electrode 16 on the side surface B of the first dielectric layer 14A on which the end surface-exposed internal electrode 15A is arranged, where the end surface-exposed internal electrode 15A is not exposed.
  • the side surface-exposed auxiliary internal electrode 16A is arranged at approximately the center in the length direction L, separated from the end surface-exposed internal electrode 15A by a predetermined dimension in the length direction L.
  • the side surface-exposed auxiliary internal electrode 16A is exposed to the side surface B, and faces a side surface drawn portion 15Bb of the side surface-exposed internal electrode 15B, which is another internal electrode 15 adjacent in the stacking direction T to the end surface-exposed internal electrode 15A.
  • the dimension in the width direction W of the auxiliary internal electrode 16 is represented as d
  • the dimension in the width direction W from one surface to an edge of one surface of the internal electrode 15 is represented as D.
  • the side surface exposed auxiliary internal electrode 16A is provided with a plurality of through holes 16h penetrating in the stacking direction T.
  • a dielectric material that is the same as the material of the dielectric layer 14 is disposed in the through holes 16h.
  • the through holes 16h are provided in the central region 16b.
  • the through holes 16h are provided at least in the central region 16b, and they may be provided in the side-surface region 16a.
  • the number of through holes 16h provided in the central region 16b is greater than the number of through holes 16h provided in the side-surface region 16a.
  • the plurality of through holes 16h have a dimension r in the width direction W satisfying d 1 /200 ⁇ r ⁇ d 1 /5, and the central region 16b includes one or more, preferably two or more, through holes 16h.
  • Fig. 6 is a diagram for explaining the steps for manufacturing the laminate 2 in the method for manufacturing the multilayer ceramic capacitor 1.
  • Fig. 7 is a flow chart for explaining the method for manufacturing the multilayer ceramic capacitor 1.
  • An end face exposed internal electrode 15A and a side face exposed auxiliary internal electrode 16A are formed with a conductive paste on a ceramic green sheet that is to become the first dielectric layer 14A.
  • a side face exposed internal electrode 15B is formed with a conductive paste on a ceramic green sheet that is to become the second dielectric layer 14B.
  • Ceramic green sheets are strip-shaped sheets made by forming a ceramic slurry containing ceramic powder, binder, and solvent onto a carrier film using a die coater, gravure coater, microgravure coater, etc.
  • the end-face-exposed internal electrode 15A, the side-face-exposed internal electrode 15B, and the side-face-exposed auxiliary internal electrode 16A are formed by printing, such as screen printing, gravure printing, or letterpress printing.
  • the side surface exposed auxiliary internal electrode 16A having the through hole 16h formed therein may be formed simultaneously with the end surface exposed internal electrode 15A by using a printed pattern of the side surface exposed auxiliary internal electrode 16A having the through hole 16h formed therein in advance.
  • the end-exposed internal electrode 15A may be printed on the ceramic green sheet with ink of a predetermined viscosity, and then the side-exposed auxiliary internal electrode 16A may be printed with ink of a lower viscosity than the predetermined viscosity, so that a through hole 16h is formed in the side-exposed auxiliary internal electrode 16A during sintering.
  • the side-exposed auxiliary internal electrode 16A may be printed separately with ink having a lower metal content than the predetermined metal content, so that a through hole 16h is formed in the side-exposed auxiliary internal electrode 16A during sintering. Furthermore, after printing the end-face-exposed internal electrode 15A on the ceramic green sheet with ink having a metal with a predetermined particle size, the side-face-exposed auxiliary internal electrode 16A may be separately printed with ink having a metal with a particle size different from the predetermined particle size, so that a through hole 16h is formed in the side-face-exposed auxiliary internal electrode 16A during sintering.
  • end surface external electrodes 3 are formed on both end surfaces C of the laminate 2, and side surface external electrodes 4 are formed on both side surfaces B of the laminate 2.
  • An end surface lead portion 15Ab of an end surface exposed internal electrode 15A is connected to the end surface external electrode 3.
  • the end surface external electrode 3 is formed so as to cover not only the end surface C, but also parts of the end surface C side of the main surface A and the side surface B.
  • a side surface lead portion 15Bb of a side surface exposed internal electrode 15B is connected to the side surface external electrode 4.
  • the side surface external electrode 4 is formed so as to cover not only the side surface B, but also parts of the side surface B side of the main surface A.
  • step S5 The laminate is then heated in a nitrogen atmosphere for a predetermined time at a set firing temperature, thereby baking the end surface external electrodes 3 and the side surface external electrodes 4 onto the laminate 2, thereby producing the multilayer ceramic capacitor 1 shown in FIG.
  • auxiliary internal electrode 16 In general, in a multi-terminal multilayer ceramic capacitor such as a multilayer ceramic capacitor with a three-terminal structure, the direction in which the internal electrodes extend is different for each layer. If the auxiliary internal electrodes 16 as in the embodiment are not provided, in the lead-out region, one of the adjacent layers has a lead-out portion as an internal electrode, but the other has no internal electrode. Therefore, during sintering, the amount of shrinkage of each layer differs in the lead-out region, and the difference in internal stress between the layers becomes large. This increases the possibility of peeling between the layers.
  • a side-exposed auxiliary internal electrode 16A is arranged as an auxiliary internal electrode 16 on the side of the first dielectric layer 14A on which the end-exposed internal electrode 15A is arranged, the side of the side B on which the end-exposed internal electrode 15A is not exposed.
  • the draw-out portion 15b is arranged on one of the adjacent layers, and the auxiliary internal electrode 16 is arranged on the other layer.
  • internal electrodes are arranged on both of the adjacent dielectric layers 14 in the draw-out region. This reduces the difference in the amount of shrinkage of each layer during sintering, reduces the internal stress difference, and reduces the possibility of peeling between layers.
  • the dimension d of the auxiliary internal electrode 16 in the width direction W satisfies D/5 ⁇ d ⁇ D ⁇ 4/5, where D is the dimension in the width direction W from the side face B to the edge of the end surface exposed internal electrode 15A on the side face B side. This ensures a sufficient dimension d of the auxiliary internal electrode 16 in the width direction W, making it possible to more effectively suppress peeling between layers due to internal stress differences.
  • the auxiliary internal electrode 16 is provided with a plurality of through holes 16h penetrating in the stacking direction T.
  • a dielectric material that is the same as the material of the dielectric layer 14 is disposed in the through holes 16h. This dielectric connects the second dielectric layer 14B on the first principal surface A side in contact with the auxiliary internal electrode 16 to the first dielectric layer 14A on the second principal surface A side.
  • the dielectric in the through hole 16h serves as an anchor, making it possible to more effectively suppress peeling between layers due to an internal stress difference.
  • the plurality of through holes 16h have a dimension r in the width direction W satisfying d 1 /200 ⁇ r ⁇ d 1 /5, and the central region 16b includes one or more, preferably two or more, through holes 16h.
  • d1 /200 is the minimum size that can be provided as the through hole 16h in the grain region.
  • two or more through holes 16h can be arranged side by side in the width direction W in the central region 16b of the auxiliary internal electrode 16, where the width dimension is d1 /2, and peeling between layers due to internal stress differences can be more effectively suppressed.
  • a multilayer ceramic capacitor 100 according to a second embodiment of the present invention will be described.
  • Fig. 1 is common to the first embodiment.
  • parts common to the multilayer ceramic capacitor 1 according to the first embodiment are denoted by common reference numerals, and common descriptions will be omitted.
  • FIG. 8 is a cross-sectional view of the multilayer ceramic capacitor 100 according to the second embodiment cut in the II-II direction in FIG. 1.
  • FIG. 9 is a cross-sectional view of the multilayer ceramic capacitor 100 according to the second embodiment cut in the III-III direction in FIG. 1.
  • the side surface-exposed auxiliary internal electrode 16A is arranged as the auxiliary internal electrode 16 on the side surface B of the first dielectric layer 14A on which the end surface-exposed internal electrode 15A is arranged, where the end surface-exposed internal electrode 15A is not exposed.
  • the side surface-exposed auxiliary internal electrode 16A is not arranged.
  • an end face exposed auxiliary internal electrode 16B as an auxiliary internal electrode 16 is arranged on the side of the end face C on which the side face exposed internal electrode 15B is arranged, where the side face exposed internal electrode 15B is not exposed, of the second dielectric layer 14B.
  • the end-face exposed auxiliary internal electrode 16B is disposed at approximately the center in the width direction W, spaced apart from the side-face exposed internal electrode 15B by a predetermined dimension in the width direction W.
  • the end-face exposed auxiliary internal electrode 16B is exposed at the end face C, and faces the end-face drawn portion 15Ab of the end-face exposed internal electrode 15A, which is the other internal electrode 15 adjacent in the stacking direction T to the side-face exposed internal electrode 15B.
  • the draw-out portion 15b is arranged on one of the adjacent layers, and the end-surface-exposed auxiliary internal electrode 16B is arranged on the other layer.
  • internal electrodes are arranged on both of the adjacent dielectric layers 14 in the draw-out region. This reduces the difference in the amount of shrinkage of each layer during sintering, reduces the internal stress difference, and reduces the possibility of peeling between layers.
  • the dimension d2 in the length direction L of the end face exposed auxiliary internal electrode 16B satisfies D2/5 ⁇ d2 ⁇ D2 ⁇ 4 /5, where D2 is the dimension in the length direction L from the end face C to the edge of the side face exposed internal electrode 15B on the end face C side. This ensures a sufficient dimension d2 in the length direction L of the end surface exposed auxiliary internal electrode 16B, making it possible to more effectively suppress peeling between layers due to an internal stress difference.
  • the end surface exposed auxiliary internal electrode 16B is provided with a plurality of through holes 16h penetrating in the lamination direction T.
  • a dielectric material that is the same as the material of the dielectric layer 14 is disposed in the through holes 16h. This dielectric connects the second dielectric layer 14B on the first principal surface A side in contact with the auxiliary internal electrode 16 to the first dielectric layer 14A on the second principal surface A side.
  • the dielectric in the through hole 16h serves as an anchor, making it possible to more effectively suppress peeling between layers due to an internal stress difference.
  • the through holes 16h are provided in the central region 16b.
  • the through holes 16h are provided in at least the central region 16b, and they may be provided in the side region 16a.
  • the number of the through holes 16h provided in the central region 16b is greater than the number of the through holes 16h provided in the side region 16a. Therefore, an anchor effect is exerted in the central region 16b, so that peeling between layers due to an internal stress difference can be more effectively suppressed.
  • the plurality of through holes 16h have a dimension r in the length direction L satisfying d 2 /200 ⁇ r ⁇ d 2 /5, and the central region 16b includes one or more, preferably two or more, through holes 16h.
  • the size d2 /200 is the minimum size that can be provided as the through hole 16h in the grain region. Since r ⁇ d2 /5, two or more through holes 16h can be arranged side by side in the length direction L in the central region 16b of the auxiliary internal electrode 16, whose width dimension is d2 /2.
  • a side surface-exposed auxiliary internal electrode 16A as an auxiliary internal electrode 16 is arranged on the side of the first dielectric layer 14A on which the end surface-exposed internal electrode 15A is arranged, the side surface B on which the end surface-exposed internal electrode 15A is not exposed.
  • an end face exposed auxiliary internal electrode 16B as an auxiliary internal electrode 16 is arranged on the second dielectric layer 14B, on the side of the end face C where the side face exposed internal electrode 15B is not exposed, on which the side face exposed internal electrode 15B is arranged. Therefore, the third embodiment has the effects of both the first and second embodiments.
  • the laminate includes an end face external electrode disposed on the end face and a side face external electrode disposed on the side face
  • the internal electrodes include end surface exposed internal electrodes exposed at the end surfaces and side surface exposed internal electrodes exposed at the side surfaces, the end surface exposed internal electrodes and the side surface exposed internal electrodes each having an opposing portion opposing to each other and an extraction portion extracted from the opposing portion
  • the dielectric layer includes a first dielectric layer on which the end surface exposed internal electrodes are arranged, and a second dielectric layer on which the side surface exposed internal electrodes are arranged and which is laminated alternately with the first dielectric layer, In at least one of the first dielectric layer and the second di
  • ⁇ 2> The multilayer ceramic capacitor described in ⁇ 1>, in which the auxiliary internal electrode is disposed on the first dielectric layer.
  • ⁇ 3> The multilayer ceramic capacitor described in ⁇ 1> or ⁇ 2>, in which the auxiliary internal electrode is disposed on the second dielectric layer.
  • ⁇ 4> The multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 3>, in which the auxiliary internal electrode is divided in the center from the one surface on which the auxiliary internal electrode is exposed toward the internal electrode into a side region on the side of the side and a central region on the side of the internal electrode, and the through hole is disposed in the central region.
  • ⁇ 5> A multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 4>, in which D is the dimension from the one surface on which the auxiliary internal electrode is exposed to the edge of the one surface of the internal electrode in the direction parallel to the width direction or the length direction, and d is the dimension of the auxiliary internal electrode from the one surface toward the internal electrode in the direction parallel to the width direction or the length direction, such that D/5 ⁇ d ⁇ D ⁇ 4/5.
  • ⁇ 6> The multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 5>, wherein the auxiliary internal electrode has a through hole whose maximum dimension r in the direction parallel to the width direction or the length direction from the surface on which the auxiliary internal electrode is exposed toward the internal electrode satisfies d/200 ⁇ r ⁇ d/5.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
PCT/JP2023/037365 2022-12-19 2023-10-16 積層セラミックコンデンサ Ceased WO2024135066A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2024565622A JPWO2024135066A1 (https=) 2022-12-19 2023-10-16
KR1020257008939A KR20250051085A (ko) 2022-12-19 2023-10-16 적층 세라믹 콘덴서
CN202380068011.0A CN119895517A (zh) 2022-12-19 2023-10-16 层叠陶瓷电容器
US18/905,344 US20250029783A1 (en) 2022-12-19 2024-10-03 Multilayer ceramic capacitor

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JP2022202429 2022-12-19
JP2022-202429 2022-12-19

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US18/905,344 Continuation US20250029783A1 (en) 2022-12-19 2024-10-03 Multilayer ceramic capacitor

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CN (1) CN119895517A (https=)
WO (1) WO2024135066A1 (https=)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09190947A (ja) * 1996-01-11 1997-07-22 Murata Mfg Co Ltd 積層セラミック電子部品
JPH09260198A (ja) * 1996-03-25 1997-10-03 Taiyo Yuden Co Ltd 積層コンデンサ
JP2003022932A (ja) * 2001-07-10 2003-01-24 Murata Mfg Co Ltd 貫通型三端子電子部品
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