WO2024134719A1 - パワーオンリセット回路 - Google Patents

パワーオンリセット回路 Download PDF

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Publication number
WO2024134719A1
WO2024134719A1 PCT/JP2022/046664 JP2022046664W WO2024134719A1 WO 2024134719 A1 WO2024134719 A1 WO 2024134719A1 JP 2022046664 W JP2022046664 W JP 2022046664W WO 2024134719 A1 WO2024134719 A1 WO 2024134719A1
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Prior art keywords
voltage
node
power supply
circuit
rate detection
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French (fr)
Japanese (ja)
Inventor
友和 小島
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2024565403A priority Critical patent/JP7764635B2/ja
Priority to PCT/JP2022/046664 priority patent/WO2024134719A1/ja
Publication of WO2024134719A1 publication Critical patent/WO2024134719A1/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Definitions

  • This disclosure relates to a power-on reset circuit.
  • Patent Document 1 Japanese Patent Laid-Open Publication No. 2019-186943
  • Patent Document 1 describes a power-on reset circuit with low current consumption.
  • a voltage detector 115 detects that the power supply voltage has risen above a threshold voltage level (VPOR_R) when the power supply voltage is started, and the output signal of the voltage detector 115 is held by a POR latch 120 to generate a POR signal. Then, after the power supply voltage has risen, the voltage detector 115 is turned off to suppress power consumption.
  • VPOR_R threshold voltage level
  • Patent Document 1 describes that, as shown in Figures 2A and 2B, adjustable resistors (R1, R2) are arranged in a voltage divider circuit for the power supply voltage (V_BUS), and that the threshold voltage level (VPOR_R) of the power-on reset circuit is determined by changing the resistance value of the adjustable resistor.
  • V_BUS power supply voltage
  • VOR_R threshold voltage level
  • the present disclosure has been made to solve these problems, and the purpose of the present disclosure is to provide a power-on reset circuit that reduces power consumption and can operate properly even if the rate of voltage change at power-on of the power supply voltage changes.
  • the power-on reset circuit includes a power supply wiring that receives a supply voltage, a reference voltage wiring that transmits a reference voltage, a voltage divider circuit, a voltage rate detection circuit, and a voltage evaluation circuit.
  • the voltage divider circuit is connected between the power supply wiring and the reference voltage, and outputs a divided voltage of the power supply voltage on the power supply wiring to a first node.
  • the voltage rate detection circuit detects the voltage change rate of the power supply voltage when the power supply voltage is started up.
  • the voltage evaluation circuit generates an output signal that indicates a comparison result between the voltage of the first node and a predetermined voltage.
  • the voltage divider circuit is configured to variably set the impedance between the power supply wiring and the reference voltage while maintaining a constant division ratio of the divided voltage to the power supply voltage according to the voltage change rate detected by the voltage rate detection circuit. This impedance is set to be lower as the voltage change rate increases.
  • the present disclosure by appropriately changing the impedance of the voltage divider circuit in accordance with the rate of voltage change at the time of power-on of the power supply voltage, it is possible to provide a power-on reset circuit that can reduce power consumption and operate appropriately even if the rate of voltage change at the time of power-on of the power supply voltage changes.
  • FIG. 1 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a comparative example.
  • 1 is a conceptual operational waveform diagram of a power-on reset circuit when a power supply voltage is started up;
  • 1 is a block diagram illustrating a configuration of a power-on reset circuit according to a first embodiment.
  • FIG. 4 is a circuit diagram illustrating a configuration example of a voltage divider circuit in FIG. 3 .
  • 4 is a circuit diagram illustrating a configuration example of a voltage determination circuit in FIG. 3.
  • 1 is an equivalent circuit diagram of a power-on reset circuit according to a first embodiment;
  • FIG. 11 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to a second embodiment.
  • FIG. 8 is a conceptual waveform diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 7.
  • 8 is a table illustrating the operation of the voltage rate detection circuit shown in FIG. 7 .
  • FIG. 11 is a circuit diagram illustrating a configuration example of a voltage determination circuit according to a third embodiment.
  • FIG. 11 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to a third embodiment.
  • 4 is a conceptual operational waveform diagram at the time of starting up the power supply voltage of the power-on reset circuit according to the first embodiment;
  • Embodiment 1 Before describing the power-on reset circuit according to the first embodiment, a comparative example will be described.
  • FIG. 1 is a circuit diagram illustrating a configuration of a power-on reset circuit 5# according to a comparative example.
  • the power-on reset circuit 5# includes a voltage divider circuit 10# and a voltage determination circuit 20#.
  • the voltage divider circuit 10# has resistive elements RH and RL connected in series between a power supply line PL that receives the power supply voltage AVDD and a reference voltage line NL that transmits a reference voltage VSS.
  • the reference voltage VSS is typically ground (ground voltage)
  • the reference voltage VSS will be referred to as the ground voltage VSS
  • the reference voltage line NL will also be referred to as the ground line NL.
  • the resistor element RH is connected between the power supply line PL and the node N1, and the resistor element RL is connected between the node N1 and the ground line NL. Therefore, a divided voltage Vdiv of the power supply voltage AVDD by the resistor elements RH and RL is generated at the node N1.
  • Voltage evaluation circuit 20# has a transistor 21, a current supply circuit 22, and a signal generation circuit 25 configured with an inverter.
  • Transistor 21 is an N-type field effect transistor, connected between node N2 and ground wiring NL, and has a gate (control electrode) connected to node N1.
  • Current supply circuit 22 has a resistive element RD connected between power supply wiring PL and node N2.
  • Signal generation circuit 25 outputs an output signal VPOR having a logic level according to the voltage Vdet of node N2.
  • the output signal VPOR corresponds to a so-called power-on reset signal (POR signal).
  • the output signal VPOR when the voltage Vdet drops to the ground voltage VSS in response to the transistor 21 being turned on, the output signal VPOR is set to a logical high level (hereinafter referred to as the "H level").
  • the output signal VPOR is set to a logical low level (hereinafter referred to as the "L level") in response to the node N2 being pulled up to the power supply voltage AVDD.
  • Vt1 of the transistor 21 when Vdiv ⁇ Vt1, the transistor 21 is off, and when Vdiv>Vt1, the transistor 21 is on.
  • the output signal VPOR is at L level (ground voltage VSS) while Vdiv ⁇ Vt1, and is at H level (power supply voltage AVDD) while Vdiv>Vt1.
  • Vt1/Kv the determination voltage Vpr equivalent to (Vt1/Kv).
  • Figure 2 shows a conceptual waveform diagram of the power-on reset circuit when the power supply voltage is turned on.
  • FIG. 2 shows waveforms 101 to 103 of the power supply voltage AVDD at startup.
  • Waveforms 101 to 103 differ in the voltage change rate (dAVDD/dt) at startup.
  • dAVDD/dt the voltage change rate
  • waveform 101 the power supply voltage AVDD reaches the judgment voltage Vpr at time t1.
  • waveform 102 the power supply voltage AVDD reaches the judgment voltage Vpr at time t2, which is later than time t1.
  • waveform 103 the power supply voltage AVDD reaches the judgment voltage Vpr at time t3, which is later than time t2.
  • the divided voltage Vdiv reaches the threshold voltage Vt1 of the transistor 21 at the timing when the power supply voltage AVDD reaches the determination voltage Vpr. Therefore, ideally, as shown by the solid lines in FIG. 2, the transistor 21 turns on at each of times t1 to t3, causing the output signal VPOR to change from the L level (ground voltage VSS) to the H level (power supply voltage AVDD).
  • the voltage error ⁇ Ver between the power supply voltage AVDD and the judgment voltage Vpr when the output signal VPOR actually changes to the H level changes depending on the voltage change rate. Specifically, the greater the voltage change rate, the greater the voltage error ⁇ Ver.
  • the delay time from times t1-t3 to times t1x-t3x is mainly determined by the RC time constant according to the product of the R component of voltage divider circuit 10# and the parasitic capacitance Cp. Therefore, if the resistance value (RH+RL) of voltage divider circuit 10# is reduced, the charging current of parasitic capacitance Cp increases, and the delay time due to the RC time constant can be shortened. In other words, the power-on reset circuit 5# can be increased.
  • the output signal VPOR POR signal
  • the output signal VPOR POR signal
  • the resistance value (RH+RL) is reduced in the voltage divider circuit 10#, the operating speed increases but the power consumption increases, and when the resistance value (RH+RL) is increased, the power consumption decreases but the operating speed decreases.
  • the speed at which voltage Vdet at node N2 changes to ground voltage VSS is affected by the magnitude of the current supplied by current supply circuit 22.
  • the lower the resistance value RD the larger the supply current becomes, and the faster voltage Vdet can be changed to ground voltage VSS.
  • the timing at which output signal VPOR changes to H level can be advanced, shortening the delay time from time t1-t3 to time t1x-t3x. In other words, the power-on reset circuit 5# can be increased.
  • transistor 21 is maintained in the ON state while output signal VPOR is at H level. Therefore, due to resistive element RD and transistor 21 (ON state), a steady current is generated between power supply line PL and ground line NL in voltage evaluation circuit 20# as well. As a result, in power-on reset circuit 5# of FIG. 1, lowering resistance value RD in voltage evaluation circuit 20# also increases operating speed but power consumption, and increasing resistance value RD reduces power consumption but reduces operating speed.
  • FIG. 3 is a block diagram illustrating the configuration of the power-on reset circuit 5 according to the present embodiment.
  • the power-on reset circuit 5 includes a voltage divider circuit 10, a voltage evaluation circuit 20, and a voltage rate detection circuit 30, which are connected between the power supply line PL and the ground line NL.
  • the voltage divider circuit 10 outputs a divided voltage Vdiv of the power supply voltage AVDD on the power supply line PL to a node N1.
  • the voltage evaluation circuit 20 generates an output signal VPOR that indicates the result of comparing the voltage of the node N1 with a predetermined threshold voltage (e.g., the threshold voltage Vt1 of the transistor 21). In other words, the node N1 corresponds to the "first node.”
  • the voltage rate detection circuit 30 detects the voltage change rate (i.e., dAVdd/dt) of the power supply wiring PL when the power supply voltage AVDD is started, for example, using a differential circuit with a capacitor.
  • the voltage rate detection circuit 30 judges the voltage change rate VRT [V/s] in a predetermined N-stage (N: an integer of 2 or more) and sets one of the selection signals SEL(0) to SEL(N-1) to the H level depending on the judgment result.
  • a preferred configuration example of the voltage rate detection circuit 30 will be described in detail in the second embodiment.
  • FIG. 4 shows a circuit diagram for explaining an example of the configuration of the voltage divider circuit 10 in FIG. 4, the voltage dividing circuit 10 includes N voltage dividing resistors connected in parallel between a power supply line PL and a ground line NL, and a selection circuit 15.
  • the N voltage dividing resistors each have resistive elements RH(0) to RH(N-1) connected between the power supply line PL and node N1, and resistive elements RL(0) to RL(N-1) connected between node N1 and ground line NL.
  • resistive elements RH(0) and RL(0) constituting the voltage dividing resistor on the lowest bit side, RH(N-1) and RL(N-1) constituting the voltage dividing resistor on the highest bit side, and RH(M) and RL(M) constituting the voltage dividing resistor on the intermediate bit side are shown (0 ⁇ M ⁇ (N-1)).
  • the voltage dividing ratio Kv i.e., the ratio of the resistance values of the resistive elements RH(0) through RH(N-1) to those of the resistive elements RL(0) through RL(N-1), is equal.
  • the sum of the resistance values of each of the resistive elements RH(0) to RH(N-1) and each of the resistive elements RL(0) to RL(N-1) - that is, the impedance between the power supply wiring PL and the ground wiring NL - differs among the N voltage dividing resistors. Specifically, RH(0) + RL(0) > ... > RH(M) + RL(M) > ... > RH(N-1) + RL(N-1).
  • the selection circuit 15 has switch elements SWH(0) to SWH(N-1) and switch elements SWL(0) to SWL(N-1).
  • the switch elements SWH(0) to SWH(N-1) are connected in series with the resistance elements RH(0) to RH(N-1), respectively, between the power supply wiring PL and the node N1.
  • the switch elements SWL(0) to SWL(N-1) are connected in series with the resistance elements RL(0) to RL(N-1), respectively, between the ground wiring NL and the node N1.
  • Switch elements SWH(0) to SWH(N-1) and switch elements SWL(0) to SWL(N-1) are turned on and off in response to selection signals SEL(0) to SEL(N-1). Specifically, each of switch elements SWH(0) to SWH(N-1) and SWL(0) to SWL(N-1) is turned on when the corresponding selection signal SEL is at H level, and turned off when the corresponding selection signal SEL is at L level.
  • the switch elements SWH(0) and SWL(0) are turned on.
  • the other selection signals SEL(1) to SEL(N-1) are at the L level, so the other switch elements SWH(1) to SWH(N-1) and SWL(1) to SWL(N-1) are turned off.
  • the voltage rate detection circuit 30 sets one of the N selection signals SEL to H level and the remaining (N-1) to L level in accordance with the voltage change rate of the power supply voltage AVDD. This turns on the switch element SWH and the switch element SWL to which the selection signal SEL set to H level has been input.
  • one of the N voltage divider resistors is selected according to the voltage rate detected by the voltage rate detection circuit 30, and is connected between the power supply line PL and the ground line NL.
  • the corresponding switch elements SWH, SWL are turned off, so no current is generated between the power supply line PL and the ground line NL.
  • the switch elements SWH(0) to SWH(N-1) and SWL(0) to SWL(N-1) are all in the off state.
  • the selection signal SEL(M) is set to H level by the voltage rate detection circuit 30, so that the switch elements SWH(M) and SWL(M) are turned on, and the voltage dividing resistors formed by the resistance elements RH(M) and RL(M) are selectively connected between the power supply wiring PL and the ground wiring NL.
  • each of the resistance elements RH(0) to RH(N-1) corresponds to an embodiment of a "second resistance element”
  • each of the resistance elements RL(0) to RL(N-1) corresponds to an embodiment of a "third resistance element.”
  • node N1 corresponds to an embodiment of the "first node” as described above.
  • FIG. 5 shows a circuit diagram for explaining an example of the configuration of the voltage determination circuit 20 in FIG. 5, voltage evaluation circuit 20 differs from voltage evaluation circuit 20# shown in FIG 1 in that it has a current control circuit 27 instead of current supply circuit 22.
  • Current control circuit 27 has resistance elements RD(0) to RD(N-1) and switch elements SWD(0) to SWD(N-1) connected in parallel between power supply wiring PL and node N2. Switch elements SWD(0) to SWD(N-1) are connected in series with resistance elements RD(0) to RD(N-1), respectively, between power supply wiring PL and node N2.
  • the switch elements SWD(0) to SWD(N-1) are turned on and off in response to the selection signals SEL(0) to SEL(N-1). Specifically, each of the switch elements SWD(0) to SWD(N-1) is turned on when the corresponding selection signal SEL is at H level, and turned off when the corresponding selection signal SEL is at L level. Furthermore, until the voltage rate is detected by the voltage rate detection circuit 30, all of the switch elements SWD(0) to SWD(N-1) are in the off state.
  • the selection signal SEL(M) is set to H level by the voltage rate detection circuit 30, so that the switch element SWD(M) is turned on and the resistor element RD(M) is selectively connected between the power supply line PL and the node N2.
  • the resistance values of the resistor elements RD(0) to RD(N-1) are different, and specifically, the resistance values are set so that RD(0)>RD(1)>...RD(M)...>RD(N-1) are larger on the lower bit side.
  • the rest of the configuration of the voltage evaluation circuit 20 is the same as that of the voltage evaluation circuit 20# shown in FIG. 1.
  • the switch element SWD when the switch element SWD is turned on with the selection signal SEL set to H level, one of the N resistance elements RD(0) to RD(N-1) with different resistance values is selected according to the voltage rate detected by the voltage rate detection circuit 30, and is connected between the power supply line PL and node N2.
  • the supply current Idet from the current control circuit 27 to node N2 becomes larger. This makes it possible to increase the rate of change of the voltage at node N2 when the transistor 21 is turned on.
  • the current control circuit 27 can variably control the supply current Idet so that the supply current Idet increases as the voltage change rate increases.
  • the resistance elements RD(0) to RD(N-1) correspond to one embodiment of "plurality of first resistance elements”
  • the node N2 corresponds to one embodiment of the "second node.”
  • the switch elements SWD(0) to SWD(N-1) correspond to one embodiment of “plurality of switch elements”
  • the transistor 21 corresponds to one embodiment of the "first transistor.”
  • FIG. 6 is an equivalent circuit diagram of the power-on reset circuit 5 according to the first embodiment.
  • the selection signal SEL(M) is set to the H level in accordance with the voltage change rate detected by the voltage rate detection circuit 30.
  • a voltage dividing resistor constituted by the resistance elements RH(M) and RL(M) is connected between the power supply wiring PL and the ground wiring NL.
  • the voltage division ratio Kv is constant, while the voltage division resistors (RH and RL) are selected so that the impedance (resistance value) between the power supply wiring PL and the ground wiring NL is higher the larger the voltage change rate is, and conversely, is lower the smaller the voltage change rate is.
  • the impedance between the power supply wiring PL and the ground wiring NL by the voltage divider circuit 10 can be reduced. This reduces the delay time until the transistor 21 turns on when the power supply voltage AVDD reaches the determination voltage Vpr (Vdiv>Vt1), thereby increasing the operating speed.
  • the impedance between the power supply wiring PL and the ground wiring NL by the voltage divider circuit 10 can be increased to suppress the current steadily generated between the power supply wiring PL and the ground wiring NL, thereby reducing power consumption.
  • a resistive element RD(M) is connected between the power supply line PL and node N2, and a supply current Idet according to the resistance value RD(M) is provided to node N2. Therefore, in the voltage evaluation circuit 20, the resistive element RD is selected according to the voltage change rate detected by the voltage rate detection circuit 30 so that the greater the voltage change rate, the greater the supply current Idet, and conversely, the smaller the voltage change rate, the smaller the supply current Idet.
  • the supply current Idet by the current control circuit 27 is increased, thereby shortening the time required for the output signal VPOR to change from L level to H level when the transistor 21 is turned on, and thus the operating speed can be further increased.
  • the supply current Idet by the current control circuit 27 is decreased, thereby suppressing the current steadily generated between the power supply wiring PL and the ground wiring NL during the ON period of the transistor 21, thereby achieving low power consumption.
  • FIG. 12 shows a conceptual operational waveform diagram of the power-on reset circuit according to embodiment 1 at the time of starting up the power supply voltage, which is compared with FIG. 2.
  • the waveforms 101 to 103 at the time of starting up the power supply voltage AVDD are the same as those in FIG. 2.
  • the timing at which the output signal VPOR changes from an L level to an H level for each of the waveforms 101 to 103 is between times t1y and t3y, which is later than times t1 and t3, depending on the time required for the voltage rate detection circuit 30 to detect the voltage rate and the charging time of the node N1 (parasitic capacitance Cp).
  • the impedance of the voltage divider circuit 10 is mainly changed according to the voltage change rate, and the supply current Idet by the current control circuit 27 is also changed, so that the time delay (e.g., time t1 to t1y) when the voltage change rate is large is shorter than in the comparative example of FIG. 2.
  • the POR signal can be generated at an appropriate timing without increasing power consumption. Furthermore, since a transistor connected in series with a voltage dividing resistor as in Patent Document 1 and a latch circuit at a subsequent stage are not arranged, the POR signal can be generated at high speed. Furthermore, as shown in FIG. 12, even if the voltage change rate differs, the level of the power supply voltage AVDD when the output signal VPOR actually changes to the H level is the same, so that the operation at the time of startup of a semiconductor device equipped with the power-on reset circuit can be stabilized.
  • Embodiment 2 In the second embodiment, a preferred configuration example of a voltage rate detection circuit will be described.
  • FIG. 7 is a circuit diagram illustrating an example of the configuration of a voltage rate detection circuit according to the second embodiment.
  • the voltage rate detection circuit 30 includes N rate detection units RDUT(0) to RDUT(N-1) and a control logic 35.
  • the rate detection units RDUT(0) to RDUT(N-1) output rate detection signals SRDET(0) to SRDET(N-1), respectively, based on the voltage change rate of the power supply voltage AVDD.
  • the control logic 35 generates the selection signals SEL(0) to SEL(N-1) in FIG. 1 according to the rate detection signals SRDET(0) to SRDET(N-1).
  • rate detection units RDUT(0), RDUT(M), and RDUT(N-1) are shown as examples, but the circuit configurations of each are the same, and only some of the circuit constants are different, as described below. Below, the configuration of the Mth rate detection unit RDUT(M) is explained as a representative example.
  • the rate detection unit RDUT(M) includes a detection capacitor CDET(M), a charging capacitor CREF(M), transistors MND1(M) and MND2(M), a current supply circuit 36(M), and an inverter INVD(M).
  • the detection capacitor CDET(M) is connected between the power supply line PL and node N3(M), and the transistor MND1(M) is connected between node N3(M) and the ground line NL.
  • the transistor MND2(M) is connected between node N4(M) and the ground line NL.
  • the gates of the transistors MND1(M) and MND2(M) are connected to the node N3(M), and the charging capacitor CREF(M) is connected between the node N3(M) and the ground line NL.
  • the transistor MND1(M) is diode-connected.
  • the charging capacitor CREF(M) includes at least the gate capacitance (parasitic capacitance) of the transistor MND2(M), and may further include a parallel plate capacitor, a MOS (Metal Oxide Semiconductor) capacitor, etc., which may be additionally connected.
  • the capacitance values of each capacitor will be denoted by the same symbol.
  • the current supply circuit 36(M) is connected between the power supply wiring PL and node N4(M) and supplies a current to node N4(M).
  • the current supply circuit 36(M) has a resistive element RDET(M) connected between the power supply wiring PL and node N4(M). That is, the supply current Ird(M) by the current supply circuit 36(M) is adjusted by the resistance value of the resistive element RDET(M), and the lower the RDET(M), the larger the supply current Ird(M).
  • Inverter INVD(M) outputs a rate detection signal SRDET(M) having a logic level according to the voltage of node N4(M).
  • the voltage of node N4(M) is the power supply voltage AVDD while transistor MND2(M) is off, and changes to ground voltage VSS at a speed according to the supply current Ird(M) according to the on-state of transistor MND2(M). Therefore, while the rate detection signal SRDET(M) is at L level (ground voltage VSS) when transistor MND2(M) is off, it changes from L level to H level according to the on-state of transistor MND2(M).
  • Ic(M) CDET(M) ⁇ VRT...(2)
  • the charging capacitor CREF(M) of the node N3(M) is charged by the detection current Ic(M) generated in response to the change in the power supply voltage AVDD.
  • the rate detection signal SRDET(M) changes from the L level to the H level.
  • a detection signal SRDET(M) is generated.
  • the capacitance ratios Kc of the detection capacitors CDET(0) to CDET(N-1) to the charging capacitors CREF(0) to CREF(N-1) are different between the rate detection units RDUT(0) to RDUT(N-1).
  • the rate detection units RDUT on the lower bit side are designed to have a larger capacitance ratio Kc.
  • the element constants other than the capacitance ratio Kc are set in common between the rate detection units RDUT(0) to RDUT(N-1).
  • the threshold voltage Vt2 is also common between the transistors MND2(0) to MND2(N-1).
  • the capacitance values of the charging capacitors CREF(0) to CREF(N-1) are common between the rate detection units RDUT(0) to RDUT(N-1), while the capacitance values of the detection capacitors CDET(0) to CDET(N-1) are designed to be gradually larger for the rate detection units RDUT on the lower bit side. That is, CDET(0)>...>CDET(M)>...>CDET(N-1).
  • the capacitance values of the detection capacitors CDET(0) to CDET(N-1) can be gradually set so that the capacitance value decreases by a factor of (1/2) in accordance with a factorial ratio of 2.
  • the transistor MND2 of each rate detection unit RDUT corresponds to an embodiment of a "second transistor”
  • the node N3 corresponds to an embodiment of a "third node”
  • the node N4 corresponds to an embodiment of a "fourth node”.
  • the transistor MND2, the current supply circuit 36, and the inverter INVD can constitute an embodiment of a "rate determination circuit" for generating the rate detection signal SRDET.
  • FIG. 8 is a conceptual waveform diagram that explains the operation of the voltage rate detection circuit.
  • the vertical axis of FIG. 8 shows the voltage VN3 at node N3.
  • the detection currents Ic(0) to Ic(N-1) generated in each of the rate detection units RDUT(0) to RDUT(N-1) are proportional to the capacitance values of the detection capacitors CDET(0) to CDET(N-1).
  • the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set so that when the power supply voltage AVDD of the minimum rate value is applied to the rate detection unit RDUT(0) in which the capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET is maximum, the voltage of the node N3 rises to the threshold voltage Vt2 in a predetermined reference time.
  • the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set so that when the power supply voltage AVDD of the maximum rate value is applied, the voltage of the node N3 rises to the threshold voltage Vt2 in the same reference time.
  • the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set in stages so that the value becomes smaller toward the higher bit side in the range between the rate detection units RDUT(0) and RDUT(N-1).
  • the rate detection signals SRDET(0) to SRDET(N-1) from the rate detection units RDUT(0) to RDUT(N-1) are generated as shown in FIG. 9.
  • FIG. 9 shows a diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 9, when the power supply voltage AVDD having the minimum rate value R1 is input to the rate detection units RDUT(0) to RDUT(N-1), at the time when the reference time has elapsed since the start of the power supply voltage AVDD was detected based on the voltage of the power supply wiring PL, the transistor MND2(0) is turned on only in the rate detection unit RDUT(0) having the largest capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET. Meanwhile, in the other rate detection units RDUT(1) to RDUT(N-1), the transistors MND2(1) to MND2(N-1) remain off.
  • the rate detection signal SRDET(0) is at H level, while the rate detection signals SRDET(1) to SRDET(N-1) are at L level. That is, the rate detection signal SRDET is generated only in the rate detection unit RDUT(0).
  • the rate detection units RDUT(M+1) to RDUT(N-1) which are on the higher bit side and have a smaller capacitance value of the detection capacitor CDET (i.e., capacitance ratio Kc) than the rate detection unit RDUT(M), transistors MND2(M+1) to MND2(N-1) remain off.
  • the rate detection signals SRDET(0) to SRDET(M) are at H level, while the rate detection signals SRDET(M+1) to SRDET(N-1) are at L level. That is, the rate detection signal SRDET is generated in the (M+1) rate detection units RDUT(0) to RDUT(M).
  • the control logic 35 sets only one of the selection signals SEL(0) to SEL(N-1) to the H level and sets the remaining (N-1) signals to the L level according to the rate detection signals SRDET(0) to SRDET(N-1) generated as described above.
  • control logic 35 can be constructed so that only one bit of the selection signal SEL corresponding to the most significant bit of the rate detection signals SRDET(0) to SRDET(N-1) that is set to the H level is set to the H level. Also, when all of the rate detection signals SRDET(0) to SRDET(N-1) are at the L level, the selection signal SEL(0) is set to the H level.
  • the power-on reset circuit 5 can operate according to the equivalent circuit diagram shown in FIG. 6.
  • the voltage rate detection circuit 30 described in the second embodiment has a simple configuration and can quickly detect the voltage change rate in multiple stages (N stages) when the power supply voltage AVDD is started.
  • the resistance values of the resistor elements RD are set in the order RD(0)>...>RD(M)>...>RD(N-1), which allows for such settings of the supply currents Ird(0) to Ird(N-1).
  • each of the resistor elements RD(0) to RD(N-1) corresponds to an example of a "fourth resistor element.”
  • the threshold voltage Vt1 of the transistor 21 of the voltage determination circuit 20 and the threshold voltage Vt2 of the transistor MND2 of each rate detection unit RDUT it is preferable that the threshold voltage Vt1 (transistor 21) is set higher than the threshold voltage Vt2 (transistor MND2) (Vt1>Vt2). That is, it is preferable that the voltage of the node N1 when the transistor 21 is turned on is higher than the voltage of the node N3 when the transistor MND2 is turned on.
  • Embodiment 3 In the third embodiment, a modified example of the configuration of the voltage evaluation circuit and the voltage rate detection circuit exemplified in the first and second embodiments will be described.
  • FIG. 10 is a circuit diagram illustrating a configuration example of a voltage evaluation circuit according to the third embodiment.
  • a voltage evaluation circuit 20X according to the third embodiment differs from voltage evaluation circuit 20 shown in FIG. 5 in that it has a current control circuit 27X instead of current control circuit 27.
  • Current control circuit 27X differs from current control circuit 27 in that it has current source circuits CSD(0) to CSD(N-1) configured to include transistors instead of resistance elements RD(0) to RD(N-1).
  • the other configuration of current control circuit 27X is the same as that of current control circuit 27. That is, current control circuit 27X has current source circuits CSD(0) to CSD(N-1) connected in parallel between power supply wiring PL and node N2, and switch elements SWD(0) to SWD(N-1). Switch elements SWD(0) to SWD(N-1) are connected in series with each of current source circuits CSD(0) to CSD(N-1) between power supply wiring PL and node N2.
  • the output currents Id(0) to Id(N-1) of the current source circuits CSD(0) to CSD(N-1) are different, and specifically, they are set so that Id(0) ⁇ Id(1) ⁇ ... Id(M) ... ⁇ Id(N-1) so that the output current is larger on the higher-order bit side.
  • the switch elements SWD(0) to SWD(N-1) are turned on and off in the same manner as described in the first embodiment according to the selection signals SEL(0) to SEL(N-1). Therefore, the higher the voltage change rate detected by the voltage rate detection circuit 30, the larger the output current of the current source circuit CSD is connected between the power supply wiring PL and node N2 by the switch element SWD.
  • each of the current source circuits CSD(0) to CSD(N-1) corresponds to an example of a "first current source circuit.”
  • FIG. 11 is a circuit diagram illustrating an example of the configuration of a voltage rate detection circuit according to the third embodiment.
  • a voltage rate detection circuit 30X according to the third embodiment differs from the voltage rate detection circuit 30 shown in FIG. 7 in that rate detection units RDUT(0) to RDUT(N-1) have current supply circuits 36X(0) to 36X(N-1) instead of current supply circuits 36(0) to 36(N-1).
  • Current supply circuits 36X(0) to 36X(N-1) differ in that they have current source circuits CSDT(0) to CSDT(N-1) configured to include transistors (not shown) instead of resistive elements RD(0) to RD(N-1).
  • the rest of the configuration of voltage rate detection circuit 30X is the same as that of voltage rate detection circuit 30.
  • the supply currents Ird(0) to Ird(N-1) of the current supply circuits 36(0) to 36(N-1) are Ird(0) ⁇ ... ⁇ Ird(M) ⁇ ... ⁇ to Ird(N-1) so that the supply current Ird becomes larger as the rate detection unit RDUT becomes more significant.
  • the output currents of the current source circuits CSDT(0) to CSDT(N-1) are designed so that the output current becomes larger in the rate detection unit RDUT on the more significant bit side, thereby making it possible to realize such settings of the supply currents Ird(0) to Ird(N-1).
  • each of the current source circuits CSDT(0) to CSDT(N-1) corresponds to an example of a "second current source circuit".
  • the transistor MND2, the current supply circuit 36X, and the inverter INVD constitute one embodiment of a "rate determination circuit" for generating the rate detection signal SRDET.

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PCT/JP2022/046664 2022-12-19 2022-12-19 パワーオンリセット回路 Ceased WO2024134719A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252808A (ja) * 1999-02-26 2000-09-14 Sharp Corp 集積回路
US20090160540A1 (en) * 2007-12-20 2009-06-25 Kwang Myoung Rho Power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit
JP2014183384A (ja) * 2013-03-18 2014-09-29 Seiko Instruments Inc 受光回路
US20150244356A1 (en) * 2014-02-25 2015-08-27 SK Hynix Inc. Power-up signal generation circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252808A (ja) * 1999-02-26 2000-09-14 Sharp Corp 集積回路
US20090160540A1 (en) * 2007-12-20 2009-06-25 Kwang Myoung Rho Power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit
JP2014183384A (ja) * 2013-03-18 2014-09-29 Seiko Instruments Inc 受光回路
US20150244356A1 (en) * 2014-02-25 2015-08-27 SK Hynix Inc. Power-up signal generation circuit

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