WO2024131410A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024131410A1
WO2024131410A1 PCT/CN2023/132653 CN2023132653W WO2024131410A1 WO 2024131410 A1 WO2024131410 A1 WO 2024131410A1 CN 2023132653 W CN2023132653 W CN 2023132653W WO 2024131410 A1 WO2024131410 A1 WO 2024131410A1
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WO
WIPO (PCT)
Prior art keywords
transistor
display
scan
line
transmission line
Prior art date
Application number
PCT/CN2023/132653
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English (en)
French (fr)
Inventor
李明月
田超
艾飞
Original Assignee
武汉华星光电技术有限公司
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Publication of WO2024131410A1 publication Critical patent/WO2024131410A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a display device.
  • the present application provides a display panel and a display device to alleviate the technical problem that the pulse end edge of a scanning signal varies greatly during transmission.
  • the present application provides a display panel, which is provided with a display area and a non-display area, and the display panel includes a plurality of scan lines and a plurality of groups of waveform sorting units located in the display area, the plurality of scan lines include an N-1th scan line, an Nth scan line and an N+1th scan line arranged in sequence; wherein each waveform sorting unit in the Nth group includes a first transistor and a second transistor, the gate of the first transistor is connected to the Nth scan line, the first electrode of the first transistor is connected to the N-1th scan line, and the second electrode of the first transistor is connected to the first potential transmission line; the gate of the second transistor is connected to the N scan line, the first electrode of the first transistor is connected to the N+1th scan line, and the second electrode of the first transistor is connected to the second potential transmission line.
  • the present application provides a display device, which includes a display panel in at least one of the above-mentioned embodiments, and the display panel also includes two gate driving circuits located on opposite sides of the display area, and both ends of each scanning line are respectively connected to a corresponding gate driving unit in a gate driving circuit.
  • FIG. 1 is a schematic diagram of the structure of a display panel in the related art.
  • FIG. 2 is a schematic diagram of a first structure of a display panel provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a second structure of a display panel provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a third structure of a display panel provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a fourth structure of a display panel provided in an embodiment of the present application.
  • FIG. 6 is a fifth structural schematic diagram of a display panel provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram showing the improvement in the display panel provided by an embodiment of the present application.
  • FIG8 is a timing diagram of a forward scan provided in an embodiment of the present application.
  • FIG. 9 is a timing diagram of reverse scanning provided in an embodiment of the present application.
  • FIG1 is a schematic diagram of the structure of a display panel in the related art, and the display panel includes a plurality of scan lines, a plurality of data lines, and sub-pixels (Pixel).
  • Each scan line is connected to a corresponding row of sub-pixels, for example, the N-1th scan line GateN-1 is connected to the N-1th row of sub-pixels, the Nth scan line GateN is connected to the Nth row of sub-pixels, and the N+1th scan line GateN+1 is connected to the N+1th row of sub-pixels.
  • Each data line is connected to a corresponding column of sub-pixels, for example, the data line datar is connected to a column of red sub-pixels (R), the data line datag is connected to a column of green sub-pixels (G), and the data line datab is connected to a column of blue sub-pixels (B).
  • R red sub-pixels
  • G green sub-pixels
  • B blue sub-pixels
  • a virtual routing line is also set on one side of the corresponding data line.
  • a virtual routing line dummy1 is set on the left side of the data line datar
  • a virtual routing line dummy2 is set on the left side of the data line datag
  • a virtual routing line dummy3 is set on the left side of the data line datab.
  • the present embodiment provides a display panel, please refer to Figures 2 to 9.
  • the display panel is provided with a display area and a non-display area, and the display panel includes a plurality of scanning lines and a plurality of groups of waveform sorting units 20 located in the display area, and the plurality of scanning lines include the N-1th scanning line GateN-1, the Nth scanning line GateN and the N+1th scanning line GateN+1 arranged in sequence; wherein each waveform sorting unit 20 in the Nth group includes a first transistor NTA and a second transistor NTB, the gate of the first transistor NTA is connected to the Nth scanning line GateN, the first electrode of the first transistor NTA is connected to the N-1th scanning line GateN-1, and the second electrode of the first transistor NTA is connected to the first potential transmission line; the gate of the second transistor NTB is connected to the Nth scanning line GateN, the first electrode of the first transistor NTA is connected
  • the display panel provided in this embodiment can control the opening of the first transistor NTA through the Nth scan line GateN so that the end edge of the pulse transmitted in the N-1th scan line GateN-1 can be steeper or closer to the ideal target during the forward scanning process, or can control the opening of the second transistor NTB through the Nth scan line GateN so that the end edge of the pulse transmitted in the N+1th scan line GateN+1 can be steeper or closer to the ideal target during the reverse scanning process.
  • This can improve the deformation of the pulse end edge of the scanning signal during the transmission process, which not only reduces the risk of charging errors, but also increases the charging time or is conducive to achieving higher frequency display.
  • the display panel provided in this embodiment can be applied to the forward scanning or reverse scanning driving mode.
  • the first electrode can be one of the source and the drain, and the second electrode can be the other of the source and the drain.
  • the first electrode when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.
  • Each scanning line is configured with a corresponding group of waveform arranging units 20 , for example, the Nth scanning line GateN is configured with the Nth group of waveform arranging units 20 .
  • Each group of waveform arranging units 20 may include one or more waveform arranging units 20 .
  • the first transistor NTA and the second transistor NTB can be a low temperature polycrystalline silicon (LTPS) thin film transistor, an amorphous silicon (a_Si) thin film transistor, an indium gallium zinc oxide (IGZO) thin film transistor, or a hybrid thin film transistor such as LTPS&IGZO.
  • LTPS low temperature polycrystalline silicon
  • a_Si amorphous silicon
  • IGZO indium gallium zinc oxide
  • hybrid thin film transistor such as LTPS&IGZO.
  • the forward scan, the pulse of the scanning signal Gaten-1 transmitted in the N-1th scanning line GateN-1, the pulse of the scanning signal Gaten transmitted in the Nth scanning line GateN, and the pulse of the scanning signal Gaten+1 transmitted in the N+1th scanning line GateN+1 arrive in sequence, and the N-1th row of sub-pixels, the Nth row of sub-pixels, and the N+1th row of sub-pixels are opened in sequence to write corresponding data signals respectively.
  • the pulse rising edge of the scan signal Gaten and the falling edge of the scan signal Gaten-1 occur at the same time, or the time interval between the two is 0us.
  • the scan signal Gaten is at a high potential, and the first transistor NTA in the waveform sorting unit 20 of the Nth group is turned on or opened, and the falling edge of the scan signal Gaten-1 can be pulled down to a low level at the end of the time period T1; similarly, at the beginning of the time period T3, the scan signal Gaten+1 is at a high potential, and the first transistor NTA in the waveform sorting unit 20 of the N+1th group is turned on or opened, and the falling edge of the scan signal Gaten can be pulled down to a low level at the end of the time period T2. In this way, the pulse ending edge of each scan signal is steeper or closer to the ideal target.
  • the reverse scan is performed.
  • the pulse of the scan signal Gaten+1 transmitted in the N+1th scan line GateN+1, the pulse of the scan signal Gaten transmitted in the Nth scan line GateN, and the pulse of the scan signal Gaten-1 transmitted in the N-1th scan line GateN-1 arrive successively, and the N+1th row of sub-pixels, the Nth row of sub-pixels, and the N-1th row of sub-pixels are opened successively to write corresponding data signals respectively.
  • the pulse rising edge of the scan signal Gaten and the falling edge of the scan signal Gaten+1 occur at the same time, or the time interval between the two is 0us.
  • the scan signal Gaten is at a high potential
  • the second transistor NTB in the waveform sorting unit 20 of the Nth group is turned on or opened, and the falling edge of the scan signal Gaten+1 can be pulled down to a low level at the end of time period T1;
  • the scan signal Gaten-1 is at a high potential, and the second transistor NTB in the waveform sorting unit 20 of the N-1th group is turned on or opened, and the falling edge of the scan signal Gaten can be pulled down to a low level at the end of time period T2. It can also make the pulse ending edge of each scan signal steeper or closer to the ideal target.
  • the N-1th scan line GateN-1 may be the first scan line Gate1 connected to the first row of sub-pixels
  • the Nth scan line GateN may be the second scan line Gate2 connected to the second row of sub-pixels
  • the N+1th scan line GateN+1 may be the third scan line Gate3 connected to the third row of sub-pixels
  • the N+2th scan line may be the fourth scan line Gate4 connected to the fourth row of sub-pixels.
  • the scan line Gate0 and the scan line Gate5 may be virtual scan lines respectively and are not connected to the corresponding sub-pixels.
  • the display panel when the display panel performs forward scanning, it provides a corresponding electrical signal to the first potential transmission line, and does not provide an electrical signal to the second potential transmission line; or, when the display panel performs reverse scanning, it provides a corresponding electrical signal to the second potential transmission line, and does not provide an electrical signal to the first potential transmission line.
  • the first potential transmission line pulls down or pulls up the ending edge of the corresponding scanning signal through each first transistor NTA; and the second potential transmission line does not pull down or pull up the ending edge of the corresponding scanning signal through each second transistor NTB, nor does it affect the normal transmission of the corresponding scanning signal.
  • the second potential transmission line pulls down or pulls up the end edge of the corresponding scanning signal through each second transistor NTB; while the first potential transmission line does not pull down or pull up the end edge of the corresponding scanning signal through each first transistor NTA, and will not affect the normal transmission of the corresponding scanning signal.
  • the end edge refers to the falling edge of a positive pulse or the rising edge of a negative pulse.
  • the first transistor NTA and the second transistor NTB are both N-channel thin film transistors, and the first potential transmission line or the second potential transmission line is used to transmit a low potential signal; or, when the scan line transmits a scan signal with a negative pulse, the first transistor NTA and the second transistor NTB are both P-channel thin film transistors, and the first potential transmission line or the second potential transmission line is used to transmit a high potential signal.
  • the potential of the low potential signal in this embodiment can be less than or equal to the low level of the corresponding scanning signal to pull down the falling edge of the positive pulse.
  • the potential of the high potential signal can be greater than or equal to the high level of the corresponding scanning signal to pull up the rising edge of the negative pulse.
  • the display area includes a plurality of display sub-areas distributed sequentially in the extension direction of the scan lines; in a part of each display sub-area, a plurality of first transistors NTA in different groups are distributed column by column in the arrangement direction of the scan lines; in another part of each display sub-area, a plurality of second transistors NTB in different groups are distributed column by column in the arrangement direction of the scan lines.
  • the area shown in FIG. 3 may be a display sub-area, the left half of which is distributed with the corresponding first transistor NTA, and the right half of which is distributed with the corresponding second transistor NTB.
  • This embodiment can not only achieve a more ideal improvement on the end edge of the scanning signal, but also can differentially configure different improvement effects during forward scanning and reverse scanning, which is conducive to meeting different application requirements.
  • the display area includes a plurality of display sub-areas sequentially distributed in the extension direction of the scan lines.
  • a waveform sorting unit 20 in each group is distributed column by column in the arrangement direction of the scan lines.
  • a waveform sorting unit 20 in each group is distributed column by column in the arrangement direction of the scanning lines, which means that the first transistor NTA and the second transistor NTB whose gate is connected to the N-1th scanning line GateN-1 are located in the left column, the first transistor NTA and the second transistor NTB whose gate is connected to the Nth scanning line GateN are located in the middle column, and the first transistor NTA and the second transistor NTB whose gate is connected to the N+1th scanning line GateN+1 are located in the right column.
  • each waveform sorting unit 20 in each waveform sorting unit 20 , the first transistor NTA and the second transistor NTB are adjacently distributed.
  • the adjacent distribution of the first transistor NTA and the second transistor NTB in each waveform sorting unit 20 means that in the extension direction of the scan line, there is no other first transistor NTA or second transistor NTB between the first transistor NTA and the second transistor NTB in each waveform sorting unit 20.
  • each dummy wiring (dummy) is continuously used as the first potential transmission line or the second potential transmission line, so that the waveform sorting unit 20 is placed adjacent to each other in the extension direction of the scanning line. This ensures that there is no obvious difference in the improvement effect on the end edge of the scanning signal during forward scanning and reverse scanning, and can also meet the needs of more application scenarios.
  • the display area includes a plurality of display sub-areas sequentially distributed in the extension direction of the scan lines.
  • a waveform sorting unit 20 in each group is distributed in alternate columns in the arrangement direction of the scan lines.
  • a waveform sorting unit 20 is distributed in alternate columns in the arrangement direction of the scanning lines, which means that: the first transistor NTA and the second transistor NTB whose gate is connected to the N-1th scanning line GateN-1 are located in the left column, the first transistor NTA and the second transistor NTB whose gate is connected to the N-1th scanning line GateN are located in the middle column, and the first transistor NTA and the second transistor NTB whose gate is connected to the N+1th scanning line GateN+1 are located in the right column.
  • FIG5 there are two columns between the left column and the middle column and between the middle column and the right column where no waveform sorting unit 20 is placed; or, as shown in FIG6 , there is one column between the left column and the middle column and between the middle column and the right column where no waveform sorting unit 20 is placed.
  • each waveform sorting unit 20 there is a data line between the first transistor NTA and the second transistor NTB.
  • each waveform sorting unit 20 the first transistors NTA and the second transistors NTB are arranged in alternate columns; or, a plurality of data lines are provided between the first transistors NTA and the second transistors NTB.
  • the first transistor NTA and the second transistor NTB are arranged in alternate columns; or, there are multiple data lines between the first transistor NTA and the second transistor NTB, which means that the first transistor NTA and the second transistor NTB in the same waveform sorting unit 20 are not adjacent to each other, which makes it possible to have no obvious difference in the improvement effect on the end edge of the scanning signal during the forward scanning and reverse scanning processes.
  • the wiring difficulty of these virtual routing is further reduced.
  • the first potential transmission line is used to transmit the first low potential signal VGL, and the potential of the first low potential signal VGL can be less than or equal to the low level of the corresponding scanning signal;
  • the second potential transmission line is used to transmit the second low potential signal VGL2, and the potential of the second low potential signal VGL2 can be less than or equal to the low level of the corresponding scanning signal.
  • the data line datar may be connected to a corresponding column of red sub-pixels (R), the data line datag may be connected to a corresponding column of green sub-pixels (G), and the data line datab may be connected to a corresponding column of blue sub-pixels (B).
  • R red sub-pixels
  • G green sub-pixels
  • B blue sub-pixels
  • a dummy line can be used as a touch line (TP), a first potential transmission line, or a second potential transmission line.
  • the first electrode of the first transistor NTA is connected to the N-2th scan line GateN-2, the gate of the first transistor NTA is connected to the N-1th scan line GateN-1, and the second electrode of the first transistor NTA is connected to a corresponding first potential transmission line;
  • the first electrode of the second transistor NTB is connected to the N-th scan line GateN, the gate of the second transistor NTB is connected to the N-1th scan line GateN-1, and the second electrode of the second transistor NTB is connected to a corresponding second potential transmission line.
  • the first electrode of the first transistor NTA is connected to the Nth scan line GateN, the gate of the first transistor NTA is connected to the N+1th scan line GateN+1, and the second electrode of the first transistor NTA is connected to a corresponding first potential transmission line;
  • the first electrode of the second transistor NTB is connected to the N+2th scan line GateN+2, the gate of the second transistor NTB is connected to the N+1th scan line GateN+1, and the second electrode of the second transistor NTB is connected to a corresponding second potential transmission line.
  • the above-mentioned embodiments can achieve the improvement of the ending edge of the in-plane scanning signal during forward drive scanning, and can also achieve the improvement of the ending edge of the in-plane scanning signal during reverse drive scanning. Since the improvement of the ending edge of the in-plane scanning signal during forward and reverse drive scanning can be satisfied respectively, the application of each embodiment can realize the liberalization of the installation method of the ultra-wide screen.
  • two gate driving circuits 100 are constructed for the ultra-wide screen.
  • the two gate driving circuits 100 are respectively located on opposite sides of the display area, and the data driving chip 300 that provides the corresponding data signal is located in the lower frame area.
  • the first row of sub-pixels to the last row of sub-pixels are opened in sequence from the first scan line (Gate1) to the last scan line (GateM); during reverse scanning, the last row of sub-pixels to the first row of sub-pixels are opened in sequence from the last scan line (GateM) to the first scan line (Gate1).
  • the display area is simply divided into four areas: area A, area B, area C, and area D.
  • Area A and area B are close to the gate drive circuit 100 and are symmetrical.
  • Area C and area D are far from the gate drive circuit 100 and are also symmetrical.
  • the present embodiment provides a display device, which includes the display panel of at least one of the above-mentioned embodiments, as shown in Figures 2 and 7, the display panel also includes two gate driving circuits 100 respectively located on opposite sides of the display area, and the two ends of each scanning line are respectively connected to the corresponding gate driving unit in a gate driving circuit 100.
  • the first transistor NTA can be controlled to open through the Nth scan line GateN, so that the end edge of the pulse transmitted in the N-1th scan line GateN-1 can be steeper or closer to the ideal target during the forward scanning process
  • the second transistor NTB can be controlled to open through the Nth scan line GateN, so that the end edge of the pulse transmitted in the N+1th scan line GateN+1 can be steeper or closer to the ideal target during the reverse scanning process.
  • This can improve the deformation of the pulse end edge of the scanning signal during the transmission process, which not only reduces the risk of charging errors, but also increases the charging time or is conducive to achieving higher frequency display.
  • the display device provided in this embodiment can also be applied to the forward scanning or reverse scanning driving mode.
  • the above-mentioned display device can be but is not limited to a liquid crystal display device, and can also be a self-luminous display device, for example, an organic light emitting diode display device, a mini light emitting diode display device, a micro light emitting diode display device or a quantum dot light emitting diode display device.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
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Abstract

公开了一种显示面板及显示装置。一种显示面板包括多条扫描线和位于显示区中的多组波形整理单元（20），这可以改善扫描信号的脉冲结束沿在传输过程中的形变，不仅减低了充电错误的风险，还提高了充电时间或者有利于实现更高频显示。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
随着显示技术的飞速发展，人们对产品形态的需求也多样化。为了给客户更完美的使用体验，提高分辨率是显示面板发展的重要方向。
然而，随着分辨率的不断增大，信号波形在传输过程中也随之发生变化，这会导致显示异常。
 发明概述
本申请提供一种显示面板及显示装置，以缓解扫描信号的脉冲结束沿在传输过程中变化较大的技术问题。
第一方面，本申请提供一种显示面板，该显示面板设置有显示区和非显示区，显示面板包括多条扫描线和位于显示区中的多组波形整理单元，多条扫描线包括依次排列的第N-1条扫描线、第N条扫描线以及第N+1条扫描线；其中，第N组中的每个波形整理单元包括第一晶体管和第二晶体管，第一晶体管的栅极与第N条扫描线连接，第一晶体管的第一极与第N-1条扫描线连接，第一晶体管的第二极与第一电位传输线连接；第二晶体管的栅极与第N条扫描线连接，第一晶体管的第一极与第N+1条扫描线连接，第一晶体管的第二极与第二电位传输线连接。
第二方面，本申请提供一种显示装置，该显示装置包括上述至少一实施方式中的显示面板，显示面板还包括分别位于显示区对侧的两个栅极驱动电路，每一扫描线的两端分别与一栅极驱动电路中对应的栅极驱动单元连接。
 附图说明
图1为相关技术中显示面板的结构示意图。
图2为本申请实施例提供的显示面板的第一种结构示意图。
图3为本申请实施例提供的显示面板的第二种结构示意图。
图4为本申请实施例提供的显示面板的第三种结构示意图。
图5为本申请实施例提供的显示面板的第四种结构示意图。
图6为本申请实施例提供的显示面板的第五种结构示意图。
图7为本申请实施例提供的显示面板的效果改善示意图。
图8为本申请实施例提供的正向扫描的时序示意图。
图9为本申请实施例提供的反向扫描的时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
图1为相关技术中显示面板的结构示意图，该显示面板包括多条扫描线、多条数据线以及子像素（Pixel）。每条扫描线与对应的一行子像素连接，例如，第N-1条扫描线GateN-1与第N-1行子像素连接，第N条扫描线GateN与第N行子像素连接，第N+1条扫描线GateN+1与第N+1行子像素连接。每条数据线与对应的一列子像素连接，例如，数据线datar与一列的红色子像素（R）连接，数据线datag与一列的绿色子像素（G）连接，数据线datab与一列的蓝色子像素（B）连接。
另外，为了各子像素的开口率一致，还在对应数据线的一侧设置了虚拟走线，例如，在数据线datar的左侧设置了虚拟走线dummy1，在数据线datag的左侧设置了虚拟走线dummy2，在数据线datab的左侧设置了虚拟走线dummy3。
有鉴于扫描信号的脉冲结束沿在传输过程中变化较大的技术问题，本实施例提供了一种显示面板，请参阅图2至图9，如图2所示，该显示面板设置有显示区和非显示区，显示面板包括多条扫描线和位于显示区中的多组波形整理单元20，多条扫描线包括依次排列的第N-1条扫描线GateN-1、第N条扫描线GateN以及第N+1条扫描线GateN+1；其中，第N组中的每个波形整理单元20包括第一晶体管NTA和第二晶体管NTB，第一晶体管NTA的栅极与第N条扫描线GateN连接，第一晶体管NTA的第一极与第N-1条扫描线GateN-1连接，第一晶体管NTA的第二极与第一电位传输线连接；第二晶体管NTB的栅极与第N条扫描线GateN连接，第一晶体管NTA的第一极与第N+1条扫描线GateN+1连接，第一晶体管NTA的第二极与第二电位传输线连接。
可以理解的是，本实施例提供的显示面板，通过第N条扫描线GateN控制第一晶体管NTA打开可以在正向扫描过程中使得第N-1条扫描线GateN-1中传输的脉冲结束沿更为陡峭或者更接近理想目标，或者，通过第N条扫描线GateN控制第二晶体管NTB打开可以在反向扫描过程中使得第N+1条扫描线GateN+1中传输的脉冲结束沿更为陡峭或者更接近理想目标，这可以改善扫描信号的脉冲结束沿在传输过程中的形变，不仅减低了充电错误的风险，还提高了充电时间或者有利于实现更高频显示。
又，由于既可以在正向扫描过程中改善扫描信号的脉冲结束沿，又可以在反向扫描过程中改善扫描信号的脉冲结束沿，本实施例提供的显示面板能够适用于正向扫描或者反向扫描的驱动方式。
需要进行说明的是，第一极可以为源极或者漏极中的一个，第二极可以为源极或者漏极中的另一个。例如，第一极为源极时，第二极为漏极；或者，第一极为漏极时，第二极为源极。
每条扫描线配置对应一组的波形整理单元20，例如，第N条扫描线GateN配置第N组的波形整理单元20。每组波形整理单元20可以包括一个或者多个波形整理单元20。
需要进行说明的是，第一晶体管NTA、第二晶体管NTB中的至少一个可以为低温多晶硅（LTPS）薄膜晶体管、非晶硅（a_Si）薄膜晶体管、铟镓锌氧化物（IGZO）薄膜晶体管、或LTPS&IGZO等杂化型薄膜晶体管。
正向扫描如图8所示，第N-1条扫描线GateN-1中传输的扫描信号Gaten-1的脉冲、第N条扫描线GateN中传输的扫描信号Gaten的脉冲、以及第N+1条扫描线GateN+1中传输的扫描信号Gaten+1的脉冲先后依次到来，对应先后依次打开第N-1行子像素、第N行子像素、以及第N+1行子像素，以分别写入对应的数据信号。
其中，为了达到更好的下拉效果，扫描信号Gaten的脉冲上升沿与扫描信号Gaten-1的下降沿发生于同一时刻，或者，两者之间的时间间隔为0us。这样在时间段T2的开始时刻，扫描信号Gaten为高电位，第N组的波形整理单元20中第一晶体管NTA导通或者打开，可以在时间段T1的结束时刻将扫描信号Gaten-1的下降沿下拉为低电平；同理，在时间段T3的开始时刻，扫描信号Gaten+1为高电位，第N+1组的波形整理单元20中第一晶体管NTA导通或者打开，可以在时间段T2的结束时刻将扫描信号Gaten的下降沿下拉为低电平。这样使得每个扫描信号的脉冲结束沿更为陡峭或者更接近理想目标。
反向扫描如图9所示，第N+1条扫描线GateN+1中传输的扫描信号Gaten+1的脉冲、第N条扫描线GateN中传输的扫描信号Gaten的脉冲、以及第N-1条扫描线GateN-1中传输的扫描信号Gaten-1的脉冲先后依次到来，对应先后依次打开第N+1行子像素、第N行子像素、以及第N-1行子像素，以分别写入对应的数据信号。
其中，为了达到更好的下拉效果，扫描信号Gaten的脉冲上升沿与扫描信号Gaten+1的下降沿发生于同一时刻，或者，两者之间的时间间隔为0us。这样在时间段T2的开始时刻，扫描信号Gaten为高电位，第N组的波形整理单元20中第二晶体管NTB导通或者打开，可以在时间段T1的结束时刻将扫描信号Gaten+1的下降沿下拉为低电平；同理，在时间段T3的开始时刻，扫描信号Gaten-1为高电位，第N-1组的波形整理单元20中第二晶体管NTB导通或者打开，可以在时间段T2的结束时刻将扫描信号Gaten的下降沿下拉为低电平。同样能够使得每个扫描信号的脉冲结束沿更为陡峭或者更接近理想目标。
如图2所示，当N等于2时，第N-1条扫描线GateN-1可以为与第一行子像素连接的第一条扫描线Gate1，第N条扫描线GateN可以为第二行子像素连接的第二条扫描线Gate2，第N+1条扫描线GateN+1可以为第三行子像素连接的第三条扫描线Gate3，第N+2条扫描线可以为第四行子像素连接的第四条扫描线Gate4。假设一个显示面板中仅有四行子像素的话，扫描线Gate0、扫描线Gate5可以分别为一条虚拟扫描线，并不与对应的子像素连接。
在其中一个实施例中，显示面板执行正向扫描时，提供对应的电信号至第一电位传输线，且不提供电信号至第二电位传输线；或者，显示面板执行反向扫描时，提供对应的电信号至第二电位传输线，且不提供电信号至第一电位传输线。
需要进行说明的是，正向扫描时，由第一电位传输线通过各个第一晶体管NTA下拉或者上拉对应扫描信号的结束沿；而第二电位传输线不通过各个第二晶体管NTB下拉或者上拉对应扫描信号的结束沿，也不会影响对应扫描信号的正常传输。
反向扫描时，由第二电位传输线通过各个第二晶体管NTB下拉或者上拉对应扫描信号的结束沿；而第一电位传输线不通过各个第一晶体管NTA下拉或者上拉对应扫描信号的结束沿，也不会影响对应扫描信号的正常传输。
其中，结束沿是指正脉冲的下降沿或者负脉冲的上升沿。
在其中一个实施例中，扫描线传输具有正脉冲的扫描信号时，第一晶体管NTA、第二晶体管NTB均为N沟道型薄膜晶体管，第一电位传输线或者第二电位传输线用于传输低电位信号；或者，扫描线传输具有负脉冲的扫描信号时，第一晶体管NTA、第二晶体管NTB均为P沟道型薄膜晶体管，第一电位传输线或者第二电位传输线用于传输高电位信号。
需要进行说明的是，本实施例中的低电位信号的电位可以为小于或者等于对应扫描信号的低电平，以下拉正脉冲的下降沿。高电位信号的电位可以大于或者等于对应扫描信号的高电平，以上拉负脉冲的上升沿。
在其中一个实施例中，显示区包括在扫描线的延伸方向上依次分布的多个显示子区；在每个显示子区的一部分中，不同组中的多个第一晶体管NTA在扫描线的排列方向上逐列分布；在每个显示子区的另一部分中，不同组中的多个第二晶体管NTB在扫描线的排列方向上逐列分布。
需要进行说明的是，图3所示的区域可以为一个显示子区，该显示子区的左半部分分布着对应的第一晶体管NTA，该显示子区的右半部分分布着对应的第二晶体管NTB。
本实施例不仅可以实现对扫描信号的结束沿的改善的更为理想，还可以差异化配置正向扫描、反向扫描过程中不同的改善效果，有利于适用不同的应用需求。
在其中一个实施例中，如图4所示，显示区包括在扫描线的延伸方向上依次分布的多个显示子区，在每个显示子区中，每组中的一个波形整理单元20在扫描线的排列方向上逐列分布。
需要进行说明的是，每组中的一个波形整理单元20在扫描线的排列方向上逐列分布是指：栅极与第N-1条扫描线GateN-1连接的第一晶体管NTA、第二晶体管NTB位于左边的一列，栅极与第N条扫描线GateN连接的第一晶体管NTA、第二晶体管NTB位于中间的一列，栅极与第N+1条扫描线GateN+1连接的第一晶体管NTA、第二晶体管NTB位于右边的一列。
在其中一个实施例中，如图4所示，在每个波形整理单元20中，第一晶体管NTA、第二晶体管NTB相邻分布。
需要进行说明的是，在每个波形整理单元20中第一晶体管NTA、第二晶体管NTB相邻分布是指：在扫描线的延伸方向上，每个波形整理单元20中第一晶体管NTA、第二晶体管NTB之间没有其他的第一晶体管NTA或者第二晶体管NTB。
本实施例在没有增加面内走线的情况下，通过连续利用各虚拟走线（dummy）作为第一电位传输线或者第二电位传输线，实现了波形整理单元20在扫描线的延伸方向上相邻放置，这使得正向扫描、反向扫描过程中对扫描信号的结束沿的改善效果不会存在明显差异，也能够适用更多应用场景的需求。
在其中一个实施例中，如图5、图6所示，显示区包括在扫描线的延伸方向上依次分布的多个显示子区，在每个显示子区中，每组中的一个波形整理单元20在扫描线的排列方向上隔列分布。
需要进行说明的是，每组中的一个波形整理单元20在扫描线的排列方向上隔列分布是指：栅极与第N-1条扫描线GateN-1连接的第一晶体管NTA、第二晶体管NTB位于左列，栅极与第N条扫描线GateN连接的第一晶体管NTA、第二晶体管NTB位于中列，栅极与第N+1条扫描线GateN+1连接的第一晶体管NTA、第二晶体管NTB位于右列，如图5所示，左列与中列之间、中列与右列之间均存在两列没有放置波形整理单元20的情况；或者，如图6所示，左列与中列之间、中列与右列之间均存在一列没有放置波形整理单元20的情况。
在其中一个实施例中，如图5所示，在每个波形整理单元20中，第一晶体管NTA与第二晶体管NTB之间具有一条数据线。
需要进行说明的是，在每个波形整理单元20中第一晶体管NTA与第二晶体管NTB之间具有一条数据线，这说明同一波形整理单元20中的第一晶体管NTA、第二晶体管NTB是相邻分布的，这使得正向扫描、反向扫描过程中对扫描信号的结束沿的改善效果不会存在明显差异，同时，由于没有如图3、图4所示的连续利用虚拟走线，也降低了这些虚拟走线的布线难度。
在其中一个实施例中，如图6所示，在每个波形整理单元20中，第一晶体管NTA、第二晶体管NTB隔列分布；或者，第一晶体管NTA与第二晶体管NTB之间具有多条数据线。
需要进行说明的是，在每个波形整理单元20中，第一晶体管NTA、第二晶体管NTB隔列分布；或者，第一晶体管NTA与第二晶体管NTB之间具有多条数据线，这说明同一波形整理单元20中的第一晶体管NTA、第二晶体管NTB是不相邻分布的，这使得正向扫描、反向扫描过程中对扫描信号的结束沿的改善效果不会存在明显差异，同时，由于更为分散地利用虚拟走线，进一步降低了这些虚拟走线的布线难度。
另外，在图3至图6中，以第一晶体管NTA、第二晶体管NTB均为N沟道型薄膜晶体管为例，第一电位传输线用于传输第一低电位信号VGL，该第一低电位信号VGL的电位可以小于或者等于对应扫描信号的低电平；第二电位传输线用于传输第二低电位信号VGL2，该第二低电位信号VGL2的电位可以小于或者等于对应扫描信号的低电平。
其中，数据线datar可以与对应一列的红色子像素（R）连接，数据线datag可以与对应一列的绿色子像素（G）连接，数据线datab可以与对应一列的蓝色子像素（B）连接。
为了保持各子像素的开口率的一致和不增加新的布线，可以利用虚拟走线（dummy）作为触控走线（TP）、第一电位传输线、或者第二电位传输线。
在第N-1组的波形整理单元20中，第一晶体管NTA的第一极与第N-2条扫描线GateN-2连接，第一晶体管NTA的栅极与第N-1条扫描线GateN-1连接，第一晶体管NTA的第二极与对应的一第一电位传输线连接；第二晶体管NTB的第一极与第N条扫描线GateN连接，第二晶体管NTB的栅极与第N-1条扫描线GateN-1连接，第二晶体管NTB的第二极与对应的一第二电位传输线连接。
在第N+1组的波形整理单元20中，第一晶体管NTA的第一极与第N条扫描线GateN连接，第一晶体管NTA的栅极与第N+1条扫描线GateN+1连接，第一晶体管NTA的第二极与对应的一第一电位传输线连接；第二晶体管NTB的第一极与第N+2条扫描线GateN+2连接，第二晶体管NTB的栅极与第N+1条扫描线GateN+1连接，第二晶体管NTB的第二极与对应的一第二电位传输线连接。
综上，上述各实施例可以实现正向驱动扫描时面内扫描信号的结束沿的改善，也可以实现反向驱动扫描时面内扫描信号的结束沿的改善，由于可分别满足正向、反向驱动扫描时面内扫描信号的结束沿的改善，各实施例的应用可以实现超宽屏的安装方式自由化。
如图2、图7所示，为了提高扫描信号的驱动能力，针对超宽屏，构建了两个栅极驱动电路100（GOA电路），两个栅极驱动电路100分别位于显示区的对侧，同于提供对应数据信号的数据驱动芯片300位于下边框区。
正向扫描时，从第一条扫描线（Gate1）至最后一条扫描线（GateM）依次分别打开第一行子像素至最后一行子像素；反向扫描时，从最后一条扫描线（GateM）至第一条扫描线（Gate1）依次分别打开最后一行子像素至第一行子像素。
将显示区简单分为A区、B区、C区、D区四个区域，其中A区、B区两个区域靠近栅极驱动电路100，且左右对称；C区、D区远离栅极驱动电路100，同时也是对称的。根据图7中未进行面内下拉的第一行波形与进行了面内下拉的第二行波形的对比可知，超宽屏经过面内下拉之后，不仅各区中扫描信号的下降沿变得更为接近理想目标，而且A区、B区中扫描信号的下降沿比C区、D区中扫描信号的下降沿更为陡峭即改善的更为理想。
在其中一个实施例中，本实施例提供一种显示装置，该显示装置包括上述至少一实施例中的显示面板，如图2、图7所示，显示面板还包括分别位于显示区对侧的两个栅极驱动电路100，每一扫描线的两端分别与一栅极驱动电路100中对应的栅极驱动单元连接。
可以理解的是，由于本实施例提供的显示装置包括了上述至少一实施例中的显示面板，同样能够通过第N条扫描线GateN控制第一晶体管NTA打开可以在正向扫描过程中使得第N-1条扫描线GateN-1中传输的脉冲结束沿更为陡峭或者更接近理想目标，或者，通过第N条扫描线GateN控制第二晶体管NTB打开可以在反向扫描过程中使得第N+1条扫描线GateN+1中传输的脉冲结束沿更为陡峭或者更接近理想目标，这可以改善扫描信号的脉冲结束沿在传输过程中的形变，不仅减低了充电错误的风险，还提高了充电时间或者有利于实现更高频显示。
又，由于既可以在正向扫描过程中改善扫描信号的脉冲结束沿，又可以在反向扫描过程中改善扫描信号的脉冲结束沿，本实施例提供的显示装置也同样能够适用于正向扫描或者反向扫描的驱动方式。
需要进行说明的是，上述显示装置可以但不限于为液晶显示装置，也可以为自发光型显示装置，例如，有机发光二极管显示装置、迷你发光二极管显示装置、微发光二极管显示装置或者量子点发光二极管显示装置。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板设置有显示区和非显示区，所述显示面板包括：
    多条扫描线，所述多条扫描线包括依次排列的第N-1条扫描线、第N条扫描线以及第N+1条扫描线；
    位于所述显示区中的多组波形整理单元，其中，第N组中的每个所述波形整理单元包括：
    第一晶体管，所述第一晶体管的栅极与所述第N条扫描线连接，所述第一晶体管的第一极与所述第N-1条扫描线连接，所述第一晶体管的第二极与第一电位传输线连接；
    第二晶体管，所述第二晶体管的栅极与所述第N条扫描线连接，所述第一晶体管的第一极与所述第N+1条扫描线连接，所述第一晶体管的第二极与第二电位传输线连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板执行正向扫描时，提供对应的电信号至所述第一电位传输线，且不提供电信号至所述第二电位传输线；或者，所述显示面板执行反向扫描时，提供对应的电信号至所述第二电位传输线，且不提供电信号至所述第一电位传输线。
  3. 根据权利要求2所述的显示面板，其中，所述扫描线传输具有正脉冲的扫描信号时，所述第一晶体管、所述第二晶体管均为N沟道型薄膜晶体管，所述第一电位传输线或者所述第二电位传输线用于传输低电位信号；或者，所述扫描线传输具有负脉冲的扫描信号时，所述第一晶体管、所述第二晶体管均为P沟道型薄膜晶体管，所述第一电位传输线或者所述第二电位传输线用于传输高电位信号。
  4. 根据权利要求1所述的显示面板，其中，所述显示区包括在所述扫描线的延伸方向上依次分布的多个显示子区；在每个所述显示子区的一部分中，不同组中的多个第一晶体管在所述扫描线的排列方向上逐列分布；在每个所述显示子区的另一部分中，不同组中的多个第二晶体管在所述扫描线的排列方向上逐列分布。
  5. 根据权利要求1所述的显示面板，其中，所述显示区包括在所述扫描线的延伸方向上依次分布的多个显示子区，在每个所述显示子区中，每组中的一个波形整理单元在所述扫描线的排列方向上逐列分布。
  6. 根据权利要求5所述的显示面板，其中，在每个所述波形整理单元中，第一晶体管、第二晶体管相邻分布。
  7. 根据权利要求1所述的显示面板，其中，所述显示区包括在所述扫描线的延伸方向上依次分布的多个显示子区，在每个所述显示子区中，每组中的一个波形整理单元在所述扫描线的排列方向上隔列分布。
  8. 根据权利要求7所述的显示面板，其中，在每个所述波形整理单元中，第一晶体管与第二晶体管之间具有一条数据线。
  9. 根据权利要求7所述的显示面板，其中，在每个所述波形整理单元中，第一晶体管、第二晶体管隔列分布；或者，第一晶体管与第二晶体管之间具有多条数据线。
  10. 一种显示装置，其中，所述显示装置包括如权利要求1所述的显示面板，所述显示面板还包括分别位于所述显示区对侧的两个栅极驱动电路，每一扫描线的两端分别与一栅极驱动电路中对应的栅极驱动单元连接。
  11. 根据权利要求10所述的显示装置，其中，所述显示面板执行正向扫描时，提供对应的电信号至所述第一电位传输线，且不提供电信号至所述第二电位传输线；或者，所述显示面板执行反向扫描时，提供对应的电信号至所述第二电位传输线，且不提供电信号至所述第一电位传输线。
  12. 根据权利要求11所述的显示装置，其中，所述扫描线传输具有正脉冲的扫描信号时，所述第一晶体管、所述第二晶体管均为N沟道型薄膜晶体管，所述第一电位传输线或者所述第二电位传输线用于传输低电位信号；或者，所述扫描线传输具有负脉冲的扫描信号时，所述第一晶体管、所述第二晶体管均为P沟道型薄膜晶体管，所述第一电位传输线或者所述第二电位传输线用于传输高电位信号。
  13. 根据权利要求10所述的显示装置，其中，所述显示区包括在所述扫描线的延伸方向上依次分布的多个显示子区；在每个所述显示子区的一部分中，不同组中的多个第一晶体管在所述扫描线的排列方向上逐列分布；在每个所述显示子区的另一部分中，不同组中的多个第二晶体管在所述扫描线的排列方向上逐列分布。
  14. 根据权利要求10所述的显示装置，其中，所述显示区包括在所述扫描线的延伸方向上依次分布的多个显示子区，在每个所述显示子区中，每组中的一个波形整理单元在所述扫描线的排列方向上逐列分布。
  15. 根据权利要求14所述的显示装置，其中，在每个所述波形整理单元中，第一晶体管、第二晶体管相邻分布。
  16. 根据权利要求10所述的显示装置，其中，所述显示区包括在所述扫描线的延伸方向上依次分布的多个显示子区，在每个所述显示子区中，每组中的一个波形整理单元在所述扫描线的排列方向上隔列分布。
  17. 根据权利要求16所述的显示装置，其中，在每个所述波形整理单元中，第一晶体管与第二晶体管之间具有一条数据线。
  18. 根据权利要求16所述的显示装置，其中，在每个所述波形整理单元中，第一晶体管、第二晶体管隔列分布；或者，第一晶体管与第二晶体管之间具有多条数据线。
  19. 根据权利要求10所述的显示装置，其中，所述显示装置为液晶显示装置或者自发光型显示装置。
  20. 根据权利要求10所述的显示装置，其中，所述第一晶体管、所述第二晶体管中的至少一个为低温多晶硅薄膜晶体管、非晶硅薄膜晶体管、或者铟镓锌氧化物薄膜晶体管。
PCT/CN2023/132653 2022-12-20 2023-11-20 显示面板及显示装置 WO2024131410A1 (zh)

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