WO2024124566A1 - 阵列基板及其制备方法、显示面板、显示装置 - Google Patents

阵列基板及其制备方法、显示面板、显示装置 Download PDF

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Publication number
WO2024124566A1
WO2024124566A1 PCT/CN2022/139736 CN2022139736W WO2024124566A1 WO 2024124566 A1 WO2024124566 A1 WO 2024124566A1 CN 2022139736 W CN2022139736 W CN 2022139736W WO 2024124566 A1 WO2024124566 A1 WO 2024124566A1
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Prior art keywords
layer
base substrate
electrode
gate
organic
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PCT/CN2022/139736
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English (en)
French (fr)
Inventor
袁广才
胡合合
谢昌翰
杨维
董立文
贺家煜
侯东飞
张震
谷新
宁策
李正亮
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京东方科技集团股份有限公司
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Priority to PCT/CN2022/139736 priority Critical patent/WO2024124566A1/zh
Publication of WO2024124566A1 publication Critical patent/WO2024124566A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device.
  • Flexible display devices are favored by consumers due to their good flexibility, light volume, low power consumption, and rubbing resistance.
  • Flexible OLED (Organic Electroluminescence Display) display devices are relatively mature, but flexible LCD (Liquid Crystal Display) devices have not yet been mass-produced.
  • the purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and to provide an array substrate and a preparation method thereof, a display panel, and a display device.
  • an array substrate comprising:
  • a first electrode layer disposed on one side of the base substrate, the first electrode layer comprising a first electrode
  • a first conductive layer is provided on a side of the first electrode layer away from the base substrate, the first conductive layer comprises a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode, and an orthographic projection of the drain electrode on the base substrate overlaps with an orthographic projection of the first electrode layer on the base substrate;
  • an organic planarization layer comprising a plurality of organic planarization portions arranged at intervals, wherein the organic planarization portions are at least arranged in the first gap, and the organic planarization portions at least do not cover ends of the source electrode and the drain electrode away from the first gap, and an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer;
  • the organic active layer is disposed on a side of the organic planarization layer away from the base substrate, and the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap.
  • a distance between a side of the organic planar portion facing away from the base substrate and the base substrate is greater than or equal to a distance between a side of the first conductive layer facing away from the base substrate and the base substrate.
  • a portion of the organic flat portion is disposed on a side of the first conductive layer facing away from the base substrate, and at a position close to the first gap, an orthographic projection of the organic flat portion on the base substrate overlaps with an orthographic projection of the source electrode on the base substrate, and an orthographic projection of the organic flat portion on the base substrate overlaps with an orthographic projection of the drain electrode on the base substrate.
  • an angle between a side wall of the organic planar portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is less than or equal to 70°.
  • a distance between a side of the organic flat portion facing away from the base substrate and the first conductive layer is smaller than a thickness of the first conductive layer in a third direction, and the third direction is perpendicular to a side of the base substrate close to the first electrode layer.
  • a surface of the organic flat portion facing away from the base substrate is connected to a side wall of the organic flat portion via a curved surface.
  • the first conductive layer further includes a data line, the data line is connected to the source electrode, and the first electrode layer further includes:
  • the resistance-reducing connection portion is spaced apart from the first electrode, and the orthographic projections of the source electrode and the data line on the base substrate are located within the orthographic projection of the resistance-reducing connection portion on the base substrate.
  • the array substrate further includes:
  • a gate insulating layer group is provided on a side of the organic active layer away from the base substrate, and an orthographic projection of the gate insulating layer group on the base substrate coincides with an orthographic projection of the organic active layer on the base substrate;
  • the gate layer is arranged on a side of the gate insulating layer group away from the base substrate, the gate layer comprises a gate, and the orthographic projection of the gate on the base substrate coincides with the orthographic projection of the organic active layer on the base substrate.
  • the gate insulating layer group includes:
  • a first gate insulating layer is provided on a side of the organic active layer away from the base substrate;
  • the second gate insulating layer is disposed on a side of the first gate insulating layer away from the base substrate, and the second gate insulating layer has a stronger barrier performance to the etching liquid of the gate layer than the first gate insulating layer.
  • the array substrate further includes:
  • a passivation layer is provided on a side of the gate layer away from the substrate;
  • the second electrode layer is arranged on the side of the passivation layer away from the base substrate, and the second electrode layer includes a second electrode and a gate connecting portion which are arranged at intervals, and the gate connecting portion is connected to two adjacent gates.
  • the gate layer further includes:
  • a gate extension portion is connected to at least one side of a first direction of the gate, and the first direction is parallel to a side of the array substrate close to the first electrode layer.
  • the array substrate further includes:
  • a passivation layer is provided on a side of the gate layer away from the substrate;
  • the second electrode layer is arranged on a side of the passivation layer away from the base substrate, and the second electrode layer comprises a second electrode and a gate connecting portion which are arranged at intervals, and the gate connecting portion is connected to two adjacent gate extension portions.
  • the array substrate further includes:
  • the conductive enhancement layer is arranged on a side of the second electrode layer away from the base substrate, and the orthographic projection of the conductive enhancement layer on the base substrate is located within the orthographic projection of the gate connection portion on the base substrate.
  • the array substrate further includes:
  • a light shielding layer is provided on one side of the base substrate, and the orthographic projection of the organic active layer on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate;
  • a second planarization layer disposed on a side of the light shielding layer away from the base substrate, the first electrode layer disposed on a side of the second planarization layer away from the base substrate, and a third via hole disposed on the second planarization layer;
  • a passivation layer is provided on a side of the gate layer away from the base substrate, and a first via hole and a second via hole are provided on the passivation layer, wherein the first via hole is connected to the gate, and the second via hole is connected to the third via hole and connected to the light shielding layer;
  • the second electrode layer is arranged on the side of the passivation layer away from the base substrate, and the second electrode layer includes a second electrode and a gate connecting portion arranged at intervals.
  • the gate connecting portion is connected to the gate through the first via hole, and is connected to the shading layer through the second via hole and the third via hole.
  • the shading layer is multiplexed as a gate line and a second gate.
  • the array substrate further includes:
  • the protective layer at least covers the side wall of the organic active layer.
  • the protective layer is arranged between the gate layer and the first electrode and the passivation layer, and covers the organic active layer, the gate insulation layer group and the side wall of the gate, and the matching between the protective layer and the organic active layer is stronger than the matching between the passivation layer and the organic active layer.
  • a work function of the first conductive layer is greater than 4.5 eV.
  • the array substrate is a flexible array substrate.
  • a method for preparing an array substrate comprising:
  • a first electrode layer and a first conductive layer are sequentially stacked on one side of the base substrate, wherein the first electrode layer includes a first electrode, the first conductive layer includes a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode, and an orthographic projection of the drain electrode on the base substrate overlaps with an orthographic projection of the first electrode layer on the base substrate;
  • the organic planarization layer comprises a plurality of organic planarization portions arranged at intervals, and the organic planarization portions are arranged at least in the first gap;
  • the organic flat portion at least does not cover the ends of the source and the drain away from the first gap, and the angle between the side wall of the organic flat portion close to the first gap and a side of the first conductive layer close to the organic planarization layer is smaller than the angle between the side wall of the first conductive layer close to the first gap and a side of the first electrode layer close to the first conductive layer.
  • a gate insulating layer group and a gate layer are formed simultaneously with forming an organic active layer on a side of the organic planarization layer facing away from the base substrate.
  • a gate insulating layer group and a gate layer are formed while an organic active layer is formed on a side of the organic planarization layer away from the base substrate, including:
  • the gate insulating material layer group and the organic active material layer are patterned by using the gate layer as a mask to form the gate insulating layer group and the organic active layer.
  • a first electrode layer and a first conductive layer stacked in sequence are formed on one side of the base substrate, including:
  • a first electrode material layer and a first conductive material layer are sequentially formed on one side of the base substrate.
  • the mask pattern comprises a first portion and a second portion, the thickness of the first portion is greater than the thickness of the second portion, the first portion is arranged opposite to the first conductive layer and a portion of the first electrode layer, and the second portion is arranged opposite to another portion of the first electrode layer;
  • the remaining first conductive material layer is patterned to form the first conductive layer.
  • the preparation method further comprises:
  • a passivation layer is formed on a side of the gate layer facing away from the substrate, and the passivation layer is patterned to form a first via hole.
  • the preparation method further comprises:
  • a protection layer and a passivation layer are sequentially formed on a side of the gate layer away from the base substrate, and the passivation layer is patterned to form a first via hole, and the protection layer is patterned to form a fourth via hole.
  • the preparation method further comprises:
  • a protective layer and a passivation layer are sequentially formed on the side of the gate layer facing away from the base substrate, and the passivation layer is patterned to form a first via and a second via, and the protective layer is patterned to form a fourth via and a fifth via at the same time, and the second planarization layer is patterned to form a third via at the same time, the fourth via is connected to the first via, and the fifth via is connected to the second via and the third via.
  • the preparation method further comprises:
  • a second electrode material layer is formed on a side of the passivation layer away from the substrate, and the second electrode material layer is patterned to form a second electrode layer.
  • the preparation method further comprises:
  • a second electrode material layer and a conductive enhancement material layer are sequentially formed on a side of the passivation layer away from the substrate, and the conductive enhancement material layer and the second electrode material layer are patterned to form a conductive enhancement layer and a second electrode layer.
  • a display panel comprising:
  • An array substrate is any one of the array substrates described above;
  • a color filter substrate arranged opposite to the array substrate
  • the liquid crystal layer is arranged between the array substrate and the color filter substrate.
  • the array substrate is a flexible array substrate
  • the color filter substrate is a flexible color filter substrate
  • a display device comprising: a display panel as described in any one of the above, wherein the display device is a roll-up display device, a foldable display device or a curved display device.
  • FIG. 1 is a schematic structural diagram of a first exemplary embodiment of an array substrate disclosed in the present invention.
  • FIG. 2 is a schematic structural diagram of the light shielding layer in FIG. 1 .
  • FIG. 3 is a schematic structural diagram after a first electrode layer and a first conductive layer are formed on the basis of FIG. 2 .
  • FIG. 4 is a schematic diagram of a structure after an organic planarization layer is formed on the basis of FIG. 3 .
  • FIG. 5 is a schematic structural diagram after an organic active layer, a gate insulating layer group and a gate layer are formed on the basis of FIG. 4 .
  • FIG. 6 is a schematic structural diagram of the organic active layer, the gate insulating layer group and the gate layer in FIG. 5 .
  • FIG. 7 is a schematic structural diagram after a second electrode layer is formed on the basis of FIG. 5 .
  • FIG. 8 is a schematic structural diagram of the second electrode layer in FIG. 7 .
  • Fig. 9 is a cross-sectional schematic diagram after cutting along the line B-B in Fig. 7 .
  • FIG. 10 is a schematic structural diagram of a second exemplary embodiment of an array substrate disclosed in the present invention.
  • FIG. 11 is a schematic structural diagram of a third exemplary embodiment of an array substrate disclosed in the present invention.
  • FIG. 12 is a schematic structural diagram of another exemplary embodiment after an organic active layer, a gate insulating layer group and a gate layer are formed on the basis of FIG. 4 .
  • FIG. 13 is a schematic structural diagram of the organic active layer, the gate insulating layer group and the gate layer in FIG. 12 .
  • FIG. 14 is a schematic diagram of the structure after a second electrode layer is formed on the basis of FIG. 12 .
  • FIG. 15 is a schematic structural diagram of the second electrode layer in FIG. 14 .
  • FIG16 is a schematic structural diagram of the fourth exemplary embodiment of the array substrate disclosed in the present invention cut along the B-B section in FIG7 or FIG14 .
  • FIG17 is a schematic structural diagram of the fourth exemplary embodiment of the array substrate disclosed in the present invention cut along the A-A section in FIG7 or FIG14 .
  • FIG18 is a schematic structural diagram of the fifth exemplary embodiment of the array substrate disclosed in the present invention cut along the A-A section in FIG7 or FIG14 .
  • FIG19 is a schematic structural diagram of the fifth exemplary embodiment of the array substrate disclosed in the present invention cut along the B-B section in FIG7 or FIG14 .
  • FIG. 20 is a schematic structural diagram of a sixth exemplary embodiment of an array substrate according to the present disclosure.
  • FIG. 21 is a schematic flow chart of an exemplary embodiment of a method for preparing an array substrate according to the present invention.
  • 22 to 40 are schematic structural diagrams of the various steps of the method for preparing the array substrate disclosed herein.
  • Base substrate 21. First planarization layer; 22. Second planarization layer; 221. Third via hole;
  • Organic active material layer 7. Organic active layer;
  • gate insulating layer group 810. first gate insulating material layer; 81. first gate insulating layer; 820. second gate insulating material layer; 82. second gate insulating layer;
  • X first direction
  • Y second direction
  • Z third direction
  • Fig. 1 is a cross-sectional schematic diagram cut along A-A in Fig. 7; since the organic active layer 7, the gate insulating layer group 8 and the gate layer 9 are formed by the same patterning process, only the top gate layer 9 is shown in Figs. 5, 12 and 37.
  • Figs. 2 to 8 and 12 to 15 In order to show the connection relationship of the gate, Figs. 2 to 8 and 12 to 15 only show the specific structure of a complete sub-pixel and the data line of another adjacent sub-pixel, part of the gate and part of the light shielding layer.
  • Fig. 20 is a cross-sectional schematic diagram cut along C-C in Fig. 40. In Fig. 40, in order to avoid the second electrode 111 blocking the lower layer, the second electrode 111 is omitted, and only the gate connection portion 112 is drawn.
  • the array substrate may include a base substrate 1, a first electrode layer 4, a first conductive layer 5, an organic planarization layer 6, and an organic active layer 7;
  • the first electrode layer 4 is arranged on one side of the base substrate 1, and the first electrode layer 4 includes a first electrode 41;
  • the first conductive layer 5 is arranged on the side of the first electrode layer 4 away from the base substrate 1, and the first conductive layer 5 includes a source electrode 51 and a drain electrode 52, a first gap 54 is arranged between the source electrode 51 and the drain electrode 52, and the orthographic projection of the drain electrode 52 on the base substrate 1 overlaps with the orthographic projection of the first electrode layer 4 on the base substrate 1;
  • the organic planarization layer 6 may include a plurality of organic planar portions 61 arranged at intervals The organic flat portion 61 is at least arranged in the first gap 54, and the organic flat portion 61 at least does not cover the ends of the source electrode 51 and the drain electrode 52 away from the first gap 54, and the angle between the side wall of the organic flat portion
  • the angle between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle between the side wall of the first conductive layer 5 close to the first gap 54 and the side of the first electrode layer 4 close to the first conductive layer 5, and the organic active layer 7 will not generate a gap on the side wall of the organic planarization layer 6, and will not be broken due to the gap.
  • the organic flat portion 61 is at least arranged in the first gap 54, and the distance between the side of the organic flat portion 61 facing away from the base substrate 1 and the base substrate 1 is greater than or equal to the distance between the side of the first conductive layer 5 facing away from the base substrate 1 and the base substrate 1, so that the organic flat portion 61 can block the corner of the source 51 and the drain 52 close to the first gap 54, and avoid the sharp corner formed by the corner of the source 51 and the drain 52 close to the first gap 54 so that the organic active layer 7 cannot cover it, that is, the organic active layer 7 can well cover the organic flat portion 61 and the first conductive layer 5, and achieve a better conductive effect.
  • the array substrate uses an organic active layer 7 and an organic planarization layer 6, and the overall process temperature is less than 100° C., so that the array substrate has sufficient flexibility and can be used in a flexible display panel.
  • the array substrate is a flexible array substrate. Therefore, the base substrate 1 is a flexible substrate.
  • the material of the base substrate 1 is a flexible material.
  • the material of the base substrate 1 can be a resin material such as triacetate film, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.
  • the base substrate 1 can be formed by multiple layers of material layers.
  • the base substrate 1 can include multiple layers of substrate layers, and the material of the substrate layer can be any of the above materials.
  • the base substrate 1 can also be set as a single layer, which can be any of the above materials.
  • the base substrate 1 can be bonded to the peeling substrate through the adhesive layer 12, and the glass substrate 13 can be peeled off when used.
  • the glass substrate 13 can be left intact or not used, and other hard substrates can be used.
  • a plurality of thin film transistors arranged in an array may be disposed on one side of the base substrate 1 .
  • the thin film transistor may at least include a source electrode 41 , a drain electrode 42 , an organic active layer 7 and a first gate electrode 91 .
  • a first planarization layer 21 may be provided on one side of the substrate 1.
  • the material of the first planarization layer 21 has strong adhesion, strong corrosion resistance to chemical solvents, good planarization effect, and high light transmittance.
  • the material of the first planarization layer 21 may be epoxy resin photoresist, such as SU-8 series epoxy resin photoresist.
  • a light shielding layer 3 is provided on the side of the first planarization layer 21 away from the substrate 1. The light incident from the substrate 1 side into the organic active layer 7 will generate photogenerated carriers in the organic active layer 7, thereby having a great impact on the characteristics of the thin film transistor, and ultimately affecting the display quality of the display device.
  • the light shielding layer 3 can shield the light incident from the substrate 1 side, thereby avoiding affecting the characteristics of the thin film transistor and avoiding affecting the display quality of the display device. Depending on the type of thin film transistor, the light shielding layer 3 may be omitted.
  • the light shielding layer 3 may include a plurality of light shielding portions 31 arranged at intervals, and one thin film transistor is provided with one light shielding portion 31.
  • the light shielding layer 3 may include a plurality of strip-shaped light shielding portions 31 extending along a first direction, and one strip-shaped light shielding portion 31 may correspond to a plurality of thin film transistors arranged along the first direction, that is, the organic active layer 7 of the plurality of thin film transistors arranged along the first direction is shielded by one strip-shaped light shielding portion 31.
  • a second planarization layer 22 may be provided on the side of the light shielding layer 3 away from the base substrate 1.
  • the material of the second planarization layer 22 is an insulating material.
  • the second planarization layer 22 can insulate and isolate the light shielding layer 3 from the first conductive layer 5.
  • the material of the second planarization layer 22 has strong adhesion, strong corrosion resistance to chemical solvents, good planarization effect, high light transmission, and low polarity to reduce channel effect and leakage current.
  • the material of the second planarization layer 22 may be epoxy resin photoresist, for example, SU-8 series epoxy resin photoresist.
  • the thickness of the second planarization layer 22 is greater than or equal to 1 micron.
  • a first electrode layer 4 may be provided on the side of the second planarization layer 22 away from the base substrate 1.
  • the first electrode layer 4 may include first electrodes 41 and resistance-reducing connecting portions 42 arranged at intervals.
  • the first electrodes 41 may be pixel electrodes, and therefore, a plurality of first electrodes 41 are arranged at intervals.
  • One sub-pixel is provided with a first electrode 41.
  • the resistance-reducing connecting portion 42 is arranged in a strip shape extending along the second direction.
  • the material of the first electrode layer 4 may be a transparent conductive material, for example, ITO (indium tin oxide), IZO (indium zinc oxide), and the like.
  • a first conductive layer 5 may be provided on a side of the first electrode layer 4 facing away from the base substrate 1, and the first conductive layer 5 may include a data line 53, a source electrode 51, and a drain electrode 52.
  • the data line 53 extends along the second direction Y, and a portion of the data line 53 may be reused as the source electrode 51; or, the data line 53 connects a plurality of source electrodes 51 arranged along the second direction Y, and a data signal may be input to the plurality of source electrodes 51 arranged along the second direction Y through one data line 53.
  • a first gap 54 is provided between the source electrode 51 and the drain electrode 52.
  • the first electrode layer 4 and the first conductive layer 5 are formed by the same patterning process, and the first conductive layer 5 is located above the first electrode layer 4, there must be a first electrode layer 4 between the first conductive layer 5 and the base substrate 1, that is, the area of the first electrode layer 4 is at least the same as the area of the first conductive layer 5, or the area of the first electrode layer 4 is larger than the area of the first conductive layer 5; specifically, the orthographic projection of the drain 52 on the base substrate 1 overlaps with the orthographic projection of the first electrode layer 4 on the base substrate 1, for example, the orthographic projection of the first electrode layer 4 on the base substrate 1 covers the orthographic projection of the drain 52 on the base substrate 1, and the area of the orthographic projection of the first electrode layer 4 on the base substrate 1 is larger than the area of the orthographic projection of the drain 52 on the base substrate 1.
  • the orthographic projections of the source electrode 51 and the data line 53 on the substrate 1 are located within the orthographic projection of the resistance reduction connection portion 42 on the substrate 1.
  • the orthographic projection of the resistance reduction connection portion 42 on the substrate 1 coincides with the orthographic projections of the source electrode 51 and the data line 53 on the substrate 1; or, the orthographic projection of the resistance reduction connection portion 42 on the substrate 1 covers the orthographic projections of the source electrode 51 and the data line 53 on the substrate 1, and the orthographic projection area of the resistance reduction connection portion 42 on the substrate 1 is larger than the orthographic projection area of the source electrode 51 and the data line 53 on the substrate 1.
  • the thickness of the first conductive layer 5 is greater than or equal to 500 angstroms and less than or equal to 8000 angstroms.
  • the thickness of the first conductive layer 5 can be 650 angstroms, 982 angstroms, 1020 angstroms, 1190 angstroms, 1380 angstroms, 1850 angstroms, 2340 angstroms, 2840 angstroms, 3240 angstroms, 3840 angstroms, 4180 angstroms, 4586 angstroms, 5170 angstroms, 5760 angstroms, 6230 angstroms, 6840 angstroms, 7520 angstroms, 7850 angstroms, etc.
  • overlap does not mean complete overlap, but has a certain error.
  • the error range varies depending on the equipment and preparation process. Therefore, within the error range of the equipment and preparation process, it is considered to be overlap.
  • the functions of the "source 41" and the “drain 42" may be interchanged when using thin film transistors with opposite polarities or when the current direction changes during circuit operation. Therefore, in this specification, the "source 41” and the “drain 42" may be interchanged.
  • an organic planarization layer 6 may be provided on the side of the first conductive layer 5 away from the base substrate 1.
  • the material of the organic planarization layer 6 needs to be resistant to chemical solvents to protect the first conductive layer 4. It also has high light transmittance to avoid affecting the light transmittance of the display panel. It also has low polarity. Low polarity means that the dipole in the molecule is small and the charge distribution is relatively uniform. In simple terms, it is relatively symmetrical and generally has few lone pairs of electrons. Low polarity can reduce the induced charge to form polarization, thereby reducing the back channel effect and reducing leakage current.
  • the material of the organic planarization layer 6 may be SU-8 series epoxy photoresist, and other materials with low dielectric constants may also be selected.
  • the organic planarization layer 6 may include a plurality of organic planar portions 61 arranged at intervals, that is, the organic planar portions 61 are arranged as an island structure, and one thin film transistor may include one organic planar portion 61 .
  • the organic flat portion 61 is at least arranged in the first gap 54, and the organic flat portion 61 at least does not cover the ends of the source electrode 51 and the drain electrode 52 away from the first gap 54; such an arrangement enables the source electrode 51 and the drain electrode 52 to ensure connection with the organic active layer 7 even when the area is small, so that the area of the subsequently formed organic active layer 7 is smaller, the area of the thin film transistor is smaller, and the aperture ratio of the entire array substrate and the display panel is increased.
  • the orthographic projection of the organic active layer 7 on the base substrate 1 is located within the orthographic projection of the light shielding layer 3 on the base substrate 1, so that the light shielding layer 3 can play a role in shielding light from reaching the organic active layer 7.
  • the orthographic projection of the organic active layer 7 on the base substrate 1 can overlap with the orthographic projection of the light shielding layer 3 on the base substrate 1, or the orthographic projection of the light shielding layer 3 on the base substrate 1 covers the orthographic projection of the organic active layer 7 on the base substrate 1, and the orthographic projection area of the light shielding layer 3 on the base substrate 1 is larger than the orthographic projection area of the organic active layer 7 on the base substrate 1.
  • the distance between the edge line of the orthographic projection of the light shielding layer 3 on the base substrate 1 and the edge line of the orthographic projection of the organic active layer 7 on the base substrate 1 is greater than or equal to 2 micrometers. Such an arrangement ensures that in the case of errors in the process or equipment, the orthographic projection of the organic active layer 7 on the base substrate 1 can also be located within the orthographic projection of the light shielding layer 3 on the base substrate 1.
  • the organic flat portion 61 is only arranged in the first gap 54, so that the distance between the side of the organic flat portion 61 facing away from the substrate 1 and the substrate 1 is equal to the distance between the side of the first conductive layer 5 facing away from the substrate 1 and the substrate 1, that is, the organic flat portion 61 fills the first gap 54 between the source 51 and the drain 52, and the organic flat portion 61 covers the sharp corners of the corners of the source 51 and the drain 52; so that the subsequently formed organic active layer 7 does not need to climb, and the organic active layer 7 will not form gaps and will not be broken due to the gaps.
  • the organic flat portion 61 is not only arranged in the first gap 54, but also protrudes from the first conductive layer 5, so that the distance between the side of the organic flat portion 61 facing away from the substrate substrate 1 and the substrate substrate 1 is greater than the distance between the side of the first conductive layer 5 facing away from the substrate substrate 1 and the substrate substrate 1.
  • the organic flat portion 61 does not cover the first conductive layer 5.
  • the organic flat portion 61 fills the first gap 54 between the source 51 and the drain 52, and the organic flat portion 61 covers the sharp corners of the corners of the source 51 and the drain 52; so that the subsequently formed organic active layer 7 does not need to climb the side walls of the source 51 and the drain 52, thereby avoiding the appearance of gaps in the organic active layer 7 and not breaking due to the gaps.
  • the distance H1 between the side of the organic flat portion 61 facing away from the base substrate 1 and the first conductive layer 5 is less than the thickness H2 of the first conductive layer 5 in the third direction Z, that is, the height of the organic flat portion 61 protruding from the first conductive layer 5 is less than the thickness of the first conductive layer 5;
  • the third direction Z is perpendicular to the side of the base substrate 1 close to the first electrode layer 4.
  • the thickness of the first conductive layer 54 needs to be set smaller to avoid the climbing height of the organic active layer 77 being too high, and the material of the first conductive layer 54 also needs to be considered to avoid the side wall formed by the first conductive layer 54 being too steep.
  • the slope of the side wall of the first conductive layer 54 is still relatively steep.
  • the angle between the side wall of the first conductive layer 54 close to the first gap 54 and the side of the substrate 11 close to the first conductive layer 54 is generally greater than 70 degrees, and a sharp angle structure is easily formed at the corner position of the first conductive layer 54 away from the substrate 11; the organic active layer 77 formed subsequently will form a gap on the side wall of the first conductive layer 54, and the organic active layer 77 is easily broken due to the gap, resulting in a short circuit; and due to the existence of the sharp angle structure, the organic active layer 77 has poor coverage at the corner position of the first conductive layer 54 away from the substrate 11, which is also easy to cause the organic active layer 77 to break, resulting in a short circuit.
  • an angle ⁇ between the side wall of the organic planarization layer 6 close to the first gap 54 and a side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than an angle ⁇ between the side wall of the first conductive layer 5 close to the first gap 54 and a side of the first electrode layer 4 close to the first conductive layer 5; that is, the inclination angle of the side wall of the organic planarization layer 6 is smaller than the inclination angle of the side wall of the source 51 and the drain 52 of the first conductive layer 5; specifically, an angle ⁇ between the side wall of the organic flat portion 61 close to the first gap 54 and a side of the first conductive layer 5 away from the base substrate 1 is less than or equal to 70°, that is, although the organic flat portion 61 has a side wall, the slope of the side wall of the organic flat portion 61 is relatively gentle, and even if the subsequently formed organic active layer 7 climbs the side wall of the organic flat portion 61, no gap will appear and the layer will not break due to the
  • the material of the organic flat portion 61 is an organic material, and the corner of the organic flat portion 61 is relatively smooth.
  • the corner of the organic flat portion 61 can be a curved surface, that is, the side of the organic flat portion 61 facing away from the base substrate 1 is connected to the side wall through the curved surface. No sharp corner structure is formed at the corner of the source 51 and the drain 52. Therefore, the subsequently formed organic active layer 7 has good coverage at the corner of the organic flat portion 61, and no fracture defects will occur at the corner bend.
  • the organic flat portion 61 is not only arranged in the first gap 54, but also protrudes from the first conductive layer 5, so that the distance between the side of the organic flat portion 61 facing away from the substrate 1 and the substrate 1 is greater than the distance between the side of the first conductive layer 5 facing away from the substrate 1 and the substrate 1.
  • a part of the organic flat portion 61 is arranged on the side of the first conductive layer 5 facing away from the substrate 1, that is, a part of the organic flattening layer 6 is arranged on the side of the source electrode 51 facing away from the substrate 1, and another part of the organic flattening layer 6 is arranged on the side of the drain electrode 52 facing away from the substrate 1, so that the orthographic projection of the organic flat portion 61 on the substrate 1 overlaps with the orthographic projection of the source electrode 51 on the substrate 1, and the orthographic projection of the organic flat portion 61 on the substrate 1 overlaps with the orthographic projection of the drain electrode 52 on the substrate 1.
  • the width of the overlapping portion of the orthographic projection of the organic flat portion 61 on the substrate substrate 1 and the orthographic projection of the source electrode 51 on the substrate substrate 1 is less than 5 microns, and the width of the overlapping portion of the orthographic projection of the organic flat portion 61 on the substrate substrate 1 and the orthographic projection of the drain electrode 52 on the substrate substrate 1 is also less than 5 microns, so as to avoid the organic flat portion 61 covering more of the source electrode 51 and the drain electrode 52, thereby preventing the subsequently formed organic active layer 7 from being unstable in connection with the source electrode 51 and the drain electrode 52.
  • the width of the overlapping portion of the orthographic projection of the organic flat portion 61 on the base substrate 1 and the orthographic projection of the source electrode 51 on the base substrate 1 is greater than or equal to 2 microns, for example, it can be 2.5 microns, 2.85 microns, 3.1 microns, 3.6 microns, 4.25 microns, 4.7 microns, etc.; similarly, the width of the overlapping portion of the orthographic projection of the organic flat portion 61 on the base substrate 1 and the orthographic projection of the drain electrode 52 on the base substrate 1 is also greater than or equal to 2 microns, for example, it can be 2.5 microns, 2.85 microns, 3.1 microns, 3.6 microns, 4.25 microns, 4.7 microns, etc.
  • the above data may also be other values depending on the accuracy of the product and process equipment.
  • Such arrangement enables the organic flat portion 61 to fill up the first gap 54 between the source electrode 51 and the drain electrode 52, and the organic flat portion 61 to completely cover the sharp corners of the corners of the source electrode 51 and the drain electrode 52; the subsequently formed organic active layer 7 does not need to climb the side walls of the source electrode 51 and the drain electrode 52, thereby avoiding the appearance of gaps in the organic active layer 7 and preventing it from breaking due to the gaps; moreover, the requirements for process and equipment accuracy are relatively low, and even if errors occur during the preparation process and the position of the organic flat portion 61 is shifted, the organic flat portion 61 will fill up the first gap 54 between the source electrode 51 and the drain electrode 52, and the organic flat portion 61 will completely cover the sharp corners of the corners of the source electrode 51 and the drain electrode 52.
  • the distance H1 between the side of the organic flat portion 61 facing away from the base substrate 1 and the first conductive layer 5 may be less than the thickness H2 of the first conductive layer 5 in the third direction Z, that is, the height of the organic flat portion 61 protruding from the first conductive layer 5 is less than the thickness of the first conductive layer 5; the third direction Z is perpendicular to the side of the base substrate 1 close to the first electrode layer 4.
  • the organic active layer 7 formed subsequently climbs on the side wall of the organic flat portion 61, but the climbing height is low, avoiding the organic active layer 7 from having gaps and will not be broken due to the gaps.
  • the distance H1 between the side of the organic flat portion 61 facing away from the base substrate 1 and the first conductive layer 5 may also be equal to or greater than the thickness H2 of the first conductive layer 5 in the third direction Z.
  • the angle ⁇ between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle ⁇ between the side wall of the first conductive layer 5 close to the first gap 54 and the side of the first electrode layer 4 close to the first conductive layer 5; that is, the inclination angle of the side wall of the organic planarization layer 6 is smaller than the inclination angle of the side wall of the source 51 and the drain 52 of the first conductive layer 5; specifically, the angle ⁇ between the side wall of the organic flat portion 61 close to the first gap 54 and the side of the first conductive layer 5 away from the base substrate 1 is less than or equal to 70°, that is, although the organic flat portion 61 has a side wall, the slope of the side wall of the organic flat portion 61 is relatively gentle, and even if the subsequently formed organic active layer 7 climbs the side wall of the organic flat portion 61, no gap will appear and the layer will not break due to the gap.
  • the material of the organic flat portion 61 is an organic material, and the corner of the organic flat portion 61 is relatively smooth.
  • the corner of the organic flat portion 61 can be a curved surface, that is, the side of the organic flat portion 61 facing away from the base substrate 1 can be connected to the side wall through the curved surface.
  • the sharp corner structure of the source 51 and the drain 52 will not be formed. Therefore, the subsequently formed organic active layer 7 has good coverage of the corner of the organic flat portion 61, and will not produce a bad break at the corner bend.
  • the side of the organic flat portion 61 facing away from the base substrate 1 can also be directly connected to the side wall to form an obtuse angle.
  • the angle between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 54 facing away from the base substrate 11 cannot be too small. If it is too small, the area of the organic planarization portion 61 will be larger, so that the area of the subsequently formed organic active layer 7 will be larger, resulting in a larger area of the entire thin film transistor, which affects the aperture ratio of the display panel. Specifically, the angle between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 54 facing away from the base substrate 11 is greater than or equal to 30 degrees.
  • the angle between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 54 facing away from the base substrate 11 can be 32 degrees, 36 degrees, 42.5 degrees, 46.8 degrees, 51 degrees, 54.7 degrees, 58.4 degrees, 62 degrees, 65.3 degrees, 67.5 degrees, etc.
  • the thickness of the organic planarization layer 6 is greater than or equal to 300 nanometers and less than or equal to 800 nanometers.
  • the thickness of the organic planarization layer 6 can be 326 nanometers, 375 nanometers, 430 nanometers, 480 nanometers, 517 nanometers, 589 nanometers, 625 nanometers, 673 nanometers, 741 nanometers, 789 nanometers, etc.
  • an organic active layer 7 may be provided on the side of the organic planarization layer 6 facing away from the base substrate 1, and the organic active layer 7 is connected to the source electrode 51 and the drain electrode 52 on the side of the organic planar portion 61 facing away from the first gap 54.
  • the material of the organic active layer 7 may be an organic semiconductor (OSC) material.
  • the material selection space of the first conductive layer 5 is larger, so that the flexible array substrate can be mass-produced; and, since the organic semiconductor (OSC) material of the organic active layer 7 is a P-type material, the first conductive layer 5 needs to form an ohmic contact with the organic active layer 7, and the first conductive layer 5 needs to select a material with a larger work function, for example, the work function of the material of the first conductive layer 5 needs to be greater than 4.5 eV; therefore, considering the work function, the material of the first conductive layer 5 can be Ag+SAM, whose work function is about 5.86 eV, and Ag is closer to the base substrate 1; it can be ITO (Indium Tin Oxide), whose work function is greater than or equal to 4.57 and less than or equal to 4.93eV; it can be Mo + surface oxidation (molybdenum oxide), whose work function is about 5.58eV, and Mo is closer to the substrate 1; it can be
  • ITO Indium Tin Oxide
  • the first conductive layer 5 can be stacked.
  • the first conductive layer 5 can include BF (Buffer Film), LRF (Low Resistance Film), and HWF (High Work Function Film) stacked in sequence; the buffer film is closer to the base substrate 1.
  • BF Buffer Film
  • LRF Low Resistance Film
  • HWF High Work Function Film
  • the buffer film can be selected from: Mo, Mo alloy, Ti, ITO, IZO (indium zinc oxide), etc.;
  • the low resistance film can be selected from: Cu, Al, Ag, etc.;
  • the high work function film can be Ag+SAM, whose work function is about 5.86eV; it can be ITO (indium tin oxide), whose work function is greater than or equal to 4.57 and less than or equal to 4.93eV; it can be Mo+surface oxidation (molybdenum oxide), whose work function is about 5.58eV, and Mo is closer to the substrate 1; it can be Mo alloy+surface oxidation (molybdenum oxide), whose work function is about 5.5eV, and Mo alloy is closer to the substrate 1; it can also be TiN, whose work function is greater than or equal to 4.49 and less than or equal to 5.29eV; it can also be Au, whose work function is about 5.2eV; it can also be Pt, whose work function is about 5.6eV; it can
  • SAM is a self-assembled monolayer film that can form a monomolecular layer and modify the interface between the first conductive layer 4 and the organic active layer 7 to improve the work function.
  • the material of the first conductive layer 5 is a stacked structure of MoAlMo or a stacked structure of MoNd/Cu/MoNd. Since the surface is Mo or Mo alloy material, the work function is small ( ⁇ 4.5eV), which does not meet the requirements.
  • the present invention performs surface oxidation treatment, and the treatment methods include annealing, plasma, etc., so that the work function is increased to greater than or equal to 4.5eV, and the temperature of the surface oxidation treatment process is relatively low, generally not exceeding 100°C.
  • a gate insulating layer group 8 may be provided on the side of the organic active layer 7 facing away from the base substrate 1, and the orthographic projection of the gate insulating layer group 8 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1, that is, the orthographic projection of the gate insulating layer group 8 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1, so that the gate insulating layer group 8 and the organic active layer 7 may be formed by the same patterning process, thereby reducing the process steps and lowering the cost.
  • the gate insulating layer group 8 may include a first gate insulating layer 81 and a second gate insulating layer 82.
  • the first gate insulating layer 81 is arranged on the side of the organic active layer 7 away from the substrate 1.
  • the first gate insulating layer 81 needs to be a flexible film layer with insulating properties; and it is orthogonal to the solvent for etching the organic active layer 7 and has good matching performance, that is, the material of the first gate insulating layer 81 will not react with the material of the organic active layer 7, thereby ensuring the channel characteristics of the organic active layer 7; for example, the material of the first gate insulating layer 81 can be a material with a low dielectric constant.
  • an orthogonal solvent refers to a solvent with a large difference in polarity.
  • An orthogonal solvent system is a solvent system used for applying a subsequent layer, in which the previously applied layer is insoluble.
  • the second gate insulating layer 82 is arranged on the side of the first gate insulating layer 81 away from the substrate 1, and the second gate insulating layer 82 has a stronger barrier performance against the etching liquid of the gate layer 9 than the first gate insulating layer 81.
  • the second gate insulating layer 82 needs to be a flexible film layer with insulation, good environmental stability, and can block water and oxygen; it can be a cross-linked material, which is a material that undergoes a cross-linking reaction.
  • the cross-linking reaction refers to the reaction of two or more molecules (generally linear molecules) that are bonded and cross-linked to form a relatively stable molecule (bulk molecule) of a network structure.
  • This reaction transforms linear or slightly branched macromolecules into a three-dimensional network structure, thereby improving the strength, heat resistance, wear resistance, solvent resistance and other properties;
  • the material of the second gate insulating layer 82 can be a cross-linkable dielectric material, which can improve electrical durability.
  • a gate layer 9 may be provided on the side of the gate insulating layer group 8 facing away from the base substrate 1, and the gate layer 9 may include a gate 91.
  • the orthographic projection of the gate layer 9 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1, that is, the orthographic projection of the gate layer 9 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1, that is, the orthographic projection of the gate layer 9 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1 completely, so that the gate layer 9 and the organic active layer 7 can be formed by the same patterning process, reducing the process steps and reducing the cost.
  • the orthographic projection of the gate layer 9 on the base substrate 1 may be located within the orthographic projection of the light shielding layer 3 on the base substrate 1.
  • the gate layer 9, the gate insulating layer group 8 and the organic active layer 7 are formed by the same patterning process, but in the case where only the first gate insulating layer 81 is provided, since the barrier properties of the first gate insulating layer 81 and the organic active layer 7 are relatively poor, when etching the gate material layer 90, the etching liquid easily penetrates the first gate insulating layer 81 and the organic active layer 7 to corrode the first conductive layer 5, and in the case where the gate insulating layer group 8 includes the first gate insulating layer 81 and the second gate insulating layer 82, since the barrier properties of the second gate insulating layer 82 to the etching liquid of the gate layer 9 are stronger than the barrier properties of the first gate insulating layer 81 to the etching liquid of the gate layer 9.
  • the second gate insulating material layer 820 can protect the first conductive layer 5, prevent the etching liquid of the gate layer 9 from corroding the first conductive layer 5, ensure the electrical properties of the first conductive layer 5, and thus ensure the performance of the array substrate.
  • the gate layer 9 can protect the gate insulation layer group 8 and the organic active layer 7 thereunder, so as to prevent the etching solution of the gate layer 9 from corroding the first conductive layer 5. Therefore, the material selection space of the gate layer 9 is relatively large, so that the flexible array substrate can be mass-produced; for example, the material of the gate layer 9 can be Ag, Mo, Cu, Al, Ti, ITO, a stacked structure of ITO/Ag/ITO, a stacked structure of Mo/Al/Mo, a stacked structure of Mo/Cu/Mo, a stacked structure of Ti/Al/Ti, and the like.
  • a passivation layer 10 may be provided on the side of the gate layer 9 facing away from the base substrate 1 .
  • the passivation layer 10 needs to be a flexible film layer with insulating properties, good environmental stability, and the ability to block water and oxygen. Specifically, it may be a cross-linked material.
  • the material of the passivation layer 10 may be the same as that of the second gate insulating layer 82 .
  • a first via hole 101 is provided on the passivation layer 10 , and the first via hole 101 is connected to the gate 91 .
  • a second electrode layer 11 may be provided on the side of the passivation layer 10 away from the base substrate 1 , and the material of the second electrode layer 11 may be a transparent conductive material, for example, ITO (indium tin oxide), IZO (indium zinc oxide), etc.
  • the second electrode layer 11 includes second electrodes 111 and gate line connecting portions 112 arranged at intervals, and the second electrode 111 may be a common electrode, so a plurality of second electrodes 111 need to be connected together, and the gate line connecting portion 112 needs to be connected to the gate 91, so the second electrode 111 and the gate line connecting portion 112 need to be arranged at intervals; the specific structure may be that the second electrode 111 may be arranged in a strip extending along the first direction X, the gate connecting portion 112 may be arranged in a strip extending along the first direction X, and the second electrode 111 and the gate connecting portion 112 may be arranged alternately in the second direction, that is, a gate connecting portion 112 is arranged between two adjacent second electrodes 111, and a second electrode 111 is arranged between two adjacent gate connecting portions 112.
  • the plurality of second electrodes 111 may be connected in the peripheral region.
  • the plurality of second electrodes 111 may also be bridged by other conductive film layers.
  • the gate connection portion 112 serves as a gate line alone.
  • the gate connection portion 112 can extend along the first direction X.
  • the gate connection portion 112 is connected to two adjacent gates 91 through the first via hole 101 on the passivation layer 10.
  • a plurality of gates 91 arranged along the first direction X are connected together through a plurality of gate connection portions 112.
  • the gate connection portion 112 serves as a gate line to provide a scanning signal to each gate 91.
  • the gate layer 9 may include not only the gate 91 but also a gate extension 92, which is connected to opposite sides of the gate 91 in the first direction X.
  • the gate extension 92, the gate 91, the gate insulating layer group 8 and the organic active layer 7 are formed by the same patterning process, in order to avoid mutual connection between the organic active layers 7 of different thin film transistors, the gate extension 92 is spaced apart from another adjacent gate 91, and the gate extension 92 extends along the first direction X, which is parallel to a side of the base substrate 1 close to the first conductive layer 5.
  • the gate extension 92 may be connected to one side of the gate 91 in the first direction X.
  • a portion of the orthographic projection of the gate extension portion 92 on the base substrate 1 may be located within the orthographic projection of the light-shielding layer 3 on the base substrate 1, and another portion of the orthographic projection of the gate extension portion 92 on the base substrate 1 may be located outside the orthographic projection of the light-shielding layer 3 on the base substrate 1, that is, the gate extension portion 92 protrudes beyond the light-shielding layer 3 in the first direction.
  • the gate layer 9 is made of metal with low resistance, such a configuration can reduce the resistance of the gate line and the power consumption of the array substrate.
  • a passivation layer 10 can be provided on the side of the gate layer 9 facing away from the base substrate 1.
  • the passivation layer 10 needs to be a flexible film layer with insulating properties, good environmental stability, and the ability to block water and oxygen. Specifically, it can be a cross-linked material; the material of the passivation layer 10 can be the same as that of the second gate insulating layer 82.
  • a first via hole 101 is provided on the passivation layer 10 , and the first via hole 101 is connected to the gate extension portion 92 .
  • a second electrode layer 11 may be provided on the side of the passivation layer 10 away from the base substrate 1, and the material of the second electrode layer 11 may be a transparent conductive material, for example, ITO (indium tin oxide), IZO (indium zinc oxide), etc.
  • the second electrode layer 11 includes a second electrode 111 and a gate connecting portion 112 arranged at intervals.
  • the second electrode 111 may be a common electrode, so a plurality of second electrodes 111 need to be connected together, and the gate connecting portion 112 needs to be connected to the gate extension portion 92, so the second electrode 111 and the gate connecting portion 112 need to be arranged at intervals; the specific structure may be that a plurality of openings are provided on the second electrode layer 11 to form the second electrode layer 11, and the gate connecting portion 112 is provided in the opening.
  • the gate connection portion 112 can extend along the first direction X.
  • the gate connection portion 112 is connected to two adjacent gate extension portions 92 through the first via hole 101 on the passivation layer 10, that is, the gate connection portion 112 and the gate extension portion 92 are connected to form a gate line to connect multiple gates 91 arranged along the first direction X and provide scanning signals for each gate 91.
  • the array substrate may further include a conductive enhancement layer 15, which is disposed on the side of the second electrode layer 11 away from the base substrate 1, and the orthographic projection of the conductive enhancement layer 15 on the base substrate 1 coincides with the orthographic projection of the gate connection portion 112 on the base substrate 1, that is, the conductive enhancement layer 15 is not disposed on the side of the second electrode 111 away from the base substrate 1, so as to ensure the light transmission area of the array substrate, that is, to ensure the aperture ratio of the array substrate.
  • the conductive enhancement layer 15 is made of metal with low resistance.
  • the conductive enhancement layer 15 can reduce the resistance of the gate connection portion 112, thereby reducing the resistance of the gate line of the array substrate, reducing power consumption, and ensuring the uniformity of the electric field of the second electrode 111 of the array substrate.
  • the conductive enhancement layer 15 can also be disposed on the side of the second electrode 111 away from the base substrate 1, but the conductive enhancement layer 15 is only disposed in the area of the second electrode 111 that is not the display area, for example, the conductive enhancement layer 15 can be disposed in the portion where the second electrode 111 overlaps with the data line 53.
  • the array substrate may further include a protective layer 14 .
  • the protective layer 14 at least covers the side wall of the organic active layer 7 .
  • the protective layer 14 may protect the organic active layer 7 .
  • the protective layer 14 is disposed between the gate layer 9 and the organic planarization layer 6 and the passivation layer 10, and covers the organic active layer 7, the gate insulating layer group 8 and the sidewalls of the gate 91. That is, the protective layer 14 is formed after the gate layer 9 is formed.
  • the thickness of the protective layer 14 is greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms.
  • the thickness of the protective layer 14 can be 1030 angstroms, 1085 angstroms, 1162 angstroms, 1238 angstroms, 1348 angstroms, 1586 angstroms, 1651 angstroms, 1752 angstroms, 1830 angstroms, 1985 angstroms, 2162 angstroms, 2338 angstroms, 2481 angstroms, 2568 angstroms, 2615 angstroms, 2725 angstroms, 2856 angstroms, 2965 angstroms, etc.
  • the material of the protective layer 14 may be the same as the material of the first insulating layer 81 or the material of the first planarization layer 21.
  • the specific requirements of the material of the first insulating layer 81 and the material of the first planarization layer 21 have been described in detail above, and therefore will not be repeated here.
  • the matching of the protective layer 14 and the organic active layer 7 is stronger than the matching of the passivation layer 10 and the organic active layer 7.
  • the protective layer 14 can prevent the organic active layer 7 from contacting the passivation layer 10. Since the material matching between the organic active layer 7 and the passivation layer 10 is poor, for example, the organic active layer 7 and the passivation layer 10 will react, and additional by-products will be produced during the film formation process, or the organic active layer 7 and the passivation layer 10 will be mutually dissolved, resulting in damage to the organic active layer 7 and the passivation layer 10.
  • the material matching between the protective layer 14 and the organic active layer 7 is better, that is, the material of the protective layer 14 is orthogonal to the material solvent of the organic active layer 7, that is, the material of the protective layer 14 and the material of the organic active layer 7 do not react with each other, so that the protective layer 14 and the organic active layer 7 can maintain integrity, and improve the stability of the thin film transistor, and ensure the performance of the array substrate.
  • the gate connecting portion 112 can be connected to the gate 91 through the first via 101 on the passivation layer 10 and the fourth via 141 on the protective layer 14, and the first via 101 on the passivation layer 10 and the fourth via 141 on the protective layer 14 can be formed by the same composition process.
  • the light-shielding layer 3 may be configured as a strip extending along the first direction X, and one light-shielding layer 3 may correspond to a plurality of thin-film transistors arranged along the first direction X, that is, the orthographic projections of the plurality of organic active layers 7 arranged along the first direction X on the base substrate 1 are located within the orthographic projections of the light-shielding layer 3 on the base substrate 1.
  • a passivation layer 10 can be provided on the side of the gate layer 9 facing away from the base substrate 1.
  • the passivation layer 10 needs to be a flexible film layer with insulating properties, good environmental stability, and the ability to block water and oxygen. Specifically, it can be a cross-linked material; the material of the passivation layer 10 can be the same as that of the second gate insulating layer 82.
  • the passivation layer 10 is provided with a first via hole 101 and a second via hole 102, and the first via hole 101 is connected to the gate 91.
  • the second planarization layer 22 is provided with a third via hole 221, and the second via hole 102 is connected to the third via hole 221 and connected to the light shielding layer 3.
  • a second electrode layer 11 may be provided on the side of the passivation layer 10 facing away from the base substrate 1.
  • the material of the second electrode layer 11 may be a transparent conductive material, for example, ITO (indium tin oxide), IZO (indium zinc oxide), etc.
  • the second electrode layer 11 may include a second electrode 111 and a gate connection portion 112 arranged at intervals.
  • the second electrode 111 may be a common electrode.
  • the gate connection portion 112 is arranged at intervals from the second electrode 111.
  • the gate connection portion 112 is connected to the gate 91 through the first via 101, and is connected to the light shielding layer 3 through the second via 102 and the third via 221.
  • the light shielding layer 3 is multiplexed as a gate line and a second gate 91.
  • the thin film transistor includes two gates 91, and the two gates 91 are respectively located on the upper and lower sides of the organic active layer 7 to ensure the performance of the thin film transistor.
  • an exemplary embodiment of the present disclosure provides a method for preparing an array substrate.
  • the method for preparing the array substrate may include the following steps:
  • Step S10 providing a substrate.
  • a first electrode layer and a first conductive layer are formed on one side of the base substrate, which are stacked in sequence, wherein the first electrode layer includes a first electrode, and the first conductive layer includes a source and a drain, a first gap is provided between the source and the drain, and an orthographic projection of the drain on the base substrate overlaps with an orthographic projection of the first electrode layer on the base substrate.
  • Step S30 forming an organic planarization layer, wherein the organic planarization layer includes a plurality of organic planarization portions arranged at intervals, and the organic planarization portions are at least arranged in the first gap.
  • Step S40 forming an organic active layer on a side of the organic planarization layer away from the base substrate, wherein the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap.
  • the organic flat portion 61 at least does not cover the ends of the source 51 and the drain 52 away from the first gap 54, and the angle between the side wall of the organic flat portion 61 close to the first gap 54 and the side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle between the side wall of the first conductive layer 5 close to the first gap 54 and the side of the first electrode layer 4 close to the first conductive layer 5.
  • the array substrate of the present disclosure can be formed by six patterning processes. The following describes in detail each step of the method for preparing the array substrate 100 .
  • a base substrate 1 is provided, specifically, as shown in FIG22 , a glass substrate 13 is provided, and the base substrate 1 is bonded to the glass substrate 13 via an adhesive layer 12 (not shown in FIG22 to FIG40 ).
  • a first planarization layer 21 is formed on the side of the base substrate 1 away from the glass substrate 13 .
  • a light shielding material layer is formed on the side of the first planarization layer 21 away from the base substrate 1, and the light shielding material layer is patterned to form a light shielding layer 3.
  • the first patterning process is now completed. The specific structure of the light shielding layer 3 has been described in detail above, so it will not be repeated here.
  • a second planarization layer 22 , a first electrode material layer 40 and a first conductive material layer 50 are sequentially formed on a side of the light shielding layer 3 facing away from the base substrate 1 .
  • the mask layer is subjected to a half-mask process to form a mask pattern 16, specifically, a mask layer is formed on the side of the first conductive material layer 50 away from the substrate 1, and a mask plate is placed on the side of the mask layer away from the substrate 1, and the mask plate may include a light-transmitting portion, a light-shielding portion 31, and a semi-transmitting portion; the semi-transmitting portion is arranged opposite to the second portion 162, that is, the orthographic projection of the semi-transmitting portion on the substrate 1 coincides with the orthographic projection of the second portion 162 on the substrate 1; the light-shielding portion 31 is arranged opposite to the first portion 161, that is, the orthographic projection of the light-shielding portion 31 on the substrate 1 coincides with the orthographic projection of the first portion 161 on the substrate 1.
  • the light-transmitting portion is arranged opposite to other portions of the mask layer.
  • the mask layer is exposed and developed to form a mask pattern 16, and the mask pattern 16 includes a first part 161 and a second part 162, that is, the mask layer arranged opposite to the light-transmitting part is removed; the mask layer arranged opposite to the semi-transmitting part is removed by a certain thickness to form the second part 162; the mask layer arranged opposite to the shading part 31 is completely retained to form the first part 161, so that the thickness of the first part 161 is greater than the thickness of the second part 162, the first part 161 is arranged opposite to the first conductive layer 5 and a part of the first electrode layer 4, and the second part 162 is arranged opposite to another part of the first electrode layer 4.
  • the exposed first conductive material layer 50 is etched and removed for the first time, and the first electrode material layer 40 is etched and removed to form a first electrode layer 4, forming a first gap 54 between the source 51 and the drain 52 and a second gap 43 between the first electrode 41 and the resistance reduction connection part 42; the first electrode layer 4 covered by the mask pattern 16 and the remaining first conductive material layer 50 are retained.
  • the mask pattern 16 is ashed to remove the second portion 162, so that the first conductive material layer 50 covered by the second portion 162 is exposed;
  • the gas used in the ashing process may include SF6 and O2.
  • the second portion 162 is removed by the ashing process, so that the first conductive material layer 50 covered by the second portion 162 is exposed, and the thickness of the first portion 161 is also reduced.
  • the remaining first conductive material layer 50 is patterned to form the first conductive layer 5, that is, the first conductive material layer 50 covered by the second portion 162 is etched away, and the first conductive material layer 50 covered by the first portion 161 is retained to form the first conductive layer 5. Finally, the remaining first portion 161 is removed. The second patterning process is now completed.
  • an organic planarization layer 6 is formed on the side of the first conductive layer 5 away from the base substrate 1 , and the organic planarization layer 6 is patterned to form a plurality of organic planar portions 61 disposed at intervals.
  • the third patterning process is now completed.
  • an organic active material layer 70, a first gate insulating material layer 810, a second gate insulating material layer 820 and a gate material layer are sequentially formed on the side of the organic flat portion 61 away from the base substrate 1; and a mask layer is formed on the side of the gate material layer away from the base substrate 1, and the mask layer is exposed and developed to form a second mask pattern 17.
  • the gate material layer is etched using the second mask pattern 17 as a mask to form a gate layer 9.
  • the second mask pattern 17 is removed, and the first gate insulating material layer 810, the second gate insulating material layer 820 and the organic active material layer 70 are etched using the gate layer 9 as a mask to form a gate insulating layer group 8 (a first gate insulating layer 81, a second gate insulating layer 82) and an organic active layer 7.
  • the mask pattern 16 can also be removed after the gate insulating layer group 8 and the organic active layer 7 are formed. So far, the fourth patterning process is completed.
  • a passivation layer 10 is formed on the side of the gate layer 9 facing away from the base substrate 1. As shown in FIG. 39 , the passivation layer 10 is patterned to form a first via hole 101 and a second via hole 102, and a third via hole 221 is formed on the second planarization layer 22. The fifth patterning process is completed. In addition, in some other exemplary embodiments of the present disclosure, as shown in FIG. 9 , the passivation layer 10 may be patterned to form only the first via hole 101.
  • the array substrate includes a protective layer 14, a protective layer 14 and a passivation layer 10 are sequentially formed on the side of the gate layer 9 facing away from the base substrate 1, and the passivation layer 10 is patterned to form a first via hole 101, and the protective layer 14 is patterned to form a fourth via hole 141 at the same time, and the fourth via hole 141 is connected to the first via hole 101; or, the passivation layer 10 is patterned to form the first via hole 101 and the second via hole 102, and a third via hole 221 is formed on the second planarization layer 22, and the protective layer 14 is patterned to form a fourth via hole 141 and a fifth via hole at the same time, and the fourth via hole 141 is connected to the first via hole 101, and the fifth via hole is connected to the second via hole 102 and the third via hole 221.
  • the fifth patterning process is completed.
  • a second electrode material layer is formed on the side of the passivation layer 10 away from the base substrate 1, and the second electrode material layer is patterned to form a second electrode layer 11 and a gate connecting portion 112.
  • the sixth patterning process is now completed.
  • the array substrate includes a conductive enhancement layer 15
  • a second electrode material layer and a conductive enhancement material layer are sequentially formed on the side of the passivation layer 10 away from the base substrate 1, and the conductive enhancement material layer is patterned to form the conductive enhancement layer 15, and the second electrode material layer is patterned to form the second electrode layer 11 and the gate connection portion 112.
  • the formation process of the second electrode layer 11 and the conductive enhancement layer 15 is the same as the formation process of the gate layer 9 and the organic active layer 7, that is, the mask layer is first subjected to a half-mask process and then subjected to an ashing process, and the specific steps are not repeated here.
  • the sixth patterning process is now completed.
  • an example embodiment of the present disclosure provides a display panel, which is a liquid crystal display panel.
  • the display panel may include an array substrate, a color filter substrate and a liquid crystal layer;
  • the array substrate may be any one of the array substrates described above, and the specific structure of the array substrate has been described in detail above, so it will not be repeated here;
  • the color filter substrate is arranged opposite to the array substrate;
  • the liquid crystal layer is arranged between the array substrate and the color filter substrate.
  • the color filter substrate may be a flexible color filter substrate, which may include a flexible substrate, a shading portion 31 and a filter portion provided on one side of the flexible substrate, and the filter portion may include a red filter portion, a green filter portion, a blue filter portion, and the like.
  • an exemplary embodiment of the present disclosure provides a display device, which may be a roll-up display device, a foldable display device or a curved display device.
  • the display device may include a display panel described in any one of the above. The specific structure of the display panel has been described in detail above, so it will not be repeated here.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in the field can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Technical personnel in this field can make corresponding choices based on the specific purpose of the display device, which will not be elaborated here.
  • the display device in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

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Abstract

一种阵列基板及其制备方法、显示面板、显示装置。阵列基板包括衬底基板(1)；第一电极层(4)设于衬底基板(1)的一侧，第一电极层(4)包括第一电极(41)；第一导电层(5)设于第一电极层(4)背离衬底基板(1)的一侧，第一导电层(5)包括源极(51)和漏极(52)，源极(51)和漏极(52)之间设置有第一间隙(54)，漏极(52)在衬底基板(1)上的正投影与第一电极层(4)在衬底基板(1)上的正投影有交叠；有机平坦化层(6)包括多个间隔设置的有机平坦部(61)，有机平坦部(61)至少设于第一间隙(54)内，且至少未覆盖源极(51)和漏极(52)背离第一间隙(54)的端部，有机平坦部(61)靠近第一间隙(54)的侧壁与第一导电层(5)靠近有机平坦化层(6)的一面之间的夹角小于第一导电层(5)靠近第一间隙(54)的侧壁与第一电极层(4)靠近第一导电层(5)的一面之间的夹角；有机有源层(7)设于有机平坦化层(6)背离衬底基板(1)的一侧，且在有机平坦部(61)背离第一间隙(54)的一侧与源极(51)及漏极(52)连接。

Description

阵列基板及其制备方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板及其制备方法、显示面板、显示装置。
背景技术
柔性显示装置由于其具有良好的柔韧性、轻薄的体积、较低的功耗、耐揉搓的特性，备受消费者青睐。柔性OLED(Organic Electroluminescence Display，有机发光半导体)显示装置已经较为成熟，但是，柔性LCD(Liquid Crystal Display，液晶显示)装置还无法实现量产。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板及其制备方法、显示面板、显示装置。
根据本公开的一个方面，提供了一种阵列基板，包括：
衬底基板；
第一电极层，设于所述衬底基板的一侧，所述第一电极层包括第一电极；
第一导电层，设于所述第一电极层背离所述衬底基板的一侧，所述第一导电层包括源极和漏极，所述源极和所述漏极之间设置有第一间隙，所述漏极在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影有交叠；
有机平坦化层，包括多个间隔设置的有机平坦部，所述有机平坦部至少设于所述第一间隙内，且所述有机平坦部至少未覆盖所述源极和所述漏极背离所述第一间隙的端部，所述有机平坦部靠近所述第一间隙的侧壁与所述第一导电层靠近所述有机平坦化层的一面之间的夹角小于所述第一导电层靠近所述第一间隙的侧壁与所述第一电极层靠近所述第一导电层的一面之间的夹角；
有机有源层，设于所述有机平坦化层背离所述衬底基板的一侧，所述有机有源层在所述有机平坦部背离所述第一间隙的一侧与所述源极以及所述漏极连接。
在本公开的一种示例性实施例中，所述有机平坦部背离所述衬底基板的一面与所述衬底基板之间的距离大于或等于所述第一导电层背离所述衬底基板的一面与所述衬底基板之间的距离。
在本公开的一种示例性实施例中，所述有机平坦部的一部分设于所述第一导电层背离所述衬底基板的一侧，在靠近所述第一间隙的位置，所述有机平坦部在所述衬底基板上的正投影与所述源极在所述衬底基板上的正投影有交叠，且所述有机平坦部在所述衬底基板上的正投影与所述漏极在所述衬底基板上的正投影有交叠。
在本公开的一种示例性实施例中，所述有机平坦部靠近所述第一间隙的侧壁与所述第一 导电层靠近所述有机平坦化层的一面之间的夹角小于等于70°。
在本公开的一种示例性实施例中，所述有机平坦部背离所述衬底基板的一面与所述第一导电层之间的距离小于所述第一导电层在第三方向的厚度，所述第三方向与所述衬底基板靠近所述第一电极层的一面垂直。
在本公开的一种示例性实施例中，所述有机平坦部背离所述衬底基板的一面与所述有机平坦部的侧壁之间通过弧面连接。
在本公开的一种示例性实施例中，所述第一导电层还包括数据线，所述数据线与所述源极连接，所述第一电极层还包括：
降阻连接部，与所述第一电极间隔设置，所述源极以及所述数据线在所述衬底基板上的正投影位于所述降阻连接部在所述衬底基板上的正投影之内。
在本公开的一种示例性实施例中，所述阵列基板还包括：
栅绝缘层组，设于所述有机有源层背离所述衬底基板的一侧，所述栅绝缘层组在所述衬底基板上的正投影与所述有机有源层在所述衬底基板上的正投影重合；
栅极层，设于所述栅绝缘层组背离所述衬底基板的一侧，所述栅极层包括栅极，所述栅极在所述衬底基板上的正投影与所述有机有源层在所述衬底基板上的正投影重合。
在本公开的一种示例性实施例中，所述栅绝缘层组包括：
第一栅绝缘层，设于所述有机有源层背离所述衬底基板的一侧；
第二栅绝缘层，设于所述第一栅绝缘层背离所述衬底基板的一侧，所述第二栅绝缘层对所述栅极层的刻蚀液的阻挡性能强于所述第一栅绝缘层对所述栅极层的刻蚀液的阻挡性能。
在本公开的一种示例性实施例中，所述阵列基板还包括：
钝化层，设于所述栅极层背离所述衬底基板的一侧；
第二电极层，设于所述钝化层背离所述衬底基板的一侧，所述第二电极层包括间隔设置的第二电极和栅极连接部，所述栅极连接部连接于相邻两个所述栅极。
在本公开的一种示例性实施例中，所述栅极层还包括：
栅极延伸部，所述栅极延伸部连接于所述栅极的第一方向的至少一侧，所述第一方向与所述阵列基板靠近所述第一电极层的一面平行。
在本公开的一种示例性实施例中，所述阵列基板还包括：
钝化层，设于所述栅极层背离所述衬底基板的一侧；
第二电极层，设于所述钝化层背离所述衬底基板的一侧，所述第二电极层包括间隔设置的第二电极和栅极连接部，所述栅极连接部连接于相邻两个所述栅极延伸部。
在本公开的一种示例性实施例中，所述阵列基板还包括：
导电增强层，设于所述第二电极层背离所述衬底基板的一侧，所述导电增强层在所述衬底基板上的正投影位于所述栅极连接部在所述衬底基板上的正投影之内。
在本公开的一种示例性实施例中，所述阵列基板还包括：
遮光层，设于所述衬底基板的一侧，所述有机有源层在所述衬底基板上的正投影位于所 述遮光层在所述衬底基板上的正投影之内；
第二平坦化层，设于所述遮光层背离所述衬底基板的一侧，所述第一电极层设于所述第二平坦化层背离所述衬底基板的一侧，所述第二平坦化层上设置有第三过孔；
钝化层，设于所述栅极层背离所述衬底基板的一侧，所述钝化层上设置有第一过孔和第二过孔，所述第一过孔连通至所述栅极，所述第二过孔与所述第三过孔连通，并连通至所述遮光层；
第二电极层，设于所述钝化层背离所述衬底基板的一侧，所述第二电极层包括间隔设置的第二电极和栅极连接部，所述栅极连接部通过所述第一过孔连接至所述栅极，并通过所述第二过孔和所述第三过孔连接至所述遮光层，所述遮光层复用为栅线和第二栅极。
在本公开的一种示例性实施例中，所述阵列基板还包括：
保护层，至少覆盖所述有机有源层的侧壁。
在本公开的一种示例性实施例中，所述保护层设于所述栅极层以及所述第一电极与所述钝化层之间，且覆盖所述有机有源层、所述栅绝缘层组和所述栅极的侧壁，所述保护层与所述有机有源层的匹配性强于所述钝化层与所述有机有源层的匹配性。
在本公开的一种示例性实施例中，所述第一导电层的功函数大于4.5eV。
在本公开的一种示例性实施例中，所述阵列基板为柔性阵列基板。
根据本公开的又一个方面，提供了一种阵列基板的制备方法，包括：
提供衬底基板；
在所述衬底基板的一侧形成依次层叠设置的第一电极层和第一导电层，所述第一电极层包括第一电极，所述第一导电层包括源极和漏极，所述源极和所述漏极之间设置有第一间隙，所述漏极在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影有交叠；
形成有机平坦化层，所述有机平坦化层包括多个间隔设置的有机平坦部，所述有机平坦部至少设于所述第一间隙内；
在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层，所述有机有源层在所述有机平坦部背离所述第一间隙的一侧与所述源极以及所述漏极连接；
其中，所述有机平坦部至少未覆盖所述源极和所述漏极背离所述第一间隙的端部，所述有机平坦部靠近所述第一间隙的侧壁与所述第一导电层靠近所述有机平坦化层的一面之间的夹角小于所述第一导电层靠近所述第一间隙的侧壁与所述第一电极层靠近所述第一导电层的一面之间的夹角。
在本公开的一种示例性实施例中，在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层的同时形成栅绝缘层组以及栅极层。
在本公开的一种示例性实施例中，在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层的同时形成栅绝缘层组以及栅极层，包括：
在所述有机平坦化层背离所述衬底基板的一侧依次形成有机有源材料层、栅绝缘材料层组以及栅极材料层；
对所述栅极材料层进行图案化处理形成所述栅极层；
以所述栅极层为掩模对所述栅绝缘材料层组以及所述有机有源材料层进行图案化处理形成所述栅绝缘层组和所述有机有源层。
在本公开的一种示例性实施例中，在所述衬底基板的一侧形成依次层叠设置的第一电极层和第一导电层，包括：
在所述衬底基板的一侧依次形成第一电极材料层和第一导电材料层，
在所述第一导电材料层背离所述衬底基板的一侧形成掩模层，对所述掩模层进行半掩模工艺形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度，所述第一部分与所述第一导电层以及所述第一电极层的一部分相对设置，所述第二部分与另一部分所述第一电极层相对设置；
对裸露的第一导电材料层进行刻蚀去除，且对所述第一电极材料层进行刻蚀去除形成所述第一电极层；
对所述掩模图案进行灰化处理，以去除所述第二部分，使所述第二部分覆盖的所述第一导电材料层裸露；
对剩余的第一导电材料层进行图案化处理形成所述第一导电层。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述栅极层背离衬底基板的一侧形成钝化层，并对所述钝化层进行图案化处理形成第一过孔。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述栅极层背离衬底基板的一侧依次形成保护层和钝化层，并对所述钝化层进行图案化处理形成第一过孔，且同时对所述保护层进行图案化处理形成第四过孔。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述栅极层背离衬底基板的一侧依次形成保护层和钝化层，并对所述钝化层进行图案化处理形成第一过孔和第二过孔，并同时对所述保护层进行图案化处理形成第四过孔和第五过孔，且同时对第二平坦化层进行图案化处理形成第三过孔，所述第四过孔与所述第一过孔连通，所述第五过孔与所述第二过孔和所述第三过孔连通。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述钝化层背离衬底基板的一侧形成第二电极材料层，并对所述第二电极材料层进行图案化处理形成第二电极层。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述钝化层背离衬底基板的一侧依次形成第二电极材料层和导电增强材料层，并对导电增强材料层和第二电极材料层进行图案化处理形成导电增强层和第二电极层。
根据本公开的另一个方面，提供了一种显示面板，包括：
阵列基板，是上述任意一项所述的阵列基板；
彩膜基板，与所述阵列基板相对设置；
液晶层，设于所述阵列基板与所述彩膜基板之间。
在本公开的一种示例性实施例中，所述阵列基板为柔性阵列基板，所述彩膜基板为柔性彩膜基板。
根据本公开的再一个方面，提供了一种显示装置，包括：上述任意一项所述的显示面板，所述显示装置为滑卷显示装置、可折叠显示装置或曲面显示装置。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开阵列基板第一示例实施方式的结构示意图。
图2为图1中遮光层的结构示意图。
图3为在图2的基础上形成第一电极层和第一导电层后的结构示意图。
图4为在图3的基础上形成有机平坦化层后的结构示意图。
图5为在图4的基础上形成有机有源层、栅绝缘层组以及栅极层后的结构示意图。
图6为图5中有机有源层、栅绝缘层组以及栅极层的结构示意图。
图7为在图5的基础上形成第二电极层后的结构示意图。
图8为图7中第二电极层的结构示意图。
图9为按照图7中的B-B剖切后的剖视示意图。
图10为本公开阵列基板第二示例实施方式的结构示意图。
图11为本公开阵列基板第三示例实施方式的结构示意图。
图12为在图4的基础上形成有机有源层、栅绝缘层组以及栅极层后另一示例实施方式的结构示意图。
图13为图12中有机有源层、栅绝缘层组以及栅极层的结构示意图。
图14为在图12的基础上形成第二电极层后的结构示意图。
图15为图14中第二电极层的结构示意图。
图16为本公开阵列基板第四示例实施方式按照图7或14中的B-B剖切的结构示意图。
图17为本公开阵列基板第四示例实施方式按照图7或14中的A-A剖切的结构示意图。
图18为本公开阵列基板第五示例实施方式按照图7或14中的A-A剖切的结构示意图。
图19为本公开阵列基板第五示例实施方式按照图7或14中的B-B剖切的结构示意图。
图20为本公开阵列基板第六示例实施方式的结构示意图。
图21为本公开阵列基板的制备方法一示例实施方式的流程示意框图。
图22-图40为本公开阵列基板的制备方法各个步骤的结构示意图。
附图标记说明：
1、衬底基板；21、第一平坦化层；22、第二平坦化层；221、第三过孔；
3、遮光层；31、遮光部；
40、第一电极材料层；4、第一电极层；41、第一电极；42、降阻连接部；43、第二间隙；
50、第一导电材料层；5、第一导电层；51、源极；52、漏极；53、数据线；54、第一间隙；
6、有机平坦化层；61、有机平坦部；
70、有机有源材料层；7、有机有源层；
8、栅绝缘层组；810、第一栅绝缘材料层；81、第一栅绝缘层；820、第二栅绝缘材料层；82、第二栅绝缘层；
90、栅极材料层；9、栅极层；91、栅极；92、栅极延伸部；
10、钝化层；101、第一过孔；102、第二过孔；
11、第二电极层；111、第二电极；112、栅极连接部；
12、粘接层；13、玻璃基板；14、保护层；141、第四过孔；
15、导电增强层；
16、掩模图案；161、第一部分；162、第二部分；17、第二掩模图案；
X、第一方向；Y、第二方向；Z、第三方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开示例实施方式提供了一种阵列基板，参照图1-图20、图22-图40所示，图1为按 照图7中的A-A剖切后的剖视示意图；由于有机有源层7、栅绝缘层组8以及栅极层9通过同一次构图工艺形成，因此在图5、图12和图37中只体现最上面的一层栅极层9。为了体现栅极的连接关系，图2-图8以及图12-图15中只体现了一个完整的子像素和相邻另一个子像素的数据线、部分栅极以及部分遮光层的具体结构。图20为按照图40中C-C剖切后的剖视示意图。图40中为了避免第二电极111对下层的遮挡，省略第二电极111，只画出栅极连接部112。
该阵列基板可以包括衬底基板1、第一电极层4、第一导电层5、有机平坦化层6以及有机有源层7；第一电极层4设于衬底基板1的一侧，第一电极层4包括第一电极41；第一导电层5设于第一电极层4背离衬底基板1的一侧，第一导电层5包括源极51和漏极52，源极51和漏极52之间设置有第一间隙54，漏极52在衬底基板1上的正投影与第一电极层4在衬底基板1上的正投影有交叠；有机平坦化层6可以包括多个间隔设置的有机平坦部61，有机平坦部61至少设于第一间隙54内，且有机平坦部61至少未覆盖源极51和漏极52背离第一间隙54的端部，有机平坦部61靠近第一间隙54的侧壁与第一导电层5靠近有机平坦化层6的一面之间的夹角小于第一导电层5靠近第一间隙54的侧壁与第一电极层4靠近第一导电层5的一面之间的夹角；有机有源层7设于有机平坦化层6背离衬底基板1的一侧，有机有源层7在有机平坦部61背离第一间隙54的一侧与源极51以及漏极52连接。
本公开的阵列基板，一方面，有机平坦化层6靠近第一间隙54的侧壁与第一导电层5靠近有机平坦化层6的一面之间的夹角小于第一导电层5靠近第一间隙54的侧壁第一电极层4靠近第一导电层5的一面之间的夹角，有机有源层7在有机平坦化层6的侧壁不会产生空隙，不会由于空隙而断裂。另一方面，有机平坦部61至少设于第一间隙54内，有机平坦部61背离衬底基板1的一面与衬底基板1之间的距离大于或等于第一导电层5背离衬底基板1的一面与衬底基板1之间的距离，使得有机平坦部61可以将源极51和漏极52靠近第一间隙54的拐角部进行遮挡，避免源极51和漏极52靠近第一间隙54的拐角部形成的尖角部使得有机有源层7无法覆盖，即使得有机有源层7能够很好地覆盖有机平坦部61和第一导电层5，达到较好的导电效果。再一方面，阵列基板采用有机有源层7和有机平坦化层6，整体制程温度小于100℃，使得阵列基板具有足够的柔性，能够用于柔性显示面板。
在本示例实施方式中，阵列基板为柔性柔性阵列基板。因此，衬底基板1为柔性基板。衬底基板1的材料是柔性材料，具体地，衬底基板1的材料可以为三醋酸纤维薄膜、聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。该衬底基板1可以由多层材料层形成，例如衬底基板1可以包括多层基材层，基材层的材料可以是上述的任意一种材料。当然，衬底基板1还可以设置为单层，可以是上述任意一种材料。
为了方便阵列基板的制备、运输等等，可以将衬底基板1通过粘接层12粘接在剥离基板上，使用时将玻璃基板13剥离，当然，该阵列基板作为刚性衬底基板1使用时，可以不剥离玻璃基板13，也可以不采用玻璃基板13，可以采用其他硬质基板。
在衬底基板1的一侧可以设置有多个阵列排布的薄膜晶体管，薄膜晶体管至少可以包括源极41、漏级42、有机有源层7以及第一栅极91。
参照图1所示，在衬底基板1的一侧可以设置有第一平坦化层21，第一平坦化层21的材质具有较强的附着力、较强的耐化学溶剂的腐蚀性、较好的平坦化作用、透过光高；而且低极性以降低沟道效应、降低漏电流，第一平坦化层21的材质可以是环氧树脂型光刻胶，例如，SU-8系列环氧树脂型光刻胶。在第一平坦化层21背离衬底基板1的一侧设置有遮光层3，从衬底基板1侧射入有机有源层7的光线会在有机有源层7产生光生载流子，进而对薄膜晶体管的特性产生巨大影响，最终影响显示装置的显示画质；通过遮光层3可以遮挡从衬底基板1侧射入的光线，从而避免对薄膜晶体管的特性产生影响，避免影响显示装置的显示画质。依据薄膜晶体管的类型，遮光层3可被省略。
参照图1和图2所示，遮光层3可以包括多个间隔设置的遮光部31，一个薄膜晶体管对应设置有一个遮光部31。参照图22所示，遮光层3可以包括沿第一方向延伸的多个条状遮光部31，一个条状遮光部31可以对应沿第一方向排列的多个薄膜晶体管，即通过一个条状遮光部31将沿第一方向排列的多个薄膜晶体管的有机有源层7遮挡。
在遮光层3背离衬底基板1的一侧可以设置有第二平坦化层22，第二平坦化层22的材质为绝缘材料，第二平坦化层22可以将遮光层3与第一导电层5绝缘隔离，第二平坦化层22的材质具有较强的附着力、较强的耐化学溶剂的腐蚀性、较好的平坦化作用、透过光高；而且低极性以降低沟道效应、降低漏电流；具体地，第二平坦化层22的材质可以是环氧树脂型光刻胶，例如，SU-8系列环氧树脂型光刻胶。第二平坦化层22的厚度大于等于1微米。
在本示例实施方式中，参照图1和图3所示，在第二平坦化层22背离衬底基板1的一侧可以设置有第一电极层4，第一电极层4可以包括间隔设置的第一电极41和降阻连接部42，第一电极41可以是像素电极，因此，多个第一电极41之间是间隔设置的。一个子像素设置有一个第一电极41。降阻连接部42设置为沿第二方向延伸的条状。第一电极层4的材质可以是透明导电材料，例如，ITO(氧化铟锡)、IZO(铟锌氧化物)等等。
在本示例实施方式中，在第一电极层4背离衬底基板1的一侧可以设置有第一导电层5，第一导电层5可以包括数据线53、源极51和漏极52。数据线53沿第二方向Y延伸，数据线53的一部分可以复用为源极51；或者，数据线53连接沿第二方向Y排列的多个源极51，通过一根数据线53可以向沿第二方向Y排列的多个源极51输入数据信号。源极51和漏极52之间设置有第一间隙54。
由于第一电极层4和第一导电层5是通过同一道构图工艺形成的，而且第一导电层5位于第一电极层4的上方，因此，第一导电层5与衬底基板1之间必然有第一电极层4，即第一电极层4的面积与第一导电层5的面积至少相同，或第一电极层4的面积比第一导电层5的面积要大；具体地，漏极52在衬底基板1上的正投影与第一电极层4在衬底基板1上的正投影有交叠，例如，第一电极层4在衬底基板1上的正投影覆盖漏极52在衬底基板1上的正投影，且第一电极层4在衬底基板1上的正投影的面积大于漏极52在衬底基板1上的正投影的 面积。而且，源极51以及数据线53在衬底基板1上的正投影位于降阻连接部42在衬底基板1上的正投影之内，例如，降阻连接部42在衬底基板1上的正投影与源极51以及数据线53在衬底基板1上的正投影重合；或者，降阻连接部42在衬底基板1上的正投影覆盖源极51以及数据线53在衬底基板1上的正投影，且降阻连接部42在衬底基板1上的正投影面积大于源极51以及数据线53在衬底基板1上的正投影面积。
第一导电层5的厚度大于等于500埃且小于等于8000埃，例如，第一导电层5的厚度可以为650埃、982埃、1020埃、1190埃、1380埃、1850埃、2340埃、2840埃、3240埃、3840埃、4180埃、4586埃、5170埃、5760埃、6230埃、6840埃、7520埃、7850埃等等。
需要说明的是，所谓的“重合”并不是完全重合，而是有一定的误差的，根据设备以及制备工艺的不同，误差范围也不同，因此，在设备以及制备工艺的误差范围之内，均认为是重合。
在使用极性相反的薄膜晶体管的情况或电路工作中的电流方向变化的情况等下，“源极41”及“漏极42”的功能有时互相调换。因此，在本说明书中，“源极41”和“漏极42”可以互相调换。
在本示例实施方式中，参照图1和图4所示，在第一导电层5背离衬底基板1的一侧可以设置有有机平坦化层6，具体地，有机平坦化层6的材质需耐化学溶剂，可以起到对第一导电层4进行保护的作用；而且透光率高，避免影响显示面板的透光率；再有极性低，极性低是指分子内偶极小，电荷分布较均匀，简单的说就是比较对称且一般很少有孤对电子，极性低可以降低感应电荷形成极化，从而降低背沟道效应，降低漏电流；具体例如，有机平坦化层6的材质可以是SU-8系列环氧型光刻胶，还可以选择其他低介电常数的材料。
有机平坦化层6可以包括多个间隔设置的有机平坦部61，即有机平坦部61设置为孤岛结构，一个薄膜晶体管可以包括一个有机平坦部61。
有机平坦部61至少设于第一间隙54内，而且有机平坦部61至少未覆盖源极51和漏极52背离第一间隙54的端部；如此设置使得源极51和漏极52在面积较小的情况下也能够保证与有机有源层7的连接，使得后续形成的有机有源层7的面积较小，使得薄膜晶体管的面积较小，增加整个阵列基板和显示面板的开口率。
有机有源层7在衬底基板1上的正投影位于遮光层3在衬底基板1上的正投影之内，使得遮光层3能够起到遮挡光线射至有机有源层7的作用，具体地，有机有源层7在衬底基板1上的正投影可以与遮光层3在衬底基板1上的正投影重合，或者遮光层3在衬底基板1上的正投影覆盖有机有源层7在衬底基板1上的正投影，且遮光层3在衬底基板1上的正投影面积大于有机有源层7在衬底基板1上的正投影面积，例如，遮光层3在衬底基板1上的正投影的边沿线与有机有源层7在衬底基板1上的正投影的边沿线之间的距离大于等于2微米。如此设置，保证在工艺或设备有误差的情况下，有机有源层7在衬底基板1上的正投影也能够位于遮光层3在衬底基板1上的正投影之内。
例如，参照图10所示，有机平坦部61仅设置在第一间隙54内，使得有机平坦部61背 离衬底基板1的一面与衬底基板1之间的距离等于第一导电层5背离衬底基板1的一面与衬底基板1之间的距离，即有机平坦部61将源极51和漏极52之间的第一间隙54填满，而且有机平坦部61将源极51和漏极52的拐角部的尖角进行覆盖；使得后续形成的有机有源层7不需要进行爬坡，有机有源层7不会形成空隙，不会由于空隙而断裂。
参照图11所示，有机平坦部61不仅设置在第一间隙54内，而且突出于第一导电层5，使得有机平坦部61背离衬底基板1的一面与衬底基板1之间的距离大于第一导电层5背离衬底基板1的一面与衬底基板1之间的距离，但是，有机平坦部61没有覆盖第一导电层5，如此设置，使得有机平坦部61将源极51和漏极52之间的第一间隙54填满，而且有机平坦部61将源极51和漏极52的拐角部的尖角进行覆盖；使得后续形成的有机有源层7不需要在源极51和漏极52的侧壁进行爬坡，避免有机有源层7出现空隙，不会由于空隙而断裂。
而且，有机平坦部61背离衬底基板1的一面与第一导电层5之间的距离H1小于第一导电层5在第三方向Z的厚度H2，即有机平坦部61突出第一导电层5的高度小于第一导电层5的厚度；第三方向Z与衬底基板1靠近第一电极层4的一面垂直。使得后续形成的有机有源层7在有机平坦部61的侧壁进行爬坡，但是爬坡高度较低，避免有机有源层7出现空隙，不会由于空隙而断裂。
在有机有源层77直接与第一导电层54接触连接时，需要将第一导电层54厚度设置的较小，避免有机有源层77的爬坡高度太高，而且第一导电层54的材料也需要考虑，避免第一导电层54形成的侧壁的坡度较陡。但是，第一导电层54的侧壁的坡度还是比较陡，例如，第一导电层54靠近第一间隙54的侧壁与衬底基板11靠近第一导电层54的一面之间的夹角一般都大于70度，而且在第一导电层54背离衬底基板11一侧的拐角位置容易形成尖角结构；后续形成的有机有源层77会在第一导电层54的侧壁形成空隙，由于空隙有机有源层77容易断裂，从而导致断路；而且由于尖角结构的存在，导致有机有源层77在第一导电层54背离衬底基板11一侧的拐角位置的覆盖性不佳，也容易导致有机有源层77断裂，从而导致断路。
再有，有机平坦化层6靠近第一间隙54的侧壁与第一导电层5靠近有机平坦化层6的一面之间的夹角α小于第一导电层5靠近第一间隙54的侧壁与第一电极层4靠近第一导电层5的一面之间的夹角β；即有机平坦化层6的侧壁的倾斜角度小于第一导电层5的源极51和漏极52的侧壁的倾斜角度；具体地，有机平坦部61靠近第一间隙54的侧壁与第一导电层5背离衬底基板1的一面之间的夹角α小于等于70°，即有机平坦部61虽然有侧壁，但是有机平坦部61的侧壁的坡度较缓，即使后续形成的有机有源层7在有机平坦部61的侧壁进行爬坡，也不会出现空隙，不会由于空隙而断裂。
另外，有机平坦部61的材料为有机材料，有机平坦部61的拐角部较为圆滑，有机平坦部61的拐角部可以是弧面，即有机平坦部61背离衬底基板1的一面与侧壁之间通过弧面连接。不会形成源极51和漏极52的拐角部的尖角结构。因此，后续形成的有机有源层7在有机平坦部61的拐角部的覆盖性较好，不会在拐角折弯处产生断裂不良。
但是，上述两种结构对工艺精度要求较高，因此，参照图1所示，有机平坦部61不仅设 置在第一间隙54内，而且突出于第一导电层5，使得有机平坦部61背离衬底基板1的一面与衬底基板1之间的距离大于第一导电层5背离衬底基板1的一面与衬底基板1之间的距离。而且，有机平坦部61的一部分设于第一导电层5背离衬底基板1的一侧，即有机平坦化层6有一部分设于源极51背离衬底基板1的一侧，有机平坦化层6还有一部分设于漏极52背离衬底基板1的一侧，使得有机平坦部61在衬底基板1上的正投影与源极51在衬底基板1上的正投影有交叠，有机平坦部61在衬底基板1上的正投影与漏极52在衬底基板1上的正投影有交叠。具体地，有机平坦部61在衬底基板1上的正投影与源极51在衬底基板1上的正投影交叠部分的宽度小于5微米，有机平坦部61在衬底基板1上的正投影与漏极52在衬底基板1上的正投影交叠部分的宽度也小于5微米，避免有机平坦部61将源极51和漏极52覆盖较多，后续形成的有机有源层7与源极51和漏极52连接不稳定。
另外，为了避免工艺或设备有误差时，有机平坦部231无法将第一间隙填满，有机平坦部61在衬底基板1上的正投影与源极51在衬底基板1上的正投影交叠部分的宽度大于等于2微米，例如，可以是2.5微米、2.85微米、3.1微米、3.6微米、4.25微米、4.7微米等等；同理，有机平坦部61在衬底基板1上的正投影与漏极52在衬底基板1上的正投影交叠部分的宽度也大于等于2微米，例如，可以是2.5微米、2.85微米、3.1微米、3.6微米、4.25微米、4.7微米等等。
当然，上述数据根据产品以及工艺设备的精度不同，还可以是其他值。
如此设置，使得有机平坦部61将源极51和漏极52之间的第一间隙54填满，而且有机平坦部61将源极51和漏极52的拐角部的尖角完全覆盖；使得后续形成的有机有源层7不需要在源极51和漏极52的侧壁进行爬坡，避免有机有源层7出现空隙，不会由于空隙而断裂；而且，对工艺以及设备精度要求较低，即使在制备过程中产生误差，有机平坦部61的位置有所偏移，有机平坦部61也会将源极51和漏极52之间的第一间隙54填满，而且有机平坦部61将源极51和漏极52的拐角部的尖角完全覆盖。
而且，有机平坦部61背离衬底基板1的一面与第一导电层5之间的距离H1可以小于第一导电层5在第三方向Z的厚度H2，即有机平坦部61突出第一导电层5的高度小于第一导电层5的厚度；第三方向Z与衬底基板1靠近第一电极层4的一面垂直。使得后续形成的有机有源层7在有机平坦部61的侧壁进行爬坡，但是爬坡高度较低，避免有机有源层7出现空隙，不会由于空隙而断裂。当然，在本公开的其他一些示例实施方式中，有机平坦部61背离衬底基板1的一面与第一导电层5之间的距离H1也可以等于或大于第一导电层5在第三方向Z的厚度H2。
再有，有机平坦化层6靠近第一间隙54的侧壁与第一导电层5靠近有机平坦化层6的一面之间的夹角α小于第一导电层5靠近第一间隙54的侧壁与第一电极层4靠近第一导电层5的一面之间的夹角β；即有机平坦化层6的侧壁的倾斜角度小于第一导电层5的源极51和漏极52的侧壁的倾斜角度；具体地，有机平坦部61靠近第一间隙54的侧壁与第一导电层5背离衬底基板1的一面之间的夹角α小于等于70°，即有机平坦部61虽然有侧壁，但是有机平 坦部61的侧壁的坡度较缓，即使后续形成的有机有源层7在有机平坦部61的侧壁进行爬坡，也不会出现空隙，不会由于空隙而断裂。
另外，有机平坦部61的材料为有机材料，有机平坦部61的拐角部较为圆滑，有机平坦部61的拐角部可以是弧面，即有机平坦部61背离衬底基板1的一面与侧壁之间可以通过弧面连接。不会形成源极51和漏极52的拐角部的尖角结构。因此，后续形成的有机有源层7在有机平坦部61的拐角部的覆盖性较好，不会在拐角折弯处产生断裂不良。当然，在本公开的其他一些示例实施方式中，有机平坦部61背离衬底基板1的一面与侧壁之间也可以直接连接，形成一个钝角。
而且，有机平坦化层6靠近第一间隙54的侧壁与第一导电层54背离衬底基板11的一面之间的夹角也不能太小，太小的话使得有机平坦部61的面积较大，从而使得后续形成的有机有源层7的面积较大，导致整个薄膜晶体管的面积较大，影响显示面板的开口率。具体地，有机平坦化层6靠近第一间隙54的侧壁与第一导电层54背离衬底基板11的一面之间的夹角大于等于30度，例如，有机平坦化层6靠近第一间隙54的侧壁与第一导电层54背离衬底基板11的一面之间的夹角可以是32度、36度、42.5度、46.8度、51度、54.7度、58.4度、62度、65.3度、67.5度等等。
有机平坦化层6的厚度大于等于300纳米小于等于800纳米，例如，有机平坦化层6的厚度可以是326纳米、375纳米、430纳米、480纳米、517纳米、589纳米、625纳米、673纳米、741纳米、789纳米等等。
在本示例实施方式中，参照图1所示，有机平坦化层6背离衬底基板1的一侧可以设置有有机有源层7，有机有源层7在有机平坦部61背离第一间隙54的一侧与源极51以及漏极52连接。有机有源层7的材质可以是有机半导体(OSC)材料。
由于有有机平坦化层6的平坦化和保护的作用，第一导电层5的材料的选择空间更大，使得该柔性阵列基板能够量产；而且，由于有机有源层7的有机半导体(OSC)材料是P型材料，第一导电层5需要与有机有源层7形成欧姆接触，第一导电层5需要选择功函数较大的材料，例如，第一导电层5的材料的功函数需要大于4.5eV；因此，考虑功函数的话，第一导电层5的材料可以是Ag+SAM，其功函数大约为5.86eV，Ag更靠近衬底基板1；可以是ITO(氧化铟锡)，其功函数大于等于4.57且小于等于4.93eV；可以是Mo+表面氧化(氧化钼)，其功函数大约为5.58eV，Mo更靠近衬底基板1；可以是Mo合金+表面氧化(氧化钼)，其功函数大约为5.5eV，Mo合金更靠近衬底基板1；也可以是TiN，其功函数大于等于4.49且小于等于5.29eV；也可以是Au，其功函数大约为5.2eV；还可以是Pt，其功函数大约为5.6eV；还可以是Pd，其功函数大约为5.12eV等等。
在同时考虑导电性能的情况下，第一导电层5可采用叠层方式，例如，第一导电层5可以包括依次层叠设置的BF(Buffer Film，缓冲膜)、LRF(Low Resistance Film，低电阻薄膜)、HWF(High Work Function Film，高功函数薄膜)；缓冲膜更靠近衬底基板1。缓冲膜可选：Mo、Mo合金、Ti、ITO、IZO(铟锌氧化物)等等；低电阻薄膜可选：Cu、Al、Ag等等；高 功函数薄膜可以是Ag+SAM，其功函数大约为5.86eV；可以是ITO(氧化铟锡)，其功函数大于等于4.57且小于等于4.93eV；可以是Mo+表面氧化(氧化钼)，其功函数大约为5.58eV，Mo更靠近衬底基板1；可以是Mo合金+表面氧化(氧化钼)，其功函数大约为5.5eV，Mo合金更靠近衬底基板1；也可以是TiN，其功函数大于等于4.49且小于等于5.29eV；也可以是Au，其功函数大约为5.2eV；还可以是Pt，其功函数大约为5.6eV；还可以是Pd，其功函数大约为5.12eV等等。
SAM是自组装单层膜，可形成单分子层，对第一导电层4与有机有源层7之间的界面起修饰作用，提高功函数。
现有技术中，第一导电层5的材料为MoAlMo的层叠结构或MoNd/Cu/MoNd的层叠结构，因表面为Mo或Mo合金材料，功函数较小(≤4.5eV)，不满足需求；而本公开进行表面氧化处理，处理方式有退火、等离子体等，使得功函数增大至大于等于4.5eV，而且表面氧化处理过程温度较低，一般不超过100℃。
在本示例实施方式中，参照图1所示，在有机有源层7背离衬底基板1的一侧可以设置有栅绝缘层组8，栅绝缘层组8在衬底基板1上的正投影与有机有源层7在衬底基板1上的正投影重合，即栅绝缘层组8在衬底基板1上的正投影与有机有源层7在衬底基板1上的正投影完全重合，使得栅绝缘层组8和有机有源层7可以通过同一次构图工艺形成，减少工艺步骤、降低成本。
参照图1所示，栅绝缘层组8可以包括第一栅绝缘层81和第二栅绝缘层82，第一栅绝缘层81设于有机有源层7背离衬底基板1的一侧，第一栅绝缘层81需要是柔性膜层，具有绝缘性；而且与刻蚀有机有源层7的溶剂正交且匹配性能较佳，即第一栅绝缘层81的材料与有机有源层7的材料不会发生反应，确保有机有源层7的沟道特性；具体例如，第一栅绝缘层81的材料可以是低介电常数的材料。
需要说明的是，正交溶剂是指极性相差较大的溶剂。正交溶剂体系是为了施加后续的层而使用的一种溶剂体系，在该溶剂体系中先前施加的层是不可溶的。
第二栅绝缘层82设于第一栅绝缘层81背离衬底基板1的一侧，第二栅绝缘层82对栅极层9的刻蚀液的阻挡性能强于第一栅绝缘层81对栅极层9的刻蚀液的阻挡性能。第二栅绝缘层82需要是柔性膜层，具有绝缘性，环境稳定性佳，可阻水氧；可以是交联材料，交联材料就是这些进行了交联反应的材料，交联反应是指两个或者更多的分子(一般为线型分子)相互键合交联成网络结构的较稳定分子(体型分子)反应。这种反应使线型或轻度支链型的大分子转变成三维网状结构，以此提高强度、耐热性、耐磨性、耐溶剂性等性能；具体例如，第二栅绝缘层82的材料可以是可交联的介电材料，可提高电气耐用性。
参照图1、图5和图6所示，在栅绝缘层组8背离衬底基板1的一侧可以设置有栅极层9，栅极层9可以包括栅极91，栅极层9在衬底基板1上的正投影与有机有源层7在衬底基板1上的正投影重合，即栅极层9在衬底基板1上的正投影与有机有源层7在衬底基板1上的正投影完全重合，使得栅极层9和有机有源层7可以通过同一次构图工艺形成，减少工艺步骤、 降低成本。栅极层9在衬底基板1上的正投影可以位于遮光层3在衬底基板1上的正投影内。
由于栅极层9、栅绝缘层组8以及有机有源层7通过同一次构图工艺形成，但是，在仅设置有第一栅绝缘层81的情况下，由于第一栅绝缘层81和有机有源层7的阻挡性较差，在对栅极材料层90进行刻蚀时，刻蚀液容易穿透第一栅绝缘层81和有机有源层7对第一导电层5进行腐蚀，在栅绝缘层组8包括第一栅绝缘层81和第二栅绝缘层82的情况下，由于第二栅绝缘层82对栅极层9的刻蚀液的阻挡性能强于第一栅绝缘层81对栅极层9的刻蚀液的阻挡性能。在对栅极材料层90进行刻蚀的过程中，第二栅绝缘材料层820能够对第一导电层5进行保护，避免栅极层9的刻蚀液对第一导电层5造成腐蚀，保证第一导电层5的电性能，从而保证阵列基板的性能。
因此，在刻蚀形成栅极层9的过程中，栅极层9可以对其下方的栅绝缘层组8以及有机有源层7进行保护，避免栅极层9的刻蚀液对第一导电层5造成腐蚀，因此，栅极层9的材料的选择空间较大，使得该柔性阵列基板能够量产；例如，栅极层9的材料可以是Ag、Mo、Cu、Al、Ti、ITO、ITO/Ag/ITO的层叠结构、Mo/Al/Mo的层叠结构、Mo/Cu/Mo的层叠结构、Ti/Al/Ti的层叠结构等等。
在本示例实施方式中，参照图1所示，在栅极层9背离衬底基板1的一侧可以设置有钝化层10，钝化层10需要是柔性膜层，具有绝缘性，环境稳定性佳，可阻水氧，具体可以是交联材料；钝化层10的材料可以与第二栅绝缘层82的材料相同。
参照图9所示，在钝化层10上设置有第一过孔101，第一过孔101连通至栅极91。
参照图1、图7、图8和图9所示，在钝化层10背离衬底基板1的一侧可以设置有第二电极层11，第二电极层11的材质可以是透明导电材料，例如，ITO(氧化铟锡)、IZO(铟锌氧化物)等等。第二电极层11包括间隔设置的第二电极111和栅线连接部112，第二电极111可以是公共电极，因此，多个第二电极111是需要连接在一起的，而栅线连接部112是需要与栅极91连接的，因此，第二电极111与栅线连接部112需要间隔设置；具体结构可以是第二电极111可以设置为沿第一方向X延伸的条状，栅极连接部112可以设置为沿第一方向X延伸的条状，第二电极111与栅极连接部112可以在第二方向上交替设置，即在相邻两个第二电极111之间设置有一个栅极连接部112，在相邻两个栅极连接部112之间设置有一个第二电极111。多个第二电极111可以在周边区域进行连接，当然，多个第二电极111也可以通过其他导电膜层桥接。
栅极连接部112单独作为栅线，栅极连接部112可以沿第一方向X延伸，栅极连接部112通过钝化层10上的第一过孔101连接于相邻两个栅极91，多个沿第一方向X排列的栅极91通过多个栅极连接部112连接在一起，栅极连接部112做为栅线为各个栅极91提供扫描信号。
参照图12和图13所示，在本公开的一些示例实施方式中，栅极层9不仅可以包括栅极91，还可以包括栅极延伸部92，栅极延伸部92连接于栅极91的第一方向X的相对两侧，但是，由于栅极延伸部92与栅极91、栅绝缘层组8以及有机有源层7是通过同一道图案化工艺形成的，为了避免不同薄膜晶体管的有机有源层7之间相互连接，栅极延伸部92与相邻的另 一个栅极91之间是间隔设置的，栅极延伸部92沿第一方向X延伸，第一方向X与衬底基板1靠近第一导电层5的一面平行。当然，栅极延伸部92可以连接于栅极91的第一方向X的一侧。
栅极延伸部92在衬底基板1上的正投影的一部分可以位于遮光层3在衬底基板1上的正投影内，栅极延伸部92在衬底基板1上的正投影的另一部分可以位于遮光层3在衬底基板1上的正投影外，即栅极延伸部92在第一方向上突出于遮光层3。
由于栅极层9的材质是金属，电阻较低，如此设置可以减小栅线的电阻，减小阵列基板的功耗。
这种情况下，在栅极层9背离衬底基板1的一侧可以设置有钝化层10，钝化层10需要是柔性膜层，具有绝缘性，环境稳定性佳，可阻水氧，具体可以是交联材料；钝化层10的材料可以与第二栅绝缘层82的材料相同。
参照图9所示，在钝化层10上设置有第一过孔101，第一过孔101连通至栅极延伸部92。
参照图1、图14、图15和图9所示，在钝化层10背离衬底基板1的一侧可以设置有第二电极层11，第二电极层11的材质可以是透明导电材料，例如，ITO(氧化铟锡)、IZO(铟锌氧化物)等等。第二电极层11包括间隔设置的第二电极111和栅极连接部112，第二电极111可以是公共电极，因此，多个第二电极111是需要连接在一起的，而栅极连接部112是需要与栅极延伸部92连接的，因此，第二电极111与栅极连接部112需要间隔设置；具体结构可以是在第二电极层11上设置多个开口形成第二电极层11，在开口内设置有栅极连接部112。
栅极连接部112和栅极延伸部92共同作为栅线，栅极连接部112可以沿第一方向X延伸，栅极连接部112通过钝化层10上的第一过孔101连接于相邻两个栅极延伸部92，即栅极连接部112与栅极延伸部92连接共同形成栅线，以连接多个沿第一方向X排列的栅极91，为各个栅极91提供扫描信号。
进一步地，参照图16所示，阵列基板还可以包括导电增强层15，导电增强层15设于第二电极层11背离衬底基板1的一侧，导电增强层15在衬底基板1上的正投影与栅极连接部112在衬底基板1上的正投影重合，即导电增强层15没有设置在第二电极111背离衬底基板1的一侧，以保证阵列基板的透光面积，即保证阵列基板的开口率。导电增强层15的材质为金属，电阻较小，通过导电增强层15可以减小栅极连接部112的电阻，进而减小阵列基板的栅线的电阻、降低功耗，保证阵列基板第二电极111的电场均一性。当然，在本公开的其他一些示例实施方式中，参照图17所示，导电增强层15也可以设置在第二电极111背离衬底基板1的一侧，但是，仅仅在第二电极111的不是显示区的区域内设置导电增强层15，例如，可以第二电极111与数据线53重叠的部分设置导电增强层15。
进一步地，参照图18所示，阵列基板还可以包括保护层14，保护层14至少覆盖有机有源层7的侧壁，保护层14可以对有机有源层7进行保护。
在本示例实施方式中，保护层14设于栅极层9以及有机平坦化层6与钝化层10之间，且覆盖有机有源层7、栅绝缘层组8和栅极91的侧壁。即在形成栅极层9之后再形成保护层 14。
保护层14的厚度大于等于1000埃且小于等于3000埃，例如，保护层14的厚度可以是1030埃、1085埃、1162埃、1238埃、1348埃、1586埃、1651埃、1752埃、1830埃、1985埃、2162埃、2338埃、2481埃、2568埃、2615埃、2725埃、2856埃、2965埃等等。
保护层14的材质可以与第一删绝缘层81材料或第一平坦化层21材料相同，第一删绝缘层81的材料和第一平坦化层21的材料的具体要求上述已经进行了详细说明，因此，此处不再赘述。
保护层14与有机有源层7的匹配性强于钝化层10与有机有源层7的匹配性。通过保护层14可以避免有机有源层7与钝化层10接触。由于有机有源层7与钝化层10之间的材料匹配性较差，例如，有机有源层7与钝化层10会反应，在成膜过程中会产出额外副产物，或，有机有源层7与钝化层10会发生互溶现象，导致有机有源层7和钝化层10损伤。而保护层14与有机有源层7之间的材料匹配性较较好，即保护层14的材料与有机有源层7的材料溶剂正交，即保护层14的材料与有机有源层7的材料互不反应，使得保护层14和有机有源层7能够保持完整性，而且提升薄膜晶体管的稳定性，保证阵列基板的性能。
这种情况下，参照图19所示，栅极连接部112可以通过钝化层10上的第一过孔101以及保护层14上的第四过孔141连接至栅极91，而且钝化层10上的第一过孔101与保护层14上的第四过孔141可以通过同一次构图工艺形成。
参照图20所示，在本公开的另一些示例实施方式中，遮光层3可以设置为沿第一方向X延伸的条状，一个遮光层3可以与沿第一方向X排列的多个薄膜晶体管相对应，即沿第一方向X排列的多个有机有源层7在衬底基板1上的正投影位于遮光层3在衬底基板1上的正投影之内。
这种情况下，在栅极层9背离衬底基板1的一侧可以设置有钝化层10，钝化层10需要是柔性膜层，具有绝缘性，环境稳定性佳，可阻水氧，具体可以是交联材料；钝化层10的材料可以与第二栅绝缘层82的材料相同。
在钝化层10上设置有第一过孔101和第二过孔102，第一过孔101连通至栅极91。在第二平坦化层22上设置有第三过孔221，第二过孔102与第三过孔221连通，并连通至遮光层3
在钝化层10背离衬底基板1的一侧可以设置有第二电极层11，第二电极层11的材质可以是透明导电材料，例如，ITO(氧化铟锡)、IZO(铟锌氧化物)等等。第二电极层11可以包括间隔设置的第二电极111和栅极连接部112，第二电极111可以是公共电极。栅极连接部112与第二电极111间隔设置，栅极连接部112通过第一过孔101连接至栅极91，并通过第二过孔102和第三过孔221连接至遮光层3，遮光层3复用为栅线和第二栅极91。使得薄膜晶体管包括两个栅极91，而且，两个栅极91分别位于有机有源层7的上下两侧，保证薄膜晶体管的性能。
基于同一发明构思，本公开示例实施方式提供了一种阵列基板的制备方法，参照图21所 示，该阵列基板的制备方法可以包括以下步骤：
步骤S10，提供衬底基板。
步骤S20，在所述衬底基板的一侧形成依次层叠设置的第一电极层和第一导电层，所述第一电极层包括第一电极，所述第一导电层包括源极和漏极，所述源极和所述漏极之间设置有第一间隙，所述漏极在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影有交叠。
步骤S30，形成有机平坦化层，所述有机平坦化层包括多个间隔设置的有机平坦部，所述有机平坦部至少设于所述第一间隙内。
步骤S40，在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层，所述有机有源层在所述有机平坦部背离所述第一间隙的一侧与所述源极以及所述漏极连接。
其中，有机平坦部61至少未覆盖源极51和漏极52背离第一间隙54的端部，有机平坦部61靠近第一间隙54的侧壁与第一导电层5靠近有机平坦化层6的一面之间的夹角小于第一导电层5靠近第一间隙54的侧壁与第一电极层4靠近第一导电层5的一面之间的夹角。
本公开的阵列基板可以通过六次图案化处理工艺形成。下面对阵列基板100的制备方法的各个步骤进行详细说明。
提供衬底基板1，具体为，参照图22所示，提供玻璃基板13，在玻璃基板13上通过粘接层12(图22-图40中未示出)粘接衬底基板1。在衬底基板1背离玻璃基板13的一侧形成第一平坦化层21。
参照图23、图2和图24所示，在第一平坦化层21背离衬底基板1的一侧形成遮光材料层，并对遮光材料层进行图案化处理工艺形成遮光层3。至此完成第一次图案化处理工艺。遮光层3的具体结构上述已经进行了详细说明，因此此处不再赘述。
参照图25和图26所示，在遮光层3背离衬底基板1的一侧依次形成第二平坦化层22、第一电极材料层40以及第一导电材料层50。
然后，对掩模层进行半掩模工艺形成掩模图案16，具体为，在第一导电材料层50背离衬底基板1的一侧形成掩模层，在掩模层背离衬底基板1的一侧放置掩模板，掩模板可以包括透光部、遮光部31以及半透光部；半透光部与第二部分162相对设置，即半透光部在衬底基板1上的正投影与第二部分162在衬底基板1上的正投影重合；遮光部31与第一部分161相对设置，即遮光部31在衬底基板1上的正投影与第一部分161在衬底基板1上的正投影重合。透光部与掩模层的其他部分相对设置。
然后，参照图27所示，对掩模层进行曝光显影形成掩模图案16，掩模图案16包括第一部分161和第二部分162，即去除与透光部相对设置的掩模层；与半透光部相对设置的掩模层去除一定厚度，形成第二部分162；与遮光部31相对设置的掩模层完全保留，形成第一部分161，使得第一部分161的厚度大于第二部分162的厚度，第一部分161与第一导电层5以及第一电极层4的一部分相对设置，第二部分162与第一电极层4的另一部分相对设置。
参照图28所示，对裸露的第一导电材料层50进行第一次刻蚀去除，且对第一电极材料 层40进行刻蚀去除形成第一电极层4，形成源极51与漏极52之间的第一间隙54和第一电极41与降阻连接部42之间的第二间隙43；保留被掩模图案16覆盖的第一电极层4和剩余的第一导电材料层50。
参照图29所示，对掩模图案16进行灰化处理，以去除第二部分162，使第二部分162覆盖的第一导电材料层50裸露；灰化工艺采用的气体可以包括SF6和O2。通过灰化工艺去除第二部分162，使得第二部分162覆盖的第一导电材料层50裸露，而且第一部分161的厚度也有减薄。
参照图30和图31所示，对剩余的第一导电材料层50进行图案化处理形成第一导电层5，即将第二部分162覆盖的第一导电材料层50刻蚀去除，保留第一部分161覆盖的第一导电材料层50形成第一导电层5。最后，去除剩余的第一部分161。至此完成第二次图案化处理工艺。
参照图32和图33所示，在第一导电层5背离衬底基板1的一侧形成有机平坦化层6，并对有机平坦化层6进行图案化处理形成多个间隔设置的有机平坦部61。至此完成第三次图案化处理工艺。
参照图34所示，在有机平坦部61背离衬底基板1的一侧依次形成有机有源材料层70、第一栅绝缘材料层810、第二栅绝缘材料层820以及栅极材料层；并在栅极材料层背离衬底基板1的一侧形成掩模层，对掩模层进行曝光显影形成第二掩模图案17。参照图35所示，以第二掩模图案17为掩模对栅极材料层进行刻蚀形成栅极层9。参照图36和37所示，去除第二掩模图案17，以栅极层9为掩模对第一栅绝缘材料层810、第二栅绝缘材料层820以及有机有源材料层70进行刻蚀形成栅绝缘层组8(第一栅绝缘层81、第二栅绝缘层82)以及有机有源层7。当然，也可以在形成栅绝缘层组8以及有机有源层7之后，再去除掩模图案16。至此完成第四次图案化处理工艺。
参照图38所示，在栅极层9背离衬底基板1的一侧形成钝化层10。参照图39所示，对钝化层10进行图案化处理形成第一过孔101和第二过孔102，且在第二平坦化层22上形成第三过孔221。至此完成第五次图案化处理工艺。另外，在本公开的其他一些示例实施方式中，参照图9所示，可以对钝化层10进行图案化处理仅形成第一过孔101。
在本公开的另一些示例实施方式中，参照图17所示，在阵列基板包括保护层14的情况下，在栅极层9背离衬底基板1的一侧依次形成保护层14和钝化层10，并对钝化层10进行图案化处理形成第一过孔101，且同时对保护层14进行图案化处理形成第四过孔141，第四过孔141与第一过孔101连通；或者，对钝化层10进行图案化处理形成第一过孔101和第二过孔102，且在第二平坦化层22上形成第三过孔221，且同时对保护层14进行图案化处理形成第四过孔141和第五过孔，第四过孔141与第一过孔101连通，第五过孔与第二过孔102和第三过孔221连通。至此完成第五次图案化处理工艺。
参照图20和图40所示，在钝化层10背离衬底基板1的一侧形成第二电极材料层，并对第二电极材料层进行图案化处理形成第二电极层11和栅极连接部112。至此完成第六次图案 化处理工艺。
在本公开的另一些示例实施方式中，参照图16和图17所示，在阵列基板包括导电增强层15的情况下，在钝化层10背离衬底基板1的一侧依次形成第二电极材料层和导电增强材料层，并对导电增强材料层进行图案化处理形成导电增强层15，且同时对第二电极材料层进行图案化处理形成第二电极层11和栅极连接部112，由于导电增强层15和第二电极层11形成的面积并不相同，因此，第二电极层11和导电增强层15的形成工艺与栅极层9以及有机有源层7的形成工艺相同，即对掩模层先进行半掩模工艺，再进行灰化工艺，具体步骤在此不再赘述。至此完成第六次图案化处理工艺。
需要说明的是，尽管在附图中以特定顺序描述了本公开中阵列基板的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
基于同一发明构思，本公开示例实施方式提供了一种显示面板，该显示面板为液晶显示面板，该显示面板可以包括阵列基板、彩膜基板以及液晶层；阵列基板可以是上述任意一项所述的阵列基板，阵列基板的具体结构上述已经进行了详细说明，因此此处不再赘述；彩膜基板与阵列基板相对设置；液晶层设于阵列基板与彩膜基板之间。
彩膜基板可以为柔性彩膜基板，彩膜基板可以包括柔性衬底，设于柔性衬底一侧的遮光部31和滤光部，滤光部可以包括红色滤光部、绿色滤光部、蓝色滤光部等等。
基于同一发明构思，本公开示例实施方式提供了一种显示装置，显示装置可以为滑卷显示装置、可折叠显示装置或曲面显示装置，显示装置可以包括上述任意一项所述的显示面板，显示面板的具体结构上述已经进行了详细说明，因此此处不再赘述。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (30)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    第一电极层，设于所述衬底基板的一侧，所述第一电极层包括第一电极；
    第一导电层，设于所述第一电极层背离所述衬底基板的一侧，所述第一导电层包括源极和漏极，所述源极和所述漏极之间设置有第一间隙，所述漏极在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影有交叠；
    有机平坦化层，包括多个间隔设置的有机平坦部，所述有机平坦部至少设于所述第一间隙内，且所述有机平坦部至少未覆盖所述源极和所述漏极背离所述第一间隙的端部，所述有机平坦部靠近所述第一间隙的侧壁与所述第一导电层靠近所述有机平坦化层的一面之间的夹角小于所述第一导电层靠近所述第一间隙的侧壁与所述第一电极层靠近所述第一导电层的一面之间的夹角；
    有机有源层，设于所述有机平坦化层背离所述衬底基板的一侧，所述有机有源层在所述有机平坦部背离所述第一间隙的一侧与所述源极以及所述漏极连接。
  2. 根据权利要求1所述的阵列基板，其中，所述有机平坦部背离所述衬底基板的一面与所述衬底基板之间的距离大于或等于所述第一导电层背离所述衬底基板的一面与所述衬底基板之间的距离。
  3. 根据权利要求2所述的阵列基板，其中，所述有机平坦部的一部分设于所述第一导电层背离所述衬底基板的一侧，在靠近所述第一间隙的位置，所述有机平坦部在所述衬底基板上的正投影与所述源极在所述衬底基板上的正投影有交叠，且所述有机平坦部在所述衬底基板上的正投影与所述漏极在所述衬底基板上的正投影有交叠。
  4. 根据权利要求1～3任意一项所述的阵列基板，其中，所述有机平坦部靠近所述第一间隙的侧壁与所述第一导电层靠近所述有机平坦化层的一面之间的夹角小于等于70°。
  5. 根据权利要求1所述的阵列基板，其中，所述有机平坦部背离所述衬底基板的一面与所述第一导电层之间的距离小于所述第一导电层在第三方向的厚度，所述第三方向与所述衬底基板靠近所述第一电极层的一面垂直。
  6. 根据权利要求1所述的阵列基板，其中，所述有机平坦部背离所述衬底基板的一面与所述有机平坦部的侧壁之间通过弧面连接。
  7. 根据权利要求1所述的阵列基板，其中，所述第一导电层还包括数据线，所述数据线与所述源极连接，所述第一电极层还包括：
    降阻连接部，与所述第一电极间隔设置，所述源极以及所述数据线在所述衬底基板上的正投影位于所述降阻连接部在所述衬底基板上的正投影之内。
  8. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    栅绝缘层组，设于所述有机有源层背离所述衬底基板的一侧，所述栅绝缘层组在所述衬底基板上的正投影与所述有机有源层在所述衬底基板上的正投影重合；
    栅极层，设于所述栅绝缘层组背离所述衬底基板的一侧，所述栅极层包括栅极，所述栅极在所述衬底基板上的正投影与所述有机有源层在所述衬底基板上的正投影重合。
  9. 根据权利要求8所述的阵列基板，其中，所述栅绝缘层组包括：
    第一栅绝缘层，设于所述有机有源层背离所述衬底基板的一侧；
    第二栅绝缘层，设于所述第一栅绝缘层背离所述衬底基板的一侧，所述第二栅绝缘层对所述栅极层的刻蚀液的阻挡性能强于所述第一栅绝缘层对所述栅极层的刻蚀液的阻挡性能。
  10. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    钝化层，设于所述栅极层背离所述衬底基板的一侧；
    第二电极层，设于所述钝化层背离所述衬底基板的一侧，所述第二电极层包括间隔设置的第二电极和栅极连接部，所述栅极连接部连接于相邻两个所述栅极。
  11. 根据权利要求8所述的阵列基板，其中，所述栅极层还包括：
    栅极延伸部，所述栅极延伸部连接于所述栅极的第一方向的至少一侧，所述第一方向与所述阵列基板靠近所述第一电极层的一面平行。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括：
    钝化层，设于所述栅极层背离所述衬底基板的一侧；
    第二电极层，设于所述钝化层背离所述衬底基板的一侧，所述第二电极层包括间隔设置的第二电极和栅极连接部，所述栅极连接部连接于相邻两个所述栅极延伸部。
  13. 根据权利要求10或12所述的阵列基板，其中，所述阵列基板还包括：
    导电增强层，设于所述第二电极层背离所述衬底基板的一侧，所述导电增强层在所述衬底基板上的正投影位于所述栅极连接部在所述衬底基板上的正投影之内。
  14. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    遮光层，设于所述衬底基板的一侧，所述有机有源层在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之内；
    第二平坦化层，设于所述遮光层背离所述衬底基板的一侧，所述第一电极层设于所述第二平坦化层背离所述衬底基板的一侧，所述第二平坦化层上设置有第三过孔；
    钝化层，设于所述栅极层背离所述衬底基板的一侧，所述钝化层上设置有第一过孔和第二过孔，所述第一过孔连通至所述栅极，所述第二过孔与所述第三过孔连通，并连通至所述遮光层；
    第二电极层，设于所述钝化层背离所述衬底基板的一侧，所述第二电极层包括间隔设置的第二电极和栅极连接部，所述栅极连接部通过所述第一过孔连接至所述栅极，并通过所述第二过孔和所述第三过孔连接至所述遮光层，所述遮光层复用为栅线和第二栅极。
  15. 根据权利要求10或12所述的阵列基板，其中，所述阵列基板还包括：
    保护层，至少覆盖所述有机有源层的侧壁。
  16. 根据权利要求15所述的阵列基板，其中，所述保护层设于所述栅极层以及所述第一电极与所述钝化层之间，且覆盖所述有机有源层、所述栅绝缘层组和所述栅极的侧壁，所述 保护层与所述有机有源层的匹配性强于所述钝化层与所述有机有源层的匹配性。
  17. 根据权利要求1所述的阵列基板，其中，所述第一导电层的功函数大于4.5eV。
  18. 根据权利要求1所述的阵列基板，其中，所述阵列基板为柔性阵列基板。
  19. 一种阵列基板的制备方法，其中，包括：
    提供衬底基板；
    在所述衬底基板的一侧形成依次层叠设置的第一电极层和第一导电层，所述第一电极层包括第一电极，所述第一导电层包括源极和漏极，所述源极和所述漏极之间设置有第一间隙，所述漏极在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影有交叠；
    形成有机平坦化层，所述有机平坦化层包括多个间隔设置的有机平坦部，所述有机平坦部至少设于所述第一间隙内；
    在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层，所述有机有源层在所述有机平坦部背离所述第一间隙的一侧与所述源极以及所述漏极连接；
    其中，所述有机平坦部至少未覆盖所述源极和所述漏极背离所述第一间隙的端部，所述有机平坦部靠近所述第一间隙的侧壁与所述第一导电层靠近所述有机平坦化层的一面之间的夹角小于所述第一导电层靠近所述第一间隙的侧壁与所述第一电极层靠近所述第一导电层的一面之间的夹角。
  20. 根据权利要求19所述的阵列基板的制备方法，其中，在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层的同时形成栅绝缘层组以及栅极层。
  21. 根据权利要求20所述的阵列基板的制备方法，其中，在所述有机平坦化层背离所述衬底基板的一侧形成有机有源层的同时形成栅绝缘层组以及栅极层，包括：
    在所述有机平坦化层背离所述衬底基板的一侧依次形成有机有源材料层、栅绝缘材料层组以及栅极材料层；
    对所述栅极材料层进行图案化处理形成所述栅极层；
    以所述栅极层为掩模对所述栅绝缘材料层组以及所述有机有源材料层进行图案化处理形成所述栅绝缘层组和所述有机有源层。
  22. 根据权利要求19所述的阵列基板的制备方法，其中，在所述衬底基板的一侧形成依次层叠设置的第一电极层和第一导电层，包括：
    在所述衬底基板的一侧依次形成第一电极材料层和第一导电材料层，
    在所述第一导电材料层背离所述衬底基板的一侧形成掩模层，对所述掩模层进行半掩模工艺形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度，所述第一部分与所述第一导电层以及所述第一电极层的一部分相对设置，所述第二部分与另一部分所述第一电极层相对设置；
    对裸露的第一导电材料层进行刻蚀去除，且对所述第一电极材料层进行刻蚀去除形成所述第一电极层；
    对所述掩模图案进行灰化处理，以去除所述第二部分，使所述第二部分覆盖的所述第一 导电材料层裸露；
    对剩余的第一导电材料层进行图案化处理形成所述第一导电层。
  23. 根据权利要求20所述的阵列基板的制备方法，其中，所述制备方法还包括：
    在所述栅极层背离衬底基板的一侧形成钝化层，并对所述钝化层进行图案化处理形成第一过孔。
  24. 根据权利要求20所述的阵列基板的制备方法，其中，所述制备方法还包括：
    在所述栅极层背离衬底基板的一侧依次形成保护层和钝化层，并对所述钝化层进行图案化处理形成第一过孔，且同时对所述保护层进行图案化处理形成第四过孔。
  25. 根据权利要求20所述的阵列基板的制备方法，其中，所述制备方法还包括：
    在所述栅极层背离衬底基板的一侧依次形成保护层和钝化层，并对所述钝化层进行图案化处理形成第一过孔和第二过孔，并同时对所述保护层进行图案化处理形成第四过孔和第五过孔，且同时对第二平坦化层进行图案化处理形成第三过孔，所述第四过孔与所述第一过孔连通，所述第五过孔与所述第二过孔和所述第三过孔连通。
  26. 根据权利要求23或24所述的阵列基板的制备方法，其中，所述制备方法还包括：
    在所述钝化层背离衬底基板的一侧形成第二电极材料层，并对所述第二电极材料层进行图案化处理形成第二电极层。
  27. 根据权利要求23或24所述的阵列基板的制备方法，其中，
    所述制备方法还包括：
    在所述钝化层背离衬底基板的一侧依次形成第二电极材料层和导电增强材料层，并对导电增强材料层和第二电极材料层进行图案化处理形成导电增强层和第二电极层。
  28. 一种显示面板，其中，包括：
    阵列基板，是权利要求1～18任意一项所述的阵列基板；
    彩膜基板，与所述阵列基板相对设置；
    液晶层，设于所述阵列基板与所述彩膜基板之间。
  29. 根据权利要求28所述的显示面板，其中，所述阵列基板为柔性阵列基板，所述彩膜基板为柔性彩膜基板。
  30. 一种显示装置，其中，包括：权利要求28或29所述的显示面板，所述显示装置为滑卷显示装置、可折叠显示装置或曲面显示装置。
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JPH11183929A (ja) * 1997-12-24 1999-07-09 Toshiba Corp 液晶表示素子
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CN101944535A (zh) * 2009-07-07 2011-01-12 乐金显示有限公司 用于液晶显示装置的阵列基板及其制造方法
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CN107275366A (zh) * 2016-03-31 2017-10-20 三星显示有限公司 显示装置及其制造方法
CN108933179A (zh) * 2018-07-05 2018-12-04 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制作方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11183929A (ja) * 1997-12-24 1999-07-09 Toshiba Corp 液晶表示素子
WO2007119442A1 (ja) * 2006-03-29 2007-10-25 Brother Kogyo Kabushiki Kaisha 電荷移動度が改善された有機トランジスタ及びその製造方法
CN101944535A (zh) * 2009-07-07 2011-01-12 乐金显示有限公司 用于液晶显示装置的阵列基板及其制造方法
CN102496625A (zh) * 2011-08-15 2012-06-13 友达光电股份有限公司 薄膜晶体管、画素结构及其制造方法
CN104078423A (zh) * 2014-06-24 2014-10-01 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
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