WO2024122495A1 - 半導体素子の製造方法および製造装置 - Google Patents

半導体素子の製造方法および製造装置 Download PDF

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Publication number
WO2024122495A1
WO2024122495A1 PCT/JP2023/043286 JP2023043286W WO2024122495A1 WO 2024122495 A1 WO2024122495 A1 WO 2024122495A1 JP 2023043286 W JP2023043286 W JP 2023043286W WO 2024122495 A1 WO2024122495 A1 WO 2024122495A1
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Prior art keywords
manufacturing
growth substrate
substrate
support substrate
semiconductor device
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PCT/JP2023/043286
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English (en)
French (fr)
Japanese (ja)
Inventor
賢太郎 村川
元久 宇佐川
知紘 北林
幸介 太田
佳伸 川口
剛 神川
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Kyocera Corp
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Kyocera Corp
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Priority to JP2024562760A priority Critical patent/JP7854514B2/ja
Publication of WO2024122495A1 publication Critical patent/WO2024122495A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Definitions

  • This disclosure relates to a method and apparatus for manufacturing semiconductor devices.
  • the method for manufacturing a semiconductor element according to the present disclosure includes the steps of bonding a plurality of elements, each of which includes a semiconductor layer grown on a growth substrate, to the surface of a support substrate, applying an external force to the back surface of one of the growth substrate and the support substrate such that the pressure distribution is non-uniform within the surface, and peeling off the plurality of elements bonded to the support substrate from the growth substrate.
  • FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment.
  • FIG. 2 is a plan view showing a growth substrate and a number of elements.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are plan views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a manufacturing apparatus for a semiconductor element according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a manufacturing apparatus for a semiconductor element according to an embodiment of the present invention.
  • 4 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor element according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a manufacturing apparatus for a semiconductor element according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a manufacturing apparatus for a semiconductor element according to an embodiment of the present invention.
  • 1 is a plan view showing a configuration of a semiconductor substrate according to an embodiment
  • 1 is a plan view showing a configuration of a semiconductor substrate according to an embodiment
  • FIG. 23 is a cross-sectional view of FIG. 21 and FIG. 22.
  • 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment.
  • 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment.
  • FIG. 1 is a flowchart showing a method for manufacturing a semiconductor element according to this embodiment.
  • FIG. 2 is a plan view showing a growth substrate and a plurality of elements.
  • FIGS. 3 to 5 are cross-sectional views showing the method for manufacturing a semiconductor element according to this embodiment.
  • FIG. 6 is a plan view showing the method for manufacturing a semiconductor element according to this embodiment. As shown in FIGS.
  • the method for manufacturing a semiconductor element includes a step (S10) of bonding a plurality of elements SL, each of which includes a semiconductor layer 8 grown on a growth substrate TS, to the surface of a support substrate MS, a step (S20) of applying an external force to the back surface UF of one of the growth substrate TS and the support substrate MS so as to result in an in-plane non-uniform pressure distribution, and a step (S30) of peeling off the plurality of elements SL bonded to the support substrate MS from the growth substrate TS.
  • the elements SL when multiple elements SL are bonded to the surface of the support substrate MS, for example, by applying an external force to the back surface UT of the growth substrate TS that results in a non-uniform pressure distribution in the plane, the elements SL will tilt with respect to the growth substrate TS, and the bonded portion J can be easily broken. Specifically, by creating a pressure distribution in which the pressure changes in the first direction X, the bonded portion J with the growth substrate TS will tilt with respect to the normal to the growth substrate TS, and shear stress will concentrate near the interface between the growth substrate TS and the bonded portion J, causing the bonded portion J to break. It is preferable to apply an external force to the back surface UM of the support substrate MS that results in a pressure distribution that is uniform in the plane and does not change over time.
  • the method of manufacturing a semiconductor element according to this embodiment improves the yield when transferring multiple elements SL to a support substrate MS.
  • the growth substrate TS and the support substrate MS may be rigid substrates.
  • Each of the growth substrate TS and the support substrate MS may include a silicon-based substrate (e.g., a Si substrate, a SiC substrate).
  • the growth substrate TS may include a base substrate BS and a mask pattern 6 including a mask portion 5 and an opening K.
  • the bonding material that bonds the element SL and the support substrate MS may be rigid. This can further increase the yield.
  • the semiconductor layer 8 contains a nitride semiconductor as a main component.
  • Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride).
  • a GaN-based semiconductor is a semiconductor that contains gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
  • the semiconductor layer 8 may be doped (e.g., n-type containing a donor) or non-doped.
  • the growth substrate TS includes a main substrate 1.
  • the main substrate 1 and the underlayer 4 are sometimes referred to as a base substrate BS.
  • the growth substrate TS includes a plurality of seed regions SA arranged in stripes in the first direction X, and each of the multiple elements SL may be connected to a plurality of seed regions SA.
  • the multiple elements SL may be spaced apart in the first direction X, and a gap GP may be formed between two adjacent elements SL.
  • the first direction X may be the a-axis direction ( ⁇ 11-20> direction) of the semiconductor layer 8 (a nitride semiconductor such as GaN).
  • the second direction Y may be the m-axis direction ( ⁇ 1-100> direction) of the semiconductor layer 8.
  • the third direction Z may be the c-axis direction ( ⁇ 0001> direction) of the semiconductor layer 8.
  • the semiconductor layer 8 can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the base layer 4 (seed area SA) exposed under the opening K.
  • the base layer 4 may be, for example, a single layer of AlN, a multilayer of an AlN layer (lower layer) and a GaN layer (upper layer), or a multilayer of an Al layer (lower layer) and an AlN layer (upper layer).
  • the bonding portion J located within the opening K is an initial formation layer, and bonds with the exposed base layer 4 (seed area SA).
  • the base portion B located above the opening K becomes a dislocation inheritance portion with many threading dislocations
  • the wing portion F located above the mask portion 5 becomes a low-defect portion with a lower threading dislocation density than the dislocation inheritance portion.
  • the base substrate BS may have a main substrate 1 which is a heterogeneous substrate having a lattice constant different from that of the semiconductor layer 8.
  • the semiconductor layer 8 may include a GaN-based semiconductor, and the heterogeneous substrate, the main substrate 1, may be a silicon substrate.
  • examples of the heterogeneous substrate include a sapphire (Al 2 O 3 ) substrate and a silicon carbide (SiC) substrate.
  • the surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any substrate and surface orientation may be used as long as the semiconductor layer 8 can be grown by the ELO method.
  • the mask pattern 6 includes a mask portion 5 and an opening portion K.
  • the opening portion K functions as a growth initiation hole that exposes a portion (seed area SA) of the underlayer 4 and initiates the growth of the semiconductor layer 8, and the mask portion 5 may function as a selective growth mask (deposition inhibition mask) for growing the semiconductor layer 8 laterally, and the surface of the mask portion 5 becomes a growth inhibition area (non-seed area) DA.
  • the mask portion 5 may be, for example, a single layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher), or a laminated film including at least two of these.
  • a thermal oxide film obtained by subjecting a silicon substrate, a silicon nitride substrate, etc. to a thermal oxidation process may also be used as the mask portion 5.
  • the mask portion 5 may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order.
  • the upper film in contact with the semiconductor layer 8 may be a silicon nitride film.
  • the element SL may include a functional layer 9 located on the semiconductor layer 8, and the functional layer 9 may include an active layer, a p-type layer, and electrodes (e.g., an anode and a cathode).
  • the active layer may have a quantum well structure.
  • the semiconductor layer 8 and the active layer and p-type layer may be GaN-based semiconductors, and may be formed successively in an MOCVD apparatus.
  • the support substrate MS may be a submount substrate and may include electrode pads PA and PC.
  • the element SL and the electrode pad PA may be joined via solder H.
  • the anode of the element SL and the electrode pad PA may be joined via solder H.
  • the solder H may be a Sn-Au alloy.
  • step S10 in Figure 1 may be selective transfer. That is, the multiple elements SL bonded to the support substrate MS may be a selected element group SG selected from all the elements on the growth substrate TS.
  • FIGs 1 to 5 multiple elements SL (selected element group) are bonded to a support substrate MS without removing the mask portion 5 of the growth substrate TS.
  • a part of the element SL may be embedded in the mask portion 5.
  • Figure 7 is a cross-sectional view showing a manufacturing method of a semiconductor element according to this embodiment. As shown in Figure 7, after removing the mask portion 5 of the growth substrate TS by wet etching or the like, multiple elements SL (selected element group) are bonded to a support substrate MS, and the element SL may be tilted with respect to the growth substrate TS to break the joint portion J.
  • FIG. 8 and 9 are cross-sectional views showing a method for manufacturing a semiconductor element according to this embodiment.
  • an external force is applied to the back surface UF of the growth substrate TS, but this is not limited thereto.
  • FIG. 8 and FIG. 9 in a state in which a plurality of elements SL are bonded to the surface of the support substrate MS, by applying an external force to the back surface UM of the support substrate MS such that the pressure distribution is non-uniform in the plane, the elements SL are tilted with respect to the growth substrate TS, and the joint J can be easily broken.
  • the joint J with the growth substrate TS is tilted with respect to the normal line of the growth substrate TS, and shear stress is concentrated near the interface between the growth substrate TS and the joint J, causing the joint J to break. It is preferable to apply an external force to the back surface UT of the growth substrate TS such that the pressure distribution is uniform in the plane and does not change with time.
  • FIG. 10 is a cross-sectional view showing the method for manufacturing a semiconductor element according to this embodiment.
  • the pressure distribution on the back surface of the growth substrate TS may be changed over time.
  • a plate PT tilted at a predetermined positive angle around an axis (Y direction, m-axis of the semiconductor layer 8) perpendicular to the first direction X is pressed against the back surface of the growth substrate TS, and then a plate PT tilted at a predetermined negative angle is pressed against the back surface of the growth substrate TS.
  • the predetermined positive angle may be 1° to 3°
  • the predetermined negative angle may be -1° to -3°.
  • the selection element group SG multiple elements SL to be subjected to selective transfer
  • the selection element group SG tilted in the positive and negative directions relative to the growth substrate TS, and even if there is a joint J (see FIG. 4) in the selection element group SG that was not broken by the positive tilt, it can be broken by the negative tilt, thereby increasing the transfer yield of the selection element group SG.
  • the inclination is less than 1°, the yield will decrease due to insufficient tilt, and if it is 3° or more, the plate PT may float above the growth substrate TS, making it difficult to apply force appropriately.
  • FIG. 11 is a cross-sectional view showing the method for manufacturing a semiconductor element according to this embodiment.
  • the pressure distribution on the rear surface of the support substrate MS may be changed over time.
  • a plate PT tilted at a predetermined positive angle around an axis (Y direction, m-axis of the semiconductor layer 8) perpendicular to the first direction X is pressed against the rear surface of the support substrate MS, and then a plate PT tilted at a predetermined negative angle is pressed against the rear surface of the support substrate MS.
  • the predetermined positive angle may be 1° to 3°
  • the predetermined negative angle may be -1° to -3°.
  • selection element group SG multiple elements SL to be subjected to selective transfer
  • the selection element group SG tilted in the positive and negative directions relative to the growth substrate TS, and even if there is a joint J (see FIG. 4) in the selection element group SG that was not broken due to the positive tilt, it can be broken by the negative tilt, and the transfer yield of the selection element group SG can be increased.
  • FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor element according to this embodiment.
  • a roller R pressed against the back surface of the growth substrate TS may be moved in a first direction X to change the pressure distribution on the back surface of the growth substrate TS over time.
  • the growth substrate TS may be adsorbed to the roller R after the transfer of the selection element group SG.
  • FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor element according to this embodiment.
  • a roller R pressed against the back surface of the support substrate MS may be moved in a first direction X to change the pressure distribution on the back surface of the support substrate MS over time.
  • the support substrate MS including the selection element group SG
  • FIG. 14 is a cross-sectional view showing a semiconductor element manufacturing apparatus according to this embodiment.
  • the semiconductor element manufacturing apparatus 50 may include a device G1 that can suction-hold and transport the workpiece 30 from its underside, and a device G2 that drives a plate PT that can change the inclination while applying a compressive force from the top surface of the workpiece 30.
  • the device G1 can move in the X direction, Y direction, and rotate within the XY plane, and aligns the position of the workpiece 30 and the orientation of the selection element group SG with respect to the plate PT.
  • the device G2 can move in the Z direction and rotate within the XZ plane.
  • the semiconductor element manufacturing apparatus 50 releases the selection element group SG from the growth substrate TS by releasing the workpiece 30 while still suction-holding its top and bottom surfaces.
  • the semiconductor device manufacturing apparatus 50 may include a device G1 that can suction-hold and transport the workpiece 30 from its underside, and a device G3 that drives a roller R that applies a compressive force from the top of the workpiece 30.
  • the device G1 can move in the X direction, the Y direction, and rotate in the XY plane, and aligns the position of the workpiece 30 and the orientation of the selection element group SG with respect to the roller R.
  • the semiconductor device manufacturing apparatus 50 applies a compressive force from the roller R to the support substrate MS from one end to the other end by moving the device G1 in the X direction.
  • the roller R is in an adsorption state, and after applying a force to the workpiece 30, the upper side of the workpiece (support substrate MS and selection element group SG) is adsorbed to the roller R side to perform peeling.
  • the pressure of the roller R is applied to the support substrate MS, but this is not limited thereto, and the pressure of the roller R may also be applied to the growth substrate TS.
  • FIG. 16 is a flowchart showing a method for manufacturing a semiconductor element according to this embodiment.
  • the method for manufacturing a semiconductor element according to this embodiment includes a step (S60) of bonding a plurality of elements SL, each of which includes a semiconductor layer 8 grown on a growth substrate TS, to a surface of a support substrate MS, a step (S70) of applying an external force in a first direction (X direction) perpendicular to the substrate thickness direction to one of the growth substrate TS and the support substrate MS, and a step (S80) of peeling off the plurality of elements SL bonded to the support substrate MS from the growth substrate TS.
  • S60 of bonding a plurality of elements SL, each of which includes a semiconductor layer 8 grown on a growth substrate TS, to a surface of a support substrate MS
  • FIGS. 17 and 18 are cross-sectional views showing a method for manufacturing a semiconductor element according to this embodiment.
  • an external force in a first direction may be applied to the growth substrate TS.
  • an external force in the opposite direction to the first direction may be applied to the support substrate MS.
  • an external force in a first direction may be applied to the support substrate MS.
  • an external force in the opposite direction to the first direction may be applied to the growth substrate TS.
  • the semiconductor device manufacturing apparatus 50 may include a device G1 capable of suction-holding and transporting the workpiece 30 from its underside, and a device G4 having a pressure unit PB that suction-holds the upper surface of the workpiece 30 and applies a force in a first direction (X direction) to the workpiece 30.
  • a device G1 capable of suction-holding and transporting the workpiece 30 from its underside
  • a device G4 having a pressure unit PB that suction-holds the upper surface of the workpiece 30 and applies a force in a first direction (X direction) to the workpiece 30.
  • an external force in the first direction (X direction) is applied to the growth substrate TS by the pressure unit PB, and then the workpiece upper and lower surfaces are released while still being held by suction, thereby peeling off the selection element group SG from the growth substrate TS.
  • an external force in the first direction (X direction) is applied to the growth substrate TS, but this is not limited thereto.
  • FIG. 20 is a cross-sectional view showing a semiconductor element manufacturing apparatus according to this embodiment.
  • semiconductor element manufacturing apparatus 50 may include device G1 that can suction-hold and transport workpiece 30 from its underside, and device G5 that moves in a first direction (X direction) while suction-holding the upper surface of workpiece 30.
  • device G5 moves a small amount in the first direction (X direction) and device G1 moves a small amount in the opposite direction to the first direction (-X direction), and then releases the workpiece upper and lower surfaces while still suction-holding them, thereby peeling off selected element group SG from growth substrate TS.
  • FIG. 21 and 22 are plan views showing the configuration of the semiconductor substrate according to this embodiment.
  • FIG. 23 is a cross-sectional view of FIG. 21 and FIG. 22.
  • an element SL including a wing portion F (one wing) of a semiconductor layer 8 includes an anode EA and a cathode EC, and the element SL may be held on a growth substrate (template substrate) TS via a tether portion TZ located on a seed region SA.
  • the element SL can be separated from the growth substrate TS by cutting (breaking) the boundary CL between the tether portion TZ and the wing portion F (one wing) and the functional layer 9 overlapping therewith using the semiconductor element manufacturing method according to this embodiment.
  • the element SL may be a light-emitting diode (LED).
  • the tether portion TZ may be provided in the center (FIG. 21), or may be provided in a plurality at intervals (FIG. 22).
  • the tether portion TZ is formed by patterning (partially removing by dry etching, etc.) the semiconductor layer 8 and the functional layer 9 overlapping it, in the region located above the seed region SA.
  • FIG. 24 and 25 are cross-sectional views showing the configuration of a semiconductor substrate according to this embodiment.
  • a gap VS may be provided between a wing portion F (one wing) of the semiconductor layer 8 and the growth substrate TS.
  • the base layer 4 is formed in a ridge shape, and the side surface of the base layer 4 is covered with a mask portion 5, so that the wing portion F of the semiconductor layer 8 can grow laterally while being raised above the growth substrate TS.
  • the method for manufacturing a semiconductor element may be used to obtain an element SL comprising a semiconductor layer 8 (including both wings) and a functional layer 9 overlapping it from the semiconductor substrate 10 of FIG. 24, or an element SL comprising a wing portion F and a functional layer 9 overlapping it.
  • the element SL may be separated from the growth substrate TS.
  • a gap VS may be provided between the wing portion F (one wing) of the semiconductor layer 8 and the growth substrate TS.
  • the wing portion F of the semiconductor layer 8 (nitride semiconductor layer) can be grown laterally while floating above the growth substrate TS.
  • the growth substrate TS template substrate
  • a modified region 4D and a non-modified region 4S are formed in the base layer 4, the non-modified region 4S functions as a seed region SA, and the modified region 4D functions as a growth suppression region (non-seed region) DA.
  • the modified region 4D can be formed by performing a plasma treatment or the like on the base layer 4 (e.g., an AlN layer).
  • the method for manufacturing a semiconductor element may be used to obtain an element SL having a semiconductor layer 8 (including both wings) and a functional layer 9 overlapping it from the semiconductor substrate 10 of FIG. 25, or an element SL having a wing portion F and a functional layer 9 overlapping it.
  • the element SL may be separated from the growth substrate TS.

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019134101A (ja) * 2018-01-31 2019-08-08 京セラ株式会社 半導体素子の製造方法
WO2020175684A1 (ja) * 2019-02-28 2020-09-03 京セラ株式会社 半導体素子の製造方法および半導体素子体
JP2021503713A (ja) * 2017-11-20 2021-02-12 廈門市三安光電科技有限公司 マイクロデバイスのマストランスファー方法
JP2021145052A (ja) * 2020-03-12 2021-09-24 京セラ株式会社 半導体素子の製造方法
JP2022523861A (ja) * 2019-03-12 2022-04-26 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア 支持板を使用して１つ以上の素子のバーを除去するための方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021503713A (ja) * 2017-11-20 2021-02-12 廈門市三安光電科技有限公司 マイクロデバイスのマストランスファー方法
JP2019134101A (ja) * 2018-01-31 2019-08-08 京セラ株式会社 半導体素子の製造方法
WO2020175684A1 (ja) * 2019-02-28 2020-09-03 京セラ株式会社 半導体素子の製造方法および半導体素子体
JP2022523861A (ja) * 2019-03-12 2022-04-26 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア 支持板を使用して１つ以上の素子のバーを除去するための方法
JP2021145052A (ja) * 2020-03-12 2021-09-24 京セラ株式会社 半導体素子の製造方法

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