WO2024121910A1 - 半導体製造装置用部材 - Google Patents

半導体製造装置用部材 Download PDF

Info

Publication number
WO2024121910A1
WO2024121910A1 PCT/JP2022/044764 JP2022044764W WO2024121910A1 WO 2024121910 A1 WO2024121910 A1 WO 2024121910A1 JP 2022044764 W JP2022044764 W JP 2022044764W WO 2024121910 A1 WO2024121910 A1 WO 2024121910A1
Authority
WO
WIPO (PCT)
Prior art keywords
plug
hole
semiconductor manufacturing
ceramic plate
manufacturing equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/044764
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
夏樹 平田
信也 吉田
達也 久野
靖也 井上
太朗 宇佐美
憲司 米本
碧惟 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
Original Assignee
NGK Insulators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Insulators Ltd filed Critical NGK Insulators Ltd
Priority to KR1020237023090A priority Critical patent/KR102815697B1/ko
Priority to CN202280007930.2A priority patent/CN120239901A/zh
Priority to PCT/JP2022/044764 priority patent/WO2024121910A1/ja
Priority to JP2023540959A priority patent/JP7560675B1/ja
Priority to US18/346,951 priority patent/US12211729B2/en
Priority to TW112138688A priority patent/TW202425176A/zh
Publication of WO2024121910A1 publication Critical patent/WO2024121910A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/72—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using electrostatic chucks
    • H10P72/722—Details of electrostatic chucks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0432—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0434—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/72—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7616—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating, a hardness or a material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7624—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support

Definitions

  • the present invention relates to components for semiconductor manufacturing equipment.
  • the electrostatic chuck in Patent Document 1 is constructed by inserting a truncated cone-shaped porous plug into a bottomed recess in a truncated cone space provided on the underside of a ceramic plate and fixing it with an adhesive, and bonding the underside of the ceramic plate to a metal base plate.
  • the electrostatic chuck in Patent Document 2 is constructed by sintering a cylindrical porous plug into a through hole in a cylindrical space formed in the ceramic plate, and bonding the underside of the ceramic plate to a metal base plate.
  • the present invention was made to solve these problems, and its main objective is to make it easier to replace plugs that allow gas to flow in both vertical directions, while also making it less likely for discharge to occur around the plug.
  • the semiconductor manufacturing equipment member of the present invention comprises: a ceramic plate having a wafer mounting surface on an upper surface thereof; a plug arrangement hole that passes through the ceramic plate in the vertical direction and has a truncated cone space whose upper opening has an area larger than that of a lower opening; a plug having a truncated cone shape, the plug being disposed in the plug disposition hole, allowing gas to flow in the vertical direction, and having an upper surface area larger than a lower surface area; an adhesive layer provided between an inner circumferential surface of the plug placement hole and an outer circumferential surface of the plug; a conductive base plate bonded to a lower surface of the ceramic plate via a bonding layer; a gas supply path provided in the base plate and the bonding layer for supplying a gas to the plug; It is equipped with the following:
  • the adhesive layer can be cut, melted or softened to pull the plug upward out of the plug placement hole in the ceramic plate.
  • a new plug can be inserted from above the plug placement hole and glued to the plug placement hole. This makes it easy to replace the plug.
  • the adhesive is less likely to run off because these surfaces are tapered. Therefore, air bubbles (air bubbles large enough to cause discharge when processing a wafer with plasma) are less likely to occur in the adhesive layer compared to when these surfaces are vertical. Therefore, discharge is less likely to occur around the plug (adhesive layer) when processing a wafer with plasma.
  • up/down, left/right, front/back are merely relative positional relationships. Therefore, when the orientation of a semiconductor manufacturing equipment component is changed, up/down may become left/right and left/right may become up/down, but such cases are also within the technical scope of this invention.
  • a space that allows the plug to enter may be provided at a position of the gas supply path that faces the plug. In this way, even if there is a manufacturing error in the plug placement hole or the plug when placing the plug in the plug placement hole, the manufacturing error can be absorbed by the space that allows the plug to enter.
  • the elevation angle of the inner peripheral surface of the plug placement hole and the elevation angle of the outer peripheral surface of the plug are preferably 65° or more and 85° or less. In this way, when an adhesive layer is provided between the inner peripheral surface of the plug placement hole and the outer peripheral surface of the plug, the adhesive tends to spread evenly, so that no or almost no air bubbles are generated in the adhesive layer. This enhances the effect of preventing discharge around the plug (adhesive layer).
  • the adhesive layer does not have bubbles whose maximum vertical length exceeds 0.2 mm. If the maximum vertical length of the bubbles exceeds 0.2 mm, there is a risk of discharge occurring inside the bubbles when the wafer is treated with plasma, but if the maximum vertical length of the bubbles does not exceed 0.2 mm, there is almost no risk of discharge occurring inside the bubbles.
  • the adhesive layer does not have any air bubbles. This further enhances the effect of preventing discharge around the plug (adhesive layer).
  • FIG. 2 is a longitudinal sectional view of a semiconductor manufacturing equipment member 10.
  • FIG. 2 is a partially enlarged view of FIG. 3A to 3C are diagrams showing the manufacturing process of the semiconductor manufacturing equipment member 10.
  • FIG. 2 is a longitudinal sectional view of a semiconductor manufacturing equipment member 110.
  • FIG. 1 is a vertical cross-sectional view of a semiconductor manufacturing equipment component 10
  • FIG. 2 is a plan view of a ceramic plate 20
  • FIG. 3 is an enlarged view of a portion of FIG. 1.
  • the semiconductor manufacturing equipment component 10 comprises a ceramic plate 20, a plug placement hole 24, a base plate 30, a metal bonding layer 40, and a porous plug 50.
  • the ceramic plate 20 is a ceramic circular plate (e.g., 300 mm in diameter, 5 mm in thickness) made of alumina sintered body or aluminum nitride sintered body.
  • the upper surface of the ceramic plate 20 is the wafer mounting surface 21.
  • the ceramic plate 20 has an electrode 22 built in.
  • the wafer mounting surface 21 of the ceramic plate 20 has a seal band 21a formed along the outer edge, and a plurality of circular small protrusions 21b formed on the entire surface.
  • the seal band 21a and the circular small protrusions 21b have the same height, for example, several ⁇ m to several tens of ⁇ m.
  • the electrode 22 is a flat mesh electrode used as an electrostatic electrode, and a DC voltage can be applied to it.
  • the wafer W When a DC voltage is applied to the electrode 22, the wafer W is attracted and fixed to the wafer mounting surface 21 (specifically, the upper surface of the seal band 21a and the upper surface of the circular small protrusions 21b) by electrostatic attraction force, and when the application of the DC voltage is released, the wafer W is released from the wafer mounting surface 21.
  • the portion of the wafer mounting surface 21 on which the seal band 21a and small circular protrusions 21b are not provided is referred to as the reference surface 21c.
  • the plug arrangement hole 24 is a through hole that penetrates the ceramic plate 20 in the vertical direction and faces the gas hole 34 of the base plate 30.
  • the plug arrangement hole 24 penetrates the electrode 22 in the vertical direction, but the electrode 22 is not exposed on the inner surface of the plug arrangement hole 24.
  • the plug arrangement hole 24 is a tapered hole having a truncated cone space with an upper opening area larger than the lower opening area.
  • the elevation angle ⁇ ( Figure 3) of the inner surface of the plug arrangement hole 24 is preferably 55° to 85°, and more preferably 65° to 85°.
  • the plug arrangement holes 24 are provided at multiple locations on the ceramic plate 20 (e.g., multiple locations equally spaced along the circumferential direction).
  • the base plate 30 is a disk with good thermal conductivity (a disk with the same diameter as or larger than the ceramic plate 20).
  • a refrigerant flow path 32 in which a refrigerant (e.g., an electrically insulating liquid such as a fluorine-based inert liquid) circulates and a gas hole 34 for supplying gas to the porous plug 50 are formed.
  • the gas hole 34 is provided to penetrate the base plate 30 in the vertical direction and has a large diameter portion 34a at the top.
  • the large diameter portion 34a includes the lower opening of the plug arrangement hole 24 in a plan view.
  • the refrigerant flow path 32 is formed in a single stroke from the inlet to the outlet over the entire surface of the base plate 30 in a plan view.
  • Examples of materials for the base plate 30 include composite materials and metals.
  • Examples of composite materials include composite materials of metal and ceramic.
  • Examples of composite materials of metal and ceramic include metal matrix composite materials (metal matrix composites (MMC)) and ceramic matrix composite materials (ceramic matrix composites (CMC)).
  • MMC metal matrix composites
  • CMC ceramic matrix composites
  • Specific examples of such composite materials include materials containing Si, SiC, and Ti, and materials in which a porous SiC body is impregnated with Al and/or Si.
  • a material containing Si, SiC, and Ti is called SiSiCTi
  • AlSiC a material in which a porous SiC body is impregnated with Al
  • SiSiC a material in which a porous SiC body is impregnated with Si
  • Examples of metals include Mo.
  • the base plate 30 is also used as an RF electrode. Specifically, an upper electrode (not shown) is disposed above the wafer mounting surface 21, and when high-frequency power is applied between the parallel plate electrodes consisting of the upper electrode and the base plate 30, plasma is generated.
  • the metal bonding layer 40 bonds the lower surface of the ceramic plate 20 and the upper surface of the base plate 30.
  • the metal bonding layer 40 is formed, for example, by TCB (thermal compression bonding).
  • TCB refers to a known method in which a metal bonding material is sandwiched between two members to be bonded, and the two members are pressurized and bonded while being heated to a temperature below the solidus temperature of the metal bonding material.
  • the metal bonding layer 40 may be a layer formed of solder or metal brazing material.
  • the metal bonding layer 40 has a through hole 42. The through hole 42 is provided at a position facing the large diameter portion 34a of the gas hole 34.
  • the through hole 42 is provided coaxially with the large diameter portion 34a, and the diameter of the through hole 42 is the same as the diameter of the large diameter portion 34a.
  • “matching” includes not only a case of perfect matching, but also a case of substantial matching (for example, a case within the range of tolerance) (the same applies below).
  • the gas hole 34 and the through hole 42 correspond to the gas supply path of the present invention.
  • the porous plug 50 is fixed in the plug placement hole 24.
  • the porous plug 50 is an electrically insulating member that allows gas to flow in the vertical direction.
  • the porosity of the porous plug 50 is preferably 30% or more, and the average pore diameter is preferably 20 ⁇ m or more.
  • the porous plug 50 is a truncated cone-shaped member whose upper surface area is larger than the lower surface area.
  • the elevation angle ⁇ of the outer peripheral surface of the porous plug 50 is the same as the elevation angle ⁇ of the inner peripheral surface of the plug placement hole 24.
  • An adhesive layer 60 is provided between the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24.
  • the adhesive layer 60 does not have bubbles of a size that would cause discharge when processing the wafer W with plasma (e.g., bubbles with a vertical height of 2 mm or more).
  • materials for the adhesive layer 60 include acrylic resin, silicone resin, and epoxy resin.
  • materials for the porous plug 50 include ceramics, and specifically, a porous body of the same material as the ceramic plate 20 can be used.
  • the upper surface 50a of the porous plug 50 is exposed to the upper opening of the plug placement hole 24 and is flush with the reference surface 21c. In this specification, “same” includes cases where they are completely identical, as well as cases where they are substantially identical (for example, within the tolerance range) (the same applies below).
  • the lower surface 50b of the porous plug 50 is exposed to the lower opening of the plug placement hole 24.
  • the semiconductor manufacturing equipment member 10 is installed in a chamber (not shown), and the wafer W is placed on the wafer placement surface 21. Then, the chamber is depressurized by a vacuum pump to adjust the chamber to a predetermined degree of vacuum, and a direct current voltage is applied to the electrode 22 of the ceramic plate 20 to generate an electrostatic adsorption force, and the wafer W is adsorbed and fixed to the wafer placement surface 21 (specifically, the upper surface of the seal band 21a or the upper surface of the circular small protrusion 21b).
  • the chamber is made into a reaction gas atmosphere of a predetermined pressure (for example, several tens to several hundreds of Pa), and in this state, a high-frequency voltage is applied between an upper electrode (not shown) provided on the ceiling part of the chamber and the base plate 30 of the semiconductor manufacturing equipment member 10 to generate plasma.
  • a coolant is circulated through the coolant flow path 32 of the base plate 30.
  • a backside gas is introduced into the gas hole 34 from a gas cylinder (not shown).
  • a thermally conductive gas for example, helium, etc.
  • the backside gas is supplied and sealed in the space between the back surface of the wafer W and the reference surface 21c of the wafer mounting surface 21 through the gas holes 34, the through holes 42, and the porous plug 50.
  • This backside gas ensures efficient thermal conduction between the wafer W and the ceramic plate 20.
  • FIG. 4 is a manufacturing process diagram of the semiconductor manufacturing equipment component 10.
  • the ceramic plate 20 incorporates an electrode 22 and has a plug placement hole 24.
  • the base plate 30 has a coolant flow path 32 and a gas hole 34.
  • the gas hole 34 has a large diameter portion 34a at the top.
  • the metal bonding material 90 has a through hole 92 at a position opposite the large diameter portion 34a of the gas hole 34.
  • a metal bonding material 90 is sandwiched between the lower surface of the ceramic plate 20 and the upper surface of the base plate 30 to form a laminate.
  • the plug placement hole 24 of the ceramic plate 20, the through hole 92 of the metal bonding material 90, and the gas hole 34 of the base plate 30 are stacked so that they are coaxial.
  • the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material 90 (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature (TCB).
  • the metal bonding material 90 and the through hole 92 become the metal bonding layer 40 and the through hole 42, respectively, and a bonded body 94 in which the ceramic plate 20 and the base plate 30 are bonded by the metal bonding layer 40 is obtained ( Figure 4B).
  • an Al-Mg-based bonding material or an Al-Si-Mg-based bonding material can be used as the metal bonding material 90. It is preferable to use a metal bonding material 90 with a thickness of about 100 ⁇ m.
  • a porous plug 50 having a truncated cone shape is prepared ( Figure 4B).
  • the height of the porous plug 50 is the same as the depth of the plug placement hole 24, which is a truncated cone space (i.e., the height of the ceramic plate 20).
  • An adhesive 70 is applied to the outer peripheral surface of the porous plug 50 along the circumferential direction for at least one revolution.
  • the adhesive 70 may be an organic adhesive or an inorganic adhesive.
  • the porous plug 50 to which the adhesive 70 has been applied is inserted into the plug placement hole 24. At this time, the porous plug 50 is rotated or moved up and down so that the adhesive 70 spreads along the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24. This allows the adhesive 70 to be uniformly spread in the gap between the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24 without trapping air bubbles.
  • the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24 are joined via the adhesive 70.
  • the upper surface of the porous plug 50 coincides with the upper surface (reference surface 21c) of the ceramic plate 20.
  • a plurality of porous plugs 50 with different heights are prepared. Therefore, according to the actual height of the ceramic plate 20 (which varies from one to another due to manufacturing errors), one is selected from the plurality of porous plugs 50 with different heights that will coincide with the upper surface (reference surface 21c) of the ceramic plate 20 when the porous plug 50 is inserted into the plug placement hole 24.
  • the adhesive 70 hardens to become an adhesive layer 60, and the semiconductor manufacturing equipment member 10 is obtained (FIG. 4C).
  • the adhesive layer 60 can be cut, melted or softened to pull the porous plug 50 upward from the plug arrangement hole 24. Also, a new porous plug 50 can be inserted from above the plug arrangement hole 24 and adhered to the plug arrangement hole 24. Therefore, the porous plug 50 can be easily replaced.
  • a space (through hole 42 and large diameter portion 34a) is provided that allows the porous plug 50 to enter. Therefore, even if there is a manufacturing error in the plug placement hole 24 or the porous plug 50 when placing the porous plug 50 in the plug placement hole 24, the manufacturing error can be absorbed by the space that allows the porous plug 50 to enter. In contrast, if the plug placement hole 24 has a bottom surface, the porous plug 50 will hit the bottom surface and the manufacturing error cannot be absorbed.
  • the elevation angle ⁇ of the inner peripheral surface of the plug placement hole 24 and the elevation angle ⁇ of the outer peripheral surface of the porous plug 50 are the same, and are preferably 55° or more and 85° or less.
  • the adhesive 70 tends to spread evenly.
  • no or almost no bubbles bubbles of a size that would cause discharge when processing the wafer W with plasma
  • the adhesive layer 60 preferably does not have any bubbles, but if it does have bubbles, the bubbles preferably have a maximum vertical length of 0.2 mm or less (i.e., it is preferable that there are no bubbles whose maximum vertical length exceeds 0.2 mm). This enhances the effect of preventing discharge around the porous plug 50 (adhesive layer 60).
  • the gas flowing through the gas supply path is helium
  • electrons generated as the helium is ionized during plasma generation accelerate and collide with other helium, causing a discharge (glow discharge).
  • the maximum vertical length of the bubbles is 0.2 mm or less, the electrons cannot be sufficiently accelerated within the bubbles, and discharge can be suppressed.
  • a porous plug 50 is exemplified as a plug that allows gas to flow in the vertical direction, but this is not particularly limited.
  • a dense plug having a flow path (e.g., a spiral flow path) inside that allows gas to flow in the vertical direction may be used as such a plug.
  • the height of the lower surface 50b of the porous plug 50 may be the same as the height of the lower surface of the ceramic plate 20 (the lower opening of the plug placement hole 24), but it may also be higher or lower than the height of the lower surface of the ceramic plate 20. In either case, it is preferable that the height of the upper surface 50a of the porous plug 50 be the same as the height of the upper surface of the ceramic plate 20 (reference surface 21c).
  • the large diameter portion 34a is provided above the gas hole 34, but this is not particularly limited.
  • the gas hole 34 may be a straight hole whose hole diameter is larger than the diameter of the lower opening of the plug placement hole 24. Even in this case, the through hole 42 of the metal bonding layer 40 and the upper part of the gas hole 34 become spaces that allow the porous plug 50 to enter.
  • the base plate 30 is provided with gas holes 34 that form a gas supply path, but the present invention is not limited to this.
  • the base plate 30 may be provided with a ring portion 64a that is concentric with the base plate 30 in a plan view, an inlet portion 64b that introduces gas from the back surface of the base plate 30 to the ring portion 64a, and a distributor portion 64c that distributes gas from the ring portion 64a to each porous plug 50.
  • the number of inlet portions 64b may be less than the number of distributor portions 64c, and may be, for example, one. In this way, the number of gas pipes connected to the base plate 30 can be less than the number of porous plugs 50.
  • an electrostatic electrode is exemplified as the electrode 22 built into the ceramic plate 20, but this is not particularly limited.
  • a heater electrode resistive heating element
  • an RF electrode may be built into the ceramic plate 20.
  • the ceramic plate 20 and the base plate 30 are joined by a metal joining layer 40, but a resin adhesive layer may be used instead of the metal joining layer 40.
  • Example 1 A visualization sample simulating the above-mentioned semiconductor manufacturing device member 10 was produced. Specifically, the ceramic plate 20 and the base plate 30 were produced from a transparent acrylic resin, and the two plates 20, 30 were bonded together. A porous alumina body with a porosity of 30% was used as the porous plug 50. The elevation angles ⁇ and ⁇ of the inner peripheral surface of the plug arrangement hole 24 and the outer peripheral surface of the porous plug 50 were set to 75°. A silicone adhesive with a viscosity of 40,000 cP was used as the adhesive 70. The adhesive 70 was applied to the outer peripheral surface of the porous plug 50 for at least one revolution along the circumferential direction, and then the porous plug 50 was inserted into the plug arrangement hole 24.
  • the porous plug 50 was rotated or moved up and down so that the adhesive 70 spread along the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug arrangement hole 24.
  • the adhesive 70 was then cured to obtain a visualization sample.
  • the adhesive layer 60 of this visualization sample was visually observed, no air bubbles were found.
  • a high frequency voltage was applied to this visualization sample, no discharge occurred around the porous plug 50 (adhesive layer 60).
  • Example 2 A visualization sample was prepared in the same manner as in Experimental Example 1, except that the elevation angle of the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24 was set to 85°. When the adhesive layer 60 of this visualization sample was visually observed, no air bubbles were found. When a high-frequency voltage was applied to this visualization sample, no discharge occurred around the porous plug 50 (adhesive layer 60).
  • Example 3 A visualization sample was prepared in the same manner as in Experimental Example 1, except that the elevation angle of the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24 was set to 65°. When the adhesive layer 60 of this visualization sample was visually observed, no air bubbles were found. When a high-frequency voltage was applied to this visualization sample, no discharge occurred around the porous plug 50 (adhesive layer 60).
  • Example 4 A visualization sample was prepared in the same manner as in Experimental Example 1, except that the elevation angle of the outer peripheral surface of the porous plug 50 and the inner peripheral surface of the plug placement hole 24 was set to 55°.
  • the adhesive layer 60 of this visualization sample was visually observed, several bubbles were present. When these bubbles were examined in detail, no bubbles were found whose maximum length in the vertical direction exceeded 0.2 mm.
  • a high-frequency voltage was applied to this visualization sample, no discharge occurred around the porous plug 50 (adhesive layer 60). Therefore, it was determined that the bubbles were not large enough to cause discharge when processing the wafer W with plasma.
  • the present invention can be used for components used in semiconductor manufacturing equipment, such as ceramic heaters, electrostatic chuck heaters, and electrostatic chucks.

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Drying Of Semiconductors (AREA)
PCT/JP2022/044764 2022-12-05 2022-12-05 半導体製造装置用部材 Ceased WO2024121910A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020237023090A KR102815697B1 (ko) 2022-12-05 2022-12-05 반도체 제조 장치용 부재
CN202280007930.2A CN120239901A (zh) 2022-12-05 2022-12-05 半导体制造装置用部件
PCT/JP2022/044764 WO2024121910A1 (ja) 2022-12-05 2022-12-05 半導体製造装置用部材
JP2023540959A JP7560675B1 (ja) 2022-12-05 2022-12-05 半導体製造装置用部材
US18/346,951 US12211729B2 (en) 2022-12-05 2023-07-05 Member for semiconductor manufacturing apparatus
TW112138688A TW202425176A (zh) 2022-12-05 2023-10-11 半導體製造裝置用部件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/044764 WO2024121910A1 (ja) 2022-12-05 2022-12-05 半導体製造装置用部材

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/346,951 Continuation US12211729B2 (en) 2022-12-05 2023-07-05 Member for semiconductor manufacturing apparatus

Publications (1)

Publication Number Publication Date
WO2024121910A1 true WO2024121910A1 (ja) 2024-06-13

Family

ID=91280269

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/044764 Ceased WO2024121910A1 (ja) 2022-12-05 2022-12-05 半導体製造装置用部材

Country Status (6)

Country Link
US (1) US12211729B2 (https=)
JP (1) JP7560675B1 (https=)
KR (1) KR102815697B1 (https=)
CN (1) CN120239901A (https=)
TW (1) TW202425176A (https=)
WO (1) WO2024121910A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026009597A1 (ja) * 2024-07-03 2026-01-08 日本碍子株式会社 半導体製造装置用部材
WO2026009583A1 (ja) * 2024-07-03 2026-01-08 日本碍子株式会社 半導体製造装置用部材
WO2026042583A1 (ja) * 2024-08-21 2026-02-26 住友大阪セメント株式会社 静電チャック部材、および静電チャック装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102721433B1 (ko) * 2023-02-27 2024-10-25 엔지케이 인슐레이터 엘티디 웨이퍼 적재대

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050813A (ja) * 1996-04-26 1998-02-20 Applied Materials Inc 静電チャック面への熱伝達流体の流れのための導管
US20200411355A1 (en) * 2019-06-28 2020-12-31 Applied Materials, Inc. Apparatus for reduction or prevention of arcing in a substrate support
JP2021044307A (ja) * 2019-09-09 2021-03-18 日本特殊陶業株式会社 保持装置
JP2022106181A (ja) * 2021-01-06 2022-07-19 日本碍子株式会社 半導体製造装置用部材及びその製法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6865145B2 (ja) * 2016-12-16 2021-04-28 日本特殊陶業株式会社 保持装置
JP2019029384A (ja) 2017-07-25 2019-02-21 新光電気工業株式会社 セラミックス混合物、多孔質体及びその製造方法、静電チャック及びその製造方法、基板固定装置
JP7269759B2 (ja) 2019-03-12 2023-05-09 新光電気工業株式会社 基板固定装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050813A (ja) * 1996-04-26 1998-02-20 Applied Materials Inc 静電チャック面への熱伝達流体の流れのための導管
US20200411355A1 (en) * 2019-06-28 2020-12-31 Applied Materials, Inc. Apparatus for reduction or prevention of arcing in a substrate support
JP2021044307A (ja) * 2019-09-09 2021-03-18 日本特殊陶業株式会社 保持装置
JP2022106181A (ja) * 2021-01-06 2022-07-19 日本碍子株式会社 半導体製造装置用部材及びその製法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026009597A1 (ja) * 2024-07-03 2026-01-08 日本碍子株式会社 半導体製造装置用部材
WO2026009583A1 (ja) * 2024-07-03 2026-01-08 日本碍子株式会社 半導体製造装置用部材
WO2026042583A1 (ja) * 2024-08-21 2026-02-26 住友大阪セメント株式会社 静電チャック部材、および静電チャック装置

Also Published As

Publication number Publication date
KR20240086599A (ko) 2024-06-18
JPWO2024121910A1 (https=) 2024-06-13
CN120239901A (zh) 2025-07-01
JP7560675B1 (ja) 2024-10-02
US12211729B2 (en) 2025-01-28
US20240186170A1 (en) 2024-06-06
KR102815697B1 (ko) 2025-06-04
TW202425176A (zh) 2024-06-16

Similar Documents

Publication Publication Date Title
JP7560675B1 (ja) 半導体製造装置用部材
JP7620578B2 (ja) 半導体製造装置用部材
KR102755205B1 (ko) 반도체 제조 장치용 부재
JP7569772B2 (ja) 半導体製造装置用部材
JP7569343B2 (ja) 半導体製造装置用部材
JP7483121B2 (ja) 半導体製造装置用部材
JP7514817B2 (ja) 半導体製造装置用部材
TWI849981B (zh) 半導體製造裝置用構件
CN116344428B (zh) 半导体制造装置用部件
JP7751079B2 (ja) 半導体製造装置用部材
JP7503708B1 (ja) 半導体製造装置用部材
WO2024180611A1 (ja) ウエハ載置台
WO2025220065A1 (ja) ウエハ載置台
WO2025134288A1 (ja) 半導体製造装置用部材
WO2025220060A1 (ja) ウエハ載置台
WO2025173083A1 (ja) 半導体製造装置用部材

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280007930.2

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2023540959

Country of ref document: JP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22967764

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 202280007930.2

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22967764

Country of ref document: EP

Kind code of ref document: A1