WO2024109554A1 - 封装产品、电子设备及封装产品的封装方法 - Google Patents

封装产品、电子设备及封装产品的封装方法 Download PDF

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Publication number
WO2024109554A1
WO2024109554A1 PCT/CN2023/130804 CN2023130804W WO2024109554A1 WO 2024109554 A1 WO2024109554 A1 WO 2024109554A1 CN 2023130804 W CN2023130804 W CN 2023130804W WO 2024109554 A1 WO2024109554 A1 WO 2024109554A1
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WO
WIPO (PCT)
Prior art keywords
substrate
electronic component
plastic
sealing layer
packaged product
Prior art date
Application number
PCT/CN2023/130804
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English (en)
French (fr)
Inventor
韩阿润
刘家政
刘文科
Original Assignee
歌尔微电子股份有限公司
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Publication of WO2024109554A1 publication Critical patent/WO2024109554A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present application relates to the technical field of packaging products, and in particular to a packaging product, an electronic device, and a packaging method for the packaging product.
  • Package stacking technology is to reintegrate packages with logic and memory chips of the same or similar appearance.
  • 3D packaging is to stack two packages vertically after plastic sealing them separately to form plastic sealing layers. Since two packages need to be made separately and plastic sealed separately, there are many processes, low production efficiency, and it is not suitable for mass production; and there are requirements for the plastic sealing height of each package. After the plastic sealing layers of two packages are stacked, the volume will be larger and the integration density will be low.
  • the main purpose of the present application is to provide a packaging product, an electronic device and a packaging method for a packaging product, aiming to solve the technical problems in the prior art of packaging products having many steps, low production efficiency, large volume and low integration density.
  • the present application provides a packaging method for a packaging product, the packaging method for the packaging product comprising the following steps:
  • first substrate and the second substrate are electrically connected through the conductive pillars, and the first electronic component and the second electronic component are arranged facing each other;
  • the package is plastic-sealed to form a plastic-sealing layer to wrap the first electronic component, the second electronic component and the third electronic component.
  • the number of the first electronic component, the number of the second electronic component and the number of the third electronic component are all one.
  • the number of the first electronic components is at least two
  • the number of the second electronic components is at least two
  • the number of the third electronic components is at least two.
  • the packaging product is obtained by cutting the plastic sealing layer, the first substrate and the second substrate.
  • the step of cutting the plastic encapsulation layer, the first substrate and the second substrate to obtain the packaged product includes:
  • the plastic sealing layer, the first substrate and the second substrate are cut in a vertical direction by a cutting knife to obtain the packaged product.
  • the step of mounting the first substrate and the second substrate so as to be electrically connected via the conductive pillars comprises:
  • the mounting makes the first pin of the first substrate and the second pin of the second substrate electrically connected through the conductive column.
  • the step of plastic-sealing the package to form a plastic-sealing layer to wrap the first electronic component, the second electronic component and the third electronic component further includes:
  • the plastic packaging layer fills up the accommodation space surrounded by the first substrate, the second substrate and the conductive pillars.
  • the present application also provides a packaging product, including a first substrate, a second substrate, a first electronic component, a second electronic component, a third electronic component, a conductive column and a plastic sealing layer, the first electronic component and the third electronic component are respectively installed on opposite sides of the first substrate, the second electronic component is installed on the second substrate, the first substrate and the second substrate are arranged opposite to each other, the first substrate, the second substrate and the conductive column form a receiving space, the first electronic component and the second electronic component are located in the receiving space, the plastic sealing layer includes a first plastic sealing layer and a second plastic sealing layer, the first plastic sealing layer fills the receiving space and wraps the first electronic component and the second electronic component, and the second plastic sealing layer wraps the third electronic component.
  • a first pin is disposed on the first substrate
  • a second pin is disposed on the second substrate
  • the conductive column is a copper column, and the conductive column connects the first pin and the second pin.
  • the first electronic component, the second electronic component and the third electronic component each include at least one of a chip, a resistor and a sensing element.
  • the present application also provides an electronic device, which includes the packaged product described above.
  • the packaging method of the packaged product includes the following steps: providing a first substrate and a second substrate, mounting at least one first electronic component on the first substrate, mounting at least one second electronic component on the second substrate; and setting a conductive column on one of the first substrate and the second substrate; mounting so that the first substrate and the second substrate are electrically connected through the conductive column, and the first electronic component and the second electronic component are arranged facing each other; mounting at least one third electronic component on the side of the first substrate away from the first electronic component to form a package; and plastic sealing the package to form a plastic sealing layer to wrap the first electronic component, the second electronic component and the third electronic component.
  • the first electronic component is first mounted on the first substrate by surface mounting technology, and the second electronic component is mounted on the second substrate, and then the first substrate and the second substrate are mounted to form a vertically stacked structure, and the third electronic component is mounted on the other side of the first substrate, and finally the package after mounting is plastic sealed once to obtain the required packaged product.
  • three plastic sealing processes are required, while this application only needs one plastic sealing, which reduces the plastic sealing process, and concentrates the mounting process, and the workpiece does not need to be transported back and forth between the equipment, which improves the production efficiency.
  • this minimum height requirement is represented by N.
  • the plastic sealing layer on the first package needs to be at least N away from the highest point of the first electronic component
  • the plastic sealing layer on the second package needs to be at least N away from the highest point of the second electronic component. Therefore, the highest point of the first electronic component needs to be at least 2N away from the highest point of the second electronic component to fill the plastic sealing layer.
  • the first substrate and the second substrate are first mounted and then plastic sealed.
  • the plastic sealing layer between the highest point of the first electronic component and the highest point of the second electronic component can only have a thickness of N, which can reduce the thickness of the plastic sealing layer, improve the integration density of the packaged product, and ultimately reduce the volume of the sealed product, which is more in line with the requirements of small-size packaged products.
  • This application has the advantages of being able to simplify the process, improve production efficiency, and have a high integration density and can reduce the packaging volume.
  • FIG1 is a schematic flow chart of a first embodiment of a packaging method for packaging a product according to an embodiment of the present application
  • FIG2 is a schematic flow chart of a second embodiment of a packaging method for packaging a product according to an embodiment of the present application
  • FIG3 is a schematic flow chart of a third embodiment of a packaging method for packaging a product according to an embodiment of the present application.
  • FIG4 is a schematic cross-sectional view of a packaging product manufactured using the prior art
  • FIG. 5 is a schematic structural diagram of a first substrate, a second substrate, a conductive column, a first electronic component, and a second electronic component of a packaged product according to an embodiment of the present application;
  • FIG6 is a schematic cross-sectional view of the structure of the first substrate and the second substrate of the packaged product according to the embodiment of the present application after bonding;
  • FIG7 is a schematic cross-sectional view of the packaged product according to the embodiment of the present application after a third electronic component is attached to the structure of FIG6 ;
  • FIG8 is a schematic cross-sectional structure diagram of the packaged product according to the embodiment of the present application after a plastic sealing layer is added to the structure of FIG7 ;
  • FIG. 9 is a schematic diagram of the cross-sectional structure of the packaged product according to an embodiment of the present application.
  • First substrate 20. Second substrate; 30. Conductive column; 40. First electronic component; 50. Second electronic component; 60. Third electronic component; 70. Plastic layer; 80. Gap.
  • FIG. 1 is a flow chart of a first embodiment of a packaging method for packaging a product of the present application.
  • the packaging method for packaging a product comprises the following steps:
  • the first substrate 1 and the second substrate 2 may be printed circuit boards, the first electronic component 4 is mounted on one side of the first substrate 1, and the second electronic component 5 is mounted on one side of the second substrate 2.
  • the first electronic component 4 and the second electronic component 5 may include one or more of chips, resistors, or inductive components, and those skilled in the art may set them according to actual needs.
  • the conductive column 3 may be mounted or welded on one of the first substrate 1 and the second substrate 2, and the conductive column 3 subsequently supports the first substrate 1 and the second substrate 2 and electrically connects the first substrate 1 and the second substrate 2.
  • the conductive pillar 3 when the conductive pillar 3 is mounted on the first substrate 1 in step S10, the other end of the conductive pillar 3 can be mounted on the second substrate 2; when the conductive pillar 3 is mounted on the second substrate 2 in step S10, the other end of the conductive pillar 3 can be mounted on the first substrate 1; the first substrate 1 and the second substrate 2 are mounted in a reverse mounting manner, and after mounting, the conductive pillar 3 is arranged between the first substrate 1 and the second substrate 2 to play a role of physical support and electrical connection for signal transmission, the first substrate 1 and the second substrate 2 are arranged relatively spaced, and the first electronic component 4 and the second electronic component 5 are arranged facing each other; the first substrate 1, the second substrate 2 and the conductive pillars enclose a receiving space 9;
  • the third electronic component 6 may include one or a combination of a chip, a resistor or a sensing element, and those skilled in the art may configure the components according to actual needs.
  • the package 8 formed after step S30 is plastic-sealed, and the first electronic component 4 , the second electronic component 5 and the third electronic component 6 can be completely encapsulated by only one plastic-sealing.
  • the material of the plastic-sealing layer 7 can be epoxy resin.
  • the first electronic component 4 is first mounted on the first substrate 1 by surface mounting technology, and the second electronic component 5 is mounted on the second substrate 2, and then the first substrate 1 and the second substrate 2 are mounted to form a vertical stacking structure, and the third electronic component 6 is mounted on the other side of the first substrate 1, and finally the package 8 after mounting is completed is plastic-sealed once to obtain the required packaged product.
  • the prior art referring to FIG.
  • the packaged product also includes a first substrate 10, a second substrate 20, a first electronic component 40, a second electronic component 50, a third electronic component 60, a conductive column 30 and a plastic sealing layer 70, but the packaging method adopted in the prior art is to first plastic-seal two packages (the package mentioned here includes an electronic component and a substrate) and then stack them, and then mount the third electronic component 6 and perform the next plastic sealing, and a total of three plastic sealing processes are required in the prior art, while the embodiment of the present application only needs to perform one plastic sealing, which reduces two plastic sealing processes, and the mounting process is concentrated, and the workpiece does not need to be transported back and forth between the equipment, thereby improving the production efficiency.
  • the packaging method adopted in the prior art is to first plastic-seal two packages (the package mentioned here includes an electronic component and a substrate) and then stack them, and then mount the third electronic component 6 and perform the next plastic sealing, and a total of three plastic sealing processes are required in the prior art, while the embodiment of the present application only needs to perform
  • the plastic sealing layer 7 on the first package needs to be at least N away from the highest point of the first electronic component 4, and the plastic sealing layer 7 on the second package needs to be at least N away from the highest point of the second electronic component 5. Therefore, the highest point of the first electronic component 4 needs to be at least 2N thick or the distance from the highest point of the second electronic component 5.
  • the first substrate 1 and the second substrate 2 are first mounted and then plastic sealed.
  • the plastic sealing layer 7 between the highest point of the first electronic component 4 and the highest point of the second electronic component 5 can be only N thick, which can reduce the thickness of the plastic sealing layer 7, thereby improving the integration density of the packaged product, and finally reducing the volume of the sealed product, which is more in line with the requirements of small-size packaged products.
  • This embodiment has the advantages of being able to simplify the process, improve production efficiency, and have a high integration density and can reduce the package volume.
  • the packaging method of the present application only one packaged product can be produced at a time, and the number of the first electronic component 4, the second electronic component 5 and the third electronic component 6 is one. At least two packaged products can also be produced at a time, which is suitable for mass production in factories. Specifically:
  • FIG. 2 is a flow chart of the second embodiment of the present application.
  • at least two electronic components can be mounted on the substrate at one time, that is, at least two first electronic components 4 are mounted on the first substrate 1, at least two second electronic components 5 are mounted on the second substrate 2, and at least two third electronic components 6 are mounted on the third substrate.
  • the number of the first electronic components 4, the second electronic components 5 and the third electronic components 6 can be equal.
  • step S40 an integrated product of multiple packaged products is formed
  • the first substrate 1 and the second substrate 2 are respectively divided into multiple sub-boards by cutting
  • the plastic sealing layer 7 is cut into multiple plastic sealing sub-layers
  • the packaged products after cutting have the same structure, including a sub-board, a plastic sealing sub-layer, a first electronic component 4, a second electronic component 5 and a third electronic component 6.
  • cutting can be performed along the dotted line A in FIG8 , and the obtained packaged product is shown in FIG9 .
  • a plurality of electronic components are mounted on the first substrate 1 and the second substrate 2 at one time and are centrally plastic-sealed.
  • An integrated product of a plurality of packaged products is first manufactured and then cut to form a single packaged product, thereby further improving production efficiency and the overall stability of the manufacturing process.
  • FIG. 3 is a schematic diagram of a flow chart of a third embodiment of the present application.
  • the step of S50 includes:
  • Cutting can be done with an ordinary cutting blade. Cutting along the vertical direction is relatively simple. It can also ensure that each product has the same shape and structure, and ensure the consistency of the packaged products obtained.
  • the step of mounting the first substrate 1 and the second substrate 2 so as to be electrically connected via the conductive pillars 3 includes:
  • the mounting makes the first pin of the first substrate 1 and the second pin of the second substrate 2 electrically connected through the conductive pillar 3.
  • the first pin and the second pin can be solder pads, and the conductive pillar 3 connects the first pin and the second pin to play the role of physical support and electrical connection to transmit signals.
  • the conductive pillar 3 can be a copper pillar.
  • step of S40 further includes:
  • the plastic sealing layer 7 fills up the accommodation space 9 surrounded by the first substrate 1, the second substrate 2 and the conductive column 3.
  • the vertical stacking of two packages after plastic sealing causes an inevitable gap 80 between the two packages, which affects the mechanical strength of the final product.
  • the first substrate 1 and the second substrate 2 are mounted first and then plastic sealed, so that the plastic sealing layer 7 can completely wrap and fill up the space between the first electronic component 4 and the second electronic component 5. There is no gap in the accommodation space 9 after the plastic sealing layer 7 is filled, which greatly improves the mechanical strength of the packaged product.
  • the present application further provides a packaged product, comprising a first substrate 1, a second substrate 2, a first electronic component 4, a second electronic component 5, a third electronic component 6, a conductive column 3 and a plastic sealing layer 7, wherein the first electronic component 4 and the third electronic component 6 are respectively mounted on opposite sides of the first substrate 1, the second electronic component 5 is mounted on the second substrate 2, the first substrate 1 and the second substrate 2 are arranged opposite to each other, the first substrate 1, the second substrate 2 and the conductive column 3 enclose a receiving space 9, the first electronic component 4 and the second electronic component 5 are located in the receiving space 9, the plastic sealing layer 7 comprises a first plastic sealing layer 71 and a second plastic sealing layer 72, the first plastic sealing layer 71 fills the receiving space 9 and wraps the first electronic component 4 and the second electronic component 5, and the second plastic sealing layer 72 wraps the third electronic component 6.
  • the vertical stacking of the two packaging bodies after plastic sealing causes an inevitable gap 80 between the two packaging bodies of the packaged product, which affects the mechanical strength of the final product.
  • the plastic layer 7 between the first substrate 1 and the second substrate 2 completely fills the space between the first electronic component 4 and the second electronic component 5, and there is no gap in the plastic layer 7 or between the plastic layer 7 and the copper column, which greatly improves the mechanical strength of the packaged product.
  • the packaged product of this embodiment can be made by the packaging method of the above-mentioned packaged product, and therefore, has all the beneficial effects of the packaging method of the above-mentioned packaged product, which will not be repeated here one by one.
  • a first pin is provided on the first substrate 1
  • a second pin is provided on the second substrate 2
  • the conductive column 3 is a copper column
  • the conductive column 3 connects the first pin and the second pin.
  • the first pin and the second pin can be pads, and the conductive column 3 connects the first pin and the second pin to play the role of physical support and electrical connection to transmit signals.
  • the first electronic component 4, the second electronic component 5 and the third electronic component 6 each include at least one of a chip, a resistor, and a sensing element. Those skilled in the art can make settings according to actual needs.
  • the present application also provides an electronic device, which includes the above-mentioned packaged product.
  • the above-mentioned electronic device may be a portable intelligent wearable device, such as a mobile phone, a tablet, a telegraph, or a bracelet. Since the electronic device includes all the technical solutions of all the embodiments of the above-mentioned packaged product, it has at least all the beneficial effects brought by all the above-mentioned technical solutions, which will not be repeated here one by one.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本申请提供一种封装产品、电子设备及封装产品的封装方法，封装产品的封装方法包括以下步骤：提供第一基板和第二基板，在第一基板上贴装至少一个第一电子组件，在第二基板上贴装至少一个第二电子组件；并在第一基板和第二基板其中一个上设置导电柱；贴装使第一基板和第二基板通过导电柱电连接，且第一电子组件和第二电子组件面对设置；在第一基板背离第一电子组件的一侧贴装至少一个第三电子组件形成封装件；对封装件进行塑封形成塑封层以包裹第一电子组件、第二电子组件和第三电子组件。

Description

封装产品、电子设备及封装产品的封装方法
本申请要求于2022年11月22号申请的、申请号为202211465484.8的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及封装产品技术领域，尤其涉及一种封装产品、电子设备及封装产品的封装方法。
 背景技术
封装体叠层技术是将具有相同或相似外形逻辑和存储芯片的封装体进行再集成。3D封装是将两个封装体分别塑封形成塑封层之后再进行垂直堆叠。由于需要单独制作两个封装体并分别塑封，工序较多，生产效率低，不适合量产；并且每个封装体的塑封高度都有要求，两个封装体的塑封层叠加后会造成体积较大，集成密度低。
鉴于此，有必要提供一种新的封装产品、电子设备及封装产品的封装方法，以解决或至少缓解上述技术缺陷。
 技术问题
本申请的主要目的是提供一种封装产品、电子设备及封装产品的封装方法，旨在解决现有技术中封装产品的封装方法工序多、生产效率低、体积较大、集成密度低的技术问题。
 技术解决方案
为实现上述目的，根据本申请的一个方面，本申请提供一种封装产品的的封装方法，所述封装产品的封装方法包括以下步骤：
提供第一基板和第二基板，在所述第一基板上贴装至少一个第一电子组件，在所述第二基板上贴装至少一个第二电子组件；并在所述第一基板和所述第二基板其中一个上设置导电柱；
贴装使所述第一基板和所述第二基板通过所述导电柱电连接，且所述第一电子组件和所述第二电子组件面对设置；
在所述第一基板背离所述第一电子组件的一侧贴装至少一个第三电子组件形成封装件；
对所述封装件进行塑封形成塑封层以包裹所述第一电子组件、第二电子组件和第三电子组件。
在一实施例中，所述第一电子组件、所述第二电子组件和所述第三电子组件的数量均为一个。
在一实施例中，所述第一电子组件的数量至少为两个，所述第二电子组件的数量至少为两个，所述第三电子组件的数量至少为两个，所述对所述封装件进行塑封形成塑封层以包裹所述第一电子组件、第二电子组件和第三电子组件的步骤之后，还包括：
切割所述塑封层、第一基板和第二基板得到所述封装产品。
在一实施例中，所述切割所述塑封层、第一基板和第二基板得到所述封装产品的步骤包括：
采用切割刀沿竖直方向切割所述塑封层、第一基板和第二基板得到所述封装产品。
在一实施例中，所述贴装使所述第一基板和所述第二基板通过所述导电柱电连接的步骤包括：
贴装使所述第一基板的第一引脚和所述第二基板的第二引脚通过所述导电柱电连接。
在一实施例中，所述对所述封装件进行塑封形成塑封层以包裹所述第一电子组件、第二电子组件和第三电子组件的步骤，还包括：
所述塑封层填充满所述第一基板、第二基板和导电柱围成的容纳空间。
根据本申请的又一个方面，本申请还提供一种封装产品，包括第一基板、第二基板、第一电子组件、第二电子组件、第三电子组件、导电柱和塑封层，所述第一电子组件和所述第三电子组件分别安装于所述第一基板相背的两侧，所述第二电子组件安装于所述第二基板，所述第一基板和所述第二基板相对设置，所述第一基板、第二基板和导电柱围成容纳空间，所述第一电子组件和所述第二电子组件位于所述容纳空间内，所述塑封层包括第一塑封层和第二塑封层，所述第一塑封层填充满所述容纳空间并包裹所述第一电子组件和第二电子组件，所述第二塑封层包裹所述第三电子组件。
在一实施例中，所述第一基板上设置有第一引脚，所述第二基板上设置有第二引脚，所述导电柱为铜柱，所述导电柱连接所述第一引脚和所述第二引脚。
在一实施例中，所述第一电子组件、所述第二电子组件和所述第三电子组件均包括芯片、电阻、感应元件中的至少一个。
根据本申请的另一个方面，本申请还提供一种电子设备，所述电子设备包括上述所述的封装产品。
 有益效果
上述方案中，封装产品的封装方法包括以下步骤：提供第一基板和第二基板，在第一基板上贴装至少一个第一电子组件，在第二基板上贴装至少一个第二电子组件；并在第一基板和第二基板其中一个上设置导电柱；贴装使第一基板和第二基板通过导电柱电连接，且第一电子组件和第二电子组件面对设置；在第一基板背离第一电子组件的一侧贴装至少一个第三电子组件形成封装件；对封装件进行塑封形成塑封层以包裹第一电子组件、第二电子组件和第三电子组件。本申请中，先通过表面贴装技术并在第一基板上贴装好第一电子组件，在第二基板上贴装好第二电子组件后，再将第一基板和第二基板贴装后组成垂直堆叠的结构，并在第一基板的另一侧贴装第三电子组件，最后再对贴装完成后的封装件进行一次塑封即可得到需要的封装产品。现有技术中需要进行三次塑封工序，而该申请只需要进行一次塑封，减少了塑封工序，并且将贴装工序集中，工件不需要在设备之间来回转运，提升了生产效率。再者，由于塑封工序中对塑封层的表面离电子组件最高点有最低高度要求，这个最低高度要求用N表示。当对封装体单独塑封后再进行堆叠时，第一个封装体上的塑封层距离第一电子组件的最高点至少需要N的距离，第二个封装体上的塑封层距离第二电子组件的最高点至少需要N的距离，因此第一电子组件的最高点距离第二电子组件的最高点至少需要有2N的厚度距离填充塑封层。而本申请中，先对第一基板和第二基板进行贴装再进行一次塑封而言，第一电子组件的最高点距离第二电子组件的最高点之间的塑封层可以仅有一个N的厚度，这样可以减小塑封层的厚度，提高封装产品的集成密度，并最终减小封住产品的体积，更符合小尺寸封装产品的要求。该申请具有能够简化工序，提升生产效率，并且集成密度大，能够减小封装体积的优点。
 附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请实施例封装产品的封装方法的第一实施例的流程示意图；
图2为本申请实施例封装产品的封装方法的第二实施例的流程示意图；
图3为本申请实施例封装产品的封装方法的第三实施例的流程示意图；
图4为现有技术制作的封装产品的剖面结构示意图；
图5为本申请实施例封装产品的第一基板、第二基板、导电柱、第一电子组件和第二电子组件的结构示意图；
图6为本申请实施例封装产品的第一基板和第二基板贴合后的剖面结构示意图；
图7为本申请实施例封装产品在图6的结构上贴合第三电子组件后的剖面结构示意图；
图8为本申请实施例封装产品的在图7的结构上增加塑封层后的剖面结构示意图；
图9为本申请实施例封装产品的剖面结构示意图。
现有技术附图4标号说明：
10、第一基板；20、第二基板；30、导电柱；40、第一电子组件；50、第二电子组件；60、第三电子组件；70、塑封层；80、间隙。
本申请附图5至图9标号说明：
1、第一基板；2、第二基板；3、导电柱；4、第一电子组件；5、第二电子组件；6、第三电子组件；7、塑封层；71、第一塑封层；72、第二塑封层；8、封装件；9、容纳空间。
本申请目的的实现、功能特点及优点将结合实施方式，参照附图做进一步说明。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请的一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
需要说明，本申请实施方式中所有方向性指示（诸如上、下……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中如涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。
并且，本申请各个实施方式之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
参照图1，图1为本申请封装产品的封装方法的第一实施例的流程示意图，封装产品的封装方法包括以下步骤：
S10，提供第一基板1和第二基板2，在第一基板1上贴装至少一个第一电子组件4，在第二基板2上贴装至少一个第二电子组件5；并在第一基板1和第二基板2其中一个上设置导电柱3；
结合参照图5，第一基板1和第二基板2可以采用印制电路板，第一电子组件4贴装于第一基板1的一侧，第二电子组件5贴装于第二基板2的一侧，第一电子组件4和第二电子组件5可以包括芯片、电阻或感应元器件中的一种或多种，本领域技术人员可以根据实际需要设置。可以在第一基板1和第二基板2中的一个上贴装或者焊接导电柱3，导电柱3后续起到支撑第一基板1和第二基板2以及电连接第一基板1和第二基板2的作用。
S20，贴装使第一基板1和第二基板2通过导电柱3电连接，且第一电子组件4和第二电子组件5面对设置；
结合参照图6，当导电柱3在S10步骤中是安装于第一基板1时，可以将导电柱3的另一端贴装到第二基板2上；当导电柱3在S10步骤中是安装于第二基板2时，可以将导电柱3的另一端贴装到第一基板1上；此处第一基板1和第二基板2采用的是倒贴装的方式，贴装完成后，导电柱3设置于第一基板1和第二基板2之间起到物理支撑和电连接传递信号的作用，第一基板1和第二基板2相对间隔设置，第一电子组件4和第二电子组件5面对设置；第一基板1、第二基板2和导电柱围成容纳空间9；
S30，在第一基板1背离第一电子组件4的一侧贴装至少一个第三电子组件6形成封装件8；
结合参照图7，与第一电子组件4和第二电子组件5类似，第三电子组件6可以包括芯片、电阻或感应元器件中的一种或集中，本领域技术人员可以根据实际需要设置。
S40，对封装件8进行塑封形成塑封层7以包裹第一电子组件4、第二电子组件5和第三电子组件6；
结合参照图8，对在S30步骤完成后形成的封装件8进行塑封，可以仅通过一次塑封将第一电子组件4、第二电子组件5和第三电子组件6全部包裹住。具体地，塑封层7的材料可以采用环氧树脂。
本申请的上述实施例中，先通过表面贴装技术并在第一基板1上贴装好第一电子组件4，在第二基板2上贴装好第二电子组件5后，再将第一基板1和第二基板2贴装后组成垂直堆叠的结构，并在第一基板1的另一侧贴装第三电子组件6，最后再对贴装完成后的封装件8进行一次塑封即可得到需要的封装产品。而现有技术中，参照图4，封装产品同样包括第一基板10、第二基板20、第一电子组件40、第二电子组件50、第三电子组件60、导电柱30和塑封层70，然而现有技术采用的封装方法是先对两个封装体（这里说的封装体包括一电子组件和一个基板）分别塑封成型后再进行堆叠，然后再贴装第三电子组件6和进行下一次塑封，现有技术中总共需要进行三次塑封工序，而本申请该实施例只需要进行一次塑封，减少了两次塑封工序，并且将贴装工序集中，工件不需要在设备之间来回转运，提升了生产效率。再者，由于塑封工序中对塑封层7的表面离电子组件最高点（这里的最高点指电子组件距离对应基板最远的点）有最低高度要求，这个最低高度要求用N表示。当对封装体单独塑封后再进行堆叠时，第一个封装体上的塑封层7距离第一电子组件4的最高点至少需要N的距离，第二个封装体上的塑封层7距离第二电子组件5的最高点至少需要N的距离，因此第一电子组件4的最高点距离第二电子组件5的最高点至少需要有2N的厚度或者说距离填充塑封层7。而本申请的实施例中，先对第一基板1和第二基板2进行贴装再进行一次塑封而言，第一电子组件4的最高点距离第二电子组件5的最高点之间的塑封层7可以仅有一个N的厚度，这样可以减小塑封层7的厚度，进而能够提高封装产品的集成密度，并最终减小封住产品的体积，更符合小尺寸封装产品的要求。该实施例具有能够简化工序，提升生产效率，并且集成密度大，能够减小封装体积的优点。
采用本申请的封装方法，可以一次只制作一个封装产品，此时第一电子组件4、第二电子组件5和第三电子组件6的数量均为一个。也可以一次制作至少两个封装产品，适合于工厂大批量生产，具体地：
请参照图2，图2为本申请的第二实施例的流程示意图，根据本申请的第二实施例，可以在基板上一次贴装至少两个电子组件，即在第一基板1上贴装至少两个第一电子组件4，在第二基板2上贴装至少两个第二电子组件5，在第三基板上贴装至少两个第三电子组件6，第一电子组件4、第二电子组件5和第三电子组件6的数量可以相等，在S40的步骤之后，还包括：
S50，切割塑封层7、第一基板1和第二基板2得到封装产品。
结合参照图8，此时，在S40步骤之后形成了多个封装产品的集成产品，通过切割的形式将第一基板1和第二基板2分别分割呈多个子板，同时将塑封层7切割成多个塑封子层，切割完成后的封装产品结构相同，均包括一个子板、塑封子层、第一电子组件4、一个第二电子组件5和一个第三电子组件6。具体地，可沿图8中的虚线A进行切割，得到的封装产品如图9所示。
本申请的上述实施例中，通过一次在第一基板1和第二基板2上贴装多个电子组件的方式，并进行集中塑封，采用先制作多个封装产品的集成产品然后通过切割形成单体的封装产品的形式，进一步提升了生产效率，也提升了制作过程整体的稳定性。
参照图3，图3为本申请的第三实施例的流程示意图，根据本申请的第三实施例，S50的步骤包括：
S50’，采用切割刀沿竖直方向切割塑封层7、第一基板1和第二基板2得到封装产品。
切割采用普通的切割刀片即可切开，沿竖直方向切割操作较为简单，还可以确保每一产品形状和结构相同，并确保得到的封装产品的一致性。
具体地，贴装使第一基板1和第二基板2通过导电柱3电连接的步骤包括：
贴装使第一基板1的第一引脚和第二基板2的第二引脚通过导电柱3电连接。第一引脚和第二引脚可以焊盘，导电柱3连接第一引脚和第二引脚起到物理支撑和电连接传递信号的作用。上述导电柱3可以是铜柱。
在一具体地实施例中，S40的步骤还包括：
塑封层7填充满第一基板1、第二基板2和导电柱3围成的容纳空间9。现有技术中，参照图4，两个封装体塑封后垂直堆叠造成两个封装体之间不可避免的存在间隙80，影响最终产品的机械强度。该实施例先将第一基板1和第二基板2贴装后再进行塑封，使得塑封层7可以完全包裹填充满第一电子组件4和第二电子组件5之间的空间，填充满塑封层7后的容纳空间9内存在任何间隙，大大提升了封装产品的机械强度。
参照图5至图9，根据本申请的又一个方面，本申请还提供一种封装产品，包括第一基板1、第二基板2、第一电子组件4、第二电子组件5、第三电子组件6、导电柱3和塑封层7，第一电子组件4和第三电子组件6分别安装于第一基板1相背的两侧，第二电子组件5安装于第二基板2，第一基板1和第二基板2相对设置，第一基板1、第二基板2和导电柱3围成容纳空间9，第一电子组件4和第二电子组件5位于容纳空间9内，塑封层7包括第一塑封层71和第二塑封层72，第一塑封层71填充满容纳空间9并包裹第一电子组件4和第二电子组件5，第二塑封层72包裹第三电子组件6。现有技术中，参照图4，两个封装体塑封后垂直堆叠造成封装产品的两个封装体之间不可避免的存在间隙80，影响最终产品的机械强度。该实施例第一基板1和第二基板2之间的塑封层7完全填充满第一电子组件4和第二电子组件5之间的空间，在塑封层7内，以及塑封层7和铜柱之间都不存在任何间隙，大大提升了封装产品的机械强度。并且，本实施例的封装产品可以由上述封装产品的封装方法制作而成，因此，具有上述封装产品的封装方法的所有有益效果，在此不在一一赘述。
在一实施例中，第一基板1上设置有第一引脚，第二基板2上设置有第二引脚，导电柱3为铜柱，导电柱3连接第一引脚和第二引脚。第一引脚和第二引脚可以焊盘，导电柱3连接第一引脚和第二引脚起到物理支撑和电连接传递信号的作用。第一电子组件4、第二电子组件5和第三电子组件6均包括芯片、电阻、感应元件中的至少一个。本领域技术人员可以根据实际需要进行设置。
根据本申请的另一个方面，本申请还提供一种电子设备，电子设备包括上述的封装产品。上述电子设备可以是便携式智能可穿戴设备，如手机、平板电报或手环等。由于电子设备包括了上述封装产品的所有实施例的全部技术方案，因此至少具有上述全部技术方案带来的所有有益效果，在此不在一一赘述。
以上仅为本申请的一些实施例，并非因此限制本申请的专利范围，凡是在本申请的技术构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围。

Claims (10)

  1. 一种封装产品的封装方法，其中，所述封装产品的封装方法包括以下步骤：
    提供第一基板和第二基板，在所述第一基板上贴装至少一个第一电子组件，在所述第二基板上贴装至少一个第二电子组件；并在所述第一基板和所述第二基板其中一个上设置导电柱；
    贴装使所述第一基板和所述第二基板通过所述导电柱电连接，且所述第一电子组件和所述第二电子组件面对设置；
    在所述第一基板背离所述第一电子组件的一侧贴装至少一个第三电子组件形成封装件；
    对所述封装件进行塑封形成塑封层以包裹所述第一电子组件、第二电子组件和第三电子组件。
  2. 根据权利要求1所述的封装产品的封装方法，其中，所述第一电子组件、所述第二电子组件和所述第三电子组件的数量均为一个。
  3. 根据权利要求1所述的封装产品的封装方法，其中，所述第一电子组件的数量至少为两个，所述第二电子组件的数量至少为两个，所述第三电子组件的数量至少为两个，所述对所述封装件进行塑封形成塑封层以包裹所述第一电子组件、第二电子组件和第三电子组件的步骤之后，还包括：
    切割所述塑封层、第一基板和第二基板得到所述封装产品。
  4. 根据权利要求3所述的封装产品的封装方法，其中，所述切割所述塑封层、第一基板和第二基板得到所述封装产品的步骤包括：
    采用切割刀沿竖直方向切割所述塑封层、第一基板和第二基板得到所述封装产品。
  5. 根据权利要求1至4中任一项所述的封装产品的封装方法，其中，所述贴装使所述第一基板和所述第二基板通过所述导电柱电连接的步骤包括：
    贴装使所述第一基板的第一引脚和所述第二基板的第二引脚通过所述导电柱电连接。
  6. 根据权利要求1至4中任一项所述的封装产品的封装方法，其中，所述对所述封装件进行塑封形成塑封层以包裹所述第一电子组件、第二电子组件和第三电子组件的步骤，还包括：
    所述塑封层填充满所述第一基板、第二基板和导电柱围成的容纳空间。
  7. 一种封装产品，其中，所述封装产品包括第一基板、第二基板、第一电子组件、第二电子组件、第三电子组件、导电柱和塑封层，所述第一电子组件和所述第三电子组件分别安装于所述第一基板相背的两侧，所述第二电子组件安装于所述第二基板，所述第一基板和所述第二基板相对设置，所述第一基板、第二基板和导电柱围成容纳空间，所述第一电子组件和所述第二电子组件位于所述容纳空间内，所述塑封层包括第一塑封层和第二塑封层，所述第一塑封层填充满所述容纳空间并包裹所述第一电子组件和第二电子组件，所述第二塑封层包裹所述第三电子组件。
  8. 根据权利要求7所述的封装产品，其中，所述第一基板上设置有第一引脚，所述第二基板上设置有第二引脚，所述导电柱为铜柱，所述导电柱连接所述第一引脚和所述第二引脚。
  9. 根据权利要求7所述的封装产品，其中，所述第一电子组件、所述第二电子组件和所述第三电子组件均包括芯片、电阻、感应元件中的至少一个。
  10. 一种电子设备，其中，所述电子设备包括权利要求7至9中任一项所述的封装产品。
PCT/CN2023/130804 2022-11-22 2023-11-09 封装产品、电子设备及封装产品的封装方法 WO2024109554A1 (zh)

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