WO2024103995A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

Info

Publication number
WO2024103995A1
WO2024103995A1 PCT/CN2023/123339 CN2023123339W WO2024103995A1 WO 2024103995 A1 WO2024103995 A1 WO 2024103995A1 CN 2023123339 W CN2023123339 W CN 2023123339W WO 2024103995 A1 WO2024103995 A1 WO 2024103995A1
Authority
WO
WIPO (PCT)
Prior art keywords
blocking
layer
display substrate
area
conductive layer
Prior art date
Application number
PCT/CN2023/123339
Other languages
English (en)
French (fr)
Inventor
陈鸿
王格
王苗
蒋志亮
李晨曦
牛戈
罗翔
王登宇
李春延
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024103995A1 publication Critical patent/WO2024103995A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • an embodiment of the present disclosure provides a display substrate, comprising a display area and a frame area, wherein the frame area is located around the display area, and the frame area is provided with a first blocking structure and a second blocking structure; in a direction perpendicular to the plane where the display substrate is located, the display substrate comprises a base and a driving structure, a light-emitting structure layer, and a packaging structure layer stacked in sequence on the base, the first blocking structure is arranged between the driving structure layer and the packaging structure layer, and the second blocking structure is arranged in the driving structure layer.
  • the first barrier structure and the second barrier structure are both in a strip shape, and an extending direction of the first barrier structure and the second barrier structure is consistent with an extending direction of an edge of the display area.
  • the first blocking structure includes a first blocking dam and a second blocking dam.
  • the frame area includes a first blocking area and a second blocking area, the first blocking area is located between the display area and the first blocking dam, and the second blocking area is located between the first blocking dam and the second blocking dam; the second blocking structure is arranged at at least one position between the first blocking area and the second blocking area.
  • the size of the first blocking structure in a direction perpendicular to the plane of the display substrate, is greater than or equal to the size of the second blocking structure, and the size of the second blocking dam is greater than or equal to the size of the first blocking dam; in an extension direction perpendicular to the edge of the display area, the size of the second blocking dam is greater than or equal to the size of the first blocking dam.
  • the driving structure layer includes a first semiconductor layer, a first gate insulation layer, a first conductive layer, a second gate insulation layer, a second conductive layer, an interlayer insulation layer, a third conductive layer, a planarization layer and a fourth conductive layer stacked in sequence on the substrate, and the second blocking structure is arranged in one or more layers of the first semiconductor layer, the first conductive layer and the second conductive layer.
  • the second blocking structure is a single-layer structure, and the second blocking structure includes a plurality of strip-shaped protruding structures, and the plurality of strip-shaped protruding structures are arranged in one or more layers of the first semiconductor layer, the first conductive layer, and the second conductive layer; in a direction perpendicular to the plane where the display substrate is located, the size of any protruding structure is consistent with the thickness of the film layer where it is located.
  • the second blocking structure is a multi-layer structure, and the second blocking structure includes a plurality of strip-shaped protruding structures, and the plurality of strip-shaped protruding structures are disposed in a plurality of film layers in the first semiconductor layer, the first conductive layer, and the second conductive layer.
  • the multiple strip-shaped protrusion structures have consistent sizes, any one protrusion structure includes sub-protrusion structures located in multiple film layers, and the orthographic projections of multiple sub-protrusion structures in the same protrusion structure on the base at least partially overlap.
  • sizes of the plurality of strip-shaped protruding structures in a direction perpendicular to a plane where the display substrate is located increase sequentially.
  • the second blocking structure includes a first convex structure, a second convex structure, and a third convex structure, wherein the first convex structure is disposed on the first semiconductor layer, the second convex structure is disposed on the first semiconductor layer and the first conductive layer, and the third convex structure is disposed on the first semiconductor layer, the first conductive layer, and the second conductive layer. layer and the second conductive layer.
  • the second convex structure includes two second sub-convex structures respectively located in the first semiconductor layer and the first conductive layer, and the orthographic projections of the two second sub-convex structures on the substrate at least partially overlap;
  • the third convex structure includes three third sub-convex structures respectively located in the first semiconductor layer, the first conductive layer, and the second conductive layer, and the orthographic projections of the three third sub-convex structures on the substrate at least partially overlap.
  • the second blocking structure further includes at least one stripe-shaped groove structure, and the stripe-shaped groove structure is disposed in one or more layers of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.
  • the groove structure in a direction parallel to the plane of the display substrate, in the first blocking area, the groove structure is located between the display area and the protrusion structure; in the second blocking area, the groove structure is located between the first blocking dam and the protrusion structure.
  • the heights of the surfaces of the groove structure and the protrusion structure in the second blocking structure away from the substrate on the side thereof increase sequentially relative to the substrate.
  • At least one of the third conductive layer and the fourth conductive layer extends to the border area in a direction parallel to the plane of the display substrate, at least one film layer of the third conductive layer and the fourth conductive layer is provided with a second power line, and an orthographic projection of the second blocking structure on the substrate and an orthographic projection of the second power line on the substrate have an overlapping area.
  • a cross-sectional shape of an orthographically projected overlapping region of the third conductive layer, the fourth conductive layer, and the second blocking structure on the substrate is consistent with a cross-sectional shape of the second blocking structure.
  • a GOA circuit is disposed in the border area, and an orthographic projection of the GOA circuit on the substrate does not overlap with an orthographic projection of the second blocking structure on the substrate.
  • the driving structure layer includes a first semiconductor layer, a first gate insulating layer, a first conductive layer, a second gate insulating layer, a second conductive layer, an interlayer insulating layer, a third conductive layer, a planarization layer, and a fourth conductive layer sequentially stacked on the substrate, and the second blocking structure is disposed on one of the first semiconductor layer, the first gate insulating layer, the first conductive layer, the second gate insulating layer, the second conductive layer, and the interlayer insulating layer or layers. Multi-layer.
  • the groove structure and the patterns on the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer are formed by a single patterning process.
  • the strip-shaped protruding structure and the film layer where it is located are manufactured through a single patterning process.
  • the second blocking structure includes at least one stripe-shaped protruding structure, or the second blocking structure includes at least one stripe-shaped groove structure, or the second blocking structure includes at least one stripe-shaped protruding structure and at least one stripe-shaped groove structure.
  • the same strip-shaped protrusion structure in the extension direction of the second blocking structure, includes multiple protrusion structure segments, and a protrusion spacing structure is provided between two adjacent protrusion structure segments; the same strip-shaped groove structure includes multiple groove structure segments, and a groove spacing structure is provided between two adjacent groove structure segments.
  • the second blocking structure includes a plurality of protruding structures, and the plurality of protruding structures are arranged in a direction perpendicular to the edge of the display area, wherein a plurality of protruding structure segments in the plurality of protruding structures are arranged in an array, or a plurality of protruding structure segments in the plurality of protruding structures are arranged in a staggered manner.
  • the extension direction of two adjacent protrusion structure segments forms a first angle and a second angle with the extension direction of the protrusion structure, respectively, and the first angle and the second angle are located on both sides of the extension direction of the protrusion structure.
  • the first angle and the second angle are both less than or equal to 15 degrees.
  • the multiple protruding structure segments include multiple protruding structure combinations, the same protruding structure combination includes at least two interconnected protruding structure segments, and two adjacent protruding structure segments form a third angle toward the display area or toward the first blocking structure.
  • the interval between two adjacent protruding structures is 0.4 micrometers to 5.5 micrometers; and the width of the protruding structures is 0.8 micrometers to 5.6 micrometers.
  • the encapsulation structure layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer
  • the first blocking structure is configured to prevent the second encapsulation layer from flowing
  • the second blocking structure is configured to slow down the flow rate of the second encapsulation layer.
  • an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.
  • the present disclosure also provides a method for preparing a display substrate, wherein the display substrate comprises a display area and a frame area, wherein the frame area is located around the display area; in a direction perpendicular to the plane where the display substrate is located, the display substrate includes a substrate and a light-emitting device layer and a packaging structure layer sequentially stacked on the substrate; the preparation method includes:
  • a first blocking structure and a second blocking structure are formed in the frame area, wherein the first blocking structure is located between the light emitting device layer and the encapsulation structure layer, and the second blocking structure is located in the light emitting device layer.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic structural diagram of a display substrate
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG6 is a working timing diagram of a pixel driving circuit
  • FIG7 is a schematic diagram showing a planar structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG8a is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG8b is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8c is a schematic diagram showing an enlarged structure of the position a1 in FIG7 ;
  • FIG8d is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8e is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8f is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8g is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8h is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8i is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG8j is a schematic diagram showing the capillary effect between the protruding structures in an exemplary embodiment of the present disclosure
  • FIG9a is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG9b is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG10a is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG10b is a schematic diagram showing an enlarged structure of the position a1 in FIG7 ;
  • FIG11a is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG11b is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG11c is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG11d is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7;
  • FIG11e is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7 ;
  • FIG11f is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7 ;
  • FIG11g is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7 ;
  • FIG11h is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG11i is a schematic diagram of a cross-sectional structure at the position L1-L1 in FIG7 ;
  • FIG11j is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG12a is a schematic diagram of a cross-sectional structure at the position L2-L2 in FIG7;
  • FIG12b is a schematic diagram of an enlarged structure of the position a1 in FIG7 ;
  • FIG12c is a schematic diagram showing an enlarged structure of the position a2 in FIG7 ;
  • FIG13a is a schematic diagram of a cross-sectional structure at the position L2-L2 in FIG7;
  • FIG. 13 b is a schematic diagram of a cross-sectional structure at the L1 - L1 position in FIG. 7 .
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged.
  • the “gate electrode” and the “drain electrode” can be interchanged, and the "source terminal” and the “drain terminal” can be interchanged. In the embodiment of the present disclosure, the gate electrode can be called the control electrode.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line and a pixel driving circuit.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample the grayscale values using the clock signal and apply the data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • Scan driver The scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm can be generated by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver can sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and the scan signal can be generated in a manner that the scan start signal provided in the form of a conduction level pulse is sequentially transmitted to the next level circuit under the control of the clock signal, and m can be a natural number.
  • the light-emitting driver can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller.
  • the light-emitting driver can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver can be constructed in the form of a shift register, and the emission signal can be generated in a manner that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next level circuit under the control of the clock signal, and o can be a natural number.
  • FIG2 is a schematic diagram of the structure of a display substrate.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, wherein the plurality of sub-pixels Pxij are configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.
  • the display substrate may further include a display area boundary BD, and the display area boundary BD may be an edge of the display area 100 close to the binding area 200.
  • the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area.
  • the fan-out area is connected to the display area and includes a plurality of data fan-out lines.
  • the data fan-out lines are configured to connect the data signal lines (Data Line) of the display area in a fan-out routing manner.
  • the fan-out area occupies a large space, resulting in a large width of the lower frame.
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area.
  • the driver chip area may include an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines.
  • the binding pin area may include a bonding pad configured to be bound and connected to an external flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence in a direction away from the display area.
  • the circuit area is connected to the display area and may include at least a gate drive circuit, which is connected to the first scan signal line, the second scan signal line, the third scan signal line, and the light emitting control line of the pixel drive circuit in the display area.
  • the power line area is connected to the circuit area and may include at least a power lead, which is The line extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area.
  • the crack dam area is connected to the power line area and may at least include a plurality of cracks set on the composite insulating layer.
  • the cutting area is connected to the crack dam area and may at least include a cutting groove set on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.
  • the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area, and the edge of the display area is the edge of one side of the display area binding area or the border area.
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light.
  • Each sub-pixel may include a circuit unit and a light-emitting element
  • the circuit unit may include at least a pixel driving circuit
  • the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line
  • the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element.
  • the light-emitting element in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal
  • the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement or a square arrangement, etc., which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangle arrangement, etc., which is not limited in the present disclosure.
  • FIG4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate The board may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor.
  • the light-emitting structure layer 103 of each sub-pixel may include a light-emitting element composed of a plurality of film layers, and the plurality of film layers may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C, and the pixel driving circuit is respectively connected to 10 signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a light emitting signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a first power line VDD, and a second power line VSS).
  • 10 signal lines a data signal line D, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a light emitting signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a first power line VDD, and a second power line VSS.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor T1, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.
  • a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .
  • control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits the first initialization voltage to the second end of the storage capacitor C to initialize the storage capacitor C.
  • a control electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and a second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode of the third transistor T3.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the light emitting element according to the potential difference between its control electrode and the first electrode.
  • a control electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 inputs a data voltage of the data signal line D to the first node N1.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E
  • the first electrode of the fifth transistor T5 is connected to the first power line VDD
  • the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E
  • the first electrode of the sixth transistor T6 is connected to the third node N3
  • the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element.
  • control electrode of the seventh transistor T7 is connected to the first scan signal line S1
  • first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2
  • second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element.
  • the light-emitting element can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer and a second electrode (cathode).
  • the second electrode of the light emitting element is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD continuously provides a high level signal.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low temperature polysilicon transistor, or an oxide transistor, or a low temperature polysilicon transistor and a metal oxide transistor.
  • the active layer of the low temperature polysilicon transistor is low temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Integrating low temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low frequency driving, reduce power consumption, and improve display quality.
  • FIG6 is a timing diagram of a pixel driving circuit.
  • the following is an exemplary embodiment of the present disclosure, using the working process of the pixel driving circuit illustrated in FIG5 .
  • the pixel driving circuit in FIG5 includes 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C.
  • the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the third transistor T3 to the seventh transistor T7 are P-type low-temperature polysilicon transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signal of the second scan signal line S2 is a turn-on signal (high level), and the signals of the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4 and the light-emitting signal line E are turn-off signals.
  • the turn-on signal of the second scan signal line S2 turns on the first transistor T1, and the signal of the first initial signal line INIT1 is provided to the second node N2 through the first transistor T1 to initialize (reset) the storage capacitor C and clear the original charge in the storage capacitor.
  • the turn-off signals of the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4 and the light-emitting signal line E turn on the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and The seventh transistor T7 is turned off, and the OLED does not emit light in this stage.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signals of the first scanning signal line S1, the third scanning signal line S3 and the fourth scanning signal line S4 are the on signals
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are the off signals
  • the data signal line D outputs the data voltage.
  • the third transistor T3 since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the on signals of the first scanning signal line S1, the third scanning signal line S3 and the fourth scanning signal line S4 turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage of the second end (the second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the signal of the second initial signal line INIT2 is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light.
  • the disconnection signal of the second scanning signal line S2 disconnects the first transistor T1
  • the disconnection signal of the light-emitting signal line E disconnects the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the light-emitting stage
  • the signal of the light-emitting signal line E is a conduction signal
  • the signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3 and the fourth scanning signal line S4 are disconnection signals.
  • the conduction signal of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • )-Vth] 2 K*[(Vdd-Vd)] 2
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • Flexible packaging design usually uses a double barrier dam (Dam, which can be called an isolation dam) to block the inkjet printing layer (Ink jet Print, abbreviated as IJP) to prevent the IJP from crossing the Dam and causing water and oxygen intrusion, which would cause the packaging to fail.
  • DI dam double barrier dam
  • IJP Ink jet Print
  • IJP Ink jet Print
  • An embodiment of the present disclosure provides a display substrate, which may include a display area and a frame area, wherein the frame area is located around the display area, and the frame area is provided with a first blocking structure and a second blocking structure; in a direction perpendicular to the plane where the display substrate is located, the display substrate may include a base and a driving structure layer, a light-emitting structure layer, and a packaging structure layer stacked in sequence on the base, the first blocking structure may be arranged between the driving structure layer and the packaging structure layer, and the second blocking structure may be arranged on the driving structure layer.
  • the display substrate provided by the embodiment of the present disclosure includes a display area and a frame area.
  • the frame area is provided with a first blocking structure and a second blocking structure.
  • the display substrate In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a base and a driving structure layer, a light-emitting structure layer, and a packaging structure layer stacked in sequence on the base.
  • the first blocking structure is arranged between the driving structure layer and the packaging structure layer, and the second blocking structure is arranged in the driving structure layer.
  • the arrangement of the second blocking structure in combination with the first blocking structure greatly improves the packaging effect of the narrow-frame display substrate.
  • the light emitting structure layer does not extend to the frame area, therefore, the first blocking structure can be disposed between the driving structure layer and the packaging structure layer.
  • the light emitting structure layer can extend to the frame area and can extend to the area where the first blocking structure is located, and the first blocking structure can be disposed between the light emitting structure layer and the packaging structure layer.
  • Figure 8a is a schematic diagram of the cross-sectional structure at the position L1-L1 in Figure 7
  • Figures 8b to 8i are several enlarged schematic diagrams of the structure at the position a1 in Figure 7.
  • the display substrate may include a display area 10 and a frame area 20, the frame area 20 is located around the display area 10, and the frame area 20 is provided with a first blocking structure 11 and a second blocking structure 12; in the direction Z perpendicular to the plane where the display substrate is located, the display substrate may include a substrate 101 and a light-emitting device layer 100 and a packaging structure layer 104 sequentially stacked on the substrate 101, the first blocking structure 11 may be arranged between the light-emitting device layer 100 and the packaging structure layer 104, and the second blocking structure 12 may be arranged in the light-emitting device layer 100.
  • the light-emitting device layer 100 may include a driving structure layer 102 and a light-emitting structure layer 103 sequentially stacked on the substrate 101.
  • the second blocking structure 12 may be arranged in the driving structure layer 102 in the light-emitting device layer 100.
  • the light emitting structure layer 103 may include a pixel definition layer 13, but is not limited to the pixel definition layer 13.
  • the light emitting structure layer 103 may include at least an anode, a pixel definition layer, an organic light emitting layer and a cathode sequentially stacked on the driving structure layer 102, the anode is connected to the pixel driving circuit, and the organic light emitting layer and the cathode are connected to the pixel driving circuit.
  • the layer is connected to the anode
  • the cathode is connected to the organic light-emitting layer
  • the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the anode, the organic light-emitting layer and the cathode do not extend to the frame area.
  • the first barrier structure 11 and the second barrier structure 12 may both be in a strip shape, and the extending direction of the first barrier structure 11 and the second barrier structure 12 may be consistent with the extending direction of the edge of the display area 10 .
  • the extending direction of the first barrier structure 11 and the second barrier structure 12 may be the second direction Y. As shown in FIG.
  • FIGS. 8a, 9a to 10b are schematic diagrams of three cross-sectional structures at the position L1-L1 in FIG. 7, and FIGS. 9b and 10b are schematic diagrams of two enlarged structures at the position a1 in FIG.
  • the first blocking structure 11 includes a first blocking dam 111 and a second blocking dam 112, and in a direction parallel to the plane where the display substrate is located, the frame area 20 may include a first blocking area H1 and a second blocking area H2, the first blocking area H1 is located between the display area 10 and the first blocking dam 111, and the second blocking area H2 is located between the first blocking dam 111 and the second blocking dam 112; the second blocking structure 12 is disposed at at least one position in the first blocking area H1 and the second blocking area H2.
  • the first blocking area H1 is provided with a second blocking structure 12, as shown in FIG. 9a, the first blocking area H1 and the second blocking area H2 are both provided with a second blocking structure 12, and as described in FIG. 10a, the second blocking area H2 is provided with a second blocking structure 12.
  • the size of the first barrier structure 11 is greater than or equal to the size of the second barrier structure 12, and the size of the second barrier dam 112 is greater than or equal to the size of the first barrier dam 111.
  • the size of the second barrier dam 112 is greater than or equal to the size of the first barrier dam 111.
  • the encapsulation structure layer 104 may include a first encapsulation layer 21, a second encapsulation layer 22 and a third encapsulation layer 23, the first blocking structure 11 may be configured to prevent the second encapsulation layer 22 from flowing, and the second blocking structure 12 may be configured to slow down the flow rate of the second encapsulation layer 22.
  • the first encapsulation layer 21 and the third encapsulation layer 23 can be formed by chemical vapor deposition (CVD), the second encapsulation layer 22 can be called an ink jet printing layer (IJP), the second encapsulation layer 22 has a certain process, and the first blocking structure 11 is provided in the border area 20 to prevent the material in the second encapsulation layer 22 from flowing out of the border area 20, as shown in FIG. 11a, and under normal circumstances, the second encapsulation layer 22 will not exceed the first blocking dam 111 and the second blocking dam 112, and the first blocking structure 11 It can block the external water vapor. With the further narrowing of the border area, even if the first blocking structure is set, there are still defects such as package leakage.
  • CVD chemical vapor deposition
  • IJP ink jet printing layer
  • the embodiment of the present disclosure adds a second blocking structure 12 in the blank position of the border area 20, which can improve the packaging effect under the narrow border.
  • the strip-shaped protrusion structure 121 can block the inkjet printing layer (that is, the second packaging layer 22) and relieve the blocking pressure of the first blocking dam 111.
  • the strip-shaped groove structure 120 can store a part of the liquid of the inkjet printing layer, which can relieve the blocking pressure of the first blocking dam 111.
  • the driving structure layer 102 may include a first semiconductor layer, a first gate insulation layer c1, a first conductive layer, a second gate insulation layer c2, a second conductive layer, an interlayer insulation layer c3, a third conductive layer c4, a planarization layer 15 and a fourth conductive layer c5 stacked in sequence on the substrate 101, and the second blocking structure 12 is arranged in one or more layers of the first semiconductor layer, the first conductive layer and the second conductive layer.
  • the second blocking structure 12 is a single-layer structure, and the second blocking structure 12 includes a plurality of strip-shaped protruding structures 121, and the plurality of strip-shaped protruding structures 121 are disposed in one or more of the first semiconductor layer, the first conductive layer, and the second conductive layer; in a direction Z perpendicular to the plane where the display substrate is located, the size of any protruding structure 121 is consistent with the thickness of the film layer in which it is located.
  • the plurality of strip-shaped protruding structures 121 are disposed in one of the first semiconductor layer, the first conductive layer, and the second conductive layer.
  • the plurality of strip-shaped protruding structures 121 are disposed in multiple layers of the first semiconductor layer, the first conductive layer, and the second conductive layer.
  • the second barrier structure 12 may be a multilayer structure, and the second barrier structure 12 may include a plurality of strip-shaped protruding structures 121, and the plurality of strip-shaped protruding structures 121 may be disposed in a plurality of film layers in the first semiconductor layer, the first conductive layer, and the second conductive layer, as shown in FIGS. 11e and 11f.
  • any one of the protrusion structures 121 includes sub-protrusion structures 121 located in multiple film layers, and the orthographic projections of the multiple sub-protrusion structures 121 in the same protrusion structure 121 on the substrate 101 at least partially overlap.
  • the sizes of the plurality of strip-shaped protruding structures 121 in the direction Z perpendicular to the plane where the display substrate is located increase successively, so that the plurality of protruding structures 121 arranged along the direction perpendicular to the edge of the display area 10 are arranged in a stepped manner, which can further improve the packaging effect.
  • the plurality of protruding structures 121 are arranged in a stepped manner, which, combined with the groove structure, increases the step height, which can further improve the packaging effect.
  • the second blocking structure 12 may include a first protrusion structure 1211, The second convex structure 1212 and the third convex structure 12120, the first convex structure 1211 is disposed on the first semiconductor layer, the second convex structure 1212 is disposed on the first semiconductor layer and the first conductive layer, and the third convex structure 12120 is disposed on the first semiconductor layer, the first conductive layer and the second conductive layer.
  • the second convex structure 121 may include two second sub-convex structures b11 and b12 respectively located in the first semiconductor layer and the first conductive layer, and the orthographic projections of the two second sub-convex structures b11 and b12 on the substrate 101 at least partially overlap;
  • the third convex structure 121 includes three third sub-convex structures c11, c12 and c13 respectively located in the first semiconductor layer, the first conductive layer and the second conductive layer, and the orthographic projections of the three third sub-convex structures c11 to c13 on the substrate 101 at least partially overlap.
  • the sizes of the first convex structure 1211, the second convex structure 1212 and the third convex structure 1213 in the direction Z perpendicular to the plane where the display substrate is located are successively increased, which is conducive to improving the packaging effect.
  • the second blocking structure 12 may further include at least one strip-shaped groove structure 120, and the strip-shaped groove structure 120 may be disposed in one or more of the first gate insulating layer c1, the second gate insulating layer c2, and the interlayer insulating layer c3.
  • the groove structure 120 cooperates with the protrusion structure 121 to form a stepped arrangement, which increases the height difference between the groove structure 120 and the protrusion structure 121, and can provide a blocking effect on the inkjet printing layer (i.e., the second encapsulation layer 22), thereby improving the encapsulation effect.
  • the groove structure 120 in the direction Z parallel to the plane where the display substrate is located, in the first barrier area H1, the groove structure 120 may be located between the display area 10 and the protrusion structure 121, as shown in Figures 11a to 11f; in the second barrier area H2, the groove structure 120 may be located between the first barrier dam 111 and the protrusion structure 121, as shown in Figures 11g and 11h.
  • Figures 11a to 11g are schematic cross-sectional structural diagrams of the L1-L1 position in Figure 7, and Figure 11h is an enlarged structural diagram of the a1 position in Figure 7.
  • the height of the surface of the groove structure 120 and the protrusion structure 121 in the second blocking structure 12 away from the substrate 101 increases in sequence relative to the substrate 101.
  • the height of the surface of the groove structure 120 and the protrusion structure 121 in the second blocking structure 12 away from the substrate 101 increases in sequence relative to the substrate 101.
  • the height of the surface of the groove structure 120 and the protrusion structure 121 in the second blocking structure 12 away from the substrate 101 increases in sequence relative to the substrate 101.
  • At least one of the third conductive layer c4 and the fourth conductive layer c5 is disposed on a plane.
  • the line extends in the direction Z of the plane where the display substrate is located to the frame area 20, at least one film layer of the third conductive layer c4 and the fourth conductive layer c5 is provided with a second power line, and the orthographic projection of the second blocking structure 12 on the substrate 101 and the orthographic projection of the second power line on the substrate 101 have an overlapping area.
  • the cross-sectional shape of the overlapping area of the third conductive layer c4, the fourth conductive layer c5 and the second blocking structure 12 in the orthographic projection on the substrate 101 is consistent with the cross-sectional shape of the second blocking structure 12, and the third conductive layer c4 and the fourth conductive layer c5 inherit the second blocking structure 12 in morphology, so that a corresponding convex or concave morphology can be formed in the second encapsulation layer 22 in the encapsulation layer 104, so as to block the liquid in the second encapsulation layer 22, reduce the blocking pressure of the first blocking structure 11, and improve the encapsulation effect.
  • the third conductive layer c4 and the fourth conductive layer c5 present a concave morphology at the position of the concave structure 120, and present a convex morphology at the position of the convex structures 1211, 1212, and 1213.
  • the border region 20 is provided with a GOA circuit 14 , and an orthographic projection of the GOA circuit 14 on the substrate 101 does not overlap with an orthographic projection of the second blocking structure 12 on the substrate 101 .
  • the driving structure layer 102 may include a first semiconductor layer, a first gate insulating layer c1, a first conductive layer, a second gate insulating layer c2, a second conductive layer, an interlayer insulating layer c3, a third conductive layer c4, a planarization layer 15, and a fourth conductive layer c5 sequentially stacked on the substrate 101, and the second blocking structure 12 may be disposed in one or more of the first semiconductor layer, the first gate insulating layer c1, the first conductive layer, the second gate insulating layer c2, the second conductive layer, and the interlayer insulating layer 15. As shown in FIG.
  • a protrusion structure 121 is disposed in the first semiconductor layer, the first conductive layer, and the second conductive layer of the driving structure layer 102, and a groove structure 120 is disposed in the planarization layer 15.
  • the first semiconductor layer, the first conductive layer, and the second conductive layer in the driving structure layer 102 do not extend to the border area 20.
  • the protruding structure 121 located in the border area can be formed with one or more of the first semiconductor layer, the first conductive layer, and the second conductive layer in the driving structure layer 102 through a single patterning process, thereby reducing the number of times the mask plate for preparing the pattern is used, so that there is no need to prepare the second blocking structure 12 separately for a separate mask plate.
  • the pattern of the second blocking structure 12 can be added to the mask plate originally used to prepare one or more of the first semiconductor layer, the first conductive layer, and the second conductive layer, thereby greatly reducing the cost of preparing the display substrate.
  • the groove structure 120 can be formed by a single patterning process with the patterns on the first gate insulating layer c1, the second gate insulating layer c2, and the interlayer insulating layer c3.
  • the groove structure 120 can be formed by a single patterning process with the patterns on the interlayer insulating layer c3.
  • the groove structure 120 and the original film layer in the display substrate are formed by a single patterning process, and no separate preparation is required, which can save the cost of preparing the display substrate.
  • the strip-shaped protruding structure 121 can be formed with the film layer where it is located through a single patterning process. As shown in FIGS. 11a to 11f , the strip-shaped protruding structure 121 and the original film layer in the display substrate are formed through a single patterning process, and there is no need to prepare the protruding structure 121 separately, which can save the process of preparing the display substrate and reduce the cost of preparing the display substrate.
  • the strip-shaped protruding structure 121 is a single-layer structure, and is formed with the first semiconductor layer through a single patterning process; as shown in FIG11b, the strip-shaped protruding structure 121 is a single-layer structure, and is formed with the first conductive layer through a single patterning process; as shown in FIG11c, the strip-shaped protruding structure 121 is a single-layer structure, and is formed with the second conductive layer through a single patterning process; as shown in FIG11d, the strip-shaped protruding structure 121 is a single-layer structure, and is formed with the second conductive layer through a single patterning process; as shown in FIG11e, the strip-shaped protruding structure 121 may include a first protruding structure 1211, a second protruding structure 1212, and a third protruding structure 1213, wherein the first protruding structure 1211 is a single-layer structure, and the second conductive layer is formed through a
  • the protruding structure 1211 is a single-layer structure and is formed with the first semiconductor layer through a single patterning process.
  • the second protruding structure 1212 is a multi-layer structure including two second sub-protruding structures b11 and b12.
  • the second sub-protruding structure b11 and the first semiconductor layer are formed through a single patterning process, and the second sub-protruding structure b12 and the first conductive layer are formed through a single patterning process.
  • the third protruding structure 1213 includes three third sub-protruding structures c11 to c13.
  • the third sub-protruding structure c11 and the first semiconductor layer are formed through a single patterning process
  • the third sub-protruding structure c12 and the first conductive layer are formed through a single patterning process
  • the third sub-protruding structure c13 and the second conductive layer are formed through a single patterning process.
  • the second blocking structure 12 may include at least one strip-shaped protrusion structure 121, or, as shown in Figures 11i to 11j, the second blocking structure 12 includes at least one strip-shaped groove structure 120, or, as shown in Figures 11a to 11h, the second blocking structure 12 includes at least one strip-shaped protrusion structure 121 and at least one strip-shaped groove structure 120.
  • the strip-shaped protruding structure 121 can block the second encapsulation layer 22 and reduce the blocking pressure of the first blocking dam 111.
  • the groove structure 120 can store a portion of the liquid in the second encapsulation layer 22 and reduce the flow rate of the liquid in the second encapsulation layer 22. To a certain extent, the blocking pressure of the first blocking dam 111 can be reduced. That is, both the protruding structure 121 and the groove structure 120 can reduce the blocking pressure of the first blocking dam 111 and improve the encapsulation effect of the narrow frame.
  • the matching method of the groove structure 120 and the protruding structure 121 can further improve the encapsulation effect.
  • the groove structure 120 or the protruding structure 121 set in the first blocking area H1 can reduce the blocking pressure of the first blocking dam 111.
  • the groove structure 120 or the protruding structure 121 set in the second blocking area H2 can reduce the blocking pressure of the second blocking dam 112.
  • the groove structure 120 and the protruding structure 121 set in both the first blocking area H1 and the second blocking area H2 can reduce the blocking pressure of the second blocking dam 112.
  • the same strip-shaped protruding structure 121 may include a plurality of protruding structure d1 segments, and the distance between two adjacent protruding structure 121 segments is A raised spacing structure d2 is provided.
  • a same strip-shaped groove structure 120 may include a plurality of groove structure segments f1 , and a groove spacing structure f2 is provided between two adjacent groove structure segments f1 .
  • the second blocking structure 12 includes a plurality of protruding structures 121, and the plurality of protruding structures 121 are arranged in a direction perpendicular to the edge of the display area 10, wherein a plurality of protruding structure segments d1 in the plurality of protruding structures 121 are arranged in an array, or a plurality of protruding structure segments d1 in the plurality of protruding structures 121 are arranged in a staggered manner.
  • multiple raised structure segments d1 in the multiple raised structures 121 are arranged in a staggered manner, and the flow path of the liquid in the second packaging layer 22 is as shown in the direction of the arrow in Figure 8d.
  • the liquid flows into the raised spacing structure d2 between any two adjacent raised structure segments d1 in the same two adjacent raised structures 121, it will be blocked by the next raised structure 121, and the liquid flow direction is changed to flow in two directions parallel to the first blocking dam 111. Therefore, the liquid will be blocked by different raised structures 121, which increases the liquid flow path and can improve the packaging effect of the narrow frame.
  • the extension direction of two adjacent protruding structure segments d1 and the extension direction of the protruding structure 121 form a first angle k1 and a second angle k2, respectively, and the first angle k1 and the second angle k2 are located on both sides of the extension direction of the protruding structure 121.
  • the extension direction of the protruding structure 121 may be Y.
  • the first angle k1 and the second angle k2 may be equal.
  • the first angle k1 and the second angle k2 are both less than or equal to 15 degrees.
  • a plurality of protrusion structure 121 segments include a plurality of protrusion structure combinations p0, and the same protrusion structure combination p0 includes at least two mutually connected protrusion structure segments d1, and two adjacent protrusion structure segments d1 form a third angle k3 toward the display area 10 or toward the first blocking structure 11.
  • the third angle k3 may be an obtuse angle.
  • a combination p0 as a whole can block the liquid and slow down the flow speed of the liquid, thereby improving the encapsulation effect of the frame.
  • the spacing m1 between two adjacent protrusion structures 121 is 0.4 ⁇ m to 5.5 ⁇ m, for example, the spacing m1 between two adjacent protrusion structures 121 is 0.4 ⁇ m to 4.8 ⁇ m; the width m2 of the protrusion structure 121 is 0.8 ⁇ m to 5.6 ⁇ m, for example, the width m2 of the protrusion structure 121 is 5 ⁇ m.
  • the spacing between two adjacent protrusion structures 121 is as small as possible while ensuring the process yield.
  • the liquid in the second encapsulation layer 22 flows to the gap between the two adjacent protrusion structures 121, due to the two adjacent protrusion structures 121, the liquid in the second encapsulation layer 22 flows to the gap between the two adjacent protrusion structures 121.
  • the intervals between the protruding structures 121 are small enough to produce a capillary phenomenon (ie, a capillary effect), so that the liquid is blocked, thereby reducing the blocking pressure of the first blocking structure 11 to a certain extent.
  • the width m2 of the protruding structure 121 is as small as possible while ensuring the process yield, so as to increase the number of the protruding structures 121, thereby improving the barrier effect.
  • the dimension of the barrier structure segment d1 along the extension direction of the display area 10 is as large as possible, so as to improve the barrier effect on the liquid in the second encapsulation layer 22.
  • the capillary effect is combined with the staggered arrangement of the raised structure segments d1 , and the superposition of the two blocking effects can further enhance the blocking of the liquid in the second packaging layer 22 , thereby further enhancing the packaging effect of the narrow frame.
  • the display substrate may include an upper frame, a lower frame, a left frame and a right frame, the upper frame and the lower frame extend in the same direction (for example, both extend in the first direction X), and the left frame and the right frame extend in the same direction (for example, both extend in the second direction Y).
  • FIG11a which is a cross-sectional structural diagram of the position L1-L1 in FIG7
  • FIG12a is a cross-sectional structural diagram of the position L2-L2 in FIG7
  • the left and right frames of the display substrate are provided with an array substrate row driver (Gate Driver on Array, abbreviated as GOA) circuit 14, the GOA circuit 14 is located between the display area 10 and the second blocking structure 12, the display area 10 is provided with a first gate insulating layer c1, a second gate insulating layer c2, a planarizing layer 15, and a pixel definition layer 13, and the second blocking structure 12 is provided between the GOA circuit 14 and the first blocking dam 111; as shown in FIG12a , in the upper and lower frame positions of the display substrate, the second blocking structure 12 is provided between the display area and the second blocking structure 12.
  • GOA array substrate row driver
  • FIG12b is an enlarged schematic diagram of the structure of the right frame a1 in FIG7
  • FIG12c is an enlarged schematic diagram of the structure of the lower frame a2 in FIG7.
  • the two ends of the upper frame in the display substrate are respectively connected to one end of the left and right frames
  • the two ends of the lower frame are respectively connected to the other ends of the left and right frames.
  • the light-emitting device layer 100 may include a driving structure layer and a light-emitting structure layer stacked in sequence on a substrate 101, and the first gate insulation layer c1, the first conductive layer, and the second gate insulation layer c2 in the driving structure layer are arranged in the display area 10, and are not arranged in the border area 20, as shown in Figures 13a and 13b,
  • Figure 13a is a schematic diagram of a cross-sectional structure at the L2-L2 position in Figure 7
  • Figure 13b is a schematic diagram of a cross-sectional structure at the L1-L1 position in Figure 7; in other exemplary embodiments, the first gate insulation layer c1 and the second gate insulation layer c2 in the driving structure layer extend to the border area 20, as shown in Figures 11a to 11e.
  • the present disclosure also provides a display device, which may include a display substrate of any of the above embodiments.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.
  • the embodiment of the present disclosure further provides a method for preparing a display substrate, wherein the display substrate may include a display area and a frame area, wherein the frame area is located around the display area; in a direction perpendicular to the plane where the display substrate is located, the display substrate may include a base, and a light-emitting device layer and a packaging structure layer sequentially stacked on the base; the preparation method may include:
  • a first blocking structure and a second blocking structure are formed in the frame area, the first blocking structure is located between the light emitting device layer and the encapsulation structure layer, and the second blocking structure is located in the light emitting device layer.
  • the display substrate and the display device provided by the embodiments of the present disclosure include a display substrate including a display area and a frame area, the frame area is provided with a first blocking structure and a second blocking structure, in a direction perpendicular to the plane where the display substrate is located, the display substrate includes a base and a driving structure layer, a light-emitting structure layer, and a packaging structure layer stacked in sequence on the base, the first blocking structure is arranged between the driving structure layer and the packaging structure layer, and the second blocking structure is arranged in the driving structure layer, and the arrangement mode of combining the second blocking structure with the first blocking structure greatly improves the packaging effect of the narrow-frame display substrate.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板和显示装置，显示基板包括显示区（10）和边框区（20），边框区（20）位于显示区（10）周边，边框区（20）设有第一阻挡结构（11）和第二阻挡结构（12）；在垂直于显示基板所在平面的方向上，显示基板包括基底（101）以及依次叠设在基底（101）上的驱动结构层（102）、发光结构层（103）、封装结构层（104），第一阻挡结构（11）设置于驱动结构层（102）与封装结构层（104）之间，第二阻挡结构（12）设置于驱动结构层（102）。

Description

显示基板、显示装置
本申请要求于2022年11月17日提交中国专利局、申请号为202211460729.8、发明名称为“一种显示基板、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括显示区和边框区，所述边框区位于所述显示区周边，所述边框区设有第一阻挡结构和第二阻挡结构；在垂直于所述显示基板所在平面的方向上，所述显示基板包括基底以及依次叠设在所述基底上的驱动结构、发光结构层、封装结构层，所述第一阻挡结构设置于所述驱动结构层与所述封装结构层之间，所述第二阻挡结构设置于所述驱动结构层。
在示例性实施方式中，所述第一阻挡结构和所述第二阻挡结构均为条形状，并且所述第一阻挡结构、所述第二阻挡结构的延伸方向与所述显示区边缘的延伸方向一致。
在示例性实施方式中，所述第一阻挡结构包括第一阻挡坝和第二阻挡坝，在平行于所 述显示基板所在平面的方向上，所述边框区包括第一阻挡区和第二阻挡区，所述第一阻挡区位于所述显示区与所述第一阻挡坝之间，所述第二阻挡区位于所述第一阻挡坝与所述第二阻挡坝之间；所述第二阻挡结构设置于所述第一阻挡区和所述第二阻挡区中的至少一个位置。
在示例性实施方式中，在垂直于所述显示基板所在平面的方向上，所述第一阻挡结构的尺寸大于或者等于所述第二阻挡结构的尺寸，所述第二阻挡坝的尺寸大于或者等于所述第一阻挡坝的尺寸；在垂直于所述显示区边缘的延伸方向上，所述第二阻挡坝的尺寸大于或者等于所述第一阻挡坝的尺寸。
在示例性实施方式中，所述驱动结构层包括依次叠设在所述基底上的第一半导体层、第一栅绝缘层、第一导电层、第二栅绝缘层、第二导电层、层间绝缘层、第三导电层、平坦化层和第四导电层，所述第二阻挡结构设置于所述第一半导体层、所述第一导电层、所述第二导电层中的其中一层或多层。
在示例性实施方式中，所述第二阻挡结构为单层结构，所述第二阻挡结构包括多个条状的凸起结构，所述多个条状的凸起结构设置于所述第一半导体层、所述第一导电层、所述第二导电层中的其中一层或多层；在垂直于所述显示基板所在平面的方向上，任意一个凸起结构的尺寸与其所在膜层的厚度一致。
在示例性实施方式中，所述第二阻挡结构为多层结构，所述第二阻挡结构包括多个条状的凸起结构，所述多个条状的凸起结构设置于所述第一半导体层、所述第一导电层、所述第二导电层中的多个膜层中。
在示例性实施方式中，在垂直于所述显示基板所在平面的方向上，所述多个条状的凸起结构的尺寸一致，任意一个凸起结构包括位于多个膜层中的子凸起结构，同一个凸起结构中的多个子凸起结构在所述基底上的正投影至少部分重叠。
在示例性实施方式中，沿远离所述显示区的方向，在所述第一阻挡区和所述第二阻挡区中的任意一个区间中，所述多个条状的凸起结构在垂直于所述显示基板所在平面的方向上的尺寸依次增大。
在示例性实施方式中，所述第二阻挡结构包括第一凸起结构、第二凸起结构和第三凸起结构，所述第一凸起结构设置于所述第一半导体层，所述第二凸起结构设置于所述第一半导体层和所述第一导电层，所述第三凸起结构设置于所述第一半导体层、所述第一导电 层和所述第二导电层。
在示例性实施方式中，所述第二凸起结构包括分别位于所述第一半导体层和所述第一导电层的两个第二子凸起结构，并且两个所述第二子凸起结构在所述基底上的正投影至少部分重叠；所述第三凸起结构包括分别位于所述第一半导体层、所述第一导电层、所述第二导电层的三个第三子凸起结构，并且三个所述第三子凸起结构在所述基底上的正投影至少部分重叠。
在示例性实施方式中，所述第二阻挡结构还包括至少一个条状的凹槽结构，所述条状的凹槽结构设置于所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层中的其中一层或多层。
在示例性实施方式中，在平行于所述显示基板所在平面的方向上，在所述第一阻挡区，所述凹槽结构位于所述显示区与所述凸起结构之间；在所述第二阻挡区，所述凹槽结构位于所述第一阻挡坝与所述凸起结构之间。
在示例性实施方式中，在所述第一阻挡区和所述第二阻挡区中的任意一个区间中，在垂直于所述显示基板所在平面的方向上，所述第二阻挡结构中的凹槽结构和凸起结构远离所述基底一侧的表面相对于所述基底的高度依次增大。
在示例性实施方式中，所述第三导电层、所述第四导电层至少一个在平行于所述显示基板所在平面的方向上延伸至所述边框区，所述第三导电层和所述第四导电层的至少一个膜层设有第二电源线，所述第二阻挡结构在所述基底上的正投影与所述第二电源线在所述基底上的正投影存在重叠区域。
在示例性实施方式中，在所述边框区域，所述第三导电层、所述第四导电层与所述第二阻挡结构在所述基底上正投影重叠区域的剖面形状与所述第二阻挡结构的剖面形状一致。
在示例性实施方式中，所述边框区设有GOA电路，所述GOA电路在所述基底上的正投影与所述第二阻挡结构在所述基底上的正投影不重叠。
在示例性实施方式中，所述驱动结构层包括依次叠设在所述基底上的第一半导体层、第一栅绝缘层、第一导电层、第二栅绝缘层、第二导电层、层间绝缘层、第三导电层、平坦化层和第四导电层，所述第二阻挡结构设置于所述第一半导体层、所述第一栅绝缘层、所述第一导电层、所述第二栅绝缘层、所述第二导电层、所述层间绝缘层中的其中一层或 多层。
在示例性实施方式中，所述凹槽结构与所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层上的图案通过一次构图工艺制成。
在示例性实施方式中，所述条状的凸起结构与其所在膜层通过一次构图工艺制成。
在示例性实施方式中，所述第二阻挡结构包括至少一个条状的凸起结构，或者，所述第二阻挡结构包括至少一个条状的凹槽结构，或者，所述第二阻挡结构包括至少一个条状的凸起结构和至少一个条状的凹槽结构。
在示例性实施方式中，在所述第二阻挡结构的延伸方向上，同一个条状的凸起结构中包括多个凸起结构段，相邻两个凸起结构段之间设有凸起间隔结构；同一个条状的凹槽结构中包括多个凹槽结构段，相邻两个凹槽结构段之间设有凹槽间隔结构。
在示例性实施方式中，所述第二阻挡结构包括多个凸起结构，多个凸起结构沿垂直于所述显示区边缘的方向排布，其中，多个凸起结构中的多个凸起结构段呈阵列排布，或者多个凸起结构中的多个凸起结构段呈错位排布。
在示例性实施方式中，在同一个凸起结构中，相邻两个凸起结构段的延伸方向与所述凸起结构的延伸方向之间分别呈第一夹角和第二夹角，所述第一夹角与所述第二夹角位于所述凸起结构的延伸方向的两侧。
在示例性实施方式中，所述第一夹角和所述第二夹角均小于或者等于15度。
在示例性实施方式中，在同一个凸起结构中，多个凸起结构段包括多个凸起结构组合，在同一个凸起结构组合中包括至少两个相互连接的凸起结构段，并且相邻两个凸起结构段形成朝向所述显示区或朝向所述第一阻挡结构的第三夹角。
在示例性实施方式中，相邻两个凸起结构之间的间距为0.4微米至5.5微米；所述凸起结构的宽度为0.8微米至5.6微米。
在示例性实施方式中，所述封装结构层包括第一封装层、第二封装层和第三封装层，所述第一阻挡结构设置为阻止所述第二封装层流动，所述第二阻挡结构设置为减缓所述第二封装层的流速。
第二方面，本公开实施例还提供一种显示装置，包括上述任一实施例所述的显示基板。
第三方面，本公开实施例还提供一种显示基板的制备方法，所述显示基板包括显示区 和边框区，所述边框区位于所述显示区周边；在垂直于所述显示基板所在平面的方向上，所述显示基板包括基底以及依次叠设在所述基底上的发光器件层、封装结构层；所述制备方法包括：
在所述边框区形成第一阻挡结构和第二阻挡结构，所述第一阻挡结构位于所述发光器件层与所述封装结构层之间，所述第二阻挡结构位于所述发光器件层。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开实施例技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中每个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7所示为本公开实施例提供的一种显示基板的平面结构示意图；
图8a所示为图7中L1-L1位置的一种剖面结构示意图；
图8b所示为图7中a1位置的一种放大结构示意图；
图8c所示为图7中a1位置的一种放大结构示意图；
图8d所示为图7中a1位置的一种放大结构示意图；
图8e所示为图7中a1位置的一种放大结构示意图；
图8f所示为图7中a1位置的一种放大结构示意图；
图8g所示为图7中a1位置的一种放大结构示意图；
图8h所示为图7中a1位置的一种放大结构示意图；
图8i所示为图7中a1位置的一种放大结构示意图；
图8j所示为本公开示例性实施例中凸起结构之间毛细效应的示意图；
图9a所示为图7中L1-L1位置的一种剖面结构示意图；
图9b所示为图7中a1位置的一种放大结构示意图；
图10a所示为图7中L1-L1位置的一种剖面结构示意图；
图10b所示为图7中a1位置的一种放大结构示意图；
图11a所示为图7中L1-L1位置的一种剖面结构示意图；
图11b所示为图7中L1-L1位置的一种剖面结构示意图；
图11c所示为图7中L1-L1位置的一种剖面结构示意图；
图11d所示为图7中L1-L1位置的一种剖面结构示意图；
图11e所示为图7中L1-L1位置的一种剖面结构示意图；
图11f所示为图7中L1-L1位置的一种剖面结构示意图；
图11g所示为图7中L1-L1位置的一种剖面结构示意图；
图11h所示为图7中a1位置的一种放大结构示意图；
图11i所示为图7中L1-L1位置的一种剖面结构示意图；
图11j所示为图7中a1位置的一种放大结构示意图；
图12a所示为图7中L2-L2位置的一种剖面结构示意图；
图12b所示为图7中a1位置的一种放大结构示意图；
图12c所示为图7中a2位置的一种放大结构示意图；
图13a所示为图7中L2-L2位置的一种剖面结构示意图；
图13b所示为图7中L1-L1位置的一种剖面结构示意图。
具体实施方式
下文中将结合附图对本公开实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不 脱离本公开实施例的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开实施例不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开实施例省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开实施例中的附图比例可以作为实际工艺中的参考，但不限于此。例如：每个膜层的厚度和间距、每个信号线的宽度和间距，可以根据实际情况进行调整。本公开实施例中所描述的附图仅是结构示意图，本公开实施例的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源 电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。在本公开实施例中，栅电极可以称为控制极。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开实施例中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器 可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。在示例性实施方式中，显示基板还可以包括显示区域边界BD，显示区域边界BD可以是显示区域100靠近绑定区域200一侧的边缘。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区，扇出区连接到显示区域，包括多条数据扇出线，数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线(Data Line)，扇出区占用空间较大，导致下边框的宽度较大。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域，可以至少包括栅极驱动电路，栅极驱动电路与显示区域中像素驱动电路的第一扫描信号线、第二扫描信号线、第三扫描信号线和发光控制线连接。电源线区连接到电路区，可以至少包括电源引线，电源引 线沿着平行于显示区域边缘的方向延伸，与显示区域中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光元件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光元件输出相应的电流。每个子像素中的发光元件分别与所在子像素的像素驱动电路连接，发光元件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基 板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括由多个晶体管和存储电容构成的像素驱动电路。每个子像素的发光结构层103可以包括由多个膜层构成的发光元件，多个膜层可以至少包括阳极、像素定义层、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1至第七晶体管T7)和1个存储电容C，像素驱动电路分别与10条信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
在示例性实施方式中，第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1的第二极与第二节点N2连接。当导通的扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始化电压传输到存储电容C的第二端，实现存储电容C的初始化。
在示例性实施方式中，第二晶体管T2的控制极与第四扫描信号线S4连接，第二晶体管T2的第一极与第一晶体管T1的第二极连接，第二晶体管T2的第二极与第三节点N3连接。当导通的扫描信号施加到第四扫描信号线S4时，第二晶体管T2使第三晶体管T3的控制极与第三晶体管T3的第二极连接。
在示例性实施方式中，第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与发光元件之间流动的驱动电流的大小。
在示例性实施方式中，第四晶体管T4的控制极与第三扫描信号线S3连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。当导通的扫描信号施加到第三扫描信号线S3时，第四晶体管T4使数据信号线D的数据电压输入到第一节点N1。
在示例性实施方式中，第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光元件的第一极连接。当导通的发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与发光元件之间形成驱动电流路径而使发光元件发光。
在示例性实施方式中，第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光元件的第一极连接。当导通的扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光元件的第一极，以使发光元件的第一极中累积的电荷量初始化或释放发光元件的第一极中累积的电荷量。
在示例性实施方式中，发光元件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光元件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，第一晶体管T1和第二晶体管T2为N型的氧化物晶体管，第三晶体管T3至第七晶体管T7为P型的低温多晶硅晶体管。在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为导通信号(高电平)，第一扫描信号线S1、第三扫描信号线S3、第四扫描信号线S4和发光信号线E的信号为断开信号。第二扫描信号线S2的导通信号使第一晶体管T1导通，第一初始信号线INIT1的信号通过第一晶体管T1提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。第一扫描信号线S1、第三扫描信号线S3、第四扫描信号线S4和发光信号线E的断开信号使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和 第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1、第三扫描信号线S3和第四扫描信号线S4的信号为导通信号，第二扫描信号线S2和发光信号线E的信号为断开信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1、第三扫描信号线S3和第四扫描信号线S4的导通信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使第二初始信号线INIT2的信号提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的断开信号使第一晶体管T1断开，发光信号线E的断开信号使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为导通信号，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3和第四扫描信号线S4的信号为断开信号。发光信号线E的导通信号使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd)]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
柔性封装设计通常采用双阻挡坝(Dam，可以称为隔离坝)对喷墨打印层(Ink jet Print，简写为IJP)进行阻挡，以防止IJP越过Dam导致水氧入侵，使得封装失效。
随着OLED显示技术的飞速发展，人们越来越追求极致窄边框。在窄化边框的过程中，边框的膜层结构不断向内收缩，这对柔性封装提出了更高的要求，相关技术中用于阻挡喷墨打印层(Ink jet Print，简写为IJP)的双阻挡坝(Dam)设计难以满足极致窄边框的要求，比如会出现封装漏气等不良问题，因此，提升窄边框下的封装效果迫在眉睫。
本公开实施例提供了一种显示基板，可以包括显示区和边框区，边框区位于显示区周边，边框区设有第一阻挡结构和第二阻挡结构；在垂直于显示基板所在平面的方向上，显示基板可以包括基底以及依次叠设在基底上的驱动结构层、发光结构层、封装结构层，第一阻挡结构可以设置于驱动结构层与封装结构层之间，第二阻挡结构可以设置于驱动结构层。
本公开实施例提供的显示基板，包括显示区和边框区，边框区设有第一阻挡结构和第二阻挡结构，在垂直于显示基板所在平面的方向上，显示基板包括基底以及依次叠设在基底上的驱动结构层、发光结构层、封装结构层，第一阻挡结构设置于驱动结构层与封装结构层之间，第二阻挡结构设置于驱动结构层，第二阻挡结构与第一阻挡结构相结合的设置方式，在很大程度上提升了窄边框显示基板的封装效果。
在本公开实施方式中，发光结构层未延伸至边框区，因此，第一阻挡结构可以设置于驱动结构层与封装结构层之间。在另一些实施方式中，发光结构层可以延伸至边框区，并可以延伸至第一阻挡结构所在区域，则第一阻挡结构可以设置于发光结构层与封装结构层之间。
如图7至图8i所示，图8a为图7中L1-L1位置的剖面结构示意图，图8b至图8i为图7中a1位置的几种放大结构示意图，在平行于显示基板所在平面的方向上，显示基板可以包括显示区10和边框区20，边框区20位于显示区10周边，边框区20设有第一阻挡结构11和第二阻挡结构12；在垂直于显示基板所在平面的方向Z上，显示基板可以包括基底101以及依次叠设在基底101上的发光器件层100、封装结构层104，第一阻挡结构11可以设置于发光器件层100与封装结构层104之间，第二阻挡结构12可以设置于发光器件层100。本公开实施例中，如图11a所示，发光器件层100可以包括依次叠设在基底101上的驱动结构层102和发光结构层103。第二阻挡结构12可以设置于发光器件层100中的驱动结构层102。在本公开实施方式中，发光结构层103可以包括像素定义层13，但不限于像素定义层13，例如，发光结构层103可以至少包括依次叠设在驱动结构层102上的阳极、像素定义层、有机发光层和阴极，阳极与像素驱动电路连接，有机发光 层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。在本公开实施方式中，阳极、有机发光层和阴极未延伸至边框区。
在示例性实施方式中，如图8b至图8i所示，第一阻挡结构11和第二阻挡结构12可以均为条形状，并且第一阻挡结构11、第二阻挡结构12的延伸方向可以与显示区10边缘的延伸方向一致。
在示例性实施方式中，第一阻挡结构11、第二阻挡结构12的延伸方向可以为第二方向Y。
在示例性实施方式中，如图8a、9a至所示10b所示，图8a、图9a和图10a为图7中国L1-L1位置的三种剖面结构示意图，图9b和图10b为图7中a1位置的两种放大结构示意图，第一阻挡结构11包括第一阻挡坝111和第二阻挡坝112，在平行于显示基板所在平面的方向上，边框区20可以包括第一阻挡区H1和第二阻挡区H2，第一阻挡区H1位于显示区10与第一阻挡坝111之间，第二阻挡区H2位于第一阻挡坝111与第二阻挡坝112之间；第二阻挡结构12设置于第一阻挡区H1和第二阻挡区H2中的至少一个位置。如图8a所示，第一阻挡区H1设有第二阻挡结构12，如图9a所示，第一阻挡区H1和第二阻挡区H2均设有第二阻挡结构12，如图10a所述，第二阻挡区H2设有第二阻挡结构12。
在示例性实施方式中，如图9a、图10a、图11a所示，在垂直于显示基板所在平面的方向Z上，第一阻挡结构11的尺寸大于或者等于第二阻挡结构12的尺寸，第二阻挡坝112的尺寸大于或者等于第一阻挡坝111的尺寸。在示例性实施方式中，在垂直于所述显示区边缘的延伸方向上，第二阻挡坝112的尺寸大于或者等于第一阻挡坝111的尺寸。
在示例性实施方式中，如图11a至图11f所示，封装结构层104可以包括第一封装层21、第二封装层22和第三封装层23，第一阻挡结构11可以设置为阻止第二封装层22流动，第二阻挡结构12可以设置为减缓第二封装层22的流速。
在示例性实施方式中，第一封装层21和第三封装层23可以通过化学气相沉积(Chemical Vapor Deposition，简写为CVD)形成，第二封装层22可以称为喷墨打印层(Ink jet Print，简写为IJP)，第二封装层22具有一定的流程性，在边框区20设置第一阻挡结构11可以阻挡第二封装层22中的材料从边框区20流出，如图11a所示，通常情况下，第二封装层22不会超出第一阻挡坝111和第二阻挡坝112，第一阻挡结构11 可以对外界的水汽起到阻挡作用，随着边框区的进一步窄化，即便设置了第一阻挡结构仍然存在封装漏气等缺陷，本公开实施例在边框区20的空白位置新增了第二阻挡结构12，可以实现在窄边框下提升封装效果，其中，条状的凸起结构121可以对喷墨打印层(即第二封装层22)起到阻挡作用，缓解第一阻挡坝111的阻挡压力。条状的凹槽结构120能够存储一部分喷墨打印层的液体，可以缓解第一阻挡坝111的阻挡压力。
在示例性实施方式中，如图11a所示，驱动结构层102可以包括依次叠设在基底101上的第一半导体层、第一栅绝缘层c1、第一导电层、第二栅绝缘层c2、第二导电层、层间绝缘层c3、第三导电层c4、平坦化层15和第四导电层c5，第二阻挡结构12设置于第一半导体层、第一导电层、第二导电层中的其中一层或多层。
在示例性实施方式中，如图11a至图11d所示，第二阻挡结构12为单层结构，第二阻挡结构12包括多个条状的凸起结构121，多个条状的凸起结构121设置于第一半导体层、第一导电层、第二导电层中的其中一层或多层；在垂直于显示基板所在平面的方向Z上，任意一个凸起结构121的尺寸与其所在膜层的厚度一致。如图11a至图11c所示，多个条状的凸起结构121设置于第一半导体层、第一导电层、第二导电层中的其中一层。如图11d所示，多个条状的凸起结构121设置于第一半导体层、第一导电层、第二导电层中的多层。
在示例性实施方式中，第二阻挡结构12可以为多层结构，第二阻挡结构12可以包括多个条状的凸起结构121，多个条状的凸起结构121可以设置于第一半导体层、第一导电层、第二导电层中的多个膜层中。如图11e和图11f所示。
在示例性实施方式中，在垂直于显示基板所在平面的方向Z上，多个条状的凸起结构121的尺寸一致，任意一个凸起结构121包括位于多个膜层中的子凸起结构121，同一个凸起结构121中的多个子凸起结构121在基底101上的正投影至少部分重叠。
在示例性实施方式中，如图11e所示，沿远离显示区10的方向，在第一阻挡区H1和第二阻挡区H2中的任意一个区间中，多个条状的凸起结构121在垂直于显示基板所在平面的方向Z上的尺寸依次增大，使得沿垂直于显示区10边缘方向排列的多个凸起结构121呈阶梯式排布，可以进一步提升封装效果，如图11e所示，多个凸起结构121呈阶梯式排布，与凹槽结构结合，加大了阶梯落差，可以进一步提升封装效果。
在示例性实施方式中，如图11e所示，第二阻挡结构12可以包括第一凸起结构1211、 第二凸起结构1212和第三凸起结构12120，第一凸起结构1211设置于第一半导体层，第二凸起结构1212设置于第一半导体层和第一导电层，第三凸起结构12120设置于第一半导体层、第一导电层和第二导电层。
在示例性实施方式中，如图11e所示，第二凸起结构121可以包括分别位于第一半导体层和第一导电层的两个第二子凸起结构b11和b12，并且两个第二子凸起结构b11和b12在基底101上的正投影至少部分重叠；第三凸起结构121包括分别位于第一半导体层、第一导电层、第二导电层的三个第三子凸起结构c11、c12和c13，三个第三子凸起结构c11至c13在基底101上的正投影至少部分重叠。在本公开实施例中，第一凸起结构1211、第二凸起结构1212、第三凸起结构1213在垂直于显示基板所在平面的方向Z上的尺寸依次增大，有利于提升封装效果。
在示例性实施方式中，如图11a至图11f所示，第二阻挡结构12还可以包括至少一个条状的凹槽结构120，条状的凹槽结构120可以设置于第一栅绝缘层c1、第二栅绝缘层c2、层间绝缘层c3中的其中一层或多层。在本公开实施方式中，凹槽结构120与凸起结构121相互配合，形成阶梯式升高的排列方式，加大了凹槽结构120和凸起结构121的落差，能够对喷墨打印层(即第二封装层22)的阻挡效果，可以提升封装效果。
在示例性实施方式中，在平行于显示基板所在平面的方向Z上，在第一阻挡区H1，凹槽结构120可以位于显示区10与凸起结构121之间，如图11a至图11f所示；在第二阻挡区H2，凹槽结构120可以位于第一阻挡坝111与凸起结构121之间，如图11g和图11h所示。其中，图11a至图11g为图7中L1-L1位置的剖面结构示意图，图11h为图7中a1位置的一种放大结构示意图。
在示例性实施方式中，如图11e所示，在第一阻挡区H1和第二阻挡区H2中的任意一个区间中，在垂直于显示基板所在平面的方向Z上，第二阻挡结构12中的凹槽结构120和凸起结构121远离基底101一侧的表面相对于基底101的高度依次增大。如图11e所示，在第一阻挡区H1中，在垂直于显示基板所在平面的方向Z上，第二阻挡结构12中的凹槽结构120和凸起结构121远离基底101一侧的表面相对于基底101的高度依次增大。如图11g所示，在第二阻挡区H2中，在垂直于显示基板所在平面的方向Z上，第二阻挡结构12中的凹槽结构120和凸起结构121远离基底101一侧的表面相对于基底101的高度依次增大。
在示例性实施方式中，如图11a所示，第三导电层c4、第四导电层c5至少一个在平 行于显示基板所在平面的方向Z上延伸至边框区20，第三导电层c4和第四导电层c5的至少一个膜层设有第二电源线，第二阻挡结构12在基底101上的正投影与第二电源线在基底101上的正投影存在重叠区域。
在示例性实施方式中，在边框区20，第三导电层c4、第四导电层c5与第二阻挡结构12在基底101上正投影重叠区域的剖面形状与第二阻挡结构12的剖面形状一致，第三导电层c4、第四导电层c5在形貌上继承第二阻挡结构12，可以使得在封装层104中的第二封装层22中形成对应的凸起或凹槽形貌，以实现对第二封装层22中的液体进行阻挡，降低第一阻挡结构11的阻挡压力，提升封装效果。如图11e所示，第三导电层c4、第四导电层c5在凹槽结构120位置呈现出凹槽形貌，在凸起结构1211、1212、1213位置呈现凸起形貌。
在示例性实施方式中，边框区20设有GOA电路14，GOA电路14在基底101上的正投影与第二阻挡结构12在基底101上的正投影不重叠。
在示例性实施方式中，驱动结构层102可以包括依次叠设在基底101上的第一半导体层、第一栅绝缘层c1、第一导电层、第二栅绝缘层c2、第二导电层、层间绝缘层c3、第三导电层c4、平坦化层15和第四导电层c5，第二阻挡结构12可以设置于第一半导体层、第一栅绝缘层c1、第一导电层、第二栅绝缘层c2、第二导电层、层间绝缘层15中的其中一层或多层。如图11e所示，在驱动结构层102的第一半导体层、第一导电层、第二导电层设置凸起结构121，在平坦化层15设置凹槽结构120。在本公开实施方式中，驱动结构层102中的第一半导体层、第一导电层、第二导电层未延伸至边框区20，位于边框区的凸起结构121可以与驱动结构层102中第一半导体层、第一导电层、第二导电层其中一层或多层通过一次构图工艺形成，减小制备图案的掩膜板的使用次数，从而不必为单独使用掩膜板单独制备第二阻挡结构12，在原有制备第一半导体层、第一导电层、第二导电层其中一层或多层的掩膜板上新增第二阻挡结构12的图案即可，在很大程度上降低显示基板制备的成本。
在示例性实施方式中，凹槽结构120可以与第一栅绝缘层c1、第二栅绝缘层c2、层间绝缘层c3上的图案通过一次构图工艺制成。例如，如图11a至图11f所示，凹槽结构120可以与层间绝缘层c3上的图案通过一次构图工艺制成。在本公开实施例中，凹槽结构120与显示基板中原有的膜层通过一次构图工艺制成，无需单独制备，可以节省制备显示基板的成本。
在示例性实施方式中，条状的凸起结构121可以与其所在膜层通过一次构图工艺制成。如图11a至图11f所示，条状的凸起结构121与显示基板中原有的膜层通过一次构图工艺制成，无需单独制备凸起结构121，可以节省制备显示基板的流程，降低制备显示基板的成本。如图11a所示，条状的凸起结构121为单层结构，并且与第一半导体层通过一次构图工艺形成；如图11b所示，条状的凸起结构121为单层结构，并且与第一导电层通过一次构图工艺形成；如图11c所示，条状的凸起结构121为单层结构，并且与第二导电层通过一次构图工艺形成；如图11d所示，条状的凸起结构121为单层结构，并且与第二导电层通过一次构图工艺形成；如图11e所示，条状的凸起结构121可以包括第一凸起结构1211、第二凸起结构1212和第三凸起结构1213，其中第一凸起结构1211为单层结构，并与第一半导体层通过一次构图工艺形成，第二凸起结构1212为包括两个第二子凸起结构b11和b12的多层结构，第二子凸起结构b11与第一半导体层通过一次构图工艺形成，第二子凸起结构b12与第一导电层通过一次构图工艺形层，第三凸起结构1213包括三个第三子凸起结构c11至c13，第三子凸起结构c11与第一半导体层通过一次构图工艺形成，第三子凸起结构c12与第一导电层通过一次构图工艺形成，第三子凸起结构c13与第二导电层通过一次构图工艺形成。
在示例性实施方式中，如图8a至图10b所示，第二阻挡结构12可以包括至少一个条状的凸起结构121，或者，如图11i至图11j所示，第二阻挡结构12包括至少一个条状的凹槽结构120，或者，如图11a至图11h所示，第二阻挡结构12包括至少一个条状的凸起结构121和至少一个条状的凹槽结构120。
在本公开实施例中，条状的凸起结构121能够对第二封装层22起到阻挡的作用，减小第一遮挡坝111的阻挡压力，凹槽结构120能够存储一部分第二封装层22中的液体，可以减小第二封装层22液体的流速，在一定程度上可以减小第一阻挡坝111的阻挡压力，即凸起结构121和凹槽结构120均能够减小第一阻挡坝111的阻挡压力，提升窄边框的封装效果，凹槽结构120与凸起结构121相配合的方式可以进一步提升封装效果。在第一阻挡区H1设置的凹槽结构120或者凸起结构121可以减小第一阻挡坝111的阻挡压力，在第二阻挡区H2设置的凹槽结构120或者凸起结构121可以减小第二阻挡坝112的阻挡压力，在第一阻挡区H1和第二阻挡区H2均设置凹槽结构120和凸起结构121可
在示例性实施方式中，如图8c、图11h所示，在第二阻挡结构12的延伸方向上，同一个条状的凸起结构121中可以包括多个凸起结构d1段，相邻两个凸起结构121段之间 设有凸起间隔结构d2。
在示例性实施方式中，如图11h所示，同一个条状的凹槽结构120中可以包括多个凹槽结构段f1，相邻两个凹槽结构段f1之间设有凹槽间隔结构f2。
在示例性实施方式中，第二阻挡结构12包括多个凸起结构121，多个凸起结构121沿垂直于显示区10边缘的方向排布，其中，多个凸起结构121中的多个凸起结构段d1呈阵列排布，或者多个凸起结构121中的多个凸起结构段d1呈错位排布。
如图8d所示，多个凸起结构121中的多个凸起结构段d1呈错位排布，第二封装层22中的液体的流动路径如图8d中的箭头方向，相邻两个在同一个凸起结构121中，液体从任意相邻的两个凸起结构段d1之间的凸起间隔结构d2流进后会被会被下一个凸起结构121挡住，液体流动方向改变为沿平行于第一阻挡坝111的两个方向流动，因此液体会被不同的凸起结构121阻挡，增加了液体流动的路径，可以提升窄边框的封装效果。
在示例性实施方式中，如图8f所示，在同一个凸起结构121中，相邻两个凸起结构段d1的延伸方向与凸起结构121的延伸方向之间分别呈第一夹角k1和第二夹角k2，第一夹角k1与第二夹角k2位于凸起结构121的延伸方向的两侧。例如，图8f中，凸起结构121的延伸方向可以为Y。在示例性实施方式中，第一夹角k1与第二夹角k2可以相等。
在示例性实施方式中，第一夹角k1和第二夹角k2均小于或者等于15度。
在示例性实施方式中，如图8e至图8i所示，在同一个凸起结构121中，多个凸起结构121段包括多个凸起结构组合p0，在同一个凸起结构组合p0中包括至少两个相互连接的凸起结构段d1，并且相邻两个凸起结构段d1形成朝向显示区10或朝向第一阻挡结构11的第三夹角k3。在示例性实施方式中，第三夹角k3可以为钝角。在同一个组合p0中，在第二封装层22中的液体沿垂直于显示区10流动的方向上，一个组合p0作为整体可以对液体进行阻挡，减缓液体的流动速度，从而提升边框的封装效果。
在示例性实施方式中，如图8c所示，相邻两个凸起结构121之间的间距m1为0.4微米至5.5微米，例如，相邻两个凸起结构121之间的间距m1为0.4微米至4.8微米；凸起结构121的宽度m2为0.8微米至5.6微米，例如，凸起结构121的宽度m2为5微米。
在本公开实施例中，相邻两个凸起结构121之间的间距(即图8c中相邻两个凸起结构121沿第一方向X的距离)在保证工艺良率的情况下尽可能的小，如图8j所示，在第二封装层22中的液体流动到相邻两个凸起结构121之间的间隙的情况下，由于相邻两个 凸起结构121之间的间距足够小而产生毛细现象(即毛细效应)，使得液体被阻挡住，在一定程度上减小了第一阻挡结构11的阻挡压力。
在本公开实施例中，为了在显示区10与第一阻挡结构11之间设置更多的凸起结构121，凸起结构121的宽度m2在保证工艺良率的情况下尽可能小，以增加凸起结构121的数量，从而提升阻挡效果。在本公开实施例中，阻挡结构段d1沿显示区10延伸方向的尺寸尽可能大，以提升对第二封装层22中的液体的阻挡效果。
在示例性实施方式中，如图8d、图9b所示，毛细效应与凸起结构段d1之间的错位排布方式相结合，两种阻挡效果叠加可以进一步提升对第二封装层22中液体的阻挡，从而可以进一步提升窄边框的封装效果。
在示例性实施方式中，如图7所示，显示基板可以包括上边框、下边框、左边框和右边框，上边框和下边框的延伸方向一致(例如均沿第一方向X延伸)，左边框和有边框的延伸方向一致(例如均沿第二方向Y延伸)。在示例性实施方式中，如图11a所示，为图7中L1-L1位置的剖面结构图，12a为图7中L2-L2位置的剖面结构图，如图11a所示，显示基板中左右边框设有阵列基板行驱动(Gate Driver on Array，简写为GOA)电路14，GOA电路14位于显示区10与第二阻挡结构12之间，显示区10设有第一栅绝缘层c1、第二栅绝缘层c2、平坦化层15、像素定义层13，第二阻挡结构12设置于GOA电路14与第一阻挡坝111之间；如图12a所示，显示基板中上下边框位置中，第二阻挡结构12设置于显示区与第二阻挡结构12之间。如图12b所示，为图7中右边框a1位置的放大结构示意图，图12c所示为图7中下边框a2位置的放大结构示意图。在示例性实施方式中，显示基板中的上边框的两端分别与左右边框的一端连接，下边框的两端分别与左右边框的另一端连接。
在示例性实施方式中，发光器件层100可以包括依次叠设在基底101上的驱动结构层和发光结构层，驱动结构层中的第一栅绝缘层c1、第一导电层、第二栅绝缘层c2设置于显示区10，未设置在边框区20，如图13a和图13b所示，图13a为图7中L2-L2位置的一种剖面结构示意图，图13b为图7中L1-L1位置的一种剖面结构示意图；在另一些示例性的实施方式中，驱动结构层中的第一栅绝缘层c1和第二栅绝缘层c2延伸至边框区20，如图11a至图11e所示。
本公开实施例还提供了一种显示装置，可以包括上述任一实施例的显示基板。在示例性实施方式中、显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制备方法，显示基板可以包括显示区和边框区，边框区位于显示区周边；在垂直于显示基板所在平面的方向上，显示基板可以包括基底以及依次叠设在基底上的发光器件层、封装结构层；所述制备方法可以包括：
在边框区形成第一阻挡结构和第二阻挡结构，第一阻挡结构位于发光器件层与封装结构层之间，第二阻挡结构位于发光器件层。
本公开实施例提供的显示基板、显示装置，显示基板包括显示区和边框区，边框区设有第一阻挡结构和第二阻挡结构，在垂直于显示基板所在平面的方向上，显示基板包括基底以及依次叠设在基底上的驱动结构层、发光结构层、封装结构层，第一阻挡结构设置于驱动结构层与封装结构层之间，第二阻挡结构设置于驱动结构层，第二阻挡结构与第一阻挡结构相结合的设置方式，在很大程度上提升了窄边框显示基板的封装效果。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
在不冲突的情况下，本公开实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开实施例所揭露的实施方式如上，但所述的内容仅为便于理解本公开实施例而采用的实施方式，并非用以限定本公开实施例。任何本公开实施例所属领域内的技术人员，在不脱离本公开实施例所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开实施例的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (25)

  1. 一种显示基板，包括显示区和边框区，所述边框区位于所述显示区周边，所述边框区设有第一阻挡结构和第二阻挡结构；在垂直于所述显示基板所在平面的方向上，所述显示基板包括基底以及依次叠设在所述基底上的驱动结构层、发光结构层、封装结构层，所述第一阻挡结构设置于所述驱动结构层与所述封装结构层之间，所述第二阻挡结构设置于所述驱动结构层。
  2. 根据权利要求1所述的显示基板，其中，所述第一阻挡结构和所述第二阻挡结构均为条形状，并且所述第一阻挡结构、所述第二阻挡结构的延伸方向与所述显示区边缘的延伸方向一致。
  3. 根据权利要求2所述的显示基板，其中，所述第一阻挡结构包括第一阻挡坝和第二阻挡坝，在平行于所述显示基板所在平面的方向上，所述边框区包括第一阻挡区和第二阻挡区，所述第一阻挡区位于所述显示区与所述第一阻挡坝之间，所述第二阻挡区位于所述第一阻挡坝与所述第二阻挡坝之间；所述第二阻挡结构设置于所述第一阻挡区和所述第二阻挡区中的至少一个位置。
  4. 根据权利要求3所述的显示基板，其中，在垂直于所述显示基板所在平面的方向上，所述第一阻挡结构的尺寸大于或者等于所述第二阻挡结构的尺寸，所述第二阻挡坝的尺寸大于或者等于所述第一阻挡坝的尺寸；在垂直于所述显示区边缘的延伸方向上，所述第二阻挡坝的尺寸大于或者等于所述第一阻挡坝的尺寸。
  5. 根据权利要求3所述的显示基板，其中，所述驱动结构层包括依次叠设在所述基底上的第一半导体层、第一栅绝缘层、第一导电层、第二栅绝缘层、第二导电层、层间绝缘层、第三导电层、平坦化层和第四导电层，所述第二阻挡结构设置于所述第一半导体层、所述第一导电层、所述第二导电层中的其中一层或多层。
  6. 根据权利要求5所述的显示基板，其中，所述第二阻挡结构为单层结构，所述第二阻挡结构包括多个条状的凸起结构，所述多个条状的凸起结构设置于所述第一半导体层、所述第一导电层、所述第二导电层中的其中一层或多层；在垂直于所述显示基板所在平面的方向上，任意一个凸起结构的尺寸与其所在膜层的厚度一致。
  7. 根据权利要求5所述的显示基板，其中，所述第二阻挡结构为多层结构，所述第二阻挡结构包括多个条状的凸起结构，所述多个条状的凸起结构设置于所述第一半导体层、 所述第一导电层、所述第二导电层中的多个膜层中。
  8. 根据权利要求7所述的显示基板，其中，在垂直于所述显示基板所在平面的方向上，所述多个条状的凸起结构的尺寸一致，任意一个凸起结构包括位于多个膜层中的子凸起结构，同一个凸起结构中的多个子凸起结构在所述基底上的正投影至少部分重叠。
  9. 根据权利要求7所述的显示基板，其中，沿远离所述显示区的方向，在所述第一阻挡区和所述第二阻挡区中的任意一个区间中，所述多个条状的凸起结构在垂直于所述显示基板所在平面的方向上的尺寸依次增大。
  10. 根据权利要求9所述的显示基板，其中，所述第二阻挡结构包括第一凸起结构、第二凸起结构和第三凸起结构，所述第一凸起结构设置于所述第一半导体层，所述第二凸起结构设置于所述第一半导体层和所述第一导电层，所述第三凸起结构设置于所述第一半导体层、所述第一导电层和所述第二导电层。
  11. 根据权利要求10所述的显示基板，其中，所述第二凸起结构包括分别位于所述第一半导体层和所述第一导电层的两个第二子凸起结构，并且两个所述第二子凸起结构在所述基底上的正投影至少部分重叠；所述第三凸起结构包括分别位于所述第一半导体层、所述第一导电层、所述第二导电层的三个第三子凸起结构，并且三个所述第三子凸起结构在所述基底上的正投影至少部分重叠。
  12. 根据权利要求6至11任一项所述的显示基板，其中，所述第二阻挡结构还包括至少一个条状的凹槽结构，所述条状的凹槽结构设置于所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层中的其中一层或多层。
  13. 根据权利要求12所述的显示基板，其中，在平行于所述显示基板所在平面的方向上，在所述第一阻挡区，所述凹槽结构位于所述显示区与所述凸起结构之间；在所述第二阻挡区，所述凹槽结构位于所述第一阻挡坝与所述凸起结构之间。
  14. 根据权利要求13所述的显示基板，其中，在所述第一阻挡区和所述第二阻挡区中的任意一个区间中，在垂直于所述显示基板所在平面的方向上，所述第二阻挡结构中的凹槽结构和凸起结构远离所述基底一侧的表面相对于所述基底的高度依次增大。
  15. 根据权利要求5所述的显示基板，其中，所述第三导电层、所述第四导电层至少一个在平行于所述显示基板所在平面的方向上延伸至所述边框区，所述第三导电层和所述第四导电层的至少一个膜层设有第二电源线，所述第二阻挡结构在所述基底上的正投影与 所述第二电源线在所述基底上的正投影存在重叠区域。
  16. 根据权利要求15所述的显示基板，其中，在所述边框区域，所述第三导电层、所述第四导电层与所述第二阻挡结构在所述基底上正投影重叠区域的剖面形状与所述第二阻挡结构的剖面形状一致。
  17. 根据权利要求1至4任一项所述的显示基板，其中，所述边框区设有GOA电路，所述GOA电路在所述基底上的正投影与所述第二阻挡结构在所述基底上的正投影不重叠。
  18. 根据权利要求1至4任一项所述的显示基板，其中，所述驱动结构层包括依次叠设在所述基底上的第一半导体层、第一栅绝缘层、第一导电层、第二栅绝缘层、第二导电层、层间绝缘层、第三导电层、平坦化层和第四导电层，所述第二阻挡结构设置于所述第一半导体层、所述第一栅绝缘层、所述第一导电层、所述第二栅绝缘层、所述第二导电层、所述层间绝缘层中的其中一层或多层。
  19. 根据权利要求2所述的显示基板，其中，所述第二阻挡结构包括至少一个条状的凸起结构，或者，所述第二阻挡结构包括至少一个条状的凹槽结构，或者，所述第二阻挡结构包括至少一个条状的凸起结构和至少一个条状的凹槽结构。
  20. 根据权利要求19所述的显示基板，其中，在所述第二阻挡结构的延伸方向上，同一个条状的凸起结构中包括多个凸起结构段，相邻两个凸起结构段之间设有凸起间隔结构；同一个条状的凹槽结构中包括多个凹槽结构段，相邻两个凹槽结构段之间设有凹槽间隔结构。
  21. 根据权利要求20所述的显示基板，其中，所述第二阻挡结构包括多个凸起结构，多个凸起结构沿垂直于所述显示区边缘的方向排布，其中，多个凸起结构中的多个凸起结构段呈阵列排布，或者多个凸起结构中的多个凸起结构段呈错位排布。
  22. 根据权利要求21所述的显示基板，其中，在同一个凸起结构中，相邻两个凸起结构段的延伸方向与所述凸起结构的延伸方向之间分别呈第一夹角和第二夹角，所述第一夹角与所述第二夹角位于所述凸起结构的延伸方向的两侧。
  23. 根据权利要求22所述的显示基板，其中，所述第一夹角和所述第二夹角均小于或者等于15度。
  24. 根据权利要求22所述的显示基板，其中，在同一个凸起结构中，多个凸起结构段包括多个凸起结构组合，在同一个凸起结构组合中包括至少两个相互连接的凸起结构段， 并且相邻两个凸起结构段形成朝向所述显示区或朝向所述第一阻挡结构的第三夹角。
  25. 一种显示装置，包括权利要求1至24任一项所述的显示基板。
PCT/CN2023/123339 2022-11-17 2023-10-08 显示基板、显示装置 WO2024103995A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211460729.8A CN115802799A (zh) 2022-11-17 2022-11-17 一种显示基板、显示装置
CN202211460729.8 2022-11-17

Publications (1)

Publication Number Publication Date
WO2024103995A1 true WO2024103995A1 (zh) 2024-05-23

Family

ID=85439676

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/123339 WO2024103995A1 (zh) 2022-11-17 2023-10-08 显示基板、显示装置

Country Status (2)

Country Link
CN (1) CN115802799A (zh)
WO (1) WO2024103995A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115802799A (zh) * 2022-11-17 2023-03-14 京东方科技集团股份有限公司 一种显示基板、显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140191203A1 (en) * 2013-01-10 2014-07-10 Samsung Display Co., Ltd. Organic light-emitting display apparatus and method of manufacturing the same
US20170331058A1 (en) * 2016-05-10 2017-11-16 Samsung Display Co., Ltd. Flexible display apparatus
WO2021017010A1 (zh) * 2019-08-01 2021-02-04 京东方科技集团股份有限公司 显示基板及显示装置
CN213042915U (zh) * 2020-09-10 2021-04-23 京东方科技集团股份有限公司 显示基板和显示装置
WO2021189669A1 (zh) * 2020-03-23 2021-09-30 京东方科技集团股份有限公司 显示基板及其制备方法、显示母板和显示装置
WO2021227027A1 (zh) * 2020-05-15 2021-11-18 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113937236A (zh) * 2020-06-29 2022-01-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114430014A (zh) * 2022-01-28 2022-05-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115802799A (zh) * 2022-11-17 2023-03-14 京东方科技集团股份有限公司 一种显示基板、显示装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140191203A1 (en) * 2013-01-10 2014-07-10 Samsung Display Co., Ltd. Organic light-emitting display apparatus and method of manufacturing the same
US20170331058A1 (en) * 2016-05-10 2017-11-16 Samsung Display Co., Ltd. Flexible display apparatus
WO2021017010A1 (zh) * 2019-08-01 2021-02-04 京东方科技集团股份有限公司 显示基板及显示装置
WO2021189669A1 (zh) * 2020-03-23 2021-09-30 京东方科技集团股份有限公司 显示基板及其制备方法、显示母板和显示装置
WO2021227027A1 (zh) * 2020-05-15 2021-11-18 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN114144886A (zh) * 2020-05-15 2022-03-04 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113937236A (zh) * 2020-06-29 2022-01-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN213042915U (zh) * 2020-09-10 2021-04-23 京东方科技集团股份有限公司 显示基板和显示装置
CN114430014A (zh) * 2022-01-28 2022-05-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115802799A (zh) * 2022-11-17 2023-03-14 京东方科技集团股份有限公司 一种显示基板、显示装置

Also Published As

Publication number Publication date
CN115802799A (zh) 2023-03-14

Similar Documents

Publication Publication Date Title
CN112673474B (zh) 电致发光显示面板及显示装置
KR102667241B1 (ko) 유기 발광 표시 장치
US20210366393A1 (en) Display substrate and display device
US20220045161A1 (en) Transparent oled display panel, display apparatus and manufacturing method
US20210408203A1 (en) Display substrate and display device
JP2018189715A (ja) 表示装置
WO2023071560A1 (zh) 显示模组和显示设备
US11176898B2 (en) Display panel and electronic apparatus
CN112420794B (zh) 显示基板和显示装置
CN110783373A (zh) 显示装置
WO2024103995A1 (zh) 显示基板、显示装置
WO2023221762A9 (zh) 显示基板及其驱动方法和制备方法、显示装置
WO2022174692A1 (zh) 显示面板及显示装置
CN113924651A (zh) 显示基板以及显示装置
WO2024131376A1 (zh) 显示基板及显示装置
WO2024082964A1 (zh) 显示基板及其制备方法、显示装置
WO2024046040A1 (zh) 显示面板和显示装置
WO2022110015A1 (zh) 显示基板、显示面板、显示装置
WO2023283768A1 (zh) 显示基板及其制备方法、显示装置
WO2023023908A1 (zh) 显示基板及其制备方法、显示装置
WO2024092434A1 (zh) 显示基板及其制备方法、显示装置
WO2024113224A1 (zh) 显示面板和显示装置
WO2024036574A1 (zh) 显示基板及其制备方法、显示装置
WO2024065629A1 (zh) 显示基板及其制备方法、显示装置
WO2023092607A1 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23890432

Country of ref document: EP

Kind code of ref document: A1