WO2024093602A1 - 基准电压产生电路、芯片及电子设备 - Google Patents

基准电压产生电路、芯片及电子设备 Download PDF

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Publication number
WO2024093602A1
WO2024093602A1 PCT/CN2023/122790 CN2023122790W WO2024093602A1 WO 2024093602 A1 WO2024093602 A1 WO 2024093602A1 CN 2023122790 W CN2023122790 W CN 2023122790W WO 2024093602 A1 WO2024093602 A1 WO 2024093602A1
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WIPO (PCT)
Prior art keywords
transistor
current
reference voltage
voltage
drain
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PCT/CN2023/122790
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English (en)
French (fr)
Inventor
赵东艳
李明节
王于波
李振国
原义栋
胡毅
赵天挺
侯佳力
王亚彬
苏萌
刘宇
常乃超
Original Assignee
北京智芯微电子科技有限公司
国家电网有限公司
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Publication of WO2024093602A1 publication Critical patent/WO2024093602A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to a reference voltage generating circuit, a chip and an electronic device.
  • Reference voltage generation circuits such as bandgap reference sources are widely used in integrated circuits to provide a voltage that is independent of process, voltage and temperature. This voltage can be used in modules and chips such as data converters, reference voltage sources, and large-scale digital System on a Chip (SoC).
  • SoC System on a Chip
  • embodiments of the present disclosure provide a reference voltage generating circuit, a chip and an electronic device.
  • embodiments of the present disclosure provide a reference voltage generating circuit, a chip, and an electronic device.
  • the reference voltage generating circuit comprises:
  • a reference voltage generating circuit wherein the reference voltage generating circuit is used to generate a first reference voltage, wherein the first reference voltage does not vary with process and temperature;
  • a voltage stabilizing circuit comprising a voltage conversion circuit, a current sourcing voltage stabilizing branch and a current sinking voltage stabilizing branch, wherein:
  • the voltage conversion circuit is used to convert the first reference voltage into the reference voltage, and when the reference voltage generating circuit receives an external pull current, convert the reference voltage into a first control voltage, and when the reference voltage generating circuit receives an external sink current, convert the reference voltage into a second control voltage, wherein the voltage conversion circuit includes a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected with a common gate, the source of the first transistor MP5 is connected to the first reference voltage, and the drain is grounded via a third current source, and the third current source is a current source formed by the mirroring of the first current; the source of the second transistor MP6 is connected to the reference voltage, and the drain is connected to the pull current stabilizing branch and the sink current.
  • the current sourcing and voltage stabilizing branch includes a third transistor MN6 and a fourth transistor MP8, wherein the source of the third transistor MN6 is connected to the first control voltage, and the drain of the fourth transistor MP8 is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external sourcing current, causing the reference voltage to decrease;
  • the current injection and voltage stabilization branch includes a fifth transistor MN7, the gate of the fifth transistor MN7 is connected to the second control voltage, and the drain is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external current injection, causing the reference voltage to increase.
  • the reference voltage generating circuit is further used to generate a first current.
  • the reference voltage generating circuit includes a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit;
  • the first bipolar transistor Q1 , the second bipolar transistor Q2 , the third bipolar transistor Q3 , the first resistor R1 , and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
  • the base and collector of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input end of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input end of the first current mirror circuit via the first resistor R1;
  • the reference voltage generating circuit also includes a second current source, the base and collector of the third bipolar transistor Q3 are grounded, the emitter is connected to the second current source and the source of the first transistor MP5 via the second resistor R2, the second current source is a current source formed by twice mirroring the first current, and the other end of the second current source is connected to the power supply voltage.
  • the first transistor MP5 and the second transistor MP6 have the same characteristic size.
  • the drain of the second transistor MP6 is also connected to a fourth current source, where the fourth current source is a current source formed by twice mirroring the first current, and the other end of the fourth current source is grounded.
  • the gate of the third transistor MN6 is connected to the first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to the power supply voltage;
  • a source of the fifth transistor MN7 is grounded.
  • the drain of the third transistor MN6 is also connected to a fifth current source, which is a current source formed by mirroring the first current, and the other end of the fifth current source is connected to a power supply voltage.
  • the first bias voltage is generated by a bias branch, and the bias branch includes a sixth current source, a sixth transistor MN8, and a seventh transistor MN9;
  • the sixth current source is a current source formed by mirroring the first current, one end of which is connected to the power supply voltage, and the other end of which is connected to the first bias voltage and the drain of the sixth transistor MN8;
  • the gate and drain of the sixth transistor MN8 are short-circuited, and the source is connected to the drain of the seventh transistor MN9;
  • the gate and drain of the seventh transistor MN9 are short-circuited, and the source is grounded.
  • the first current mirror circuit includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1 and an eleventh transistor MP2, the source of the eighth transistor MN1 is the first input terminal of the first current mirror, the source of the ninth transistor MN2 is the second input terminal of the first current mirror, the gate and drain of the eighth transistor MN1 are short-circuited and connected to the gate of the ninth transistor MN2 and the drain of the tenth transistor MP1, the gate and drain of the eleventh transistor MP2 are short-circuited and connected to the gate of the tenth transistor MP1 and the drain of the ninth transistor MN2, and the sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to the power supply voltage.
  • the second current source includes a twelfth transistor MP3 , the gate of the twelfth transistor MP3 is connected to the gate of the eleventh transistor MP2 , the drain is connected to the second resistor R2 , and the source is connected to the power supply voltage.
  • the third current source includes a thirteenth transistor MP4, a fourteenth transistor MN3 and a fifteenth transistor MN4, wherein the gate of the thirteenth transistor MP4 is connected to the gate of the twelfth transistor MP3, the drain is connected to the drain of the fourteenth transistor MN3, and the source is connected to the power supply voltage; the gate and drain of the fourteenth transistor MN3 are short-circuited and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are both grounded, and the drain of the fifteenth transistor MN4 is connected to the drain of the first transistor MP5 as one end of the third current source.
  • the fourth current source includes a sixteenth transistor MN5, the gate of the sixteenth transistor MN5 is connected to the gate of the fifteenth transistor MN4, the drain as one end of the fourth current source is connected to the drain of the second transistor MP6, and the source is grounded.
  • the fifth current source includes a seventeenth transistor MP7, the gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP3, the drain as one end of the fifth current source is connected to the drain of the third transistor MN6, and the source is connected to the power supply voltage.
  • the sixth current source includes an eighteenth transistor MP9, the gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP3, the drain as one end of the sixth current source is connected to the drain of the sixth transistor MN8, and the source is connected to the power supply voltage.
  • the transistors MP1, MP2, MP4, MP7 and MP9 have the same characteristic size
  • the transistor MP3 has a characteristic size twice that of the transistor MP1
  • the transistors MN3 and MN4 have the same characteristic size
  • the transistor MN5 has a characteristic size twice that of the transistor MN3.
  • a chip in an embodiment of the present disclosure, wherein the chip includes a reference voltage generating circuit as described in any one of the first aspect.
  • an embodiment of the present disclosure provides an electronic device, the electronic device comprising the device as described in the second aspect.
  • the reference voltage generating circuit can quickly stabilize the reference voltage to a rated value when the reference voltage is lowered due to an external pulling current, and when the reference voltage is increased due to an external injecting current, thereby improving the reliability of the circuit.
  • FIG. 1 shows a structural diagram of a reference voltage generating circuit in the prior art.
  • FIG. 2 shows a structural block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
  • FIG. 3 shows a structural diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
  • FIG. 4 shows a structural block diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG5 shows a structural block diagram of a chip according to an embodiment of the present disclosure.
  • FIG1 shows a block diagram of a reference voltage generating circuit in the prior art.
  • the circuit composed of the bipolar transistor, resistor and error amplifier can provide a bandgap reference voltage that does not change with the process and temperature, and due to the presence of the metal oxide field effect MOS transistor in the figure, the circuit also has a certain positive
  • the reference voltage generating circuit receives an external pull current
  • the MOS tube can stabilize the voltage and quickly restore the reference voltage; however, when the reference voltage generating circuit receives an external sink current, it can only rely on resistors to repair and stabilize the reference voltage, and the recovery time is long. At this time, the voltage overshoot caused by the sink current will also last longer, which is easy to cause adverse effects on the devices in the circuit, shorten the device life or even cause device damage, resulting in low circuit reliability.
  • an embodiment of the present disclosure provides a reference voltage generating circuit, including: a reference voltage generating circuit, the reference voltage generating circuit is used to generate a first reference voltage, the first reference voltage does not change with process and temperature; a voltage stabilizing circuit, the voltage stabilizing circuit includes a voltage conversion circuit, a current pulling stabilizing branch and a current injecting stabilizing branch, wherein: the voltage conversion circuit is used to convert the first reference voltage into the reference voltage, and when the reference voltage generating circuit receives an external pull current, the reference voltage is converted into a first control voltage, and when the reference voltage generating circuit receives an external injection current, the reference voltage is converted into a second control voltage; the current pulling stabilizing branch receives the first control voltage to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external pull current, causing the reference voltage to decrease; the current injecting stabilizing branch receives the second control voltage to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external injection current, causing the reference voltage to decrease;
  • the reference voltage generation circuit can quickly stabilize the reference voltage to a rated value when receiving an external sourcing current that causes the reference voltage to decrease, and when receiving an external sinking current that causes the reference voltage to increase, thereby improving the reliability of the circuit.
  • the first control voltage is the same as the second control voltage.
  • FIG. 2 shows a structural block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
  • the reference voltage generating circuit comprises:
  • a reference voltage generating circuit wherein the reference voltage generating circuit is used to generate a first reference voltage, wherein the first reference voltage does not vary with process and temperature;
  • a voltage stabilizing circuit comprising a voltage conversion circuit, a current sourcing voltage stabilizing branch and a current sinking voltage stabilizing branch, wherein:
  • the voltage conversion circuit is used to convert the first reference voltage into the reference voltage, and when the reference voltage generating circuit receives an external pull current, convert the reference voltage into a first control voltage, and when the reference voltage generating circuit receives an external sink current, convert the reference voltage into a second control voltage, wherein the voltage conversion circuit includes a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected with a common gate, the source of the first transistor MP5 is connected to the first reference voltage, and the drain is grounded via a third current source, and the third current source is a current source formed by mirroring the first current; the source of the second transistor MP6 is connected to the reference voltage, and the drain is connected to the input ends of the pull current stabilizing branch and the sink current stabilizing branch;
  • the current sourcing and voltage stabilizing branch includes a third transistor MN6 and a fourth transistor MP8, wherein the source of the third transistor MN6 is connected to the first control voltage, and the drain of the fourth transistor MP8 is connected to the reference voltage. voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external pull current, causing the reference voltage to decrease;
  • the current injection and voltage stabilization branch includes a fifth transistor MN7, the gate of the fifth transistor MN7 is connected to the second control voltage, and the drain is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external current injection, causing the reference voltage to increase.
  • the reference voltage generating circuit may be a bandgap reference voltage generating circuit, in which case the reference voltage generating circuit generates a bandgap reference first reference voltage, and the first reference voltage does not change with process and temperature.
  • the reference voltage generating circuit may be a classic circuit composed of two bipolar transistors, a differential amplifier and a plurality of resistors as shown in FIG1 , or may be an improved circuit of the above classic circuit. The improved circuit will be described in detail later with reference to FIG3 .
  • the output node when the output node receives an external pull circuit or injection current, the output voltage of the output node will be reduced or increased accordingly, thereby causing the output reference voltage to deviate from its rated value and fail to provide a stable reference voltage.
  • a voltage stabilizing circuit is further provided in the reference voltage generating circuit, and the voltage stabilizing circuit includes a voltage conversion circuit, a current sourcing voltage stabilizing branch, and a current sinking voltage stabilizing branch.
  • the voltage conversion circuit is used to convert the first reference voltage into the reference voltage, and when the reference voltage generating circuit receives an external sourcing current, convert the reference voltage into a first control voltage, and when the reference voltage generating circuit receives an external sinking current, convert the reference voltage into a second control voltage.
  • the current sourcing voltage stabilizing branch receives the first control voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external sourcing current, causing the reference voltage to decrease; the current sinking voltage stabilizing branch receives the second control voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external sinking current, causing the reference voltage to increase.
  • the rated value of the reference voltage refers to the value of the reference voltage that needs to be provided by the reference voltage generating circuit, for example, it can be 3.3V, 1.8V, etc., and is not limited here.
  • the current sourcing voltage stabilizing branch and the current sinking voltage stabilizing branch both include active devices to improve the responsiveness of the branches, and are capable of stabilizing the reference voltage that is reduced due to sourcing current to a rated value, and stabilizing the reference voltage that is increased due to sinking current to a rated voltage.
  • the reference voltage generating circuit can quickly stabilize the reference voltage to a rated value when the reference voltage is lowered due to an external pulling current, and when the reference voltage is increased due to an external injecting current, thereby improving the reliability of the circuit.
  • the reference voltage generating circuit can also be used to generate a first current, so that each branch in the voltage stabilization circuit can set its own current source by mirroring the first current, thereby reducing the current deviation of each branch and further improving the reliability of the circuit.
  • FIG. 3 shows a structural diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
  • the reference voltage generating circuit may include a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; wherein the first bipolar transistor Q1, the second bipolar transistor Q2 and the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
  • the base and collector of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input terminal of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input terminal of the first current mirror circuit via the first resistor R1.
  • the first current mirror includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1 and an eleventh transistor MP2, the source of the eighth transistor MN1 is the first input terminal of the first current mirror, the source of the ninth transistor MN2 is the second input terminal of the first current mirror, the gate and drain of the eighth transistor MN1 are short-circuited and connected to the gate of the ninth transistor MN2 and the drain of the tenth transistor MP1, the gate and drain of the eleventh transistor MP2 are short-circuited and connected to the gate of the tenth transistor MP1 and the drain of the ninth transistor MN2, and the sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to the power supply voltage.
  • the reference voltage generating circuit may further include a second current source, the base and collector of the third bipolar transistor Q3 are both grounded, the emitter is connected to the second current source and the source of the first transistor MP5 through the second resistor R2, the second current source is a current source formed by the first current being mirrored twice, and the other end of the second current source is connected to the power supply voltage.
  • the second current source may include a twelfth transistor MP3, the gate of the twelfth transistor MP3 is connected to the gate of the eleventh transistor MP2, the drain is connected to the second resistor R2, and the source is connected to the power supply voltage.
  • the emitter-base voltage difference (Veb1-Veb2) of the first bipolar transistor Q1 and the second bipolar transistor Q2 with a positive temperature coefficient and the emitter-base voltage Veb3 of the third bipolar transistor Q3 with a negative temperature coefficient can be obtained.
  • transistors MN1, MN2, MP1 and MP2 form a self-bias loop, and the source voltages of MN1 and MN2 are .
  • I C I S *e Veb/Vt
  • I S the saturation current of the bipolar transistor
  • Veb the emitter-base voltage of the bipolar transistor
  • Vt the thermal voltage
  • T the absolute temperature
  • q the electron charge.
  • the first transistor MP5 and the second transistor MP6 can be set to have the same characteristic size, so that the current flowing through the two is also equal, and then the gate-source voltage of the first transistor MP5 and the second transistor MP6 is also equal.
  • the first reference voltage Vref1 can be copied losslessly from the source of the first transistor MP5 to the source of the second transistor MP6 for output, and the first reference voltage Vref1 is buffered and isolated by the first transistor MP5, and the second transistor MP6 is used as a level conversion circuit to generate a first control voltage output to the current sourcing voltage stabilizing branch and a second control voltage output to the current sinking voltage stabilizing branch, thereby improving the circuit reliability.
  • the third current source may include a thirteenth transistor MP4, a fourteenth transistor MN3 and a fifteenth transistor MN4, wherein the gate of the thirteenth transistor MP4 is connected to the gate of the twelfth transistor MP3, the drain is connected to the drain of the fourteenth transistor MN3, and the source is connected to the power supply voltage; the gate and drain of the fourteenth transistor MN3 are short-circuited and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are both grounded, and the drain of the fifteenth transistor MN4 is connected to the drain of the first transistor MP5 as one end of the third current source.
  • the drain of the second transistor MP6 is also connected to a fourth current source, the fourth current source is a current source formed by twice mirroring the first current, and the other end of the fourth current source is grounded.
  • the fourth current source may include a sixteenth transistor MN5, the gate of the sixteenth transistor MN5 is connected to the gate of the fifteenth transistor MN4, the drain is connected to the drain of the second transistor MP6 as one end of the fourth current source, and the source is grounded.
  • the current-pulling and voltage-stabilizing branch includes a third transistor MN6 and a fourth transistor MP8, the source of the third transistor MN6 is the input end of the current-pulling and voltage-stabilizing branch, the gate is connected to the first bias voltage, the drain is connected to the gate of the fourth transistor MP8, the source of the fourth transistor MP8 is connected to the power supply voltage, and the drain is connected to the reference voltage.
  • the drain of the third transistor MN6 may also be connected to a fifth current source.
  • the fifth current source is a current source formed by mirroring the first current, and the other end of the fifth current source is connected to the power supply voltage.
  • the fifth current source may include a seventeenth transistor MP7, the gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP3, the drain as one end of the fifth current source is connected to the drain of the third transistor MN6, and the source is connected to the power supply voltage.
  • the output reference voltage Vref of the reference voltage generating circuit When the reference voltage generating circuit receives an external pull current, the output reference voltage Vref of the reference voltage generating circuit will be pulled down, and at this time, the source voltage of the second transistor MP6 is reduced, resulting in an increase in the gate-source voltage of the second transistor MP6, thereby increasing the leakage current of the second transistor MP6. Since the current provided by the fourth current source remains constant, at this time, the current flowing through the third transistor MN6 will decrease, thereby causing the drain voltage of the third transistor MN6 to decrease, that is, the gate voltage of the fourth transistor MP8 will decrease, causing the fourth transistor MP8 to turn on, and quickly stabilize the reference voltage to the rated value.
  • the current injection and voltage stabilizing branch includes a fifth transistor MN7, the gate of the fifth transistor MN7 is the input end of the current injection and voltage stabilizing branch, the source is grounded, and the drain is connected to the reference voltage.
  • the output reference voltage Vref of the reference voltage generating circuit When the reference voltage generating circuit receives an external current injection, the output reference voltage Vref of the reference voltage generating circuit will increase. At this time, the source voltage of the second transistor MP6 will increase, causing the drain voltage of the second transistor MP6 to increase. That is to say, the gate voltage of the fifth transistor MN7 will increase, causing the fifth transistor MN7 to turn on, quickly stabilizing the reference voltage to the rated value.
  • active devices MN6, MP8 and MN7 are used to form the current sourcing voltage stabilizing circuit and the current sinking voltage stabilizing circuit, not only can the output reference voltage be stabilized in both the current sourcing and current sinking conditions, but the response speed is also fast.
  • the first bias voltage is generated by a bias branch
  • the bias branch includes a sixth current source, a sixth transistor MN8, and a seventh transistor MN9.
  • the sixth current source is a current source formed by mirroring the first current, one end of which is connected to the power supply voltage, and the other end is connected to the first bias voltage and the drain of the sixth transistor MN8; the gate and drain of the sixth transistor MN8 are short-circuited, and the source is connected to the drain of the seventh transistor MN9; the gate and drain of the seventh transistor MN9 are short-circuited, and the source is grounded.
  • the sixth current source may include an eighteenth transistor MP9, the gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP3, the drain is connected to the drain of the sixth transistor MN8 as one end of the sixth current source, and the source is connected to the power supply voltage.
  • a bias branch is formed by a current source formed by a mirror image of the first current and two transistors connected in series in a diode connection manner to provide a first bias voltage for the current pulling and voltage stabilizing branch, with a simple structure and stable performance.
  • the transistors MN1-MN9 may be N-type metal oxide field effect transistors NMOS, and the transistors MP1-MP9 may be P-type metal oxide field effect transistors NMOS.
  • the transistors MP5 and MP6 have the same characteristic size
  • the transistors MP1, MP2, MP4, MP7 and MP9 have the same characteristic size
  • the transistor MP3 has a characteristic size twice that of the transistor MP1
  • the transistors MN3 and MN4 have the same characteristic size
  • the transistor MN5 has a characteristic size twice that of the transistor MN3.
  • the reference voltage generating circuit in the reference voltage generating circuit can also be replaced by other reference voltage generating circuits, that is, other reference voltage generating circuits can also be combined with the voltage stabilizing circuit in the reference voltage generating circuit to realize a reference voltage generating circuit having both current sourcing and current sinking functions.
  • other reference voltage generating circuits can also be combined with the voltage stabilizing circuit in the reference voltage generating circuit to realize a reference voltage generating circuit having both current sourcing and current sinking functions.
  • FIG. 4 shows a structural block diagram of an electronic device according to an embodiment of the present disclosure.
  • the electronic device includes the reference voltage generating circuit provided by an embodiment of the present disclosure.
  • the reference voltage generating circuit comprises:
  • a reference voltage generating circuit wherein the reference voltage generating circuit is used to generate a first reference voltage, wherein the first reference voltage does not vary with process and temperature;
  • a voltage stabilizing circuit comprising a voltage conversion circuit, a current sourcing voltage stabilizing branch and a current sinking voltage stabilizing branch, wherein:
  • the voltage conversion circuit is used to convert the first reference voltage into the reference voltage, and when the reference voltage generating circuit receives an external source current, convert the reference voltage into a first control voltage, and when the reference voltage generating circuit receives an external sink current, convert the reference voltage into a second control voltage;
  • the current sourcing and voltage stabilizing branch includes a third transistor MN6 and a fourth transistor MP8, wherein the source of the third transistor MN6 is connected to the first control voltage, and the drain of the fourth transistor MP8 is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external sourcing current, causing the reference voltage to decrease;
  • the current injection and voltage stabilization branch includes a fifth transistor MN7, the gate of the fifth transistor MN7 is connected to the second control voltage, and the drain is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external current injection, causing the reference voltage to increase.
  • the reference voltage generating circuit is further used to generate a first current.
  • the reference voltage generating circuit includes a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit;
  • the first bipolar transistor Q1 , the second bipolar transistor Q2 , the third bipolar transistor Q3 , the first resistor R1 , and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
  • the base and collector of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input end of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input end of the first current mirror circuit via the first resistor R1;
  • the reference voltage generating circuit further includes a second current source.
  • the base and collector of the third bipolar transistor Q3 are both grounded, and the emitter is connected to the second current source and the first transistor via the second resistor R2.
  • the source of MP5 the second current source is a current source formed by twice mirroring the first current, and the other end of the second current source is connected to the power supply voltage.
  • the voltage conversion circuit includes a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected with a common gate, the source of the first transistor MP5 is connected to the first reference voltage, and the drain is grounded via a third current source, and the third current source is a current source formed by mirroring the first current; the source of the second transistor MP6 is connected to the reference voltage, and the drain is connected to the input ends of the current sourcing voltage stabilization branch and the current sinking voltage stabilization branch.
  • the first transistor MP5 and the second transistor MP6 have the same characteristic size.
  • the drain of the second transistor MP6 is also connected to a fourth current source, where the fourth current source is a current source formed by twice mirroring the first current, and the other end of the fourth current source is grounded.
  • the gate of the third transistor MN6 is connected to the first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to the power supply voltage;
  • a source of the fifth transistor MN7 is grounded.
  • the drain of the third transistor MN6 is also connected to a fifth current source, which is a current source formed by mirroring the first current, and the other end of the fifth current source is connected to a power supply voltage.
  • the first bias voltage is generated by a bias branch, and the bias branch includes a sixth current source, a sixth transistor MN8, and a seventh transistor MN9;
  • the sixth current source is a current source formed by mirroring the first current, one end of which is connected to the power supply voltage, and the other end of which is connected to the first bias voltage and the drain of the sixth transistor MN8;
  • the gate and drain of the sixth transistor MN8 are short-circuited, and the source is connected to the drain of the seventh transistor MN9;
  • the gate and drain of the seventh transistor MN9 are short-circuited, and the source is grounded.
  • FIG5 shows a structural block diagram of a chip according to an embodiment of the present disclosure.
  • the chip includes the electronic device provided by the embodiment of the present disclosure, and the electronic device includes the reference voltage generating circuit provided by the embodiment of the present disclosure.
  • the reference voltage generating circuit comprises:
  • a reference voltage generating circuit the reference voltage generating circuit is used to generate a first reference voltage, the first reference voltage does not change with process and temperature;
  • a voltage stabilizing circuit comprising a voltage conversion circuit, a current sourcing voltage stabilizing branch and a current sinking voltage stabilizing branch, wherein:
  • the voltage conversion circuit is used to convert the first reference voltage into the reference voltage, and when the reference voltage generating circuit receives an external source current, convert the reference voltage into a first control voltage, and when the reference voltage generating circuit receives an external sink current, convert the reference voltage into a second control voltage;
  • the current sourcing and voltage stabilizing branch includes a third transistor MN6 and a fourth transistor MP8.
  • the source of MN6 is connected to the first control voltage, and the drain of the fourth transistor MP8 is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generation circuit receives an external pull current, causing the reference voltage to decrease;
  • the current injection and voltage stabilization branch includes a fifth transistor MN7, the gate of the fifth transistor MN7 is connected to the second control voltage, and the drain is connected to the reference voltage, so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external current injection, causing the reference voltage to increase.

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Abstract

本公开涉及集成电路技术领域，具体涉及一种基准电压产生电路、芯片及电子设备，所述基准电压产生电路包括：参考电压产生电路，所述参考电压产生电路用于生成第一参考电压；稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压；所述拉电流稳压支路接收所述第一控制电压，所述灌电流稳压支路接收所述第二控制电压，以对所述基准电压进行稳压，从而提高电路可靠性。

Description

基准电压产生电路、芯片及电子设备 技术领域
本公开涉及集成电路技术领域，具体涉及一种基准电压产生电路、芯片及电子设备。
背景技术
带隙基准参考源等基准电压产生电路广泛地应用于集成电路中，提供一个与工艺、电压和温度无关的电压，该电压可用于数据转换器、基准电压源、大规模数字片上系统(System on a Chip，SoC)等模块和芯片中。
在工业领域的高精度数据采集系统中，芯片的采样精度及采样精度随负载变化量严重依赖于芯片上的高精度基准源，为了保证芯片在宽负载范围工作时，降低绝对采样精度随负载变化的幅度，亟需研制一种同时具有拉电流和灌电流的基准电压产生电路，解决高精度采样系统面临的负载变化引起参考电压变化，从而导致采样精度降低的难题。
发明内容
为了解决相关技术中的问题，本公开实施例提供一种基准电压产生电路、芯片及电子设备。
第一方面，本公开实施例中提供了一种基准电压产生电路、芯片及电子设备。
具体地，所述基准电压产生电路包括：
参考电压产生电路，所述参考电压产生电路用于生成第一参考电压，所述第一参考电压不随工艺和温度变化；
稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：
所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压，其中，所述电压转换电路包括第一晶体管MP5和第二晶体管MP6，所述第一晶体管MP5和第二晶体管MP6采用共栅极连接，第一晶体管MP5的源极连接于所述第一参考电压，漏极经第三电流源接地，所述第三电流源为所述第一电流经镜像形成的电流源；所述第二晶体管MP6的源极连接于所述基准电压，漏极连接于所述拉电流稳压支路和灌电 流稳压支路的输入端；
所述拉电流稳压支路包括第三晶体管MN6和第四晶体管MP8，所述第三晶体管MN6的源极连接于所述第一控制电压，所述第四晶体管MP8的漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；
所述灌电流稳压支路包括第五晶体管MN7，所述第五晶体管MN7的栅极连接于所述第二控制电压，漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。
在本公开实施例中，所述参考电压产生电路还用于生成第一电流。
在本公开实施例中，所述参考电压产生电路包括第一双极型晶体管Q1、第二双极型晶体管Q2、第三双极型晶体管Q3、第一电阻R1、第二电阻R2、第一电流镜电路；其中，
所述第一双极型晶体管Q1、第二双极型晶体管Q2和第三双极型晶体管Q3、第一电阻R1、第二电阻R2用于生成所述第一参考电压，所述第一电流镜电路用于生成所述第一电流。
在本公开实施例中，所述第一双极型晶体管Q1和第二双极型晶体管Q2的基极和集电极均接地，所述第一双极型晶体管Q1的发射极连接于所述第一电流镜电路的第一输入端，所述第二双极型晶体管Q2的发射极经所述第一电阻R1连接于所述第一电流镜电路的第二输入端；
所述参考电压产生电路还包括第二电流源，所述第三双极型晶体管Q3的基极和集电极均接地，发射极经所述第二电阻R2连接于所述第二电流源和所述第一晶体管MP5的源极，所述第二电流源为所述第一电流经两倍镜像形成的电流源，所述第二电流源的另一端连接于电源电压。
在本公开实施例中，所述第一晶体管MP5和第二晶体管MP6具有相同的特征尺寸。
在本公开实施例中，所述第二晶体管MP6的漏极还连接于第四电流源，所述第四电流源为所述第一电流经两倍镜像形成的电流源，所述第四电流源的另一端接地。
在本公开实施例中，所述第三晶体管MN6的栅极连接于第一偏置电压，漏极连接于所述第四晶体管MP8的栅极，所述四晶体管MP8的源极连接于电源电压；
所述第五晶体管MN7的源极接地。
在本公开实施例中，所述第三晶体管MN6的漏极还连接于第五电流源，所述第五电流源为所述第一电流经一倍镜像形成的电流源，所述第五电流源的另一端连接于电源电压。
在本公开实施例中，所述第一偏置电压由偏置支路生成，所述偏置支路包括第六电流源、第六晶体管MN8和第七晶体管MN9；
所述第六电流源为所述第一电流经镜像形成的电流源，其一端连接于电源电压，另一端连接于所述第一偏置电压和所述第六晶体管MN8的漏极；
所述第六晶体管MN8的栅漏短接，源极连接于所述第七晶体管MN9漏极；
所述第七晶体管MN9的栅漏短接，源极接地。
在本公开实施例中，所述第一电流镜电路包括第八晶体管MN1、第九晶体管MN2、第十晶体管MP1和第十一晶体管MP2，所述第八晶体管MN1的源极为所述第一电流镜的第一输入端，所述第九晶体管MN2的源极为所述第一电流镜的第二输入端，所述第八晶体管MN1的栅漏短接，并连接于所述第九晶体管MN2的栅极和所述第十晶体管MP1的漏极，所述第十一晶体管MP2的栅漏短接，并连接于所述第十晶体管MP1的栅极和所述第九晶体管MN2的漏极，所述第十晶体管MP1和第十一晶体管MP2的源极均连接于电源电压。
在本公开实施例中，所述第二电流源包括第十二晶体管MP3，所述第十二晶体管MP3的栅极连接于第十一晶体管MP2的栅极，漏极连接于所述第二电阻R2，源极连接于电源电压。
在本公开实施例中，所述第三电流源包括第十三晶体管MP4、第十四晶体管MN3和第十五晶体管MN4，其中，所述第十三晶体管MP4的栅极连接于所述第十二晶体管MP3的栅极，漏极连接于所述第十四晶体管MN3的漏极，源极连接于电源电压；所述第十四晶体管MN3的栅漏短接，并连接于所述第十五晶体管MN4的栅极，所述第十四晶体管MN3和第十五晶体管MN4的源极均接地，所述第十五晶体管MN4的漏极作为第三电流源的一端连接于所述第一晶体管MP5的漏极。
在本公开实施例中，所述第四电流源包括第十六晶体管MN5，所述第十六晶体管MN5的栅极连接于所述第十五晶体管MN4的栅极，漏极作为第四电流源的一端连接于所述第二晶体管MP6的漏极，源极接地。
在本公开实施例中，所述第五电流源包括第十七晶体管MP7，所述第十七晶体管MP7的栅极连接于所述第十二晶体管MP3的栅极，漏极作为第五电流源的一端连接于所述第三晶体管MN6的漏极，源极连接于电源电压。
在本公开实施例中，所述第六电流源包括第十八晶体管MP9，所述第十八晶体管MP9的栅极连接于所述第十二晶体管MP3的栅极，漏极作为第六电流源的一端连接于所述第六晶体管MN8的漏极，源极连接于电源电压。
在本公开实施例中，所述晶体管MP1、MP2、MP4、MP7和MP9具有相同的特征尺寸，晶体管MP3具有两倍于晶体管MP1的特征尺寸，晶体管MN3和MN4具有相同的特征尺寸，晶体管MN5具有两倍于晶体管MN3的特征尺寸。
第二方面，本公开实施例中提供了一种芯片，所述芯片包括如第一方面中任一项所述的基准电压产生电路。
第三方面，本公开实施例提供了一种电子设备，所述电子设备包括如第二方面所 述的芯片。
根据本公开实施例提供的技术方案，通过在基准电压产生电路中增设同时包括拉电流稳压支路和灌电流稳压支路的稳压电路，使得所述基准电压产生电路在接收到外部拉电流导致基准电压降低时，以及在接收到外部灌电流导致基准电压升高时，均能快速将基准电压稳压至额定值，提高了电路的可靠性。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
结合附图，通过以下非限制性实施方式的详细描述，本公开的其它特征、目的和优点将变得更加明显。在附图中。
图1示出已有技术中的基准电压产生电路的结构图。
图2示出根据本公开实施例的基准电压产生电路的结构框图。
图3示出根据本公开实施例的基准电压产生电路的结构图。
图4示出根据本公开实施例的电子设备的结构框图。
图5示出根据本公开实施例的芯片的结构框图。
具体实施方式
下文中，将参考附图详细描述本公开的示例性实施例，以使本领域技术人员可容易地实现它们。此外，为了清楚起见，在附图中省略了与描述示例性实施例无关的部分。
在本公开中，应理解，诸如“包括”或“具有”等的术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不欲排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在或被添加的可能性。
另外还需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
上文提及，在工业领域的高精度数据采集系统中，芯片的采样精度及采样精度随负载变化量严重依赖于芯片上的高精度基准源，为了保证芯片在宽负载范围工作时，降低绝对采样精度随负载变化的幅度，亟需研制一种同时具有拉电流和灌电流的基准电压产生电路，解决高精度采样系统面临的负载变化引起参考电压变化，从而导致采样精度降低的难题。
图1示出已有技术中的基准电压产生电路的结构图。如图1所示，由图中双极型晶体管、电阻以及误差放大器组成的电路可以提供一个不随工艺和温度变化的带隙基准电压，且由于图中金属氧化物场效应MOS晶体管的存在，该电路还具备一定的正 向驱动能力。在该基准电压产生电路接收到外部拉电流的条件下，MOS管可以起到稳压作用，快速恢复基准电压；但是，在该基准电压产生电路接收到外部灌电流的条件下，只能依靠电阻来进行基准电压的修复稳压，恢复时间较长，此时灌电流造成的电压过冲持续时间也会较长，容易对电路中的器件造成不良影响，缩短器件寿命甚至导致器件损坏，进而导致电路可靠性较低。
鉴于此，本公开实施例提供了一种基准电压产生电路，包括：参考电压产生电路，所述参考电压产生电路用于生成第一参考电压，所述第一参考电压不随工艺和温度变化；稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压；所述拉电流稳压支路接收所述第一控制电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；所述灌电流稳压支路接收所述第二控制电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。通过在基准电压产生电路中增设同时包括拉电流稳压支路和灌电流稳压支路的稳压电路，使得所述基准电压产生电路在接收到外部拉电流导致基准电压降低时，以及在接收到外部灌电流导致基准电压升高时，均能快速将基准电压稳压至额定值，提高了电路的可靠性。其中，所述第一控制电压与所述第二控制电压相同。
图2示出根据本公开实施例的基准电压产生电路的结构框图。
如图2所示，所述基准电压产生电路包括：
参考电压产生电路，所述参考电压产生电路用于生成第一参考电压，所述第一参考电压不随工艺和温度变化；
稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：
所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压，其中，所述电压转换电路包括第一晶体管MP5和第二晶体管MP6，所述第一晶体管MP5和第二晶体管MP6采用共栅极连接，第一晶体管MP5的源极连接于所述第一参考电压，漏极经第三电流源接地，所述第三电流源为所述第一电流经镜像形成的电流源；所述第二晶体管MP6的源极连接于所述基准电压，漏极连接于所述拉电流稳压支路和灌电流稳压支路的输入端；
所述拉电流稳压支路包括第三晶体管MN6和第四晶体管MP8，所述第三晶体管MN6的源极连接于所述第一控制电压，所述第四晶体管MP8的漏极连接于所述基准 电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；
所述灌电流稳压支路包括第五晶体管MN7，所述第五晶体管MN7的栅极连接于所述第二控制电压，漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。
在本公开实施例中，基准电压产生电路可以是带隙基准电压产生电路，此时所述参考电压产生电路产生的是带隙基准第一参考电压，所述第一参考电压不随工艺和温度变化。所述参考电压产生电路可以是如图1所示由两个双极型晶体管、一个差分放大器和若干个电阻组成的经典电路，也可以是对上述经典电路的改进电路。所述改进电路将在后文参考图3进行详细描述。
若将所述参考电压产生电路产生的第一参考电压作为基准电压直接输出，则在输出节点收到外部拉电路或灌电流时，该输出节点的输出电压会相应地降低或拉高，进而导致输出的基准电压偏离了其额定值，无法提供稳定的基准电压。
鉴于此，在本公开实施例中，在所述基准电压产生电路中进一步设置了稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路。其中,所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压。所述拉电流稳压支路接收所述第一控制电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；所述灌电流稳压支路接收所述第二控制电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。
在本公开实施例中，所述基准电压的额定值是指需要基准电压产生电路提供的基准电压的值，例如可以是3.3V、1.8V等，此处不做限制。
在本公开实施例中，所述拉电流稳压支路和灌电流稳压支路均包括有源器件，以提高支路的响应能力，能够将拉电流导致降低的基准电压稳压至额定值，并将灌电流导致升高的基准电压稳压至额定电压。
根据本公开实施例的技术方案，通过在基准电压产生电路中增设同时包括拉电流稳压支路和灌电流稳压支路的稳压电路，使得所述基准电压产生电路在接收到外部拉电流导致基准电压降低时，以及在接收到外部灌电流导致基准电压升高时，均能快速将基准电压稳压至额定值，提高了电路的可靠性。
在本公开实施例中，所述参考电压产生电路还可用于生成第一电流，以使所述稳压电路中各支路可以通过镜像该第一电流的方式设置自身的电流源，从而减少各支路的电流偏差，进一步提高电路的可靠性。
图3示出根据本公开实施例的基准电压产生电路的结构图。
如图3所示，所述参考电压产生电路可以包括第一双极型晶体管Q1、第二双极型晶体管Q2、第三双极型晶体管Q3、第一电阻R1、第二电阻R2、第一电流镜电路；其中，所述第一双极型晶体管Q1、第二双极型晶体管Q2和第三双极型晶体管Q3、第一电阻R1、第二电阻R2用于生成所述第一参考电压，所述第一电流镜电路用于生成所述第一电流。
具体地，所述第一双极型晶体管Q1和第二双极型晶体管Q2的基极和集电极均接地，所述第一双极型晶体管Q1的发射极连接于所述第一电流镜电路的第一输入端，所述第二双极型晶体管Q2的发射极经所述第一电阻R1连接于所述第一电流镜电路的第二输入端。所述第一电流镜包括第八晶体管MN1、第九晶体管MN2、第十晶体管MP1和第十一晶体管MP2，所述第八晶体管MN1的源极为所述第一电流镜的第一输入端，所述第九晶体管MN2的源极为所述第一电流镜的第二输入端，所述第八晶体管MN1的栅漏短接，并连接于所述第九晶体管MN2的栅极和所述第十晶体管MP1的漏极，所述第十一晶体管MP2的栅漏短接，并连接于所述第十晶体管MP1的栅极和所述第九晶体管MN2的漏极，所述第十晶体管MP1和第十一晶体管MP2的源极均连接于电源电压。
在本公开实施例中，所述参考电压产生电路还可以包括第二电流源，所述第三双极型晶体管Q3的基极和集电极均接地，发射极经所述第二电阻R2连接于所述第二电流源和所述第一晶体管MP5的源极，所述第二电流源为所述第一电流经两倍镜像形成的电流源，所述第二电流源的另一端连接于电源电压。在本公开的一个具体实施方式中，所述第二电流源可以包括第十二晶体管MP3，所述第十二晶体管MP3的栅极连接于第十一晶体管MP2的栅极，漏极连接于所述第二电阻R2，源极连接于电源电压。通过合理设置第一双极型晶体管Q1、第二双极型晶体管Q2和第三双极型晶体管Q3的特征尺寸，将具有正温度系数的第一双极型晶体管Q1和第二双极型晶体管Q2的发射极-基极电压差(Veb1-Veb2)，与具有负温度系数的第三双极型晶体管Q3的发射极-基极电压Veb3，可以得到一个不随温度和工艺变化的第一参考电压Vref1。
具体地，假设忽略电路中的失配，包括电阻间失配、晶体管间失配等，晶体管MN1、MN2、MP1和MP2构成自偏置环路，且MN1和MN2的源极电压想到。由于对双极型晶体管而言，集电极电流与饱和电流的关系为：IC＝IS*eVeb/Vt，其中，IC为双极型晶体管的集电极电路，IS为双极型晶体管的饱和电路，Veb为双极型晶体管的发射极-基极电压，Vt为热电压，Vt＝kT/q，k为玻尔兹曼常数，T为绝对温度，q为电子电荷。
图3中的双极型晶体管Q1、Q2和Q3的基极、集电极均接地，因此该双极型晶体管Q1、Q2和Q3的电流均为：IQ＝IE＝IB+IC＝(1+1/□F)Is*eVeb/Vt，其中IQ为流过双极型晶体管的电流，IE为双极型晶体管的发射极电流，IB为双极型晶体管的基极电流。进一步可以得出，Veb＝Vt*ln(IQ/(Is*(1+1/□F)))。
图3中的第八晶体管MN1和第九晶体管MN2大小相等，第十晶体管MP1和第 十一晶体管MP2大小相等，因此流过双极型晶体管Q1和Q2的电流IQ1和IQ2相等，二者的发射极-基极电压差为：ΔVeb＝Veb1-Veb2＝Vt*ln((IQ1*IS2)/(IS1*IQ2))＝Vt*lnN，其中，N为第二双极型晶体管Q2和第一双极型晶体管Q1的发射极面积比，此时所述第一双极型晶体管Q1和第二双极型晶体管Q2的饱和电流之比为：IS1：IS2＝1：N。
从图3中可以看出，双极型晶体管Q1和Q2中的电流等于第一电阻R1中的电流，因此：IQ1＝IQ2＝ΔVeb/R1＝Vt*ln(N/R1)。
合理设置各器件尺寸，使得所述第二电流源产生的电流平均分配至第二电阻R2、第三双极型晶体管Q3支路和第一参考电压Vref1输出支路，可以得出，第二电阻R2中的电流与第一电阻R1中的电流相等，进而可以得到实现了一阶温度补偿的第一参考电压Vref1：Vref1＝Veb3+((Veb1-Veb2)/R1)*R2。
在本公开实施例中，可以设置所述第一晶体管MP5和第二晶体管MP6具有相同的特征尺寸，以使二者流过的电流大小也相等，进而使所述第一晶体管MP5和第二晶体管MP6的栅源电压也相等。采用这种方式，可以将所述第一参考电压Vref1由第一晶体管MP5的源极无损复制至第二晶体管MP6的源极进行输出，并将第一参考电压Vref1经第一晶体管MP5缓冲隔离后，由第二晶体管MP6作为电平转换电路来产生输出至拉电流稳压支路的第一控制电压，以及输出至灌电流稳压支路的第二控制电压，提高电路可靠性。通过晶体管MP8、MN6和MN7，得到一个同时具有拉电流、灌电流的带隙基准电压VREF1为VREF1＝VREF11-VSGMP5+VSGMP6，其中，VSGMP5为所述第一晶体管MP5的源栅电压，VSGMP6为所述第二晶体管MP6的源栅电压。
在本公开实施例中，所述第三电流源可以包括第十三晶体管MP4、第十四晶体管MN3和第十五晶体管MN4，其中，所述第十三晶体管MP4的栅极连接于所述第十二晶体管MP3的栅极，漏极连接于所述第十四晶体管MN3的漏极，源极连接于电源电压；所述第十四晶体管MN3的栅漏短接，并连接于所述第十五晶体管MN4的栅极，所述第十四晶体管MN3和第十五晶体管MN4的源极均接地，所述第十五晶体管MN4的漏极作为第三电流源的一端连接于所述第一晶体管MP5的漏极。
在本公开实施例中，所述第二晶体管MP6的漏极还连接于第四电流源，所述第四电流源为所述第一电流经两倍镜像形成的电流源，所述第四电流源的另一端接地。具体地，所述第四电流源可以包括第十六晶体管MN5，所述第十六晶体管MN5的栅极连接于所述第十五晶体管MN4的栅极，漏极作为第四电流源的一端连接于所述第二晶体管MP6的漏极，源极接地。
在本公开实施例中，所述拉电流稳压支路包括第三晶体管MN6和第四晶体管MP8，所述第三晶体管MN6的源极为该拉电流稳压支路的输入端，栅极连接于第一偏置电压，漏极连接于所述第四晶体管MP8的栅极，所述四晶体管MP8的源极连接于电源电压，漏极连接于所述基准电压。
在本公开实施例中，所述第三晶体管MN6的漏极还可以连接于第五电流源，所述 第五电流源为所述第一电流经一倍镜像形成的电流源，所述第五电流源的另一端连接于电源电压。具体地，所述第五电流源可以包括第十七晶体管MP7，所述第十七晶体管MP7的栅极连接于所述第十二晶体管MP3的栅极，漏极作为第五电流源的一端连接于所述第三晶体管MN6的漏极，源极连接于电源电压。
当基准电压产生电路接收到外部拉电流时，所述基准电压产生电路的输出基准电压Vref会被拉低，此时所述第二晶体管MP6的源极电压降低，导致所述第二晶体管MP6的栅源电压增大，进而导致所述第二晶体管MP6的漏电流增大。由于第四电流源提供的电流保持恒定，此时，流过所述第三晶体管MN6的电流将会减小，进而导致所述第三晶体管MN6的漏极电压降低，也就是说，所述第四晶体管MP8的栅极电压将会降低，使得所述第四晶体管MP8导通，快速将所述基准电压稳压至额定值。
在本公开实施例中，所述灌电流稳压支路包括第五晶体管MN7，所述第五晶体管MN7的栅极为该灌电流稳压支路的输入端，源极接地，漏极连接于所述基准电压。
当基准电压产生电路接收到外部灌电流时，所述基准电压产生电路的输出基准电压Vref会升高，此时所述第二晶体管MP6的源极电压升高，导致所述第二晶体管MP6的漏极电压升高，也就是说，所述第五晶体管MN7的栅极电压将会升高，使得所述第五晶体管MN7导通，快速将所述基准电压稳压至额定值。
根据本公开实施例的技术方案，由于采用有源器件MN6、MP8和MN7构成所述拉电流稳压电路和所述灌电流稳压电路，不仅能够在拉电流情况和灌电流情况均对输出基准电压进行稳压，且反应速度快。
在本公开实施例中，所述第一偏置电压由偏置支路生成，所述偏置支路包括第六电流源、第六晶体管MN8和第七晶体管MN9。其中，所述第六电流源为所述第一电流经镜像形成的电流源，其一端连接于电源电压，另一端连接于所述第一偏置电压和所述第六晶体管MN8的漏极；所述第六晶体管MN8的栅漏短接，源极连接于所述第七晶体管MN9漏极；所述第七晶体管MN9的栅漏短接，源极接地。进一步地，所述第六电流源可以包括第十八晶体管MP9，所述第十八晶体管MP9的栅极连接于所述第十二晶体管MP3的栅极，漏极作为第六电流源的一端连接于所述第六晶体管MN8的漏极，源极连接于电源电压。
根据本公开实施例的技术方案，通过由第一电流经镜像形成的电流源和两个串联的二极管连接方式连接的晶体管形成偏置支路，以为拉电流稳压支路提供第一偏置电压，结构简单性能稳定。
在本公开实施例中，所述晶体管MN1-MN9可以是N型金属氧化物场效应晶体管NMOS，所述晶体管MP1-MP9以是P型金属氧化物场效应晶体管NMOS。其中，晶体管MP5和MP6具有相同的特征尺寸，晶体管MP1、MP2、MP4、MP7和MP9具有相同的特征尺寸，晶体管MP3具有两倍于晶体管MP1的特征尺寸，晶体管MN3和MN4具有相同的特征尺寸，晶体管MN5具有两倍于晶体管MN3的特征尺寸。
在本公开另一实施例中，所述基准电压产生电路中的参考电压产生电路还可替换为其他参考电压产生电路，也即其他参考电压产生电路也可与所述基准电压产生电路中的稳压电路相结合，来实现同时具有拉电流和灌电流功能的基准电压产生电路。本领域技术人员可根据实际应用的需要选择不同的参考电压产生电路与所述稳压电路结合，本公开在此不做过多描述。
图4示出根据本公开实施例的电子设备的结构框图。
如图4所示，所述电子设备包括本公开实施例提供的基准电压产生电路。
具体地，所述基准电压产生电路包括：
参考电压产生电路，所述参考电压产生电路用于生成第一参考电压，所述第一参考电压不随工艺和温度变化；
稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：
所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压；
所述拉电流稳压支路包括第三晶体管MN6和第四晶体管MP8，所述第三晶体管MN6的源极连接于所述第一控制电压，所述第四晶体管MP8的漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；
所述灌电流稳压支路包括第五晶体管MN7，所述第五晶体管MN7的栅极连接于所述第二控制电压，漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。
在本公开实施例中，所述参考电压产生电路还用于生成第一电流。
在本公开实施例中，所述参考电压产生电路包括第一双极型晶体管Q1、第二双极型晶体管Q2、第三双极型晶体管Q3、第一电阻R1、第二电阻R2、第一电流镜电路；其中，
所述第一双极型晶体管Q1、第二双极型晶体管Q2和第三双极型晶体管Q3、第一电阻R1、第二电阻R2用于生成所述第一参考电压，所述第一电流镜电路用于生成所述第一电流。
在本公开实施例中，所述第一双极型晶体管Q1和第二双极型晶体管Q2的基极和集电极均接地，所述第一双极型晶体管Q1的发射极连接于所述第一电流镜电路的第一输入端，所述第二双极型晶体管Q2的发射极经所述第一电阻R1连接于所述第一电流镜电路的第二输入端；
所述参考电压产生电路还包括第二电流源，所述第三双极型晶体管Q3的基极和集电极均接地，发射极经所述第二电阻R2连接于所述第二电流源和所述第一晶体管 MP5的源极，所述第二电流源为所述第一电流经两倍镜像形成的电流源，所述第二电流源的另一端连接于电源电压。
在本公开实施例中，所述电压转换电路包括第一晶体管MP5和第二晶体管MP6，所述第一晶体管MP5和第二晶体管MP6采用共栅极连接，第一晶体管MP5的源极连接于所述第一参考电压，漏极经第三电流源接地，所述第三电流源为所述第一电流经镜像形成的电流源；所述第二晶体管MP6的源极连接于所述基准电压，漏极连接于所述拉电流稳压支路和灌电流稳压支路的输入端。
在本公开实施例中，所述第一晶体管MP5和第二晶体管MP6具有相同的特征尺寸。
在本公开实施例中，所述第二晶体管MP6的漏极还连接于第四电流源，所述第四电流源为所述第一电流经两倍镜像形成的电流源，所述第四电流源的另一端接地。
在本公开实施例中，所述第三晶体管MN6的栅极连接于第一偏置电压，漏极连接于所述第四晶体管MP8的栅极，所述四晶体管MP8的源极连接于电源电压；
所述第五晶体管MN7的源极接地。
在本公开实施例中，所述第三晶体管MN6的漏极还连接于第五电流源，所述第五电流源为所述第一电流经一倍镜像形成的电流源，所述第五电流源的另一端连接于电源电压。
在本公开实施例中，所述第一偏置电压由偏置支路生成，所述偏置支路包括第六电流源、第六晶体管MN8和第七晶体管MN9；
所述第六电流源为所述第一电流经镜像形成的电流源，其一端连接于电源电压，另一端连接于所述第一偏置电压和所述第六晶体管MN8的漏极；
所述第六晶体管MN8的栅漏短接，源极连接于所述第七晶体管MN9漏极；
所述第七晶体管MN9的栅漏短接，源极接地。
图5示出根据本公开实施例的芯片的结构框图。
如图5所示，所述芯片包括本公开实施例提供的电子设备，所述电子设备包括本公开实施例提供的基准电压产生电路。
具体地，所述基准电压产生电路包括：
参考电压产生电路，所述参考电压产生电路用于生成第一参考电压，所述第一参考电压不随工艺和温度变化；
稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：
所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压；
所述拉电流稳压支路包括第三晶体管MN6和第四晶体管MP8，所述第三晶体管 MN6的源极连接于所述第一控制电压，所述第四晶体管MP8的漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；
所述灌电流稳压支路包括第五晶体管MN7，所述第五晶体管MN7的栅极连接于所述第二控制电压，漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (18)

  1. 一种基准电压产生电路，其特征在于，包括：
    参考电压产生电路，所述参考电压产生电路用于生成第一参考电压，所述第一参考电压不随工艺和温度变化；
    稳压电路，所述稳压电路包括电压转换电路、拉电流稳压支路和灌电流稳压支路，其中：
    所述电压转换电路用于将所述第一参考电压转换成所述基准电压，并在所述基准电压产生电路接收到外部拉电流时，将所述基准电压转换为第一控制电压，在所述基准电压产生电路接收到外部灌电流时，将所述基准电压转换为第二控制电压，其中，所述电压转换电路包括第一晶体管MP5和第二晶体管MP6，所述第一晶体管MP5和第二晶体管MP6采用共栅极连接，第一晶体管MP5的源极连接于所述第一参考电压，漏极经第三电流源接地，所述第三电流源为第一电流经镜像形成的电流源；所述第二晶体管MP6的源极连接于所述基准电压，漏极连接于所述拉电流稳压支路和灌电流稳压支路的输入端；
    所述拉电流稳压支路包括第三晶体管MN6和第四晶体管MP8，所述第三晶体管MN6的源极连接于所述第一控制电压，所述第四晶体管MP8的漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部拉电流，导致所述基准电压降低时，将所述基准电压稳压至额定值；
    所述灌电流稳压支路包括第五晶体管MN7，所述第五晶体管MN7的栅极连接于所述第二控制电压，漏极连接于所述基准电压，以在所述基准电压产生电路接收到外部灌电流，导致所述基准电压升高时，将所述基准电压稳压至额定值。
  2. 根据权利要求1所述的电路，其特征在于，
    所述参考电压产生电路还用于生成第一电流。
  3. 根据权利要求2所述的电路，其特征在于，
    所述参考电压产生电路包括第一双极型晶体管Q1、第二双极型晶体管Q2、第三双极型晶体管Q3、第一电阻R1、第二电阻R2、第一电流镜电路；其中，
    所述第一双极型晶体管Q1、第二双极型晶体管Q2和第三双极型晶体管Q3、第一电阻R1、第二电阻R2用于生成所述第一参考电压，所述第一电流镜电路用于生成所述第一电流。
  4. 根据权利要求3所述的电路，其特征在于，
    所述第一双极型晶体管Q1和第二双极型晶体管Q2的基极和集电极均接地，所述第一双极型晶体管Q1的发射极连接于所述第一电流镜电路的第一输入端，所述第二双极型晶体管Q2的发射极经所述第一电阻R1连接于所述第一电流镜电路的第二输入 端；
    所述参考电压产生电路还包括第二电流源，所述第三双极型晶体管Q3的基极和集电极均接地，发射极经所述第二电阻R2连接于所述第二电流源和所述第一晶体管MP5的源极，所述第二电流源为所述第一电流经两倍镜像形成的电流源，所述第二电流源的另一端连接于电源电压。
  5. 根据权利要求1所述的电路，其特征在于，
    所述第一晶体管MP5和第二晶体管MP6具有相同的特征尺寸。
  6. 根据权利要求5所述的电路，其特征在于，
    所述第二晶体管MP6的漏极还连接于第四电流源，所述第四电流源为所述第一电流经两倍镜像形成的电流源，所述第四电流源的另一端接地。
  7. 根据权利要求6所述的电路，其特征在于，
    所述第三晶体管MN6的栅极连接于第一偏置电压，漏极连接于所述第四晶体管MP8的栅极，所述四晶体管MP8的源极连接于电源电压；
    所述第五晶体管MN7的源极接地。
  8. 根据权利要求7所述的电路，其特征在于，
    所述第三晶体管MN6的漏极还连接于第五电流源，所述第五电流源为所述第一电流经一倍镜像形成的电流源，所述第五电流源的另一端连接于电源电压。
  9. 根据权利要求8所述的电路，其特征在于，
    所述第一偏置电压由偏置支路生成，所述偏置支路包括第六电流源、第六晶体管MN8和第七晶体管MN9；
    所述第六电流源为所述第一电流经镜像形成的电流源，其一端连接于电源电压，另一端连接于所述第一偏置电压和所述第六晶体管MN8的漏极；
    所述第六晶体管MN8的栅漏短接，源极连接于所述第七晶体管MN9漏极；
    所述第七晶体管MN9的栅漏短接，源极接地。
  10. 根据权利要求9所述的电路，其特征在于，
    所述第一电流镜电路包括第八晶体管MN1、第九晶体管MN2、第十晶体管MP1和第十一晶体管MP2，所述第八晶体管MN1的源极为所述第一电流镜的第一输入端，所述第九晶体管MN2的源极为所述第一电流镜的第二输入端，所述第八晶体管MN1的栅漏短接，并连接于所述第九晶体管MN2的栅极和所述第十晶体管MP1的漏极，所述第十一晶体管MP2的栅漏短接，并连接于所述第十晶体管MP1的栅极和所述第九晶体管MN2的漏极，所述第十晶体管MP1和第十一晶体管MP2的源极均连接于电源电压。
  11. 根据权利要求10所述的电路，其特征在于，
    所述第二电流源包括第十二晶体管MP3，所述第十二晶体管MP3的栅极连接于第十一晶体管MP2的栅极，漏极连接于所述第二电阻R2，源极连接于电源电压。
  12. 根据权利要求11所述的电路，其特征在于，
    所述第三电流源包括第十三晶体管MP4、第十四晶体管MN3和第十五晶体管MN4，其中，所述第十三晶体管MP4的栅极连接于所述第十二晶体管MP3的栅极，漏极连接于所述第十四晶体管MN3的漏极，源极连接于电源电压；所述第十四晶体管MN3的栅漏短接，并连接于所述第十五晶体管MN4的栅极，所述第十四晶体管MN3和第十五晶体管MN4的源极均接地，所述第十五晶体管MN4的漏极作为第三电流源的一端连接于所述第一晶体管MP5的漏极。
  13. 根据权利要求12所述的电路，其特征在于，
    所述第四电流源包括第十六晶体管MN5，所述第十六晶体管MN5的栅极连接于所述第十五晶体管MN4的栅极，漏极作为第四电流源的一端连接于所述第二晶体管MP6的漏极，源极接地。
  14. 根据权利要求13所述的电路，其特征在于，
    所述第五电流源包括第十七晶体管MP7，所述第十七晶体管MP7的栅极连接于所述第十二晶体管MP3的栅极，漏极作为第五电流源的一端连接于所述第三晶体管MN6的漏极，源极连接于电源电压。
  15. 根据权利要求14所述的电路，其特征在于，
    所述第六电流源包括第十八晶体管MP9，所述第十八晶体管MP9的栅极连接于所述第十二晶体管MP3的栅极，漏极作为第六电流源的一端连接于所述第六晶体管MN8的漏极，源极连接于电源电压。
  16. 根据权利要求15所述的电路，其特征在于，
    所述晶体管MP1、MP2、MP4、MP7和MP9具有相同的特征尺寸，晶体管MP3具有两倍于晶体管MP1的特征尺寸，晶体管MN3和MN4具有相同的特征尺寸，晶体管MN5具有两倍于晶体管MN3的特征尺寸。
  17. 一种芯片，其特征在于，
    所述芯片包括如权利要求1-16中任一项所述的基准电压产生电路。
  18. 一种电子设备，其特征在于，
    所述电子设备包括如权利要求17所述的芯片。
PCT/CN2023/122790 2022-10-31 2023-09-28 基准电压产生电路、芯片及电子设备 WO2024093602A1 (zh)

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