WO2024093278A1 - 显示驱动电路及显示装置 - Google Patents

显示驱动电路及显示装置 Download PDF

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Publication number
WO2024093278A1
WO2024093278A1 PCT/CN2023/102772 CN2023102772W WO2024093278A1 WO 2024093278 A1 WO2024093278 A1 WO 2024093278A1 CN 2023102772 W CN2023102772 W CN 2023102772W WO 2024093278 A1 WO2024093278 A1 WO 2024093278A1
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WO
WIPO (PCT)
Prior art keywords
transistor
reference voltage
timing controller
level signal
data connection
Prior art date
Application number
PCT/CN2023/102772
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English (en)
French (fr)
Inventor
周满城
郑浩旋
Original Assignee
惠科股份有限公司
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Publication of WO2024093278A1 publication Critical patent/WO2024093278A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/06—Passive matrix structure, i.e. with direct application of both column and row voltages to the light emitting or modulating elements, other than LCD or OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3216—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes

Definitions

  • the present application belongs to the field of display, and specifically relates to a display driving circuit and a display device.
  • LED (light emitting diode) display screens have put forward higher requirements for row drivers, from simple P-type MOSFET (metal-oxide semiconductor field-effect transistor) to realize row switching, to more integrated and powerful multifunctional row drivers.
  • simple P-type MOSFET metal-oxide semiconductor field-effect transistor
  • the LED light emission time is short, and the current in the parasitic capacitor discharge path remains unchanged, resulting in a smaller proportion of the current flowing through the LED, which causes the LED to be colored.
  • the present disclosure provides a display driving circuit and a display device, which improve the color deviation problem of LED at low gray scale, thereby improving the display effect.
  • a first aspect of the present disclosure provides a display driving circuit, comprising:
  • the selection circuit having a first signal receiving end, a second signal receiving end, a data connection end, and a reference voltage end;
  • the first signal receiving end is connected to the first timing controller, and is used to receive the level signal output by the first timing controller;
  • the second signal receiving end is connected to the second timing controller, and is used to receive the level signal output by the second timing controller;
  • the data connection end is configured to be connected to a data line, and is used to output its upper level signal to the data line;
  • the selection circuit is used to select and respond to the level signal output by the first timing controller in the row scanning stage to control the reference voltage terminal and the data connection terminal to be connected; the selection circuit is used to select and respond to the level signal output by the first timing controller in the row scanning stage to control the reference voltage terminal and the data connection terminal to be connected; The stage at least selects to respond to the level signal output by the second timing controller to control the reference voltage terminal and the data connection terminal to be connected.
  • a second aspect of the present disclosure provides a display device, which includes a display panel located in a display area, a scanning drive circuit located in a non-display area, and the display drive circuit described in any one of the above items, wherein the display panel includes a plurality of light-emitting pixels arranged in an array, a plurality of columns of data lines, and a plurality of rows of scanning lines, the first electrode of the light-emitting pixel is connected to the scanning line, the scanning line is connected to the scanning drive circuit, the second electrode of the light-emitting pixel is connected to the data line, and the data line is connected to the data connection end of the display drive circuit.
  • the selection circuit utilizes the signal output by the second timing controller so that the reference voltage terminal is connected to the data connection terminal during the gap between two adjacent rows of scanning, that is, during the gap between two adjacent rows of scanning, the reference voltage of the reference voltage terminal is written into the data line, so that the charge of the parasitic capacitor on the data line is released in advance before the light-emitting pixels in this column (that is, the light-emitting pixels in the column driven by this data line) are illuminated, ensuring that the total current at the data connection terminal is equal to or substantially close to the current passing through the light-emitting pixels. In other words, it is ensured that the current for the light-emitting pixels in this column to illuminate substantially all passes through the data connection terminal, which can solve the problem of low grayscale color deviation of the light-emitting pixels and improve display uniformity.
  • the difference between the voltage provided by the scanning line and the reference voltage provided by the reference voltage terminal is smaller than the threshold voltage of the luminous pixel to avoid affecting normal data display.
  • FIG. 1 is a simplified schematic diagram showing the structure of a display device described in the present disclosure.
  • FIG. 2 is a schematic diagram showing the connection relationship between the scan drive circuit, the display drive circuit, the data lines, the scan lines and the light-emitting pixels described in the present disclosure.
  • FIG. 3 shows a timing diagram of the display device shown in FIG. 2 .
  • FIG. 4 shows a structural block diagram of a display driving circuit described in the first embodiment of the present disclosure.
  • FIG5 shows a schematic structural diagram of a display device described in Embodiment 1 of the present disclosure.
  • FIG. 6 shows a timing diagram of the display device shown in FIG. 5 .
  • FIG. 7 shows a schematic diagram of the structure of a display device described in the second embodiment of the present disclosure.
  • FIG. 8 shows a timing chart of the display device shown in FIG. 7 .
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.
  • the display device may include a display driving circuit 10, a scanning driving circuit 20 and a display panel
  • the display panel may include a plurality of array-arranged light-emitting pixels 30, a plurality of columns of data lines 40 and a plurality of rows of scanning lines 50
  • the scanning lines 50 are connected to the scanning driving circuit 20
  • the data lines 40 are connected to the data connection end of the display driving circuit 10
  • the first pole of the light-emitting pixel 30 is connected to the scanning line 50
  • the second pole of the light-emitting pixel 30 is connected to the data line 40.
  • the scanning drive circuit 20 writes a first voltage to the first electrode of the luminescent pixel 30 through the scanning line 50
  • the display driving circuit 10 writes a second voltage to the second electrode of the luminescent pixel 30 through the data line 40.
  • the difference between the first voltage and the second voltage at both ends of the luminescent pixel 30 is greater than the threshold voltage of the luminescent pixel 30, the luminescent pixel 30 can emit light.
  • the difference between the first voltage and the second voltage of the luminescent pixel 30 is less than the threshold voltage of the luminescent pixel 30, the luminescent pixel 30 does not emit light.
  • the display panel of the embodiment of the present disclosure may be an OLED display, a Mini-LED display or a Micro-LED display, that is, the light-emitting pixel 30 may be a light-emitting diode (LED for short).
  • the light-emitting pixel 30 may be a light-emitting diode (LED for short).
  • the first electrode of the light-emitting diode can be an anode and the second electrode can be a cathode; wherein each row of scan lines 50 is connected to the anodes of each light-emitting diode in a row, and each column of data lines 40 is connected to the cathodes of each light-emitting diode in a column.
  • the transistor connected to the scan line 50 in the scan drive circuit 20 in Figure 2 can be a P-type transistor, so it responds to the low-level signal to turn on to pull up the voltage on the corresponding scan line 50.
  • the control end of the transistor on the nth row of the scan line in the scan driving circuit 20 responds to the data signal Row(n)
  • the control end of the transistor on the n+1th row of the scan line in the scan driving circuit 20 responds to the data signal Row(n+1)
  • the control end of the transistor on the n+2th row of the scan line in the scan driving circuit 20 responds to the data signal Row(n+2)
  • the data signal written to the mth column of the data line by the display driving circuit 10 is Out(m)
  • the data signal written to the m+1th column of the data line by the display driving circuit 10 is Out(m+1)
  • the data signal written to the m+2th column of the data line by the display driving circuit 10 is Out(m+2)
  • the low-level signal widths of the data signal Out(m), the data signal Out(m+1), and the data signal Out(m+2) increase successively, that is, the light-emitting time of the mth, m+1th, and m+2th LEDs in the n+1th row increases successively, that is, the width of the low level of the data signal Out is positively correlated with the light-emitting time of the LED.
  • the LED lighting time is shorter, and the current in the parasitic capacitor discharge path remains unchanged, resulting in a smaller proportion of the current flowing through the LED, causing the LED color cast; for example: if the proportion of the current flowing through the red LED is affected less, the overall color will be redder; if the proportion of the current flowing through the blue LED is affected less, the overall color will be bluer; if the proportion of the current flowing through the green LED is affected less, the green color will be affected less, and the overall color will be greener.
  • Low grayscale is because the PWM is turned on for a short time, and the total current flowing through the LED is relatively small, so the display
  • the current at the data connection end of the driving circuit 10 (the port connected to the data line 40) is composed of the sum of the current flowing through the LED and the current of the parasitic capacitance on the data line 40.
  • the current ratio of the two will be different, which results in different effects of the parasitic capacitance on the R (red), G (green), and B (blue)-LEDs.
  • the effect of the current on the parasitic capacitance on the display will be very obvious, and the displayed effect will have a color cast; because the current passing through the data connection end of the display driving circuit 10 is not all passing through the LED, but also includes the charge part on the parasitic capacitance of the data line 40, that is to say, the fundamental reason for the low grayscale color cast is that the current required for the LED to emit light is less than the current flowing through the data connection end of the display driving circuit 10, that is, the actual brightness of the LED does not reach the brightness it should have.
  • the embodiment of the present disclosure improves the aforementioned display driving circuit 10 .
  • the display driving circuit 10 of the embodiment of the present disclosure may include a first timing controller 101 , a second timing controller 102 and a selection circuit 103 .
  • the first timing controller 101 is used to control the light-emitting pixel 30 to emit light in the normal display stage (row scanning stage); the second timing controller 102 is used to control the charge release of the parasitic capacitor on the data line 40 in the gap stage between two adjacent row scanning stages.
  • the selection circuit 103 has a first signal receiving terminal Cr1, a second signal receiving terminal Cr2, a data connection terminal D, and a reference voltage terminal S;
  • the first signal receiving terminal Cr1 is connected to the first timing controller 101, and is used to receive the level signal output by the first timing controller 101;
  • the second signal receiving terminal Cr2 is connected to the second timing controller 102, and is used to receive the level signal output by the second timing controller 102;
  • the data connection terminal D is configured to be connected to the data line 40, and is used to output its upper level signal to the data line 40.
  • the display driving circuit 10 may include a plurality of selection circuits 103, and the data connection terminal D of each selection circuit 103 is connected to a corresponding data line 40.
  • FIG. 5 only shows a schematic diagram of the connection between one selection circuit 103 and one data line 40, and it should be noted that the remaining data lines 40 may also be connected to a selection circuit 103 in the same manner.
  • G1, G2, and G3 are signals output by the scanning driving circuit 20 to the corresponding rows
  • Out1 and Out2 are signals output by the display driving circuit 10 to the corresponding columns.
  • the selection circuit 103 is used to select the level signal output by the first timing controller 101 in the row scanning phase (normal display phase) A, and control the reference voltage terminal S and the data connection terminal D to be turned on, so that the voltage V1 on the reference voltage terminal S is written to the second electrode of the light-emitting pixel 30 through the data connection terminal D, so that the voltage difference between the first electrode and the second electrode of the light-emitting pixel 30 is greater than the threshold voltage of the light-emitting pixel 30, so that the light-emitting pixel 30 emits light for display.
  • the threshold voltage of the light-emitting pixel 30 is usually greater than 0.
  • the voltage received by the corresponding row scanning line 50 is a high-level voltage
  • the voltage (for example: Out2) provided by the reference voltage terminal S to the data line 40 is a low-level voltage, so that a voltage difference greater than its threshold voltage is formed at both ends of the luminous pixel 30, thereby achieving normal luminous display.
  • the selection circuit 103 is used to at least select and respond to the level signal output by the second timing controller 102 in the scanning gap stage B between two adjacent rows, and control the reference voltage terminal S and the data connection terminal D to be turned on, so that the voltage on the reference voltage terminal S is written to the second electrode of the luminous pixel 30 through the data connection terminal D, as shown in the B1 stage in Figure 6, so that the charge of the parasitic capacitance on the data line 40 is released in advance before the luminous pixels in this column (that is, the luminous pixels in the column driven by this data line 40) are illuminated, that is, released in the scanning gap stage B between two adjacent rows, ensuring that the total current of the data connection terminal D is equal to or basically close to the current passing through the luminous pixel 30. In other words, it is ensured that the current for illuminating the luminous pixels 30 in this column basically passes through the data connection terminal D, which can solve the problem of low grayscale color deviation of the luminous pixels 30 and improve display uniformity.
  • the difference between the voltage received by the scanning line 50 and the reference voltage provided by the reference voltage terminal S should be smaller than the threshold voltage of the luminous pixel 30 to avoid affecting normal data display.
  • G2 is at a low level, that is, the voltage received by the corresponding row scanning line 50 is a low level voltage.
  • the voltage of Out2 in the B1 stage is the low level voltage provided by the reference voltage terminal S to the corresponding data line 40
  • the potential in the B2 stage is the blanking voltage corresponding to the data line 40, so that the voltage difference between the two electrodes of the luminous pixel 30 is equal to 0 (in the B1 stage) or less than 0 (in the B2 stage). Since the threshold value of the luminous pixel is greater than 0, the luminous pixel 30 does not emit light in the stage B between two adjacent scanning rows.
  • interval phase B between two adjacent scanning rows in this embodiment refers to the phase after the scanning of the nth row is completed and before the scanning of the (n+1)th row is started.
  • the selection circuit 103 is used to select the level signal output by the second timing controller 102 in response to a partial time period of the scanning gap stage B between two adjacent rows (for example, the B1 time period in Figure 6) to control the reference voltage terminal S and the data connection terminal D. That is, the charge release time of the parasitic capacitor on the data line 40 is less than the scanning gap time between two adjacent rows. Compared with the scheme of using the entire scanning gap time between two adjacent rows to realize the charge release, this scheme can realize the charge release of the parasitic capacitor on the data line 40 to improve the color deviation of the luminous pixel while reducing the control accuracy and reducing the occurrence of false lighting.
  • the scanning gap phase B between two adjacent rows can be divided into at least two time periods.
  • the scanning gap phase B between two adjacent rows at least includes a first time period B1 and a second time period B2 which are sequentially arranged.
  • the selection circuit 103 is used to select the first time period B1 in response to the output of the second timing controller 102.
  • the first time period B1 corresponds to the stage of releasing the parasitic capacitance charge on the data line 40; and the selection circuit 103 is also used to select the second time period B2 in response to the second level signal output by the second timing controller 102 to control the reference voltage terminal S and the data connection terminal D to be disconnected.
  • the voltage on the data line 40 is the blanking voltage.
  • This stage is the transition time period between the charge release stage and the next line light-emitting stage. This design ensures that the charge on the data line 40 is released as soon as possible between the scanning gaps of two adjacent lines to avoid the situation where the color deviation still exists due to incomplete charge release.
  • the level signals output by the second timing controller 102 in the first time period B1 and the second time period B2 of the scanning gap phase B between two adjacent rows are different, that is, one of the first level signal output by the second timing controller 102 in the first time period B1 and the second level signal output in the second time period B2 is a high level signal, and the other is a low level signal, which can be selected according to the specific structure of the selection circuit 103.
  • control signal output by the first timing controller 101 is not affected by the second timing controller 102, and only needs to control the output according to specific display requirements.
  • the selection circuit 103 will normally respond to the level signal output by the first timing controller 101 and write the reference voltage of the reference voltage terminal S to the data line 40 via the data connection terminal D.
  • the second timing controller 102 can adjust the output duration of the first level signal in the scanning gap phase B between two adjacent lines based on the display parameter information, that is, adjust the duration of the first time period B1 in the scanning gap phase B between two adjacent lines, thereby adjusting the charge release duration of the parasitic capacitor on the data line 40.
  • the display parameter information may include parameters such as color deviation.
  • the second timing controller 102 increases the output duration of the first level signal in the scanning gap stage B between two adjacent rows, that is, increases the duration of the first time period B1 in the scanning gap stage B between two adjacent rows, so that the charge of the parasitic capacitor on the data line 40 can be fully released, thereby improving the color deviation.
  • the selection circuit 103 includes an OR gate Or and a switching transistor T; wherein the OR gate Or has the first signal receiving terminal Cr1, the second signal receiving terminal Cr2 and the signal output terminal mentioned above; the control terminal of the switching transistor T is connected to the signal output terminal of the OR gate Or, the first terminal of the switching transistor T is connected to the data connection terminal D, and the second terminal of the switching transistor T is connected to the reference voltage terminal S.
  • the structure of this selection circuit 103 is simple, which is convenient for circuit design, saves space and reduces costs.
  • the switch transistor T can be an N-type transistor.
  • the level signal output by the first timing controller 101 to the first signal receiving terminal Cr1 is a low level signal
  • the level signal output by the second timing controller 102 to the second signal receiving terminal Cr2 is a high level signal.
  • the OR gate Or outputs to the switch
  • the control signal of transistor T is a high-level signal, so that the first end and the second end of the switching transistor T are turned on, that is, the reference voltage terminal S is connected to the data connection terminal D, so that the reference voltage output by the reference voltage terminal S is written to the data line 40 through the data connection terminal D, thereby realizing the charge release of the parasitic capacitance on the data line 40.
  • the first level signal output by the second timing controller 102 in the first time period B1 is a high level signal
  • the second level signal output in the second time period B2 is a low level signal
  • the level signal output by the first timing controller 101 is a high level signal
  • the level signal output by the second timing controller 102 is not limited and can be a high level signal or a low level signal.
  • the switch transistor T is not limited to being an N-type transistor, but may also be a P-type transistor. It is only necessary to adjust the level signals output by the first timing controller 101 and the second timing controller 102 accordingly, and no further limitation is made here.
  • the reference voltage provided by the reference voltage terminal S in the row scanning phase A may be equal to the reference voltage provided in the adjacent row scanning interval phase, as shown in FIG. 5 and FIG. 6 , which simplifies the structure and reduces the cost.
  • the main difference between the second embodiment and the first embodiment is that the specific architecture of the selection circuit 103 is different.
  • the remaining structures can refer to the first embodiment and will not be repeated here.
  • the reference voltage terminal includes a first reference voltage terminal S1 and a second reference voltage terminal S2; and in addition to the first signal receiving terminal Cr1, the second signal receiving terminal Cr2, the data connection terminal D, and the reference voltage terminal S mentioned above, the selection circuit 103 may also include a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.
  • the control ends of the first transistor T1, the third transistor T3 and the fourth transistor T4 are all connected to the second signal receiving end Cr2; the first end of the first transistor T1 is connected to the first signal receiving end Cr1, and the second end of the first transistor T1 is connected to the control end of the second transistor T2; the first end of the second transistor T2 is connected to the data connection end D, and the second end of the second transistor T2 is connected to the first reference voltage end S1; the first end of the third transistor T3 is connected to the data connection end D, and the second end of the third transistor T3 is connected to the second reference voltage end S2; the first end of the fourth transistor T4 is connected to the control end of the second transistor T2, and the second end of the fourth transistor T4 is connected to the first reference voltage end S1.
  • the first transistor T1 is a first type transistor
  • the second transistor T2 the third transistor T3 and the fourth transistor T4 are all second type transistors
  • one of the first type transistor and the second type transistor is a P type transistor
  • the other is an N type transistor.
  • the following description is made by taking the first transistor T1 as a P-type transistor, and the second transistor T2 , the third transistor T3 , and the fourth transistor T4 as N-type transistors as an example.
  • the level signal output by the second timing controller 102 to the second signal receiving terminal Cr2 is a low level signal.
  • the third transistor T3 and the fourth transistor T4 are turned off, the first transistor T1 is turned on, and the first timing controller 101 outputs a level signal to the first signal receiving terminal Cr1 to control the switch of the second transistor T2; when the level signal output by the first timing controller 101 to the first signal receiving terminal Cr1 is a high level signal, the second transistor T2 is turned on, and the first reference voltage terminal S1 writes its reference voltage to the data line 40 via the data connection terminal D, that is, the voltage on the data line 40 is equal to the reference voltage at the first reference voltage terminal S1 (as shown in V1 in Figure 8), and when the level signal output by the first timing controller 101 to the first signal receiving terminal Cr1 is a low level signal, the second transistor T2 is turned off, and the voltage of the data line 40 is equal to the column default voltage (which can be understood as
  • the level signal output by the second timing controller 102 to the second signal receiving terminal Cr2 is a high level signal.
  • the third transistor T3 and the fourth transistor T4 are turned on, and the first transistor T1 is turned off; because the voltages of the gate and the source (control terminal and the second terminal) of the second transistor T2 are both the voltages provided by the first reference voltage terminal S1, that is, the voltage difference Vgs between the gate and the source of the second transistor T2 is 0, which is less than the threshold voltage Vth of the second transistor T2, and the second transistor T2 is turned off; it can be seen that at this time, the voltage on the data line 40 is equal to the reference voltage provided by the second reference voltage terminal S2 (as shown in V2 in FIG8 ). It should be understood that the reference voltage provided by the second reference voltage terminal S2 written on the data line 40 does not affect the normal display stage.
  • the selection circuit 103 of this embodiment adopts this design so that the reference voltage written into the data line 40 in the row scanning phase A and the phase B of the interval between two adjacent row scanning can be different or the same, and can be adjusted and matched according to actual conditions, which is more flexible.
  • the voltages provided by the first reference voltage terminal S1 and the second reference voltage terminal S2 are not equal.
  • the voltage V2 provided by the second reference voltage terminal S2 is between the blanking voltage of the data line 40 and the reference voltage V1 provided by the first reference voltage terminal S1. This can reduce the loss while protecting the light-emitting pixel 30.

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Abstract

一种显示驱动电路(10)和显示装置，显示驱动电路(10)包括：第一时序控制器(101)和第二时序控制器(102)；及具有第一信号接收端(Cr1)、第二信号接收端(Cr2)、数据连接端(D)、参考电压端(S)的选择电路(103)；第一信号接收端(Cr1)与第一时序控制器(101)连接，用于接收第一时序控制器(101)输出的电平信号；第二信号接收端(Cr2)与第二时序控制器(102)连接，用于接收第二时序控制器(102)输出的电平信号；数据连接端(D)与数据线(40)连接，用于将其上电平信号输出至数据线(40)；其中，选择电路(103)用于在行扫描阶段选择响应第一时序控制器(101)输出的电平信号，控制参考电压端(S)与数据连接端(D)导通；选择电路(103)用于在相邻两行扫描间隙阶段至少选择响应第二时序控制器(102)输出的电平信号，控制参考电压端(S)与数据连接端(D)导通。

Description

显示驱动电路及显示装置
本申请要求于2022年11月03日提交中国专利局，申请号为2022113662298，申请名称为“显示驱动电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示领域，具体涉及一种显示驱动电路及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着小间距的发展，LED(发光二极管)显示屏对行驱动提出了更高的要求，从单纯的P型MOSFET(金属-氧化物半导体场效应晶体管)实现行切换，到集成度更高，功能更强的多功能行驱动。
目前，在低灰阶(即：低亮)下，LED发光时间较短，寄生电容放电路径的电流不变，导致流过LED的电流占比较小，从而导致LED偏色。
发明内容
本公开提供一种显示驱动电路及显示装置，改善LED在低灰阶下色偏问题，从而提高显示效果。
本公开第一方面提供了一种显示驱动电路，其包括：
第一时序控制器；
第二时序控制器；以及
至少一个选择电路，所述选择电路具有第一信号接收端、第二信号接收端、数据连接端、参考电压端；所述第一信号接收端与所述第一时序控制器连接，用于接收所述第一时序控制器输出的电平信号；所述第二信号接收端与所述第二时序控制器连接，用于接收所述第二时序控制器输出的电平信号；所述数据连接端配置为与数据线连接，用于将其上电平信号输出至所述数据线；
其中，所述选择电路用于在行扫描阶段选择响应所述第一时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端导通；所述选择电路用于在相邻两行扫描间隙 阶段至少选择响应所述第二时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端导通。
本公开第二方面提供了一种显示装置，其包括位于显示区的显示面板、位于非显示区的扫描驱动电路以及上述任一项所述的显示驱动电路，所述显示面板包括多个阵列排布的发光像素、多列数据线和多行扫描线，所述发光像素的第一极与所述扫描线连接，所述扫描线与所述扫描驱动电路连接，所述发光像素的第二极与所述数据线连接，所述数据线与所述显示驱动电路的数据连接端连接。
本公开方案在不影响正常显示的情况下，选择电路利用第二时序控制器输出的信号，使得参考电压端在相邻两行扫描间隙阶段与数据连接端连接，即：在相邻两行扫描间隙阶段，参考电压端的参考电压写入数据线，以使数据线上寄生电容的电荷在本列发光像素(即：此数据线驱动的列发光像素)发亮之前提前释放掉，确保数据连接端的电流总量与经过发光像素的电流相等或基本接近，换言之，保证本列发光像素发亮的电流基本全部经过数据连接端，这样可解决发光像素低灰度色偏的问题，提升显示均一性。
应当理解的是，为了保证发光像素在相邻两行扫描间隙阶段不发光，扫描线提供的电压与参考电压端提供的参考电压差值小于发光像素的阈值电压，以避免影响正常数据显示。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出本公开所描述的显示装置的结构示意简图。
图2示出本公开所描述的扫描驱动电路、显示驱动电路与数据线、扫描线和发光像素的连接关系示意图。
图3示出了图2中所示的显示装置的时序图。
图4示出了本公开实施例一所描述的显示驱动电路的结构框图。
图5示出了本公开实施例一所描述的显示装置的结构示意图。
图6示出了图5中所示的显示装置的时序图。
图7示出了本公开实施例二所描述的显示装置的结构示意图。
图8示出了图7中所示的显示装置的时序图。
本发明的实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。
在本公开中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知方法、装置、实现或者操作以避免模糊本公开的各方面。
实施例一
本公开中提供了一种显示装置，如图1所示，显示装置可包括显示驱动电路10、扫描驱动电路20及显示面板，显示面板可包括多个阵列排布的发光像素30、多列数据线40和多行扫描线50，扫描线50与扫描驱动电路20连接，数据线40与显示驱动电路10的数据连接端连接，且发光像素30的第一极与扫描线50连接，发光像素30的第二极与数据线40连接。
其中，扫描驱动电路20通过扫描线50向发光像素30的第一极写入第一电压，显示驱动电路10通过数据线40向发光像素30的第二极写入第二电压，在发光像素30两端的第一电压与第二电压的差值大于发光像素30的阈值电压时，发光像素30可发光，在发光像素30的第一电压与第二电压的差值小于发光像素30的阈值电压时，发光像素30不发光。
举例而言，本公开实施例的显示面板可为OLED显示、Mini-LED显示或Micro-LED显示，也就是说，此发光像素30可为发光二极管(简称：LED)。
应当理解的是，发光二极管的第一极可为阳极，第二极可为阴极；其中，每行扫描线50对应与一行中各发光二极管的阳极连接，每列数据线40对应与一列中各发光二极管的阴极连接。
其中，当扫描驱动电路20中控制行的数据信号Row为低时，对应的扫描线50上的电压(即LED的阳极电压)就会被拉高，数据线40上所接收到的显示驱动电路的输出数据(可以理解为LED的阴极电压)Out就会得到显示；图2中扫描驱动电路20中连接在扫描线50上的晶体管可为P型晶体管，因此，其响应低电平信号开启，以将对应的扫描线50上的电压拉高。
结合图2和图3所示，扫描驱动电路20中位于第n行扫描线上晶体管的控制端响应数据信号Row(n)，扫描驱动电路20中位于第n+1行扫描线上晶体管的控制端响应数据信号Row(n+1)，扫描驱动电路20中位于第n+2行扫描线上晶体管的控制端响应数据信号Row(n+2)；显示驱动电路10写入至第m列数据线数据信号为Out(m)，显示驱动电路10写入至第m+1列数据线的数据信号为Out(m+1)，显示驱动电路10写入至第m+2列数据线的数据信号为Out(m+2)，其中，数据信号Out为低的宽度不同就会得到不同的LED灯亮度，这个宽度由PWM(脉冲宽度调制信号)控制，而PWM的跨度由GCLK(灰阶时钟)的周期决定。
当扫描驱动电路20中控制行的数据信号Row(n+1)为低时，第n+1行扫描线上的电压就会被拉高，第m列、第m+1列、第m+2列数据线在此阶段对应接收数据信号Out(m)、数据信号Out(m+1)、数据信号Out(m+2)的低电平信号，以使得第n+1行中第m个、第m+1个、第m+2个LED发光，由图3可知，数据信号Out(m)、数据信号Out(m+1)、数据信号Out(m+2)的低电平信号宽度依次增大，即：第n+1行中第m个、第m+1个、第m+2个LED的发光时间依次增长，也就说是，数据信号Out低电平的宽度与LED的发光时间正相关。
其中，在低亮(低灰阶或低灰度)下，LED发光时间较短，寄生电容放电路径的电流不变，导致流过LED的电流占比较小，导致LED偏色；例如：若流过红色LED的电流占比受到的影响比较小，整体偏红；若流过蓝色LED的电流占比受到的影响比较小，整体偏蓝，若流过绿色LED的电流占比绿色受到的影响比较小，整体偏绿。
低灰度因为本身PWM打开的时间比较短，流过LED的电流总量比较小，而显示 驱动电路10的数据连接端(与数据线40连接的端口)的电流由流过LED的电流与数据线40上寄生电容的电流之和组成，相较于高灰度与低灰度的情况，两者电流比列就会不一样，这就造就了寄生电容对R(红)、G(绿)、B(蓝)-LED的影响分别不一样，且低灰度时(一般是指0～31灰阶)寄生电容上的电流对显示的影响就会很明显，显示出来的效果就会有偏色现象；由于经过显示驱动电路10的数据连接端的电流并不是全部经过了LED，还包括了数据线40的寄生电容上的电荷部分，也就是说，低灰度偏色根本原因是，LED发光所需的电流小于流过显示驱动电路10的数据连接端的电流，即：LED的实际亮度并没有达到原本应该的亮度。
为了改善这种情况，本公开实施例对前述提到的显示驱动电路10进行了改进，具体地，如图4所示，本公开实施例的显示驱动电路10可包括第一时序控制器101、第二时序控制器102及选择电路103。
其中，第一时序控制器101用于在正常显示阶段(行扫描阶段)控制发光像素30发光；第二时序控制器102用于在相邻两行扫描间隙阶段控制数据线40上寄生电容的电荷释放。
具体地，如图4所示，选择电路103具有第一信号接收端Cr1、第二信号接收端Cr2、数据连接端D、参考电压端S；第一信号接收端Cr1与第一时序控制器101连接，用于接收第一时序控制器101输出的电平信号；第二信号接收端Cr2与第二时序控制器102连接，用于接收第二时序控制器102输出的电平信号；数据连接端D配置为与数据线40连接，用于将其上电平信号输出至数据线40。
应当理解的是，显示驱动电路10中可包括多个选择电路103，每个选择电路103的数据连接端D对应于一条数据线40连接。图5中仅示出了一个选择电路103与一条数据线40的连接示意图，需要说明的是，其余数据线40也可参考此方式连接有一个选择电路103。此外，图5中，G1、G2、G3为扫描驱动电路20输出至对应行的信号，Out1和Out2为显示驱动电路10输出至对应列的信号。
其中，结合图5和图6所示，选择电路103用于在行扫描阶段(正常显示阶段)A选择响应第一时序控制器101输出的电平信号，控制参考电压端S与数据连接端D导通，以使得参考电压端S上的电压Vl通过数据连接端D写入到发光像素30的第二极，从而使得发光像素30的第一极与第二极之间的电压差大于发光像素30的阈值电压，使得此发光像素30发光显示。应当理解的是，发光像素30的阈值电压通常大于0。
举例而言，如图6所示，在行扫描阶段A，对应行扫描线50接收的电压为高电平电压，参考电压端S向数据线40提供的电压(例如：Out2)为低电平电压，使得发光像素30的两端形成大于其阈值电压的压差，实现正常发光显示。
选择电路103用于在相邻两行扫描间隙阶段B至少选择响应第二时序控制器102输出的电平信号，控制参考电压端S与数据连接端D导通，以使得参考电压端S上的电压通过数据连接端D写入到发光像素30的第二极，如图6中的B1阶段，以使数据线40上寄生电容的电荷在本列发光像素(即：此数据线40驱动的列发光像素)发亮之前提前释放掉，即：在相邻两行扫描间隙阶段B释放掉，确保数据连接端D的电流总量与经过发光像素30的电流相等或基本接近，换言之，保证本列发光像素30发亮的电流基本全部经过数据连接端D，这样可解决发光像素30低灰度色偏的问题，提升显示均一性。
应当理解的是，为了保证发光像素30在相邻两行扫描间隙阶段B不发光，扫描线50接收的电压与参考电压端S提供的参考电压差值应当小于发光像素30的阈值电压，以避免影响正常数据显示。
举例而言，在相邻两行扫描间隙阶段B阶段，G2为低电平，也就是说，对应行扫描线50接收的电压为低电平电压，在此阶段，Out2在B1阶段的电压为参考电压端S向对应数据线40提供的低电平电压，在B2阶段的电位为数据线40对应的消隐电压，这样使得发光像素30两极的压差等于0(在B1阶段)或小于0(在B2阶段)，由于发光像素的阈值为大于0，因此，发光像素30在相邻两行扫描间隙阶段B不发光。
此外，还需要说明的是，本实施例的相邻两行扫描间隙阶段B指的是在完成第n行扫描之后且在开始第n+1行扫描之前这一阶段。
在一可选实施方案中，选择电路103用于在相邻两行扫描间隙阶段B的部分时间段(例如：图6中的B1时间段)选择响应第二时序控制器102输出的电平信号，控制参考电压端S与数据连接端D，也就是说，数据线40上寄生电容的电荷释放时长小于相邻两行扫描间隙时长，这样相比于利用整个相邻两行扫描间隙时长来实现电荷释放的方案，本方案在实现数据线40上寄生电容的电荷释放以改善发光像素色偏情况的同时，还可降低控制精度，减少出现误点亮的情况。
进一步地，可将相邻两行扫描间隙阶段B划分呈至少两个时间段，例如：如图6所示，相邻两行扫描间隙阶段B至少包括依次设置的第一时间段B1和第二时间段B2。其中，选择电路103用于在第一时间段B1选择响应第二时序控制器102输出的第一 电平信号，控制参考电压端S与数据连接端D导通，此时，第一时间段B1对应为释放数据线40上寄生电容电荷的阶段；而选择电路103还用于在第二时间段B2选择响应第二时序控制器102输出的第二电平信号，控制参考电压端S与数据连接端D断开，此时，数据线40上的电压为消隐电压，此阶段为电荷释放阶段与下一行发光阶段之间的过渡时间段，这样设计保证在相邻两行扫描间隙之间尽早完成数据线40上电荷的释放，避免电荷释放不完全导致色偏仍存在的情况。
应当理解的是，第二时序控制器102在相邻两行扫描间隙阶段B的第一时间段B1和第二时间段B2输出的电平信号不同，即：第二时序控制器102在第一时间段B1输出的第一电平信号和在第二时间段B2输出的第二电平信号中的一者为高电平信号，另一者为低电平信号，可根据选择电路103的具体结构选择。
应当理解的是，第一时序控制器101输出的控制信号不受第二时序控制器102的影响，只需要根据具体显示要求控制输出即可，在正常行扫描显示阶段(即：行扫描阶段)，选择电路103则会正常响应第一时序控制101输出的电平信号将参考电压端S的参考电压经数据连接端D写入至数据线40。
在一具体实施方案中，第二时序控制器102能够基于显示参数信息调整第一电平信号在相邻两行扫描间隙阶段B的输出时长，即：调整相邻两行扫描间隙阶段B的第一时间段B1时长，从而调整数据线40上寄生电容的电荷释放时长。需要说明的是，此显示参数信息可包括色偏等参数。
比如：在检测到的显示画面仍存在色偏时，可能是数据线40上寄生电容的电荷没释放干净，第二时序控制器102增加第一电平信号在相邻两行扫描间隙阶段B的输出时长，即：增加相邻两行扫描间隙阶段B中第一时间段B1的时长，使得数据线40上寄生电容电荷得以充分释放，从而改善色偏情况。
在本公开的实施例中，如图5所示，选择电路103包括或门Or和开关晶体管T；其中，或门Or具有前述提到的第一信号接收端Cr1、第二信号接收端Cr2及信号输出端；开关晶体管T的控制端与或门Or的信号输出端连接，开关晶体管T的第一端与数据连接端D连接，开关晶体管T的第二端与参考电压端S连接，此选择电路103的结构简单，便于电路设计节省空间，降低成本。
举例而言，此开关晶体管T可为N型晶体管，在相邻两行扫描间隙阶段B，第一时序控制器101输出至第一信号接收端Cr1的电平信号为低电平信号，第二时序控制器102输出至第二信号接收端Cr2的电平信号为高电平信号，则或门Or输出至开关 晶体管T的控制信号为高电平信号，以使开关晶体管T的第一端与第二端导通，即：使得参考电压端S与数据连接端D连接，从而使得参考电压端S输出的参考电压经数据连接端D写入至数据线40上，从而实现数据线40上寄生电容的电荷释放。
具体地，在相邻两行扫描间隙阶段B包括前述提到的第一时间段B1和第二时间段B2时，第二时序控制器102在第一时间段B1输出的第一电平信号则为高电平信号，在第二时间段B2输出的第二电平信号为低电平信号。
应当理解的是，在行扫描阶段A，第一时序控制器101输出的电平信号为高电平信号，第二时序控制器102输出的电平信号不作限制，可以为高电平信号，也可为低电平信号。
其中，开关晶体管T不限于为N型晶体管，也可为P型晶体管，只需要对应调整第一时序控制器101和第二时序控制器102输出的电平信号即可，在此不作过多限定。
在本实施例中，参考电压端S在行扫描阶段A提供的参考电压与在相邻行扫描间隙阶段提供的参考电压可相等，参考图5和图6所示，简化结构，降低成本。
实施例二
本实施例二与实施例一的主要区别在于选择电路103的具体架构不同，其余结构可参考实施例一，在此不作重复赘述。
在本实施例中，如图7所示，参考电压端包括第一参考电压端S1和第二参考电压端S2；且选择电路103除了包括前述提到的第一信号接收端Cr1、第二信号接收端Cr2、数据连接端D、参考电压端S之外，选择电路103还可包括第一晶体管T1、第二晶体管T2、第三晶体管T3及第四晶体管T4。
其中，第一晶体管T1、第三晶体管T3和第四晶体管T4的控制端均与第二信号接收端Cr2连接；第一晶体管T1的第一端与第一信号接收端Cr1连接，第一晶体管T1的第二端与第二晶体管T2的控制端连接；第二晶体管T2的第一端与数据连接端D连接，第二晶体管T2的第二端与第一参考电压端S1连接；第三晶体管T3的第一端与数据连接端D连接，第三晶体管T3第二端与第二参考电压端S2连接；第四晶体管T4的第一端与第二晶体管T2的控制端连接，第四晶体管T4的第二端与第一参考电压端S1连接。
本实施例中，第一晶体管T1为第一类型晶体管，第二晶体管T2、第三晶体管T3及第四晶体管T4均为第二类型晶体管，第一类型晶体管和第二类型晶体管中的一者为P型晶体管，另一者为N型晶体管。
以第一晶体管T1为P型晶体管，第二晶体管T2、第三晶体管T3及第四晶体管T4为N型晶体管为例进行说明。
在正常显示阶段(即：在行扫描阶段A)，第二时序控制器102向第二信号接收端Cr2输出的电平信号为低电平信号，这时候第三晶体管T3和第四晶体管T4关闭，第一晶体管T1打开，第一时序控制器101向第一信号接收端Cr1输出电平信号以控制第二晶体管T2的开关；在第一时序控制器101向第一信号接收端Cr1输出的电平信号为高电平信号时，第二晶体管T2打开，第一参考电压端S1将其参考电压经数据连接端D写入至数据线40，即：数据线40上的电压等于第一参考电压端S1处的参考电压(如图8中所示V1)，在第一时序控制器101向第一信号接收端Cr1输出的电平信号为低电平信号时，第二晶体管T2关闭，数据线40的电压等于列默认电压(可理解为消隐电压)。
当行与行切换的时间段(即：相邻两行扫描间隙阶段B)，第二时序控制器102向第二信号接收端Cr2输出的电平信号为高电平信号，此时，第三晶体管T3、第四晶体管T4打开，第一晶体管T1关闭；因为，第二晶体管T2的栅极与源极(控制端与第二端)的电压均为第一参考电压端S1提供的电压，即：第二晶体管T2的栅极与源极之间的压差Vgs＝0，小于第二晶体管T2的阈值电压Vth，则第二晶体管T2关闭；可知，此时，数据线40上的电压等于第二参考电压端S2提供的参考电压(如图8中所示V2)。应当理解的是，数据线40上写入的第二参考电压端S2提供的参考电压并不影响正常显示阶段。
本实施例的选择电路103采用此种设计可使得数据线40在行扫描阶段A和相邻两行扫描间隙阶段B写入的参考电压可以不同，也可相同，可根据实际情况调整匹配，更加灵活。
举例而言，在本实施例中，第一参考电压端S1与第二参考电压端S2提供的电压不相等，具体地，第二参考电压端S2提供的电压V2介于数据线40的消隐电压与第一参考电压端S1提供的参考电压V1之间，这样可在降低损耗的同时，还可对发光像素30进行保护。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例 中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (17)

  1. 一种显示驱动电路，包括：
    第一时序控制器；
    第二时序控制器；以及
    至少一个选择电路，所述选择电路具有第一信号接收端、第二信号接收端、数据连接端、参考电压端；所述第一信号接收端与所述第一时序控制器连接，用于接收所述第一时序控制器输出的电平信号；所述第二信号接收端与所述第二时序控制器连接，用于接收所述第二时序控制器输出的电平信号；所述数据连接端配置为与数据线连接，用于将其上电平信号输出至所述数据线；
    其中，所述选择电路用于在行扫描阶段选择响应所述第一时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端导通；所述选择电路用于在相邻两行扫描间隙阶段至少选择响应所述第二时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端导通。
  2. 根据权利要求1所述的显示驱动电路，其中，所述选择电路用于在相邻两行扫描间隙阶段的部分时间段选择响应所述第二时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端。
  3. 根据权利要求2所述的显示驱动电路，其中，所述相邻两行扫描间隙阶段包括依次设置的第一时间段和第二时间段；
    所述选择电路用于在所述第一时间段选择响应所述第二时序控制器输出的第一电平信号，控制所述参考电压端与所述数据连接端导通；所述选择电路用于在所述第二时间段选择响应所述第二时序控制器输出的第二电平信号，控制所述参考电压端与所述数据连接端断开；
    所述第一电平信号和所述第二电平信号中的一者为高电平信号，另一者为低电平信号。
  4. 根据权利要求3所述的显示驱动电路，其中，所述第二时序控制器能够基于显示参数信息调整所述第一电平信号在所述相邻两行扫描间隙阶段的输出时长。
  5. 根据权利要求1所述的显示驱动电路，其中，所述选择电路包括或门和开关晶体管；
    所述或门具有所述第一信号接收端、所述第二信号接收端及信号输出端；
    所述开关晶体管的控制端与所述信号输出端连接，所述开关晶体管的第一端与所 述数据连接端连接，所述开关晶体管的第二端与所述参考电压端连接；
    其中，所述开关晶体管为N型晶体管或P型晶体管。
  6. 根据权利要求4所述的显示驱动电路，其中，所述参考电压端在行扫描阶段提供的参考电压与在相邻行扫描间隙阶段提供的参考电压相等。
  7. 根据权利要求2所述的显示驱动电路，其中，所述参考电压端包括第一参考电压端和第二参考电压端；其中，
    所述选择电路包括第一晶体管、第二晶体管、第三晶体管及第四晶体管；
    所述第一晶体管、所述第三晶体管和所述第四晶体管的控制端均与所述第二信号接收端连接；
    所述第一晶体管的第一端与所述第一信号接收端连接，第二端与所述第二晶体管的控制端连接；
    所述第二晶体管的第一端与所述数据连接端连接，第二端与所述第一参考电压端连接；
    所述第三晶体管的第一端与所述数据连接端连接，第二端与所述第二参考电压端连接；
    所述第四晶体管的第一端与所述第二晶体管的控制端连接，第二端与所述第一参考电压端连接；
    其中，所述第一晶体管为第一类型晶体管，所述第二至第四晶体管均为第二类型晶体管，所述第一类型晶体管和所述第二类型晶体管中的一者为P型晶体管，另一者为N型晶体管。
  8. 根据权利要求7所述的显示驱动电路，其中，所述第一参考电压端与所述第二参考电压端提供的电压不相等，且所述第二参考电压端提供的电压介于所述数据线的消隐电压与所述第一参考电压端提供的参考电压之间。
  9. 一种显示装置，包括显示面板、扫描驱动电路以及显示驱动电路，所述显示驱动电路包括：
    第一时序控制器；
    第二时序控制器；以及
    至少一个选择电路，所述选择电路具有第一信号接收端、第二信号接收端、数据连接端、参考电压端；所述第一信号接收端与所述第一时序控制器连接，用于接收所述第一时序控制器输出的电平信号；所述第二信号接收端与所述第二时序控制器连 接，用于接收所述第二时序控制器输出的电平信号；所述数据连接端配置为与数据线连接，用于将其上电平信号输出至所述数据线；其中，所述选择电路用于在行扫描阶段选择响应所述第一时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端导通；所述选择电路用于在相邻两行扫描间隙阶段至少选择响应所述第二时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端导通；
    所述显示面板包括多个阵列排布的发光像素、多列数据线和多行扫描线，所述发光像素的第一极与所述扫描线连接，所述扫描线与所述扫描驱动电路连接，所述发光像素的第二极与所述数据线连接，所述数据线与所述显示驱动电路的数据连接端连接。
  10. 根据权利要求9所述的显示装置，其中，所述发光像素为发光二极管，所述第一极为阳极，所述第二极为阴极；
    其中，每行所述扫描线对应与一行中各所述发光二极管的阳极连接，每列所述数据线对应与一列中各所述发光二极管的阴极连接。
  11. 根据权利要求9所述的显示装置，其中，所述选择电路用于在相邻两行扫描间隙阶段的部分时间段选择响应所述第二时序控制器输出的电平信号，控制所述参考电压端与所述数据连接端。
  12. 根据权利要求11所述的显示装置，其中，所述相邻两行扫描间隙阶段包括依次设置的第一时间段和第二时间段；
    所述选择电路用于在所述第一时间段选择响应所述第二时序控制器输出的第一电平信号，控制所述参考电压端与所述数据连接端导通；所述选择电路用于在所述第二时间段选择响应所述第二时序控制器输出的第二电平信号，控制所述参考电压端与所述数据连接端断开；
    所述第一电平信号和所述第二电平信号中的一者为高电平信号，另一者为低电平信号。
  13. 根据权利要求12所述的显示装置，其中，所述第二时序控制器能够基于显示参数信息调整所述第一电平信号在所述相邻两行扫描间隙阶段的输出时长。
  14. 根据权利要求9所述的显示装置，其中，所述选择电路包括或门和开关晶体管；
    所述或门具有所述第一信号接收端、所述第二信号接收端及信号输出端；
    所述开关晶体管的控制端与所述信号输出端连接，所述开关晶体管的第一端与所 述数据连接端连接，所述开关晶体管的第二端与所述参考电压端连接；
    其中，所述开关晶体管为N型晶体管或P型晶体管。
  15. 根据权利要求13所述的显示装置，其中，
    所述参考电压端在行扫描阶段提供的参考电压与在相邻行扫描间隙阶段提供的参考电压相等。
  16. 根据权利要求11所述的显示装置，其中，所述参考电压端包括第一参考电压端和第二参考电压端；其中，
    所述选择电路包括第一晶体管、第二晶体管、第三晶体管及第四晶体管；
    所述第一晶体管、所述第三晶体管和所述第四晶体管的控制端均与所述第二信号接收端连接；
    所述第一晶体管的第一端与所述第一信号接收端连接，第二端与所述第二晶体管的控制端连接；
    所述第二晶体管的第一端与所述数据连接端连接，第二端与所述第一参考电压端连接；
    所述第三晶体管的第一端与所述数据连接端连接，第二端与所述第二参考电压端连接；
    所述第四晶体管的第一端与所述第二晶体管的控制端连接，第二端与所述第一参考电压端连接；
    其中，所述第一晶体管为第一类型晶体管，所述第二至第四晶体管均为第二类型晶体管，所述第一类型晶体管和所述第二类型晶体管中的一者为P型晶体管，另一者为N型晶体管。
  17. 根据权利要求16所述的显示装置，其中，所述第一参考电压端与所述第二参考电压端提供的电压不相等，且所述第二参考电压端提供的电压介于所述数据线的消隐电压与所述第一参考电压端提供的参考电压之间。
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