WO2024087851A1 - 两级差分功率放大器及射频功放模组 - Google Patents

两级差分功率放大器及射频功放模组 Download PDF

Info

Publication number
WO2024087851A1
WO2024087851A1 PCT/CN2023/115050 CN2023115050W WO2024087851A1 WO 2024087851 A1 WO2024087851 A1 WO 2024087851A1 CN 2023115050 W CN2023115050 W CN 2023115050W WO 2024087851 A1 WO2024087851 A1 WO 2024087851A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
power unit
stage
driving
final
Prior art date
Application number
PCT/CN2023/115050
Other languages
English (en)
French (fr)
Inventor
许靓
郭嘉帅
Original Assignee
深圳飞骧科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳飞骧科技股份有限公司 filed Critical 深圳飞骧科技股份有限公司
Publication of WO2024087851A1 publication Critical patent/WO2024087851A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to the technical field of signal processing, and in particular to a two-stage differential power amplifier and a radio frequency power amplifier module.
  • 5G-NR is a global 5G standard based on a new OFDM aperture design.
  • the N77 and N79 bands are higher frequency bands than the Sub-3G bands. Therefore, they decay relatively quickly during propagation, the path loss is relatively large, and the coverage of a single carrier is limited. Therefore, in order to improve user experience and reduce base station construction costs, 3GPP has defined a new power standard, Power Class 2 (PC2), which means that the output power of wireless terminal equipment is increased by 3dB based on the original Power Class 3 (PC3).
  • PC2 Power Class 2
  • PC3 Power Class 3
  • the reason why the circuit gain effect of the two-stage differential power amplifier is low is that the first final power unit and the second final power unit in the circuit structure of the two-stage differential power amplifier usually work in class AB, and the heterojunction bipolar transistor (Heterojunction bipolar The base-collector capacitance (Cbc) of the high-pass transistor (HBT) provides a feedback path during operation, which will cause the gain effect of the two-stage differential power amplifier to be significantly reduced as the operating frequency increases.
  • Cbc base-collector capacitance of the high-pass transistor
  • the object of the present invention is to provide a two-stage differential power amplifier and a radio frequency power amplifier module to solve the problem of low circuit gain effect of the existing two-stage differential power amplifier.
  • the present invention provides a two-stage differential power amplifier, comprising a signal input terminal, a driving stage power unit, an amplifying stage differential power unit, an output synthesis unit and a signal output terminal connected in sequence;
  • the driving stage power unit is used to amplify the single-ended signal received by the signal input end and then output it;
  • the amplifying stage differential power unit is used to receive the single-ended signal amplified by the driving stage power unit, and convert it into two differential signals and then amplify them respectively and then output them;
  • the output synthesis unit is used to synthesize the two differential signals converted and amplified by the amplifying stage differential power unit into a single-ended signal and then output it to the signal output end;
  • the amplifier stage differential power unit includes a differential unit, a first final stage power unit, a second final stage power unit, a first capacitor and a second capacitor; the first capacitor is connected in series between the input end of the first final stage power unit and the output end of the second final stage power unit, and the second capacitor is connected in series between the input end of the second final stage power unit and the output end of the first final stage power unit.
  • the amplifier stage differential power unit also includes a first resistor and a second resistor; the first resistor is connected in series between the input end of the first final stage power unit and the first capacitor, and the second resistor is connected in series between the input end of the second final stage power unit and the second capacitor.
  • the output synthesis unit includes a first transformer, a third capacitor, a fourth capacitor and a fifth capacitor;
  • the first transformer includes a first primary coil and a first secondary coil.
  • the first end of the first primary coil serves as the first input end of the output synthesis unit to be connected to the output end of the first final power unit
  • the second end of the first primary coil serves as the second input end of the output synthesis unit to be connected to the output end of the second final power unit
  • the first end of the first secondary coil serves as the output end of the output synthesis unit to be connected to the signal output end;
  • a first end of the third capacitor is connected to the middle tap of the first primary coil, and a second end of the third capacitor is grounded;
  • a first end of the fourth capacitor is connected to the middle tap of the first primary coil, and a second end of the fourth capacitor is grounded;
  • a first end of the fifth capacitor is connected to the second end of the first secondary coil, and a second end of the fifth capacitor is grounded.
  • the output synthesis unit further includes a sixth capacitor and a third resistor; the sixth capacitor is connected in parallel between the first end and the second end of the first primary coil, and the third resistor is also connected in parallel between the first end and the second end of the first primary coil.
  • the output synthesis unit further includes a resonant circuit connected to the first end of the first secondary coil.
  • the resonant circuit includes a seventh capacitor and an inductor; the first end of the seventh capacitor is connected to the first end of the first secondary coil, the first end of the inductor is connected to the second end of the seventh capacitor, and the second end of the inductor is grounded.
  • the differential unit includes a second transformer, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor;
  • the second transformer comprises a second primary coil and a second secondary coil, wherein a first end of the second primary coil serves as an input end of the amplifier stage differential power unit to be connected to an output end of the driver stage power unit;
  • a first end of the eighth capacitor is connected to the first end of the second primary coil, and a second end of the eighth capacitor is grounded;
  • a first end of the ninth capacitor is connected to the second end of the second primary coil, and a second end of the ninth capacitor is grounded;
  • a first end of the tenth capacitor is connected to a second end of the second primary coil, and a second end of the tenth capacitor is grounded;
  • a first end of the eleventh capacitor is connected to a middle tap of the second secondary coil, and a second end of the eleventh capacitor is grounded;
  • An input end of the first final stage power unit is connected to a first end of the second secondary coil, and an input end of the second final stage power unit is connected to a second end of the second secondary coil.
  • the differential unit further includes a fourth resistor; the fourth resistor is connected in parallel to the first end and the second end of the second primary coil.
  • the driving stage power unit includes a driving transistor, a driving capacitor and a driving resistor;
  • the base of the driving transistor serves as the input end of the driving stage power unit to be connected to the signal input end, the emitter of the driving transistor is grounded, the collector of the driving transistor serves as the output end of the driving stage power unit to be connected to the input end of the amplifier stage differential power unit, the driving capacitor is connected in series between the base of the driving transistor and the signal input end, the first end of the driving resistor is connected to the first bias circuit, and the second end of the driving resistor is connected to the base of the driving transistor;
  • the circuit structure of the first final-stage power unit is the same as that of the driving-stage power unit; in the first final-stage power unit: the base of the driving transistor serves as the input end of the first final-stage power unit to be connected to the first end of the second secondary coil, the emitter of the driving transistor is grounded, the collector of the driving transistor serves as the output end of the first final-stage power unit to be connected to the first input end of the output synthesis unit, the driving capacitor is connected in series between the base of the driving transistor and the first end of the second secondary coil, the first end of the driving resistor is connected to the second bias circuit, and the second end of the driving resistor is connected to the base of the driving transistor;
  • the circuit structure of the second final-stage power unit is the same as that of the driving-stage power unit; in the second final-stage power unit: the base of the driving transistor serves as the input end of the second final-stage power unit to be connected to the second end of the second secondary coil, The emitter of the driving transistor is grounded, the collector of the driving transistor serves as the output end of the second final-stage power unit to be connected to the second input end of the output synthesis unit, the driving capacitor is connected in series between the base of the driving transistor and the second end of the second secondary coil, the first end of the driving resistor is connected to the third bias circuit, and the second end of the driving resistor is connected to the base of the driving transistor.
  • the present invention provides a radio frequency power amplifier module, which includes the two-stage differential power amplifier as described above.
  • the two-stage differential power amplifier of the present invention adds the first capacitor between the input end of the first final-stage power unit and the output end of the second final-stage power unit, and adds the second capacitor between the input end of the second final-stage power unit and the output end of the first final-stage power unit, so that the two-way RF differential signal amplified by the first final-stage power unit and the second final-stage power unit can be supplemented to the output synthesis unit of the other way, thereby reducing the influence of its base-collector capacitance on the first final-stage power unit and the second final-stage power unit, thereby improving the circuit gain effect of the two-stage differential power amplifier.
  • FIG1 is a circuit diagram of a two-stage differential power amplifier provided by an embodiment of the present invention.
  • An embodiment of the present invention provides a two-stage differential power amplifier 100, which includes a signal input terminal RFin, a driving stage power unit 2, an amplifying stage differential power unit 3, an output synthesis unit 4 and a signal output terminal RFout connected in sequence as shown in FIG. 1 .
  • the driving stage power unit 2 is used to amplify a single-ended signal received by the signal input terminal RFin and output it;
  • the amplifier stage differential power unit 3 is used to receive a single-ended signal amplified by the driving stage power unit 2, and convert it into two differential signals and then amplify them respectively and output them;
  • the output synthesis unit 4 is used to synthesize the two differential signals converted and amplified by the amplifier stage differential power unit 3 into a single-ended signal and output it to the signal output terminal RFout.
  • the amplifier stage differential power unit 3 includes a differential unit 31, a first final stage power unit 32, a second final stage power unit 33, a first capacitor C04 and a second capacitor CO5; the first capacitor C04 is connected in series between the input end of the first final stage power unit 32 and the output end of the second final stage power unit 33, and the second capacitor CO5 is connected in series between the input end of the second final stage power unit 33 and the output end of the first final stage power unit 32.
  • the driving stage power unit 2 includes a driving transistor (not labeled in the figure), a driving capacitor (not labeled in the figure) and a driving resistor (not labeled in the figure).
  • the base of the driving transistor serves as the input end of the driving stage power unit 2 to be connected to the signal input end RFin, the emitter of the driving transistor is grounded, the collector of the driving transistor serves as the output end of the driving stage power unit 2 to be connected to the input end of the amplifier stage differential power unit 3, the driving capacitor is connected in series between the base of the driving transistor and the signal input end RFin, the first end of the driving resistor is connected to the first bias circuit 5, and the second end of the driving resistor is connected to the base of the driving transistor.
  • the amplifier stage differential power unit 3 further includes a first resistor R02 and a second resistor R03; the first resistor R02 is connected in series to the input end of the first final stage power unit 32 and the first The second resistor R03 is connected in series between the input end of the second final power unit 33 and the second capacitor CO5.
  • the first resistor R02 and the first capacitor C04 can form a first RC series circuit (RC filter, RC network or phase shift circuit), and the second resistor R03 and the second capacitor CO5 can form a second RC series circuit. These two RC series circuits can attenuate out-of-band signals.
  • the differential unit 31 includes a second transformer TF1 , an eighth capacitor C01 , a ninth capacitor C02 , a tenth capacitor C10 , and an eleventh capacitor C03 .
  • the second transformer TF1 includes a second primary coil and a second secondary coil.
  • the first end of the second primary coil serves as the input end of the amplifier stage differential power unit 3 to be connected to the output end of the driving stage power unit 2, that is, the first end of the second primary coil is connected to the collector of the driving transistor in the driving stage power unit 2.
  • a first end of the eighth capacitor C01 is connected to a first end of the second primary coil, and a second end of the eighth capacitor C01 is grounded; a first end of the ninth capacitor C02 is connected to a second end of the second primary coil, and a second end of the ninth capacitor C02 is grounded; a first end of the tenth capacitor C10 is connected to a second end of the second primary coil, and a second end of the tenth capacitor C10 is grounded; a first end of the eleventh capacitor C03 is connected to a middle tap of the second secondary coil, and a second end of the eleventh capacitor C03 is grounded.
  • the second end of the second primary coil is also connected to the first supply voltage VCC1.
  • An input end of the first final stage power unit 32 is connected to a first end of the second secondary coil, and an input end of the second final stage power unit 33 is connected to a second end of the second secondary coil.
  • the differential unit 31 further includes a fourth resistor R01 which is connected in parallel to the first and second ends of the second primary coil and can improve the isolation between the two balanced ports of the second transformer TF1 (the first and second ends of the second primary coil).
  • the circuit structure of the first final stage power unit 32 is the same as that of the driving stage power unit 2 ; the circuit structure of the second final stage power unit 33 is also the same as that of the driving stage power unit 2 .
  • the base of the driving transistor serves as the input end of the first final stage power unit 32 to be connected to the first end of the second secondary coil, the emitter of the driving transistor is grounded, the collector of the driving transistor serves as the output end of the first final stage power unit 32 to be connected to the first input end of the output synthesis unit 4, the driving capacitor is connected in series between the base of the driving transistor and the first end of the second secondary coil, the first end of the driving resistor is connected to the second bias circuit 6, and the second end of the driving resistor is connected to the base of the driving transistor.
  • the base of the driving transistor serves as the input end of the second final stage power unit 33 to be connected to the second end of the second secondary coil, the emitter of the driving transistor is grounded, the collector of the driving transistor serves as the output end of the second final stage power unit 33 to be connected to the second input end of the output synthesis unit 4, the driving capacitor is connected in series between the base of the driving transistor and the second end of the second secondary coil, the first end of the driving resistor is connected to the third bias circuit 7, and the second end of the driving resistor is connected to the base of the driving transistor.
  • the output synthesis unit 4 includes a first transformer TF2, a third capacitor CO7, a fourth capacitor C11 and a fifth capacitor C08.
  • the first transformer TF2 includes a first primary coil and a first secondary coil.
  • the first end of the first primary coil serves as the first input end of the output synthesis unit 4 to be connected to the output end of the first final stage power unit 32.
  • the second end of the first primary coil serves as the second input end of the output synthesis unit 4 to be connected to the output end of the second final stage power unit 33.
  • the first end of the first secondary coil serves as the output end of the output synthesis unit 4 to be connected to the signal output end RFout.
  • the center tap of the first primary coil is also connected to the second supply voltage VCC2.
  • a first end of the third capacitor CO7 is connected to the middle tap of the first primary coil, and a second end of the third capacitor CO7 is grounded; a first end of the fourth capacitor C11 is connected to the middle tap of the first primary coil, and a second end of the fourth capacitor C11 is grounded; a first end of the fifth capacitor C08 is connected to the second end of the first secondary coil, and a second end of the fifth capacitor C08 is grounded.
  • the output synthesis unit 4 further includes a sixth capacitor 06 and a third resistor R04; the sixth capacitor 06 is connected in parallel between the first end and the second end of the first primary coil, and the third resistor R04 is also connected in parallel between the first end and the second end of the first primary coil.
  • the first transformer TF2 At two balanced ports of the first transformer TF2 (the first end of the first primary coil and the The sixth capacitor O6 and the third resistor R04 forming an RC parallel circuit are introduced into the second terminal of the first transformer TF2, so that the isolation between the two balanced ports of the first transformer TF2 can be improved.
  • the output synthesis unit 4 also includes a resonant circuit connected to the first end of the first secondary coil; the resonant circuit includes a seventh capacitor C09 and an inductor L01; the first end of the seventh capacitor C09 is connected to the first end of the first secondary coil, the first end of the inductor L01 is connected to the second end of the seventh capacitor C09, and the second end of the inductor L01 is grounded.
  • the second-order filtering of the main frequency can be suppressed, and the impedance of the two balanced ports of the first transformer TF2 can be adjusted through the seventh capacitor C09.
  • the principle of improving the circuit gain effect of the two-stage differential power amplifier 100 is as follows: a first capacitor C04 and a second capacitor CO5 (cross-coupling capacitor) are introduced between the first final-stage power unit 32 and the second final-stage power unit 33, so that two differential signals with completely opposite phases after being amplified by the first final-stage power unit 32 and the second final-stage power unit 33 can be compensated to the output synthesis unit 4 of the other path, that is, the cross-coupling capacitors introduce the effect of negative capacitance relative to the base nodes corresponding to the first final-stage power unit 32 and the second final-stage power unit 33, thereby neutralizing the influence of the base-collector capacitance (Cbc).
  • a first capacitor C04 and a second capacitor CO5 cross-coupling capacitor
  • the two-stage differential power amplifier 100 in this embodiment further includes an input matching circuit 1 connected in series between the signal input terminal RFin and the input terminal of the driving stage power unit 2 .
  • connections are all electrical connections or electrical connections, that is, the way two devices or multiple devices are connected is all electrical connection or electrical connection.
  • the two-stage differential power amplifier 100 of the present invention adds a first capacitor C04 between the input end of the first final-stage power unit 32 and the output end of the second final-stage power unit 33, and adds a second capacitor CO5 between the input end of the second final-stage power unit 33 and the output end of the first final-stage power unit 32, so that the two-way RF differential signal amplified by the first final-stage power unit 32 and the second final-stage power unit 33 can be supplemented to the output synthesis unit 4 of the other way, thereby reducing the influence of its base-collector capacitance on the first final-stage power unit 32 and the second final-stage power unit 33, thereby improving the circuit gain effect of the two-stage differential power amplifier 100.
  • the present invention further provides another embodiment, a radio frequency power amplifier module, which includes the two-stage differential power amplifier 100 in the above embodiment.
  • the RF power amplifier module in this embodiment includes the two-stage differential power amplifier 100 in the above embodiment, it can also achieve the technical effect achieved by the two-stage differential power amplifier 100 in the above embodiment, which will not be elaborated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

一种两级差分功率放大器（100）及射频功放模组，其中，两级差分功率放大器（100）包括依次连接的信号输入端（RFin）、驱动级功率单元（2）、放大级差分功率单元（3）、输出合成单元（4）以及信号输出端（RFout）；放大级差分功率单元（3）包括差分单元（31）、第一末级功率单元（32）、第二末级功率单元（33）、第一电容（C04）和第二电容（C05）。两级差分功率放大器（100）可以减少基极-集电极电容对第一末级功率单元（32）和第二末级功率单元（33）的影响，从而提升两级差分功率放大器（100）的电路增益效果。

Description

两级差分功率放大器及射频功放模组 【技术领域】
本发明涉及信号处理技术领域，尤其涉及一种两级差分功率放大器及射频功放模组。
【背景技术】
5G-NR是一种基于OFDM的全新孔口设计的全球性5G标准，其中，N77频段和N79频段相对Sub-3G频段属于较高的频段，因此，在传播过程中其衰减得相对较快，路径的损失也相对较大，单载波覆盖的范围也有限。所以，为了提升用户体验，同时减小基站建设成本，3GPP定义了一种全新的功率标准Power Class2(PC2)，即无线终端设备在原有的Power Class3(PC3)的基础上，输出功率提升了3dB。
当无线终端设备的输出功率提升至PC2后，其便可以在补偿更高TDD频率的情况下降低传播损耗，并且降低基站建设的成本，这对于用户体验和降低成本而言，是一个双赢的局面。
但现有两级差分功率放大器的电路结构工作在5G-NR的高频段时(N77频段或N79频段及更高的毫米波频段)，其电路整体的增益效果都普遍表现较低，很难满足当前无线系统对射频功率放大器的应用需求。
而两级差分功率放大器的电路增益效果表现较低的原理为：两级差分功率放大器的电路结构中第一末级功率单元和第二末级功率单元通常工作在AB类，异质结双极型晶体管(Heterojunction bipolar  transistor，简称为HBT)的基极-集电极电容(Cbc)在工作中提供了反馈路径，其随着工作频率的增加，便会引起两级差分功率放大器的增益效果明显降低。
【发明内容】
本发明的目的在于提供一种两级差分功率放大器及射频功放模组，以解决现有两级差分功率放大器的电路增益效果较低的问题。
第一方面，本发明提供了一种两级差分功率放大器，包括依次连接的信号输入端、驱动级功率单元、放大级差分功率单元、输出合成单元以及信号输出端；
所述驱动级功率单元用于将所述信号输入端接收的一路单端信号进行放大后输出；所述放大级差分功率单元用于接收经所述驱动级功率单元放大后的一路所述单端信号，并将其转换为两路差分信号后分别进行放大后输出；所述输出合成单元用于将经所述放大级差分功率单元转换并放大后的两路所述差分信号合成一路单端信号后输出至所述信号输出端；
所述放大级差分功率单元包括差分单元、第一末级功率单元、第二末级功率单元、第一电容和第二电容；所述第一电容串联至所述第一末级功率单元的输入端和所述第二末级功率单元的输出端之间，所述第二电容串联至所述第二末级功率单元的输入端和所述第一末级功率单元的输出端之间。
更优的，所述放大级差分功率单元还包括第一电阻和第二电阻；所述第一电阻串联至所述第一末级功率单元的输入端和所述第一电容之间，所述第二电阻串联至所述第二末级功率单元的输入端和所述第二电容之间。
更优的，所述输出合成单元包括第一变压器、第三电容、第四电容以及第五电容；
所述第一变压器包括第一初级线圈和第一次级线圈，所述第一初 级线圈的第一端作为所述输出合成单元的第一输入端，以与所述第一末级功率单元的输出端连接，所述第一初级线圈的第二端作为所述输出合成单元的第二输入端，以与所述第二末级功率单元的输出端连接，所述第一次级线圈的第一端作为所述输出合成单元的输出端，以与所述信号输出端连接；
所述第三电容的第一端连接至所述第一初级线圈的中抽头，所述第三电容的第二端接地；
所述第四电容的第一端连接至所述第一初级线圈的中抽头，所述第四电容的第二端接地；
所述第五电容的第一端连接至所述第一次级线圈的第二端，所述第五电容的第二端接地。
更优的，所述输出合成单元还包括第六电容和第三电阻；所述第六电容并联至所述第一初级线圈的第一端和第二端之间，所述第三电阻也并联至所述第一初级线圈的第一端和第二端之间。
更优的，所述输出合成单元还包括连接至所述第一次级线圈的第一端的谐振电路。
更优的，所述谐振电路包括第七电容和电感；所述第七电容的第一端连接至所述第一次级线圈的第一端，所述电感的第一端与所述第七电容的第二端连接，所述电感的第二端接地。
更优的，所述差分单元包括第二变压器、第八电容、第九电容、第十电容以及第十一电容；
所述第二变压器包括第二初级线圈和第二次级线圈，所述第二初级线圈的第一端作为所述放大级差分功率单元的输入端，以与所述驱动级功率单元的输出端连接；
所述第八电容的第一端连接至所述第二初级线圈的第一端，所述第八电容的第二端接地；
所述第九电容的第一端连接至所述第二初级线圈的第二端，所述第九电容的第二端接地；
所述第十电容的第一端连接至所述第二初级线圈的第二端，所述第十电容的第二端接地；
所述第十一电容的第一端连接至所述第二次级线圈的中抽头，所述第十一电容的第二端接地；
所述第一末级功率单元的输入端与所述第二次级线圈的第一端连接，所述第二末级功率单元的输入端与所述第二次级线圈的第二端连接。
更优的，所述差分单元还包括第四电阻；所述第四电阻并联至所述第二初级线圈的第一端和第二端。
更优的，所述驱动级功率单元包括驱动三极管、驱动电容以及驱动电阻；
所述驱动三极管的基极作为所述驱动级功率单元的输入端，以与所述信号输入端连接，所述驱动三极管的发射极接地，所述驱动三极管的集电极作为所述驱动级功率单元的输出端，以与所述放大级差分功率单元的输入端连接，所述驱动电容串联至所述驱动三极管的基极和所述信号输入端之间，所述驱动电阻的第一端连接至第一偏置电路，所述驱动电阻的第二端连接至所述驱动三极管的基极；
所述第一末级功率单元的电路结构与所述驱动级功率单元的电路结构相同；所述第一末级功率单元中：所述驱动三极管的基极作为所述第一末级功率单元的输入端，以与所述第二次级线圈的第一端连接，所述驱动三极管的发射极接地，所述驱动三极管的集电极作为所述第一末级功率单元的输出端，以与所述输出合成单元的第一输入端连接，所述驱动电容串联至所述驱动三极管的基极和所述第二次级线圈的第一端之间，所述驱动电阻的第一端连接至第二偏置电路，所述驱动电阻的第二端连接至所述驱动三极管的基极；
所述第二末级功率单元的电路结构与所述驱动级功率单元的电路结构相同；所述第二末级功率单元中：所述驱动三极管的基极作为所述第二末级功率单元的输入端，以与所述第二次级线圈的第二端连接， 所述驱动三极管的发射极接地，所述驱动三极管的集电极作为所述第二末级功率单元的输出端，以与所述输出合成单元的第二输入端连接，所述驱动电容串联至所述驱动三极管的基极和所述第二次级线圈的第二端之间，所述驱动电阻的第一端连接至第三偏置电路，所述驱动电阻的第二端连接至所述驱动三极管的基极。
第二方面，本发明提供了一种射频功放模组，所述射频功放模组包括如上所述的两级差分功率放大器。
与现有技术相比，本发明的两级差分功率放大器通过在第一末级功率单元的输入端和所述第二末级功率单元的输出端之间增设所述第一电容，在第二末级功率单元的输入端和所述第一末级功率单元的输出端之间增设第二电容，从而可以将经过第一末级功率单元和第二末级功率单元放大后的两路射频差分信号补充到另一路的输出合成单元中，从而减少了其基极-集电极电容对第一末级功率单元和第二末级功率单元的影响，进而提升两级差分功率放大器的电路增益效果。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为本发明实施例提供的一种两级差分功率放大器的电路图。
100、两级差分功率放大器；1、输入匹配电路；2、驱动级功率单元；3、放大级差分功率单元；31、差分单元；32、第一末级功率单元；33、第二末级功率单元；4、输出合成单元；5、第一偏置电路；6、第二偏置电路；7、第三偏置电路。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例提供了一种两级差分功率放大器100，结合图1所示，其包括依次连接的信号输入端RFin、驱动级功率单元2、放大级差分功率单元3、输出合成单元4以及信号输出端RFout。
驱动级功率单元2用于将信号输入端RFin接收的一路单端信号进行放大后输出；放大级差分功率单元3用于接收经驱动级功率单元2放大后的一路单端信号，并将其转换为两路差分信号后分别进行放大后输出；输出合成单元4用于将经放大级差分功率单元3转换并放大后的两路差分信号合成一路单端信号后输出至信号输出端RFout。
放大级差分功率单元3包括差分单元31、第一末级功率单元32、第二末级功率单元33、第一电容C04和第二电容CO5；第一电容C04串联至第一末级功率单元32的输入端和第二末级功率单元33的输出端之间，第二电容CO5串联至第二末级功率单元33的输入端和第一末级功率单元32的输出端之间。
本实施例中，驱动级功率单元2包括驱动三极管(图未标)、驱动电容(图未标)以及驱动电阻(图未标)。
驱动三极管的基极作为驱动级功率单元2的输入端，以与信号输入端RFin连接，驱动三极管的发射极接地，驱动三极管的集电极作为驱动级功率单元2的输出端，以与放大级差分功率单元3的输入端连接，驱动电容串联至驱动三极管的基极和信号输入端RFin之间，驱动电阻的第一端连接至第一偏置电路5，驱动电阻的第二端连接至驱动三极管的基极。
本实施例中，放大级差分功率单元3还包括第一电阻R02和第二电阻R03；第一电阻R02串联至第一末级功率单元32的输入端和第一 电容C04之间，第二电阻R03串联至第二末级功率单元33的输入端和第二电容CO5之间。
第一电阻R02和第一电容C04可以组成第一组RC串联电路(RC滤波器、RC网络或相移电路)，第二电阻R03和第二电容CO5组成第二组RC串联电路，这两组RC串联电路可以起到衰减带外信号的作用。
本实施例中，差分单元31包括第二变压器TF1、第八电容C01、第九电容C02、第十电容C10以及第十一电容C03。
第二变压器TF1包括第二初级线圈和第二次级线圈，第二初级线圈的第一端作为放大级差分功率单元3的输入端，以与驱动级功率单元2的输出端连接，即第二初级线圈的第一端与驱动级功率单元2中驱动三极管的集电极连接。
第八电容C01的第一端连接至第二初级线圈的第一端，第八电容C01的第二端接地；第九电容C02的第一端连接至第二初级线圈的第二端，第九电容C02的第二端接地；第十电容C10的第一端连接至第二初级线圈的第二端，第十电容C10的第二端接地；第十一电容C03的第一端连接至第二次级线圈的中抽头，第十一电容C03的第二端接地。
第二初级线圈的第二端还连接至第一供电电压VCC1。
第一末级功率单元32的输入端与第二次级线圈的第一端连接，第二末级功率单元33的输入端与第二次级线圈的第二端连接。
另外，差分单元31还包括第四电阻R01；第四电阻R01并联至第二初级线圈的第一端和第二端。该第四电阻R01可以起到提升第二变压器TF1两个平衡端口(第二初级线圈的第一端和第二端)之间的隔离度。
本实施例中，第一末级功率单元32的电路结构与驱动级功率单元2的电路结构相同；第二末级功率单元33的电路结构也与驱动级功率单元2的电路结构相同。
第一末级功率单元32中：驱动三极管的基极作为第一末级功率单元32的输入端，以与第二次级线圈的第一端连接，驱动三极管的发射极接地，驱动三极管的集电极作为第一末级功率单元32的输出端，以与输出合成单元4的第一输入端连接，驱动电容串联至驱动三极管的基极和第二次级线圈的第一端之间，驱动电阻的第一端连接至第二偏置电路6，驱动电阻的第二端连接至驱动三极管的基极。
第二末级功率单元33中：驱动三极管的基极作为第二末级功率单元33的输入端，以与第二次级线圈的第二端连接，驱动三极管的发射极接地，驱动三极管的集电极作为第二末级功率单元33的输出端，以与输出合成单元4的第二输入端连接，驱动电容串联至驱动三极管的基极和第二次级线圈的第二端之间，驱动电阻的第一端连接至第三偏置电路7，驱动电阻的第二端连接至驱动三极管的基极。
本实施例中，输出合成单元4包括第一变压器TF2、第三电容CO7、第四电容C11以及第五电容C08。
第一变压器TF2包括第一初级线圈和第一次级线圈，第一初级线圈的第一端作为输出合成单元4的第一输入端，以与第一末级功率单元32的输出端连接，第一初级线圈的第二端作为输出合成单元4的第二输入端，以与第二末级功率单元33的输出端连接，第一次级线圈的第一端作为输出合成单元4的输出端，以与信号输出端RFout连接。
第一初级线圈的中抽头还连接至第二供电电压VCC2。
第三电容CO7的第一端连接至第一初级线圈的中抽头，第三电容CO7的第二端接地；第四电容C11的第一端连接至第一初级线圈的中抽头，第四电容C11的第二端接地；第五电容C08的第一端连接至第一次级线圈的第二端，第五电容C08的第二端接地。
本实施例中，输出合成单元4还包括第六电容06和第三电阻R04；第六电容06并联至第一初级线圈的第一端和第二端之间，第三电阻R04也并联至第一初级线圈的第一端和第二端之间。
在第一变压器TF2的两个平衡端口(第一初级线圈的第一端和第 二端)引入组成RC并联电路的第六电容06和第三电阻R04，这样可以提升第一变压器TF2两个平衡端口之间的隔离度。
本实施例中，输出合成单元4还包括连接至第一次级线圈的第一端的谐振电路；该谐振电路包括第七电容C09和电感L01；第七电容C09的第一端连接至第一次级线圈的第一端，电感L01的第一端与第七电容C09的第二端连接，电感L01的第二端接地。
通过在第一变压器TF2的非平衡端口(第一次级线圈的第一端)引入谐振电路，可以对主频的二阶滤波进行抑制，且可以通过第七电容C09起到调节第一变压器TF2两个平衡端口的阻抗作用。
本实施例中，两级差分功率放大器100提升电路增益效果的原理为：在第一末级功率单元32和第二末级功率单元33之间引入第一电容C04和第二电容CO5(交叉耦合电容)，从而可以将经过第一末级功率单元32和第二末级功率单元33放大后且相位上完全相反的两路差分信号补偿到另一路的输出合成单元4中，即交叉耦合电容分别相对于对应第一末级功率单元32和第二末级功率单元33的基极节点引入了负电容的作用，进而中和了基极-集电极电容(Cbc)产生的影响。
另外，本实施例中的两级差分功率放大器100还包括串联至信号输入端RFin与驱动级功率单元2的输入端之间的输入匹配电路1。
本实施例中所描述的“连接”均为电连接或电性连接，即连接的两个器件或多个器件的方式均为电连接或电性连接。
与现有技术相比，本发明的两级差分功率放大器100通过在第一末级功率单元32的输入端和第二末级功率单元33的输出端之间增设第一电容C04，在第二末级功率单元33的输入端和第一末级功率单元32的输出端之间增设第二电容CO5，从而可以将经过第一末级功率单元32和第二末级功率单元33放大后的两路射频差分信号补充到另一路的输出合成单元4中，从而减少了其基极-集电极电容对第一末级功率单元32和第二末级功率单元33的影响，进而提升两级差分功率放大器100的电路增益效果。
本发明还提供了另一实施例，一种射频功放模组，其包括上述实施例中的两级差分功率放大器100。
由于本实施例中的射频功放模组包括了上述实施例中的两级差分功率放大器100，因此其也能达到上述实施例中两级差分功率放大器100所达到的技术效果，在此不作赘述。
以上所述的仅是本发明的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出改进，但这些均属于本发明的保护范围。

Claims (10)

  1. 一种两级差分功率放大器，包括依次连接的信号输入端、驱动级功率单元、放大级差分功率单元、输出合成单元以及信号输出端；
    所述驱动级功率单元用于将所述信号输入端接收的一路单端信号进行放大后输出；所述放大级差分功率单元用于接收经所述驱动级功率单元放大后的一路所述单端信号，并将其转换为两路差分信号后分别进行放大后输出；所述输出合成单元用于将经所述放大级差分功率单元转换并放大后的两路所述差分信号合成一路单端信号后输出至所述信号输出端，其特征在于，
    所述放大级差分功率单元包括差分单元、第一末级功率单元、第二末级功率单元、第一电容和第二电容；所述第一电容串联至所述第一末级功率单元的输入端和所述第二末级功率单元的输出端之间，所述第二电容串联至所述第二末级功率单元的输入端和所述第一末级功率单元的输出端之间。
  2. 如权利要求1所述的两级差分功率放大器，其特征在于，所述放大级差分功率单元还包括第一电阻和第二电阻；所述第一电阻串联至所述第一末级功率单元的输入端和所述第一电容之间，所述第二电阻串联至所述第二末级功率单元的输入端和所述第二电容之间。
  3. 如权利要求2所述的两级差分功率放大器，其特征在于，所述输出合成单元包括第一变压器、第三电容、第四电容以及第五电容；
    所述第一变压器包括第一初级线圈和第一次级线圈，所述第一初级线圈的第一端作为所述输出合成单元的第一输入端，以与所述第一末级功率单元的输出端连接，所述第一初级线圈的第二端作为所述输出合成单元的第二输入端，以与所述第二末级功率单元的输出端连接，所述第一次级线圈的第一端作为所述输出合成单元的输出端，以与所述信号输出端连接；
    所述第三电容的第一端连接至所述第一初级线圈的中抽头，所述第三电容的第二端接地；
    所述第四电容的第一端连接至所述第一初级线圈的中抽头，所述第四电容的第二端接地；
    所述第五电容的第一端连接至所述第一次级线圈的第二端，所述第五电容的第二端接地。
  4. 如权利要求3所述的两级差分功率放大器，其特征在于，所述输出合成单元还包括第六电容和第三电阻；所述第六电容并联至所述第一初级线圈的第一端和第二端之间，所述第三电阻也并联至所述第一初级线圈的第一端和第二端之间。
  5. 如权利要求3所述的两级差分功率放大器，其特征在于，所述输出合成单元还包括连接至所述第一次级线圈的第一端的谐振电路。
  6. 如权利要求5所述的两级差分功率放大器，其特征在于，所述谐振电路包括第七电容和电感；所述第七电容的第一端连接至所述第一次级线圈的第一端，所述电感的第一端与所述第七电容的第二端连接，所述电感的第二端接地。
  7. 如权利要求2所述的两级差分功率放大器，其特征在于，所述差分单元包括第二变压器、第八电容、第九电容、第十电容以及第十一电容；
    所述第二变压器包括第二初级线圈和第二次级线圈，所述第二初级线圈的第一端作为所述放大级差分功率单元的输入端，以与所述驱动级功率单元的输出端连接；
    所述第八电容的第一端连接至所述第二初级线圈的第一端，所述第八电容的第二端接地；
    所述第九电容的第一端连接至所述第二初级线圈的第二端，所述第九电容的第二端接地；
    所述第十电容的第一端连接至所述第二初级线圈的第二端，所述第十电容的第二端接地；
    所述第十一电容的第一端连接至所述第二次级线圈的中抽头，所述第十一电容的第二端接地；
    所述第一末级功率单元的输入端与所述第二次级线圈的第一端连接，所述第二末级功率单元的输入端与所述第二次级线圈的第二端连接。
  8. 如权利要求7所述的两级差分功率放大器，其特征在于，所述差分单元还包括第四电阻；所述第四电阻并联至所述第二初级线圈的第一端和第二端。
  9. 如权利要求7所述的两级差分功率放大器，其特征在于，所述驱动级功率单元包括驱动三极管、驱动电容以及驱动电阻；
    所述驱动三极管的基极作为所述驱动级功率单元的输入端，以与所述信号输入端连接，所述驱动三极管的发射极接地，所述驱动三极管的集电极作为所述驱动级功率单元的输出端，以与所述放大级差分功率单元的输入端连接，所述驱动电容串联至所述驱动三极管的基极和所述信号输入端之间，所述驱动电阻的第一端连接至第一偏置电路，所述驱动电阻的第二端连接至所述驱动三极管的基极；
    所述第一末级功率单元的电路结构与所述驱动级功率单元的电路结构相同；所述第一末级功率单元中：所述驱动三极管的基极作为所述第一末级功率单元的输入端，以与所述第二次级线圈的第一端连接，所述驱动三极管的发射极接地，所述驱动三极管的集电极作为所述第一末级功率单元的输出端，以与所述输出合成单元的第一输入端连接，所述驱动电容串联至所述驱动三极管的基极和第二次级线圈的第一端之间，所述驱动电阻的第一端连接至第二偏置电路，所述驱动电阻的第二端连接至所述驱动三极管的基极；
    所述第二末级功率单元的电路结构与所述驱动级功率单元的电路结构相同；所述第二末级功率单元中：所述驱动三极管的基极作为所述第二末级功率单元的输入端，以与所述第二次级线圈的第二端连接，所述驱动三极管的发射极接地，所述驱动三极管的集电极作为所述第二末级功率单元的输出端，以与所述输出合成单元的第二输入端连接，所述驱动电容串联至所述驱动三极管的基极和第二次级线圈的第二端 之间，所述驱动电阻的第一端连接至第三偏置电路，所述驱动电阻的第二端连接至所述驱动三极管的基极。
  10. 一种射频功放模组，其特征在于，所述射频功放模组包括如权利要求1至9任意一项所述的两级差分功率放大器。
PCT/CN2023/115050 2022-10-26 2023-08-25 两级差分功率放大器及射频功放模组 WO2024087851A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211323752.2 2022-10-26
CN202211323752.2A CN115567016A (zh) 2022-10-26 2022-10-26 两级差分功率放大器及射频功放模组

Publications (1)

Publication Number Publication Date
WO2024087851A1 true WO2024087851A1 (zh) 2024-05-02

Family

ID=84769613

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/115050 WO2024087851A1 (zh) 2022-10-26 2023-08-25 两级差分功率放大器及射频功放模组

Country Status (2)

Country Link
CN (1) CN115567016A (zh)
WO (1) WO2024087851A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115580244A (zh) * 2022-10-26 2023-01-06 深圳飞骧科技股份有限公司 差分功率放大电路及射频芯片
CN115567016A (zh) * 2022-10-26 2023-01-03 深圳飞骧科技股份有限公司 两级差分功率放大器及射频功放模组

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101371816B1 (ko) * 2012-09-14 2014-03-07 숭실대학교산학협력단 고조파 제거를 위한 차동 전력 증폭기
CN206332649U (zh) * 2016-12-23 2017-07-14 陕西烽火实业有限公司 一种低压射频功率放大器
US20190253027A1 (en) * 2018-02-12 2019-08-15 Georgia Tech Research Corporation Continuous-Mode Harmonically Tuned Power Amplifier Output Networks and Systems Including Same
CN111934629A (zh) * 2020-07-24 2020-11-13 成都天锐星通科技有限公司 一种宽带高线性度功率放大器
CN212518921U (zh) * 2020-06-30 2021-02-09 吉林大学 一种具有谐波抑制的高增益功率放大器芯片
CN215990714U (zh) * 2021-09-27 2022-03-08 深圳飞骧科技股份有限公司 应用于5g通信系统的射频功率放大器及射频前端架构
CN216390918U (zh) * 2021-11-05 2022-04-26 深圳飞骧科技股份有限公司 一种hbt高效率射频功率放大器
CN114785295A (zh) * 2022-06-22 2022-07-22 华南理工大学 超宽带功率放大器和相控阵发射机
CN114785289A (zh) * 2022-04-02 2022-07-22 华南理工大学 一种Doherty功率放大器
CN115567016A (zh) * 2022-10-26 2023-01-03 深圳飞骧科技股份有限公司 两级差分功率放大器及射频功放模组

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101371816B1 (ko) * 2012-09-14 2014-03-07 숭실대학교산학협력단 고조파 제거를 위한 차동 전력 증폭기
CN206332649U (zh) * 2016-12-23 2017-07-14 陕西烽火实业有限公司 一种低压射频功率放大器
US20190253027A1 (en) * 2018-02-12 2019-08-15 Georgia Tech Research Corporation Continuous-Mode Harmonically Tuned Power Amplifier Output Networks and Systems Including Same
CN212518921U (zh) * 2020-06-30 2021-02-09 吉林大学 一种具有谐波抑制的高增益功率放大器芯片
CN111934629A (zh) * 2020-07-24 2020-11-13 成都天锐星通科技有限公司 一种宽带高线性度功率放大器
CN215990714U (zh) * 2021-09-27 2022-03-08 深圳飞骧科技股份有限公司 应用于5g通信系统的射频功率放大器及射频前端架构
CN216390918U (zh) * 2021-11-05 2022-04-26 深圳飞骧科技股份有限公司 一种hbt高效率射频功率放大器
CN114785289A (zh) * 2022-04-02 2022-07-22 华南理工大学 一种Doherty功率放大器
CN114785295A (zh) * 2022-06-22 2022-07-22 华南理工大学 超宽带功率放大器和相控阵发射机
CN115567016A (zh) * 2022-10-26 2023-01-03 深圳飞骧科技股份有限公司 两级差分功率放大器及射频功放模组

Also Published As

Publication number Publication date
CN115567016A (zh) 2023-01-03

Similar Documents

Publication Publication Date Title
WO2024087851A1 (zh) 两级差分功率放大器及射频功放模组
WO2024087852A1 (zh) 两级差分功率放大器及射频功放模组
CN112187194B (zh) 推挽功率放大器、射频前端电路和无线装置
US7961048B2 (en) Integrated power amplifiers for use in wireless communication devices
CN114050792A (zh) 一种新型宽带多赫蒂射频功率放大器
JP4896996B2 (ja) Ｒｆ増幅装置
WO2022205975A1 (zh) 偏置电路及射频功率放大器
US11973474B2 (en) Power amplifiers and transmission systems and methods of broadband and efficient operations
WO2023045542A1 (zh) 应用于5g通信系统的射频功率放大器及射频前端架构
WO2024087846A1 (zh) 差分功率放大电路及射频芯片
WO2024087850A1 (zh) 差分功率放大电路及射频芯片
WO2022160892A1 (zh) 一种推挽式射频功率放大器和电路控制方法
CN111030621A (zh) 一种用于无线终端的交流堆叠功率放大器
WO2024114179A1 (zh) 双频段功率放大模组及射频功率放大器
CN213243932U (zh) 射频功率放大系统和射频前端模组
US20230163796A1 (en) High-frequency circuit and communication device
CN116232246A (zh) 射频功率放大器
CN110601668A (zh) 一种面向车联网通信的高效功率放大器
US8994451B1 (en) RF amplifier
WO2022212908A1 (en) Low noise amplifier incorporating sutardja transformer
CN111277223B (zh) 一种具有干扰抑制的高阶耦合网络及其应用
Ozkan et al. A high-gain SiGe BiCMOS LNA for 5G in-band full-duplex applications
US20210336592A1 (en) Power amplifier circuit
WO2023074253A1 (ja) 高周波回路および通信装置
You et al. A 5W ultra-broadband power amplifier using silicon LDMOSFETs

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23881434

Country of ref document: EP

Kind code of ref document: A1