WO2024087850A1 - 差分功率放大电路及射频芯片 - Google Patents
差分功率放大电路及射频芯片 Download PDFInfo
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- WO2024087850A1 WO2024087850A1 PCT/CN2023/115047 CN2023115047W WO2024087850A1 WO 2024087850 A1 WO2024087850 A1 WO 2024087850A1 CN 2023115047 W CN2023115047 W CN 2023115047W WO 2024087850 A1 WO2024087850 A1 WO 2024087850A1
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- 239000003990 capacitor Substances 0.000 claims abstract description 177
- 230000015572 biosynthetic process Effects 0.000 claims description 33
- 238000003786 synthesis reaction Methods 0.000 claims description 33
- 230000001629 suppression Effects 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 1
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 1
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45172—A transformer being added at the input of the dif amp
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45228—A transformer being added at the output or the load circuit of the dif amp
Definitions
- the present invention relates to the field of wireless communication technology, and in particular to a differential power amplifier circuit and a radio frequency chip.
- differential power amplifier circuits are one of the important components.
- PC2 Power Class 2
- 3GPP has defined a new power standard Power Class 2 (PC2), that is, the output power of wireless terminal equipment is further increased by 3dB on the basis of the original Power Class 3.
- PC2 Power Class 2
- the overall gain of the above differential power amplifier circuit is relatively low.
- the overall power consumption of the PA will further increase, and the efficiency will be significantly reduced.
- the present invention proposes a differential power amplifier circuit and a radio frequency chip that have the ability to simultaneously improve the gain of the radio frequency chip and suppress harmonics of the main frequency, so as to solve the above technical problems.
- the present invention adopts the following technical solutions:
- an embodiment of the present invention provides a differential power amplifier circuit, comprising a signal input terminal, an input matching circuit, a driving stage power unit, a power differential unit, a final stage power unit having a first final stage power unit and a second final stage power unit connected in parallel, a power synthesis unit, an output matching circuit, and a signal output terminal connected in sequence;
- the differential power amplifier circuit further comprises a first capacitor and a second capacitor forming a cross-coupled capacitor group; a first end of the first capacitor is connected to an input end of the first final-stage power unit, and a second end of the first capacitor is connected to an output end of the second final-stage power unit; a first end of the second capacitor is connected to an input end of the second final-stage power unit, and a second end of the second capacitor is connected to an output end of the first final-stage power unit;
- the differential power amplifier circuit also includes a tuning circuit, a first end of the tuning circuit is respectively connected to the output end of the first final stage power unit and the first input end of the power synthesis unit, and a second end of the tuning circuit is respectively connected to the output end of the second final stage power unit and the second input end of the power synthesis unit, and the tuning circuit is used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit.
- the first final stage power unit includes a first transistor, the base of the first transistor serving as the input end of the first final stage power unit is respectively connected to the first end of the first capacitor and the first output end of the power differential unit, the collector of the first transistor serving as the output end of the first final stage power unit is respectively connected to the first end of the second capacitor and the first input end of the power synthesis unit, and the emitter of the first transistor is grounded.
- the second final stage power unit includes a second transistor, the base of the second transistor serving as the input end of the second final stage power unit is respectively connected to the first end of the second capacitor and the second output end of the power differential unit, the collector of the second transistor serving as the output end of the second final stage power unit is respectively connected to the second end of the first capacitor and the second input end of the power synthesis unit, and the emitter of the second transistor is grounded.
- the power synthesis unit includes a combining transformer balun, a third capacitor, a The fourth capacitor and the fifth capacitor;
- the first end of the primary coil of the combining transformer balun is connected to the output end of the first final-stage power unit and the first end of the tuning circuit as the first input end of the power combining unit, and the second end of the primary coil of the combining transformer balun is connected to the output end of the second final-stage power unit and the second end of the tuning circuit as the second input end of the power combining unit;
- a first end of the third capacitor is connected to a middle tap of the primary coil of the combining transformer balun, and a second end of the third capacitor is grounded;
- the first end of the fourth capacitor is respectively connected to the first end of the third capacitor and the first power supply voltage, and the second end of the fourth capacitor is grounded;
- a first end of the secondary coil of the combining transformer balun is connected to the signal output end as the output end of the power combining unit, and a second end of the secondary coil of the combining transformer balun is connected in series with the fifth capacitor and then grounded.
- the tuning circuit includes a sixth capacitor and a first inductor, the first end of the sixth capacitor serves as the first end of the tuning circuit, the second end of the sixth capacitor is connected to the first end of the first inductor, and the second end of the first inductor serves as the second end of the tuning circuit.
- the output matching circuit includes a seventh capacitor and a second inductor, the first end of the seventh capacitor is connected to the first end of the secondary coil of the combining transformer balun, the second end of the seventh capacitor is connected to the first end of the second inductor, and the second end of the second inductor is grounded.
- the power differential unit includes a differential transformer balun, a first resistor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor;
- the first end and the second end of the primary coil of the differential transformer balun are respectively connected to the two ends of the first resistor;
- a first end of the eighth capacitor is connected to a first end of the primary coil of the differential transformer balun, and a second end of the eighth capacitor is grounded;
- the second end of the primary coil of the differential transformer balun is respectively connected to the a first end, a first end of the eleventh capacitor and a second power supply voltage, and a second end of the ninth capacitor and a second end of the eleventh capacitor are grounded respectively;
- the first end of the secondary coil of the differential transformer balun and the second end of the secondary coil of the differential transformer balun serve as the first output end and the second output end of the power differential unit, respectively, and are connected to the first final-stage power unit and the second final-stage power unit, respectively;
- a first end of the tenth capacitor is connected to a middle tap of the secondary coil of the differential transformer balun, and a second end of the tenth capacitor is grounded.
- the driving stage power unit includes a twelfth capacitor, a third transistor, a second resistor and a first bias circuit;
- a first end of the twelfth capacitor is connected to the input matching circuit, and a second end of the twelfth capacitor is connected to the base of the third transistor;
- the collector of the third triode is connected to the input of the power differential unit, and the emitter of the third triode is grounded;
- a first end of the second resistor is connected to the base of the third transistor, and a second end of the second resistor is connected to the first bias circuit.
- the first final power unit further includes a thirteenth capacitor, a third resistor and a second bias circuit; one end of the thirteenth capacitor is connected to the first output end of the power differential unit, the second end of the thirteenth capacitor is connected to the base of the first transistor, the first end of the third resistor is connected to the first end of the first capacitor, and the second end of the third resistor is connected to the second bias circuit;
- the second final stage power unit also includes a fourteenth capacitor, a fourth resistor and a third bias circuit, one end of the fourteenth capacitor is connected to the second output end of the power differential unit, the second end of the fourteenth capacitor is connected to the base of the second transistor, the first end of the fourth resistor is connected to the first end of the second capacitor, and the second end of the fourth resistor is connected to the third bias circuit.
- an embodiment of the present invention provides a radio frequency chip, comprising the above-mentioned differential power amplifier circuit.
- the tuning circuit is used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit; thereby having the ability to simultaneously improve
- FIG1 is a module diagram of a differential power amplifier circuit in an embodiment of the present invention.
- FIG2 is a circuit diagram of a differential power amplifier circuit according to an embodiment of the present invention.
- FIG3 is a circuit diagram of a driving stage power unit in an embodiment of the present invention.
- FIG. 4 is a circuit diagram of a first final-stage power unit and a second final-stage power unit in an embodiment of the present invention.
- differential power amplifier circuit 1, signal input terminal, 2, input matching circuit, 3, driving stage power unit, 31, second resistor, 32, twelfth capacitor, 33, third transistor, 34, first bias circuit, 4, power differential unit, 5, first final stage power unit, 51, third resistor, 52, thirteenth capacitor, 53, first transistor, 6, second final stage power unit, 61, fourth resistor, 62, fourteenth capacitor, 63, second transistor, 7, input Output matching circuit, 8.
- Power synthesis unit 9. Signal output terminal, 10. Tuning circuit.
- a differential power amplifier circuit 100 provided in an embodiment of the present invention includes a signal input terminal 1 (RFin), an input matching circuit 2, a driving stage power unit 3, a power differential unit 4, a final stage power unit having a first final stage power unit 5 and a second final stage power unit 6 connected in parallel, a power synthesis unit 8, an output matching circuit 7 and a signal output terminal 9 (RFout) connected in sequence.
- RFin signal input terminal 1
- driving stage power unit 3 a driving stage power unit 3
- a power differential unit 4 a final stage power unit having a first final stage power unit 5 and a second final stage power unit 6 connected in parallel
- a power synthesis unit 8 an output matching circuit 7 and a signal output terminal 9 (RFout) connected in sequence.
- Signal input terminal 1 is used to connect a single-ended input signal.
- the first end of the input matching circuit 2 is connected to the signal input end 1 for The input signal is matched and output.
- the first end of the driving stage power unit 3 is connected to the second end of the input matching circuit 2 for driving the input signal to output.
- the first end of the power differential unit 4 is connected to the second end of the driving stage power unit 3, and is used to convert the received input signal into two differential signals.
- the differential power amplifier circuit 100 also includes a first capacitor C01 and a second capacitor C02 forming a cross-coupled capacitor group; the first end of the first capacitor C01 is connected to the input end of the first final stage power unit 5, and the second end of the first capacitor C01 is connected to the output end of the second final stage power unit 6; the first end of the second capacitor C02 is connected to the input end of the second final stage power unit 6, and the second end of the second capacitor C02 is connected to the output end of the first final stage power unit 5.
- the differential power amplifier circuit 100 also includes a tuning circuit 10, a first end of the tuning circuit 10 is respectively connected to the output end of the first final stage power unit 5 and the first input end of the power synthesis unit 8, and a second end of the tuning circuit 10 is respectively connected to the output end of the second final stage power unit 6 and the second input end of the power synthesis unit 8, and the tuning circuit 10 is used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit.
- the input signal inputted from the signal input terminal 1 is received by the input matching circuit 2, matched and outputted to the driving stage power unit 3, power amplified by the driving stage power unit 3, and connected to the second end of the driving stage power unit 3 through the first end of the power differential unit 4, so as to convert the received amplified input signal into two differential signals, which are respectively outputted to the first final stage power unit 5 and the second final stage power unit 6, and are fed back through the first final stage power unit 5 and the second final stage power unit 6 to increase the operating frequency.
- the first end of the first capacitor C01 is connected to the input end of the first final stage power unit 5, and the second end of the first capacitor C01 is connected to the output end of the second final stage power unit 6.
- the first end of the second capacitor C02 is connected to the input end of the second final stage power unit 6, and the second end of the second capacitor C02 is connected to the output end of the first final stage power unit 5.
- the cross-coupling first capacitor C01 and the second capacitor C02 are introduced at the output end of the differential pair, and the RF signal outputted after the differential pair amplification is compensated to the common transmission line of another channel.
- the cross-coupled first capacitor C01 and the second capacitor C02 are equivalent to the base nodes corresponding to the first final power unit 5 and the second final power unit 6 respectively, and the negative capacitor is introduced to neutralize the influence of Cbc.
- the tuning circuit 10 is used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit, thereby having the ability to simultaneously improve the gain of the RF chip and suppress the harmonics of the main frequency.
- the first final power unit 5 includes a first transistor 53, the base of the first transistor 53 is connected to the first end of the first capacitor C01 and the first output end of the power differential unit 4 as the input end of the first final power unit 5, the collector of the first transistor 53 is connected to the first end of the second capacitor C02 and the first input end of the power synthesis unit 8 as the output end of the first final power unit 5, and the emitter of the first transistor 53 is grounded.
- the signal output from the first output end of the power differential unit 4 is amplified by the first transistor 53, and the amplified signal is transmitted to the power synthesis unit 8 for power synthesis, and then output to the signal output end 9.
- the first final power unit 5 includes a first field effect tube (not shown), the gate of the first field effect tube is connected to the first end of the first capacitor C01 and the first output end of the power differential unit 4 as the input end of the first final power unit 5, the drain of the first field effect tube is connected to the first end of the second capacitor C02 and the first input end of the power synthesis unit 8 as the output end of the first final power unit 5, and the source of the first field effect tube is grounded.
- the signal output from the first output end of the power differential unit 4 is amplified by the first field effect tube, and the amplified signal is transmitted to the power synthesis unit 8 for power synthesis, and then output to the signal output end 9.
- the second final-stage power unit 6 includes a second transistor 63, and the base of the second transistor 63 is connected to the first end of the second capacitor C02 and the second output end of the power differential unit 4 as the input end of the second final-stage power unit 6.
- the collector of the second transistor 63 is connected to the second end of the first capacitor C01 and the second input end of the power synthesis unit 8 as the output end of the second final power unit 6, and the emitter of the second transistor 63 is grounded.
- the signal output from the second output end of the power differential unit 4 is amplified by the second transistor 63, and the amplified signal is transmitted to the power synthesis unit 8 for power synthesis, and then output to the signal output end 9.
- the second triode 63 may also be replaced by a field effect transistor, which has the same function as the second diode 63 in the second final-stage power unit 6 and will not be described one by one here.
- the power combining unit 8 includes a combining transformer balun TF2, a third capacitor C03, a fourth capacitor C04 and a fifth capacitor C05.
- the first end of the primary coil of the combining transformer balun TF2 is connected to the output end of the first final stage power unit 5 and the first end of the tuning circuit 10 as the first input end of the power synthesis unit 8, and the second end of the primary coil of the combining transformer balun TF2 is connected to the output end of the second final stage power unit 6 and the second end of the tuning circuit 10 as the second input end of the power synthesis unit 8.
- a first end of the third capacitor C03 is connected to a middle tap of the primary coil of the combining transformer balun, and a second end of the third capacitor C03 is grounded.
- the first end of the fourth capacitor C04 is respectively connected to the first end of the third capacitor C03 and the first power supply voltage VCC1 , and the second end of the fourth capacitor C04 is grounded.
- the first end of the secondary coil of the combining transformer balun TF2 is connected to the signal output terminal 9 as the output terminal of the power synthesis unit 8, and the second end of the secondary coil of the combining transformer balun TF2 is connected in series with the fifth capacitor C05 and then grounded.
- the third capacitor C03 and the fourth capacitor C04 are connected to the primary coil of the combining transformer balun TF2, and the fifth capacitor C05 is connected to the balanced port of the secondary coil of the combining transformer balun TF2, so as to suppress harmonics of the combining transformer balun TF2.
- the tuning circuit 10 includes a sixth capacitor C06 and a first inductor L01.
- the first end of the sixth capacitor C06 is connected to the first end of the primary coil of the combining transformer balun TF2 as the first end of the tuning circuit 10.
- the second end of the sixth capacitor C06 is connected to the first end of the first inductor L01.
- the second end of the first inductor L01 is connected to the first end of the primary coil of the combining transformer balun TF2.
- the second end of the tuning circuit 10 is connected to the second end of the primary coil of the combining transformer balun TF2.
- the second-order harmonic frequency of the main frequency is suppressed by a series resonant circuit composed of the sixth capacitor C06 and the first inductor L01, and the suppression effect is good.
- the output matching circuit 7 includes a seventh capacitor C07 and a second inductor L02, the first end of the seventh capacitor C07 is connected to the first end of the secondary coil of the combining transformer balun, the second end of the seventh capacitor C07 is connected to the first end of the second inductor L02, and the second end of the second inductor L02 is grounded.
- the third-order harmonic of the main frequency can be suppressed by forming a series resonant circuit composed of the seventh capacitor C07 and the second inductor L02. That is, the second-order and third-order harmonics of the main frequency can be suppressed by the tuning circuit 10 and the output matching circuit 7, and the harmonic suppression effect is good.
- the power differential unit 4 includes a differential transformer balun TF1, a first resistor R01, an eighth capacitor C08, a ninth capacitor C09, a tenth capacitor C10 and an eleventh capacitor C11.
- the first end and the second end of the primary coil of the differential transformer balun TF1 are respectively connected to the two ends of the first resistor R01.
- a first end of the eighth capacitor C08 is connected to a first end of the primary coil of the differential transformer balun TF1 , and a second end of the eighth capacitor C08 is grounded.
- the second end of the primary coil of the differential transformer balun TF1 is respectively connected to the first end of the ninth capacitor C09, the first end of the eleventh capacitor C11 and the second power supply voltage VCC2, and the second end of the ninth capacitor C09 and the second end of the eleventh capacitor C11 are respectively grounded.
- the first end of the secondary coil of the differential transformer balun TF1 and the second end of the secondary coil of the differential transformer balun TF1 serve as the first output end and the second output end of the power differential unit 4 respectively, and are connected to the first final stage power unit 5 and the second final stage power unit 6 respectively.
- the first end of the tenth capacitor C10 is connected to the middle tap of the secondary coil of the differential transformer balun TF1, and the second end of the tenth capacitor C10 is grounded.
- the differential transformer balun TF1 can be improved.
- the isolation between the two ends of the primary coil of TF1 is improved, so as to suppress the third-order harmonics of the main frequency of the circuit.
- the driving stage power unit 3 includes a twelfth capacitor 32, a third transistor 33, a second resistor 31 and a first bias circuit 34;
- a first end of the twelfth capacitor 32 is connected to the input matching circuit 2, and a second end of the twelfth capacitor 32 is connected to the base of the third transistor 33;
- the collector of the third transistor 33 is connected to the input of the power differential unit 4, and the emitter of the third transistor 33 is grounded;
- a first end of the second resistor 31 is connected to the base of the third transistor 33 , and a second end of the second resistor 31 is connected to the first bias circuit 34 .
- the DC signal is isolated by the twelfth capacitor 32, the input signal is amplified by the third transistor 33, and output to the input end of the power differential unit 4.
- the input signal is power-differentiated by the power differential unit 4 into two differential signals and are output to the first final stage power unit 5 and the second final stage power unit 6 respectively.
- the first final power unit 5 further includes a thirteenth capacitor 52, a third resistor 51 and a second bias circuit 54; one end of the thirteenth capacitor 52 is connected to the first output end of the power differential unit 4, the second end of the thirteenth capacitor 52 is connected to the base of the first transistor 53, the first end of the third resistor 51 is connected to the first end of the first capacitor C01, and the second end of the third resistor 51 is connected to the second bias circuit 54.
- the thirteenth capacitor 52 is used to isolate the DC bias circuits of the front and rear stages of the first transistor 53 to prevent the first transistor 53 from affecting each other under static operation, thereby achieving a capacitive coupling effect. After the thirteenth capacitor 52 and the base of the first transistor 53 are connected in series, the collector of the first transistor 53 can work normally, and the signal amplification effect is good.
- the second final stage power unit 6 also includes a fourteenth capacitor 62, a fourth resistor 61 and a third bias circuit 64, one end of the fourteenth capacitor 62 is connected to the second output end of the power differential unit 4, the second end of the fourteenth capacitor 62 is connected to the base of the second transistor 63, the first end of the fourth resistor 61 is connected to the first end of the second capacitor C02, and the second end of the fourth resistor 61 is connected to the third bias circuit 64.
- the fourteenth capacitor 62 is used to isolate the DC bias circuits of the front and rear stages of the second triode 63 to prevent the second triode 63 from affecting each other in static operation, thereby achieving a capacitive coupling effect. After the fourteenth capacitor 62 and the base of the second triode 63 are connected in series, the collector of the second triode 63 can work normally, and the signal amplification effect is good.
- An embodiment of the present invention provides a radio frequency chip, comprising the differential power amplifier circuit 100 described in the first embodiment.
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Abstract
一种差分功率放大电路（100）及射频芯片，包括：依次连接的信号输入端（1）、输入匹配电路（2）、驱动级功率单元（3）、功率差分单元（4）、具有相互并联的第一末级功率单元（5）和第二末级功率单元（6）的末级功率单元、功率合成单元（8）、输出匹配电路（7）以及信号输出端（9），差分功率放大电路（100）还包括形成交叉耦合电容组的第一电容（C01）和第二电容（C02）；差分功率放大电路（100）还包括调谐电路（10），调谐电路（10）的第一端分别连接至第一末级功率单元（5）的输出端和功率合成单元（8）的第一输入端，调谐电路（10）的第二端分别连接至第二末级功率单元（6）的输出端和功率合成单元（8）的第二输入端，调谐电路（10）用于抑制差分功率放大电路（100）的主频二阶谐波，能同时提升射频芯片的增益和对主频的二、三阶谐波的抑制能力。
Description
本发明涉及无线通信技术领域，尤其涉及一种差分功率放大电路及射频芯片。
随着人类进入信息化时代，无线通信技术有了飞速发展，从手机，无线局域网，蓝牙等已成为社会生活和发展不可或缺的一部分。无线通信技术的进步离不开差分功率放大电路的发展。目前，在无线收发系统中，差分功率放大电路是重要的组成部分之一。
现有的差分功率放大电路在5G-NR中N77和N79频段，相对Sub-3G属于较高的频段，因此在传播过程中衰减比较快，路径的损失比较大，单载波覆盖的范围也有限，为提升用户体验，同时减小运营商建设基站成本，3GPP定义了一种全新的功率标准Power Class2(PC2),即无线终端设备在原有Power Class3的基础上，输出功率继续提升3dB。当无线终端设备的输出功率提升至PC2，就可以补偿更高TDD频率下更大的传播损耗，并且降低运营商建设昂贵基站的成本。
然而，上述的差分功率放大电路的整体增益较低，另外，通过引入更高阶数的电路放大结构，将会导致PA整体功耗也将随之进一步增加，效率明显降低。
发明内容
针对以上现有技术的不足，本发明提出一种具有同时提升射频芯片的增益和对主频的谐波抑制的能力的差分功率放大电路及射频芯片，以解决上述技术问题。
为了解决上述技术问题，本发明采用如下技术方案：
第一方面，本发明实施例提供一种差分功率放大电路，包括依次连接的信号输入端、输入匹配电路、驱动级功率单元、功率差分单元、具有相互并联的第一末级功率单元和第二末级功率单元的末级功率单元、功率合成单元、输出匹配电路以及信号输出端；
所述差分功率放大电路还包括形成交叉耦合电容组的第一电容和第二电容；所述第一电容的第一端连接至所述第一末级功率单元的输入端，所述第一电容的第二端连接至所述第二末级功率单元的输出端；所述第二电容的第一端连接至所述第二末级功率单元的输入端，所述第二电容的第二端连接至所述第一末级功率单元的输出端；
所述差分功率放大电路还包括调谐电路，所述调谐电路的第一端分别连接至所述第一末级功率单元的输出端和所述功率合成单元的第一输入端，所述调谐电路的第二端分别连接至所述第二末级功率单元的输出端和所述功率合成单元的第二输入端，所述调谐电路用于抑制所述差分功率放大电路的主频二阶谐波。
优选的，所述第一末级功率单元包括第一三极管，所述第一三极管的基极作为所述第一末级功率单元的输入端分别连接至所述第一电容的第一端和所述功率差分单元的第一输出端，所述第一三极管的集电极作为所述第一末级功率单元的输出端分别与所述第二电容的第一端和所述功率合成单元的第一输入端连接，所述第一三极管的发射极接地。
优选的，所述第二末级功率单元包括第二三极管，所述第二三极管的基极作为所述第二末级功率单元的输入端分别连接至所述第二电容的第一端和所述功率差分单元的第二输出端，所述第二三极管的集电极作为所述第二末级功率单元的输出端分别与所述第一电容的第二端和所述功率合成单元的第二输入端连接，所述第二三极管的发射极接地。
优选的，所述功率合成单元包括合路变压器巴伦、第三电容、第
四电容和第五电容；
所述合路变压器巴伦的初级线圈的第一端作为所述功率合成单元的第一输入端分别连接至所述第一末级功率单元的输出端和所述调谐电路的第一端，所述合路变压器巴伦的初级线圈的第二端作为所述功率合成单元的第二输入端分别连接至所述第二末级功率单元的输出端和所述调谐电路的第二端；
所述第三电容的第一端与所述合路变压器巴伦的初级线圈的中抽头连接，所述第三电容的第二端接地；
所述第四电容的第一端分别连接于所述第三电容的第一端和第一电源电压，所述第四电容的第二端接地；
所述合路变压器巴伦的次级线圈的第一端作为所述功率合成单元的输出端与所述信号输出端连接，所述合路变压器巴伦的次级线圈的第二端经串联所述第五电容后接地。
优选的，所述调谐电路包括第六电容和第一电感，所述第六电容的第一端作为所述调谐电路的第一端，所述第六电容的第二端与所述第一电感的第一端连接，所述第一电感的第二端作为所述调谐电路的第二端。
优选的，所述输出匹配电路包括第七电容和第二电感，所述第七电容的第一端连接至所述合路变压器巴伦的次级线圈的第一端，所述第七电容的第二端连接至所述第二电感的第一端，所述第二电感的第二端接地。
优选的，所述功率差分单元包括差分变压器巴伦、第一电阻、第八电容、第九电容、第十电容和第十一电容；
所述差分变压器巴伦的初级线圈的第一端和第二端分别与所述第一电阻的两端连接；
所述第八电容的第一端连接所述差分变压器巴伦的初级线圈的第一端，所述第八电容的第二端接地；
所述差分变压器巴伦的初级线圈的第二端分别与所述第九电容的
第一端、所述第十一电容的第一端以及第二电源电压，所述第九电容的第二端和所述第十一电容的第二端分别接地；
所述差分变压器巴伦的次级线圈的第一端和所述差分变压器巴伦的次级线圈的第二端分别作为所述功率差分单元的第一输出端和第二输出端，并分别连接至所述第一末级功率单元和所述第二末级功率单元；
所述第十电容的第一端连接所述差分变压器巴伦的次级线圈的中抽头，所述第十电容的第二端接地。
优选的，所述驱动级功率单元包括第十二电容、第三三极管、第二电阻和第一偏置电路；
所述第十二电容的第一端连接所述输入匹配电路，所述第十二电容的第二端与所述第三三极管的基极连接；
所述第三三极管的集电极与所述功率差分单元的输入连接，所述第三三极管的发射极接地；
所述第二电阻的第一端连接于所述第三三极管的基极，所述第二电阻的第二端连接至所述第一偏置电路。
优选的，所述第一末级功率单元还包括第十三电容、第三电阻和第二偏置电路；所述第十三电容的一端与所述功率差分单元的第一输出端连接，所述第十三电容的第二端与所述第一三极管的基极连接，所述第三电阻的第一端与所述第一电容的第一端连接，所述第三电阻的第二端连接至所述第二偏置电路；
所述第二末级功率单元还包括第十四电容、第四电阻和第三偏置电路，所述第十四电容的一端与所述功率差分单元的第二输出端连接，所述第十四电容的第二端与所述第二三极管的基极连接，所述第四电阻的第一端与所述第二电容的第一端连接，所述第四电阻的第二端连接至所述第三偏置电路。
第二方面，本发明实施例提供一种射频芯片，包括上述的差分功率放大电路。
与相关技术相比，本发明的实施例中，通过将所述第一电容的第一端连接至所述第一末级功率单元的输入端，所述第一电容的第二端连接至所述第二末级功率单元的输出端；所述第二电容的第一端连接至所述第二末级功率单元的输入端，所述第二电容的第二端连接至所述第一末级功率单元的输出端；可以减少Cbc对末级功率单元的影响，通过所述功率合成单元的输入分别与所述第一末级功率单元的输出端和所述第二末级功率单元的输出端连接，用于将两路所述差分信号实现功率合成后输出，通过将所述调谐电路的第一端分别连接至所述第一末级功率单元的输出端和所述功率合成单元的第一输入端，所述调谐电路的第二端分别连接至所述第二末级功率单元的输出端和所述功率合成单元的第二输入端，所述调谐电路用于抑制所述差分功率放大电路的主频二阶谐波；从而可以具有同时提升射频芯片的增益和对主频的谐波抑制的能力。
下面结合附图详细说明本发明。通过结合以下附图所作的详细描述，本发明的上述或其他方面的内容将变得更清楚和更容易理解。附图中：
图1为本发明实施例中差分功率放大电路的模块图；
图2为本发明实施例中差分功率放大电路的电路图；
图3为本发明实施例中驱动级功率单元的电路图；
图4为本发明实施例中第一末级功率单元和第二末级功率单元的电路图。
其中，100、差分功率放大电路，1、信号输入端，2、输入匹配电路，3、驱动级功率单元，31、第二电阻，32、第十二电容，33、第三三极管，34、第一偏置电路，4、功率差分单元，5、第一末级功率单元，51、第三电阻，52、第十三电容，53、第一三极管，6、第二末级功率单元，61、第四电阻，62、第十四电容，63、第二三极管，7、输
出匹配电路，8、功率合成单元，9、信号输出端，10、调谐电路。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同；本文中在申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请；本申请的说明书和权利要求书及上述附图说明中的术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。本申请的说明书和权利要求书或上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
请参阅图1-4所示，本发明实施例提供的一种差分功率放大电路100，包括依次连接的信号输入端1(RFin)、输入匹配电路2、驱动级功率单元3、功率差分单元4、具有相互并联的第一末级功率单元5和第二末级功率单元6的末级功率单元、功率合成单元8、输出匹配电路7以及信号输出端9(RFout)。
信号输入端1用于连接单端的输入信号。
所述输入匹配电路2的第一端与所述信号输入端1连接，用于将
所述输入信号进行匹配输出。
所述驱动级功率单元3的第一端与所述输入匹配电路2的第二端连接，用于将所述输入信号进行驱动输出。
所述功率差分单元4的第一端与所述驱动级功率单元3的第二端连接，用于将接收的所述输入信号转换为两路差分信号。
所述差分功率放大电路100还包括形成交叉耦合电容组的第一电容C01和第二电容C02；所述第一电容C01的第一端连接至所述第一末级功率单元5的输入端，所述第一电容C01的第二端连接至所述第二末级功率单元6的输出端；所述第二电容C02的第一端连接至所述第二末级功率单元6的输入端，所述第二电容C02的第二端连接至所述第一末级功率单元5的输出端。
所述差分功率放大电路100还包括调谐电路10，所述调谐电路10的第一端分别连接至所述第一末级功率单元5的输出端和所述功率合成单元8的第一输入端，所述调谐电路10的第二端分别连接至所述第二末级功率单元6的输出端和所述功率合成单元8的第二输入端，所述调谐电路10用于抑制所述差分功率放大电路的主频二阶谐波。
具体的，通过输入匹配电路2接收信号输入端1输入的输入信号，进行匹配后输出到驱动级功率单元3上，通过驱动级功率单元3进行功率放大，通过所述功率差分单元4的第一端与所述驱动级功率单元3的第二端连接，用于将接收的放大的所述输入信号转换为两路差分信号，分别输出到第一末级功率单元5和第二末级功率单元6，通过第一末级功率单元5和第二末级功率单元6进行反馈用于增加工作频率。所述第一电容C01的第一端连接至所述第一末级功率单元5的输入端，所述第一电容C01的第二端连接至所述第二末级功率单元6的输出端。所述第二电容C02的第一端连接至所述第二末级功率单元6的输入端，所述第二电容C02的第二端连接至所述第一末级功率单元5的输出端。这样在差分对的输出端引入交叉耦合第一电容C01和第二电容C02，将经过差分对放大输出的射频信号补偿到另一路的共发
射极功率放大器中，即交叉耦合第一电容C01和第二电容C02分别相当于对应第一末级功率单元5和第二末级功率单元6的基极节点引入了负电容的作用，用于中和了Cbc的影响。
具体的，通过将所述调谐电路10的第一端分别连接至所述第一末级功率单元5的输出端和所述功率合成单元8的第一输入端，所述调谐电路10的第二端分别连接至所述第二末级功率单元6的输出端和所述功率合成单元8的第二输入端，所述调谐电路10用于抑制所述差分功率放大电路的主频二阶谐波，从而可以具有同时提升射频芯片的增益和对主频的谐波抑制的能力。
在本实施例中，所述第一末级功率单元5包括第一三极管53，所述第一三极管53的基极作为所述第一末级功率单元5的输入端分别连接至所述第一电容C01的第一端和所述功率差分单元4的第一输出端，所述第一三极管53的集电极作为所述第一末级功率单元5的输出端分别与所述第二电容C02的第一端和所述功率合成单元8的第一输入端连接，所述第一三极管53的发射极接地。通过第一三极管53将功率差分单元4的第一输出端输出的信号进行放大，并将放大的信号传输到功率合成单元8进行功率合成后，输出到所述信号输出端9。
可选的，所述第一末级功率单元5包括第一场效应管(未示出)，所述第一场效应管的栅极作为所述第一末级功率单元5的输入端分别连接至所述第一电容C01的第一端和所述功率差分单元4的第一输出端，所述第一场效应管的漏极作为所述第一末级功率单元5的输出端分别与所述第二电容C02的第一端和所述功率合成单元8的第一输入端连接，所述第一场效应管的源极接地。通过第一场效应管将功率差分单元4的第一输出端输出的信号进行放大，并将放大的信号传输到功率合成单元8进行功率合成后，输出到所述信号输出端9。
在本实施例中，所述第二末级功率单元6包括第二三极管63，所述第二三极管63的基极作为所述第二末级功率单元6的输入端分别连接至所述第二电容C02的第一端和所述功率差分单元4的第二输出端，
所述第二三极管63的集电极作为所述第二末级功率单元6的输出端分别与所述第一电容C01的第二端和所述功率合成单元8的第二输入端连接，所述第二三极管63的发射极接地。通过第二三极管63将功率差分单元4的第二输出端输出的信号进行放大，并将放大的信号传输到功率合成单元8进行功率合成后，输出到所述信号输出端9。
可选的，第二三极管63也可以用场效应管代替，功能与第二二极管63在第二末级功率单元6中功能相同，此处不再一一描述。
在本实施例中，所述功率合成单元8包括合路变压器巴伦TF2、第三电容C03、第四电容C04和第五电容C05。
所述合路变压器巴伦TF2的初级线圈的第一端作为所述功率合成单元8的第一输入端分别连接至所述第一末级功率单元5的输出端和所述调谐电路10的第一端，所述合路变压器巴伦TF2的初级线圈的第二端作为所述功率合成单元8的第二输入端分别连接至所述第二末级功率单元6的输出端和所述调谐电路10的第二端。
所述第三电容C03的第一端与所述合路变压器巴伦的初级线圈的中抽头连接，所述第三电容C03的第二端接地。
所述第四电容C04的第一端分别连接于所述第三电容C03的第一端和第一电源电压VCC1，所述第四电容C04的第二端接地。
所述合路变压器巴伦TF2的次级线圈的第一端作为所述功率合成单元8的输出端与所述信号输出端9连接，所述合路变压器巴伦TF2的次级线圈的第二端经串联所述第五电容C05后接地。通过在合路变压器巴伦TF2的初级线圈连接第三电容C03和第四电容C04，在合路变压器巴伦TF2的次级线圈的平衡端口连接第五电容C05，用于对合路变压器巴伦TF2进行谐波抑制。
在本实施例中，所述调谐电路10包括第六电容C06和第一电感L01，第六电容C06的第一端作为所述调谐电路10的第一端连接至所述合路变压器巴伦TF2的初级线圈的第一端，所述第六电容C06的第二端与所述第一电感L01的第一端连接，所述第一电感L01的第二端
作为所述调谐电路10的第二端连接至所述合路变压器巴伦TF2的初级线圈的第二端。通过将第六电容C06和第一电感L01组成的串联谐振电路对主频的二阶谐波频点进行二阶谐波抑制，抑制效果好。
在本实施例中，所述输出匹配电路7包括第七电容C07和第二电感L02，所述第七电容C07的第一端连接至所述合路变压器巴伦的次级线圈的第一端，所述第七电容C07的第二端连接至所述第二电感L02的第一端，所述第二电感L02的第二端接地。通过将第七电容C07和第二电感L02组成的串联谐振电路可以对主频的三阶谐波进行抑制。即，通过调谐电路10和输出匹配电路7能对主频进行二阶、三阶谐波抑制，谐波抑制效果良好。
在本实施例中，所述功率差分单元4包括差分变压器巴伦TF1、第一电阻R01、第八电容C08、第九电容C09、第十电容C10和第十一电容C11。
所述差分变压器巴伦TF1的初级线圈的第一端和第二端分别与所述第一电阻R01的两端连接。
所述第八电容C08的第一端连接所述差分变压器巴伦TF1的初级线圈的第一端，所述第八电容C08的第二端接地。
所述差分变压器巴伦TF1的初级线圈的第二端分别与所述第九电容C09的第一端、所述第十一电容C11的第一端以及第二电源电压VCC2，所述第九电容C09的第二端和所述第十一电容C11的第二端分别接地。
所述差分变压器巴伦TF1的次级线圈的第一端和所述差分变压器巴伦TF1的次级线圈的第二端分别作为所述功率差分单元4的第一输出端和第二输出端，并分别连接至所述第一末级功率单元5和所述第二末级功率单元6。
所述第十电容C10的第一端连接所述差分变压器巴伦TF1的次级线圈的中抽头，所述第十电容C10的第二端接地。通过在差分变压器巴伦TF1初级线圈的两端连接第一电阻R01，可以提升差分变压器巴
伦TF1的初级线圈两端端口的隔离度，从而便于对电路主频的三阶谐波进行抑制。
在本实施例中，所述驱动级功率单元3包括第十二电容32、第三三极管33、第二电阻31和第一偏置电路34；
所述第十二电容32的第一端连接所述输入匹配电路2，所述第十二电容32的第二端与所述第三三极管33的基极连接；
所述第三三极管33的集电极与所述功率差分单元4的输入连接，所述第三三极管33的发射极接地；
所述第二电阻31的第一端连接于所述第三三极管33的基极，所述第二电阻31的第二端连接至所述第一偏置电路34。
具体的，通过第十二电容32隔离直流信号，将输入信号通过第三三极管33进行放大，输出到功率差分单元4的输入端，通过功率差分单元4对输入信号进行功率差分成两路差分信号并进行分别输出至第一末级功率单元5和第二末级功率单元6。
在本实施例中，所述第一末级功率单元5还包括第十三电容52、第三电阻51和第二偏置电路54；所述第十三电容52的一端与所述功率差分单元4的第一输出端连接，所述第十三电容52的第二端与所述第一三极管53的基极连接，所述第三电阻51的第一端与所述第一电容C01的第一端连接，所述第三电阻51的第二端连接至所述第二偏置电路54。第十三电容52用于将第一三极管53的前后级的直流偏置电路隔离，以防止第一三极管53在静态工作下相互影响，起到电容耦合的效果。通过第十三电容52和第一三极管53的基极串流后，使得第一三极管53的集电极能正常工作，信号放大效果良好。
所述第二末级功率单元6还包括第十四电容62、第四电阻61和第三偏置电路64，所述第十四电容62的一端与所述功率差分单元4的第二输出端连接，所述第十四电容62的第二端与所述第二三极管63的基极连接，所述第四电阻61的第一端与所述第二电容C02的第一端连接，所述第四电阻61的第二端连接至所述第三偏置电路64。
第十四电容62用于将第二三极管63的前后级的直流偏置电路隔离，以防止第二三极管63在静态工作下相互影响，起到电容耦合的效果。通过第十四电容62和第二三极管63的基极串流后，使得第二三极管63的集电极能正常工作，信号放大效果良好。
实施例二
本发明实施例提供一种射频芯片，包括上述实施例一所述的差分功率放大电路100。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。
Claims (10)
- 一种差分功率放大电路，包括依次连接的信号输入端、输入匹配电路、驱动级功率单元、功率差分单元、具有相互并联的第一末级功率单元和第二末级功率单元的末级功率单元、功率合成单元、输出匹配电路以及信号输出端，其特征在于，所述差分功率放大电路还包括形成交叉耦合电容组的第一电容和第二电容；所述第一电容的第一端连接至所述第一末级功率单元的输入端，所述第一电容的第二端连接至所述第二末级功率单元的输出端；所述第二电容的第一端连接至所述第二末级功率单元的输入端，所述第二电容的第二端连接至所述第一末级功率单元的输出端；所述差分功率放大电路还包括调谐电路，所述调谐电路的第一端分别连接至所述第一末级功率单元的输出端和所述功率合成单元的第一输入端，所述调谐电路的第二端分别连接至所述第二末级功率单元的输出端和所述功率合成单元的第二输入端，所述调谐电路用于抑制所述差分功率放大电路的主频二阶谐波。
- 根据权利要求1所述的差分功率放大电路，其特征在于，所述第一末级功率单元包括第一三极管，所述第一三极管的基极作为所述第一末级功率单元的输入端分别连接至所述第一电容的第一端和所述功率差分单元的第一输出端，所述第一三极管的集电极作为所述第一末级功率单元的输出端分别与所述第二电容的第一端和所述功率合成单元的第一输入端连接，所述第一三极管的发射极接地。
- 根据权利要求2所述的差分功率放大电路，其特征在于，所述第二末级功率单元包括第二三极管，所述第二三极管的基极作为所述第二末级功率单元的输入端分别连接至所述第二电容的第一端和所述功率差分单元的第二输出端，所述第二三极管的集电极作为所述第二末级功率单元的输出端分别与所述第一电容的第二端和所述功率合成单元的第二输入端连接，所述第二三极管的发射极接地。
- 根据权利要求3所述的差分功率放大电路，其特征在于，所述 功率合成单元包括合路变压器巴伦、第三电容、第四电容和第五电容；所述合路变压器巴伦的初级线圈的第一端作为所述功率合成单元的第一输入端分别连接至所述第一末级功率单元的输出端和所述调谐电路的第一端，所述合路变压器巴伦的初级线圈的第二端作为所述功率合成单元的第二输入端分别连接至所述第二末级功率单元的输出端和所述调谐电路的第二端；所述第三电容的第一端与所述合路变压器巴伦的初级线圈的中抽头连接，所述第三电容的第二端接地；所述第四电容的第一端分别连接于所述第三电容的第一端和第一电源电压，所述第四电容的第二端接地；所述合路变压器巴伦的次级线圈的第一端作为所述功率合成单元的输出端与所述信号输出端连接，所述合路变压器巴伦的次级线圈的第二端经串联所述第五电容后接地。
- 根据权利要求4所述的差分功率放大电路，其特征在于，所述调谐电路包括第六电容和第一电感，所述第六电容的第一端作为所述调谐电路的第一端，所述第六电容的第二端与所述第一电感的第一端连接，所述第一电感的第二端作为所述调谐电路的第二端。
- 根据权利要求4所述的差分功率放大电路，其特征在于，所述输出匹配电路包括第七电容和第二电感，所述第七电容的第一端连接至所述合路变压器巴伦的次级线圈的第一端，所述第七电容的第二端连接至所述第二电感的第一端，所述第二电感的第二端接地。
- 根据权利要求2所述的差分功率放大电路，其特征在于，所述功率差分单元包括差分变压器巴伦、第一电阻、第八电容、第九电容、第十电容和第十一电容；所述差分变压器巴伦的初级线圈的第一端和第二端分别与所述第一电阻的两端连接；所述第八电容的第一端连接所述差分变压器巴伦的初级线圈的第一端，所述第八电容的第二端接地；所述差分变压器巴伦的初级线圈的第二端分别与所述第九电容的第一端、所述第十一电容的第一端以及第二电源电压，所述第九电容的第二端和所述第十一电容的第二端分别接地；所述差分变压器巴伦的次级线圈的第一端和所述差分变压器巴伦的次级线圈的第二端分别作为所述功率差分单元的第一输出端和第二输出端，并分别连接至所述第一末级功率单元和所述第二末级功率单元；所述第十电容的第一端连接所述差分变压器巴伦的次级线圈的中抽头，所述第十电容的第二端接地。
- 根据权利要求1所述的差分功率放大电路，其特征在于，所述驱动级功率单元包括第十二电容、第三三极管、第二电阻和第一偏置电路；所述第十二电容的第一端连接所述输入匹配电路，所述第十二电容的第二端与所述第三三极管的基极连接；所述第三三极管的集电极与所述功率差分单元的输入连接，所述第三三极管的发射极接地；所述第二电阻的第一端连接于所述第三三极管的基极，所述第二电阻的第二端连接至所述第一偏置电路。
- 根据权利要求3所述的差分功率放大电路，其特征在于，所述第一末级功率单元还包括第十三电容、第三电阻和第二偏置电路；所述第十三电容的一端与所述功率差分单元的第一输出端连接，所述第十三电容的第二端与所述第一三极管的基极连接，所述第三电阻的第一端与所述第一电容的第一端连接，所述第三电阻的第二端连接至所述第二偏置电路；所述第二末级功率单元还包括第十四电容、第四电阻和第三偏置电路，所述第十四电容的一端与所述功率差分单元的第二输出端连接，所述第十四电容的第二端与所述第二三极管的基极连接，所述第四电阻的第一端与所述第二电容的第一端连接，所述第四电阻的第二端连 接至所述第三偏置电路。
- 一种射频芯片，其特征在于，包括如权利要求1-9任一项所述的差分功率放大电路。
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| CN115580244A (zh) * | 2022-10-26 | 2023-01-06 | 深圳飞骧科技股份有限公司 | 差分功率放大电路及射频芯片 |
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