WO2022160892A1 - 一种推挽式射频功率放大器和电路控制方法 - Google Patents

一种推挽式射频功率放大器和电路控制方法 Download PDF

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Publication number
WO2022160892A1
WO2022160892A1 PCT/CN2021/132161 CN2021132161W WO2022160892A1 WO 2022160892 A1 WO2022160892 A1 WO 2022160892A1 CN 2021132161 W CN2021132161 W CN 2021132161W WO 2022160892 A1 WO2022160892 A1 WO 2022160892A1
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Prior art keywords
transistor
transformer
push
pull
circuit
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PCT/CN2021/132161
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English (en)
French (fr)
Inventor
温华东
戴大杰
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广州慧智微电子股份有限公司
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Publication of WO2022160892A1 publication Critical patent/WO2022160892A1/zh
Priority to US17/929,729 priority Critical patent/US20220416739A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H03F3/265—Push-pull amplifiers; Phase-splitters therefor with field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/307—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in push-pull amplifiers
    • H03F1/308—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in push-pull amplifiers using MOSFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/117—A coil being coupled in a feedback path of an amplifier stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/537—A transformer being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • the present application relates to wireless communication technologies, and in particular, to a push-pull radio frequency power amplifier and a circuit control method.
  • 5G NR (5th-Generation New Radio), as a global 5G standard based on a new air interface design based on Orthogonal Frequency Division Multiplexing (OFDM), is also very important for the next generation.
  • cellular mobile technology foundation The 3rd Generation Partnership Project (3GPP) defines the frequency range of 5G NR, from FR1 (Frequency range 1) (450MHz-6000MHz) to FR2 (Frequency range 2) (24250MHz-52600MHz).
  • 3GPP 3rd Generation Partnership Project
  • a push-pull RF power amplifier needs to adopt a cascade design of a driver stage and a power output stage.
  • the two-stage push-pull RF power amplifier is limited by the upper limit of the gain of the single-stage transistor, and in the sub 6GHz and even millimeter-wave frequency bands, the transistor grounding inductance and its own parasitic parameters will degrade the gain more and more. , the problem of insufficient gain margin will become more and more serious; in addition, in order to achieve higher gain, it is necessary to add a driving amplifier tube in the two-stage push-pull RF power amplifier, which in turn increases the design complexity of the RF power amplifier. .
  • the present application provides a push-pull radio frequency power amplifier and a circuit control method.
  • the present application provides a push-pull radio frequency power amplifier.
  • the push-pull radio frequency power amplifier includes: a coupling feedback circuit, a driver stage circuit, and a power output stage circuit; the coupling feedback circuit and the driver stage circuit and/or the the power output stage circuit connection;
  • the coupling feedback circuit is configured to generate an alternating voltage at the input terminal of the first transistor and/or the push-pull transistor; when the alternating voltage has the same direction as the voltage of the input terminal, the input terminal is realized Positive feedback of the terminal input signal; the first transistor represents the transistor in the driver stage circuit, and the push-pull transistor represents the second transistor and the third transistor forming a push-pull structure in the power output stage circuit.
  • the driver stage circuit includes a first transformer
  • the primary coil of the first transformer is coupled with the secondary coil drawn from the base of the first transistor to form a first Two transformers;
  • the coupling feedback circuit includes a secondary coil drawn from the base of the first transistor;
  • the primary coil of the first transformer and the gate of the first transistor lead out
  • the secondary coil is coupled to form a second transformer;
  • the coupling feedback circuit includes a secondary coil drawn from the gate of the first transistor.
  • the secondary coil of the second transformer is directly connected to ground
  • the secondary coil of the second transformer is connected to the ground terminal through the emitter of the first transistor
  • the secondary coil of the second transformer is connected to the ground terminal through the source of the first transistor.
  • the power output stage circuit includes a third transformer
  • the primary coil of the third transformer is coupled with the secondary coil drawn from the base of the second transistor to form a fourth transformer
  • the primary coil of the third transformer is coupled with the secondary coil drawn from the base of the third transistor to form a fifth transformer
  • the coupling feedback circuit includes a secondary coil drawn from the base of the second transistor and a secondary coil drawn from the base of the third transistor;
  • the primary coil of the third transformer is coupled with the secondary coil drawn from the gate of the second transistor to form a fourth transformer
  • the primary coil of the third transformer is coupled with the secondary coil drawn from the gate of the third transistor to form a fifth transformer
  • the coupling feedback circuit includes a secondary coil drawn from the gate of the second transistor and a secondary coil drawn from the gate of the third transistor.
  • the secondary winding of the fourth transformer is directly connected to the ground terminal; or, in the case where the second transistor is an HBT, the secondary winding of the fourth transformer is connected to the second transistor via the second transistor.
  • the emitter is connected to the ground terminal;
  • the secondary coil of the fourth transformer is connected to the ground terminal through the source of the second transistor;
  • the secondary coil of the fifth transformer is directly connected to the ground terminal;
  • the secondary coil of the fifth transformer is connected to the ground terminal through the emitter of the third transistor;
  • the secondary coil of the fourth transformer is connected to the ground terminal through the source of the third transistor.
  • the coupled feedback circuit further includes: a feedback device
  • One end of the feedback device is configured to receive the alternating voltage, and the other end of the feedback device is connected to the input end of the first transistor and/or the push-pull transistor.
  • the feedback device is any one of the following: a coupled feedback capacitor, a variable capacitor, a varactor diode, a resistor-diode series branch, an RC series branch, a resistor, and a filter.
  • the coupling feedback circuit is configured to generate an alternating voltage at the input terminal of the first transistor and/or the push-pull transistor; in the case where the alternating voltage and the input terminal voltage are in opposite directions, The negative feedback of the input signal at the input terminal is realized.
  • the coupling feedback circuit and the driving stage circuit when the coupling feedback circuit and the driving stage circuit are connected, the coupling feedback circuit and the driving stage circuit are located in different metal layers, so as to realize interlayer coupling between metal surfaces;
  • the coupling feedback circuit and the power output stage circuit are connected, the coupling feedback circuit and the power output stage circuit are located in different metal layers to realize interlayer coupling between metal surfaces.
  • Embodiments of the present application further provide a circuit control method, which is applied to a push-pull radio frequency power amplifier, and is applied to a push-pull radio frequency power amplifier, where the push-pull radio frequency power amplifier includes: a coupling feedback circuit, a driver stage circuit, and a a power output stage circuit; the coupling feedback circuit is connected to the driver stage circuit and/or the power output stage circuit; wherein the method further comprises:
  • An alternating voltage is generated at the input terminal of the first transistor and/or the push-pull transistor; when the alternating voltage has the same direction as the voltage at the input terminal, positive feedback of the input signal at the input terminal is realized;
  • the first transistor represents a transistor in the driver stage circuit
  • the push-pull transistor represents a second transistor and a third transistor that form a push-pull structure in the power output stage circuit.
  • Embodiments of the present application provide a push-pull radio frequency power amplifier and a circuit control method.
  • the push-pull radio frequency power amplifier includes: the push-pull radio frequency power amplifier includes: a coupling feedback circuit, a driver stage circuit, and a power output stage circuit; the coupling feedback circuit is connected to the driver stage circuit and/or the power output stage circuit; wherein the coupling feedback circuit is configured to generate alternating current at the input end of the first transistor and/or the push-pull transistor When the alternating voltage is in the same direction as the voltage at the input terminal, the positive feedback of the input signal at the input terminal is realized; the first transistor represents the transistor in the driving stage circuit, and the push-pull The transistors represent the second transistor and the third transistor in the power output stage circuit that form a push-pull structure.
  • the gain and output power of the push-pull RF power amplifier can be effectively improved, and the design complexity of the RF power amplifier can be reduced.
  • 1a is a schematic diagram of a circuit structure of a push-pull RF power amplifier in the related art
  • Fig. 1b is a schematic plan view of the realization structure of the first transformer T1 in the related art
  • FIG. 1c is a schematic structural diagram of the substrate stack of the first transformer T1 in the related art
  • FIG. 1d is a schematic diagram of the relationship between the gain of the radio frequency power amplifier and the output power in the related art
  • 2a is a schematic diagram 1 of a push-pull radio frequency power amplifier according to an embodiment of the present application
  • 2b is a second schematic diagram of a push-pull radio frequency power amplifier according to an embodiment of the present application.
  • FIG. 2c is a schematic diagram 3 of a push-pull radio frequency power amplifier according to an embodiment of the present application.
  • 2d is a schematic diagram 1 of a circuit structure of a push-pull RF power amplifier according to an embodiment of the present application
  • FIG. 2e is a second schematic diagram of the circuit structure of the push-pull radio frequency power amplifier according to an embodiment of the present application.
  • 2f is a third schematic diagram of the circuit structure of the push-pull radio frequency power amplifier according to the embodiment of the application;
  • Figure 2g is a schematic diagram 1 of the relationship between the induced voltage and the coil polarity generated by the electromagnetic coupling of an ideal transformer in the related art
  • Figure 2h is a schematic diagram 2 of the relationship between the induced voltage and the coil polarity generated by the electromagnetic coupling of an ideal transformer in the related art
  • 2i is a first schematic plan view of the realization structure of the first transformer T1 and the second transformer T2 in the embodiment of the application;
  • 2j is a second schematic plan view of the implementation structure of the first transformer T1 and the second transformer T2 in the embodiment of the application;
  • 2k is a third schematic plan view of the implementation structure of the first transformer T1 and the second transformer T2 in the embodiment of the application;
  • FIG. 3a is a schematic diagram of an alternating voltage at point B of a circuit node in an embodiment of the present application
  • 3b is a schematic diagram of the alternating voltage at point C of a circuit node in an embodiment of the present application.
  • 3c is a schematic diagram of the alternating voltage at point F of the circuit node in an embodiment of the present application.
  • 3d is a schematic diagram 1 of the alternating voltage at point C of a circuit node according to an embodiment of the present application;
  • 3e is a second schematic diagram of the alternating voltage at point C of a circuit node according to an embodiment of the present application.
  • 3f is a schematic diagram 3 of the alternating voltage at point C of a circuit node according to an embodiment of the present application.
  • 4a is a schematic diagram 1 of gain improvement in an embodiment of the present application.
  • FIG. 4b is a second schematic diagram of gain improvement in an embodiment of the present application.
  • 4c is a schematic diagram 3 of gain improvement in an embodiment of the present application.
  • FIG. 4d is a second schematic diagram of the circuit structure of the push-pull RF power amplifier in the embodiment of the present application.
  • FIG. 5a is a schematic plan view of different transformer stack structures in the embodiment of the present application.
  • FIG. 5b is a schematic diagram of a stacked structure in which metal traces are located on the third layer of the substrate according to an embodiment of the present application;
  • FIG. 5c is a schematic diagram of a stacked structure in which metal traces are located on the fourth layer of the substrate according to an embodiment of the present application;
  • 6a is a schematic diagram of a circuit structure in which the feedback device is a variable capacitor in an embodiment of the present application
  • 6b is a schematic diagram of a circuit structure in which the feedback device is a varactor diode according to an embodiment of the present application;
  • 6c is a schematic diagram of a circuit structure in which the feedback device is a series branch of a resistor diode in an embodiment of the present application;
  • 6d is a schematic diagram of a circuit structure in which the feedback device is an RC series branch in an embodiment of the present application;
  • 6e is a schematic diagram of a circuit structure in which the feedback device is a resistor in an embodiment of the present application
  • 6f is a schematic diagram of a circuit structure in which the feedback device is a filter in an embodiment of the present application.
  • 6g is a schematic diagram 1 of a circuit structure in which the feedback device is an L-type low-pass filter in an embodiment of the present application;
  • 6h is a schematic diagram 2 of a circuit structure in which the feedback device is an L-type high-pass filter in an embodiment of the application;
  • 6i is a schematic diagram 1 of a circuit structure in which the feedback device is a pi-type filter in an embodiment of the present application;
  • 6j is a schematic diagram 2 of the circuit structure in which the feedback device is a pi-type filter in an embodiment of the present application;
  • FIG. 7a is a schematic diagram of a circuit structure in which the secondary coil of the second transformer T2 is directly connected to the ground according to an embodiment of the present application;
  • 7b is a schematic plan view of the secondary coil of the second transformer T2 being directly connected to the ground according to the embodiment of the application;
  • 7c is a schematic plan view of the structure when the output terminal to the input terminal is negative feedback in the embodiment of the present application;
  • FIG. 8a is a third schematic diagram of a circuit structure of a push-pull radio frequency power amplifier according to an embodiment of the present application.
  • FIG. 8b is a schematic plan view of the implementation structure of different transformers in the embodiment of the application.
  • 8c is a schematic diagram of the circuit structure in which the secondary coils of the fourth transformer T4 and the fifth transformer T5 are directly connected to the ground terminal according to the embodiment of the application;
  • FIG. 8d is a schematic plan view of the secondary coils of the fourth transformer T4 and the fifth transformer T5 being directly connected to the ground according to the embodiment of the present application.
  • FIG. 1a is a schematic diagram of the circuit structure of a push-pull RF power amplifier in the related art.
  • the HBT process is used as an example to illustrate. Since the gain of a single stage is about 10-18dB, in order to provide sufficient gain, it is necessary to use Cascaded design of driver stage circuit and power output stage circuit.
  • the driver stage circuit includes: a first input matching capacitor C1, a first transistor Q1, a first transformer T1, a first bypass coupling capacitor C3 and a grounding inductor L1; wherein, points E, B and C correspond to the first transistor Q1 respectively The emitter, base, and collector of ; L1 represents the equivalent inductance generated by grounding, not the real inductance in the driver circuit.
  • the power output stage circuit includes: a second input matching capacitor C4, a second transistor Q2, a third input matching capacitor C5, a third transistor Q3, a third transformer T3, a second bypass coupling capacitor C6 and a load RL.
  • the first bypass coupling capacitor C3 and the second bypass coupling capacitor C6 can couple the AC component in the DC power supply to the ground, and play the role of purifying the DC power supply.
  • one end of the first input matching capacitor C1 is configured to receive the input signal RFin, and the other end is connected to the base of the first transistor Q1; the bias current I1 of the driver stage provides bias for the base of the first transistor Q1
  • the emitter of the first transistor Q1 is connected to the ground terminal; the collector of the first transistor Q1 is connected to one end of the primary coil of the first transformer T1, and the other end of the primary coil of the first transformer T1 is connected to the first DC power supply Vcc1 is powered and coupled to ground via the bypass coupling C3 capacitor.
  • the secondary coil of the first transformer T1 is connected to the base input terminals of the second transistor Q2 and the third transistor Q3 via the second input matching capacitor C4 and the third input matching capacitor C5, respectively, and an external tap is drawn in the middle of the coil or at other positions.
  • the tap can be grounded, open-circuited, or connected to any load; exemplarily, Figure 1a shows the situation where the tap is grounded.
  • the first power stage bias current I2 provides bias current for the base of the second transistor Q2; the second power stage bias current I3 provides bias current for the base of the third transistor Q3; the second transistor Q2 and the third transistor
  • the emitter of Q3 is grounded; the collector of the second transistor Q2 and the collector of the third transistor Q3 are respectively connected to the two terminals of the primary coil of the third transformer T3; the primary coil of the third transformer T3 leads to a tap in the middle of the coil or other positions
  • the second DC power supply Vcc2 is connected to supply power, and is grounded through the bypass coupling capacitor C6; one end of the secondary coil of the third transformer T3 is grounded, and the other end is connected to the load RL to output a signal RFout.
  • the third transformer T3 can realize the power synthesis of the second transistor Q2 and the third transistor Q3, output the synthesized power to the load RL, and match the impedance to the impedance required by the application end; here, the impedance is generally 50Ohm, but not limited to 50Ohm.
  • the first transformer T1 provides power distribution and impedance transformation from the balanced end to the unbalanced end
  • the third transformer T3 provides power synthesis and impedance transformation from the unbalanced end to the balanced end.
  • Fig. 1b is a schematic plan view of the realization structure of the first transformer T1 in the related art.
  • the first transformer T1 is composed of two winding inductances coupled to each other, and the primary coil is connected to the first transformer from the collector of the first transistor Q1.
  • the current power supply Vcc1 the secondary coil is connected to the base input terminals of the second transistor Q2 and the third transistor Q3, and an external tap is drawn in the middle of the coil or at other positions.
  • FIG. 1c is a schematic structural diagram of the first transformer T1 substrate stack in the related art. As shown in FIG.
  • the first transformer T1 substrate stack includes: a metal layer 1, a metal layer 2 and a metal ground layer; wherein, the metal layer 1 It is connected with the metal layer 2 through the metal connection hole 1 of the dielectric layer 1; the metal layer 2 and the metal ground layer are connected through the metal connection hole 2 of the dielectric layer 2.
  • the metal trace indicated by the solid line is located in the substrate metal layer 1; the metal trace indicated by the dotted line is located in the substrate metal layer 2, and the metal layers are connected through metal vias.
  • Fig. 1d is a schematic diagram showing the variation relationship between the gain of the RF power amplifier and the output power in the related art, wherein the variation relationship curve is a RF power amplifier in the frequency band n79 (4400MHz-5000MHz) designed based on the circuit structure of Fig. 1a, and its gain varies with the output power.
  • Power variation curve in Figure 1d, the horizontal axis represents the output power, in dBm, and the vertical axis represents the gain of the RF power amplifier, in dB; the solid line indicates that when the frequency is 4400MHz, its gain varies with the output power.
  • Change relationship curve; dotted line represents the change relationship curve of its gain with output power when the frequency is 4700MHz; dotted line represents the change relationship curve of its gain with output power when the frequency is 5000MHz.
  • embodiments of the present application provide a push-pull radio frequency power amplifier and a circuit control method.
  • FIG. 2a is a schematic diagram 1 of a push-pull RF power amplifier according to an embodiment of the present application.
  • the push-pull RF power amplifier includes: a coupling feedback circuit 20, a driver stage circuit 21 and a power output stage circuit 22; a coupling feedback circuit 22; The circuit 20 is connected with the driver stage circuit 21 ; the driver stage circuit is connected with the power output stage circuit 22 .
  • FIG. 2b is a second schematic diagram of a push-pull radio frequency power amplifier according to an embodiment of the application; as shown in FIG. 2b, the push-pull radio frequency power amplifier includes: a coupling feedback circuit 20, a driver stage circuit 21 and a power output stage circuit 22; The circuit 20 is connected with the power output stage circuit 22 ; the driver stage circuit is connected with the power output stage circuit 22 .
  • the push-pull radio frequency power amplifier includes: a coupling feedback circuit 20, a driver stage circuit 21 and a power output stage circuit 22; the coupling feedback circuit 20 and the driver stage circuit 21 is connected with the power output stage circuit 22 ; the driver stage circuit is connected with the power output stage circuit 22 .
  • the coupling feedback circuit 20 is configured to generate an alternating voltage at the input end of the first transistor Q1 and/or the push-pull transistor; when the alternating voltage and the voltage of the input end have the same direction, the positive feedback of the input signal at the input end is realized.
  • the first transistor Q1 represents the transistor in the driver stage circuit 21, and the push-pull transistor represents the second transistor Q2 and the third transistor Q3 in the push-pull structure in the power output stage circuit 22.
  • the first transistor Q1 and the push-pull transistor may be a solid-state semiconductor device, having multiple functions such as detection, amplification, and signal modulation; for example, the first transistor Q1 may include: HBT or MOSFET; push-pull Pull transistors can also include: HBTs or MOSFETs.
  • the coupled feedback circuit 20 is configured to generate an alternating voltage, which may represent a voltage whose instantaneous value changes with time and direction; for example, the alternating voltage may be of different magnitudes , sinusoidal AC voltages in different directions; it can be determined according to the actual circuit structure, which is not limited in the embodiments of the present application.
  • the driver stage circuit 21 is connected with the power output stage circuit 22 to form a two-stage cascade structure; the driver stage circuit 21 may represent an intermediate circuit that amplifies the input signal; that is, it can drive the signal by amplifying the signal.
  • the second transistor Q2 and the third transistor Q3 of the power output stage circuit 22 operate.
  • the second transistor Q2 and the third transistor Q3 forming the push-pull structure in the power output stage circuit 22 may represent two HBT transistors or MOSFET transistors; here, the second transistor Q2 and the third transistor Q3 are respectively responsible for For the waveform amplification task of the positive and negative half cycles, when the power output stage circuit 22 is working, only one of the two symmetrical second transistors Q2 and the third transistor Q3 is turned on at a time, thereby reducing the conduction loss.
  • the coupling feedback circuit 20 when the coupling feedback circuit 20 is connected to the driving stage circuit 21, if the alternating voltage generated by the coupling feedback circuit 20 is in the same direction as the voltage at the input terminal of the first transistor Q1, so that the input terminal of the first transistor Q1 is in the same direction.
  • the voltage and the alternating voltage are superimposed in the same direction; positive feedback from the output end of the first transistor Q1 to the input end can be realized; further, the signal strength of the input signal is improved.
  • the coupling feedback circuit 20 when the coupling feedback circuit 20 is connected to the power output stage circuit 22, if the alternating voltage generated by the coupling feedback circuit 20 is in the same direction as the voltage at the input terminal of the second transistor Q2, the second transistor Q2 input The terminal voltage and the alternating voltage are superimposed in the same direction; the positive feedback from the output terminal of the second transistor Q2 to the input terminal can be realized; further, the signal strength of the input signal is improved; similarly, if the alternating voltage generated by the coupling feedback circuit 20 and the third transistor The voltage directions of the input terminals of Q3 are the same, so that the voltage of the input terminal of the third transistor Q3 and the alternating voltage are superimposed in the same direction; the positive feedback from the output terminal of the third transistor Q3 to the input terminal can be realized; further, the signal strength of the input signal can be improved.
  • the signal strength of the input signal can be effectively improved;
  • the gain and output power of the push-pull RF power amplifier can be effectively improved, and the design complexity of the RF power amplifier can be reduced.
  • FIG. 2d is a schematic diagram 1 of the circuit structure of the push-pull RF power amplifier according to the embodiment of the present application, and the HBT process is used as an example to illustrate; the push-pull RF power amplifier in FIG. 2d is based on the push-pull RF power amplifier of FIG. 2a . 2d shows the specific connection relationship between the coupling feedback circuit 20, the driving stage circuit 21 and the power output stage circuit 22 when the coupling feedback circuit 20 is connected with the driving stage circuit 21.
  • the first transformer T1 is formed by coupling the primary coil drawn from the collector of the first transistor Q1 and the secondary coil drawn from the bases of the second transistor Q2 and the third transistor Q3; the driving stage circuit 21 is connected to the power The output stage circuit 22 is connected through a first transformer T1; wherein the first transformer T1 can transmit both signals and power.
  • the primary coil of the first transformer T1 is coupled with the secondary coil drawn from the base of the first transistor Q1 to form the second transformer T2;
  • the coupling feedback circuit 20 includes The secondary coil drawn from the base of the first transistor Q1. That is, the coupling feedback circuit 20 is connected to the driver stage circuit 21 .
  • the positive electrode of the secondary coil of the second transformer T2 is connected to the input end of the first transistor Q1, and the negative electrode is connected to the ground end; one end of the primary coil of the second transformer T2 is connected to the first DC power supply Vcc1 for power supply .
  • the driver stage bias current I1 provides bias current for the base of the first transistor Q1; the first power stage bias current I2 provides bias current for the base of the second transistor Q2; the second power stage bias current I3 A bias current is provided to the base of the third transistor Q3.
  • FIG. 2e is a second schematic diagram of the circuit structure of the push-pull RF power amplifier according to the embodiment of the present application. As shown in FIG. 2e, the circuit structure diagram is based on FIG. 2d, and the secondary coil of the first transformer T1 is not grounded.
  • FIG. 2f is a third schematic diagram of the circuit structure of the push-pull RF power amplifier according to the embodiment of the application. As shown in FIG. 2f, the circuit structure diagram is based on FIG. The tap of the capacitor is connected to ground.
  • the first transformer T1 , the second transformer T2 and the third transformer T3 in FIGS. 2 d , 2 e and 2 f may be transformers equivalent to balun converters.
  • a transformer is a device that uses the principle of electromagnetic induction to change AC and voltage.
  • the main components are the primary coil, the secondary coil and the iron core (magnetic core).
  • the main functions of the transformer are: voltage transformation, current transformation, impedance transformation, isolation, voltage regulation, etc.
  • the primary coil represents the input end of the transformer, which is generally connected to the DC power supply.
  • the primary coil absorbs energy from the DC power supply and transfers the energy to the secondary coil in the form of electromagnetic induction; the secondary coil represents the output end of the transformer, and the secondary coil receives the energy. After the electromagnetic induction of the primary coil, an alternating voltage is generated in the secondary coil.
  • Figure 2g is a schematic diagram of the relationship between the induced voltage and coil polarity generated by the electromagnetic coupling of an ideal transformer in the related art
  • Figure 2h is the electromagnetic coupling of an ideal transformer in the related art.
  • Schematic diagram 2 of the relationship between the induced voltage and the coil polarity as shown in Figure 2g and Figure 2h, T represents the balun converter, Ui is the input voltage, and Uo is the induced voltage, which can be adjusted by adjusting the polarity of the primary and secondary coils. It can realize the induced voltage Uo with the same or opposite phase as the input voltage Ui.
  • the coupled feedback circuit 20 further includes: a feedback device; one end of the feedback device is configured to receive an alternating voltage, and the other end of the feedback device is connected to the input end of the first transistor and/or the push-pull transistor.
  • one end of the feedback device is connected to the secondary coil in the coupling feedback circuit 20, and the other end is connected to the input end of the first transistor Q1; further, when the coupling feedback circuit generates an alternating current at the input end of the first transistor Q1 When changing the voltage, the alternating voltage can be received through the feedback device, and the alternating voltage can be sent to the input terminal of the first transistor Q1.
  • the feedback device is a coupling feedback capacitor C2, one end of the coupling feedback capacitor C2 is configured to receive the alternating voltage generated by the second transformer T2, and the other end of the coupling feedback capacitor C2 is connected to the input end of the first transistor Q1.
  • the position where the coupling feedback capacitor C2 is connected to the input end of the first transistor Q1 may be before or after the first input matching capacitor C1.
  • FIG. 2i is a first schematic plan view of the realization structure of the first transformer T1 and the second transformer T2 in the embodiment of the application.
  • the first transformer T1 and the second transformer T2 are composed of two winding inductances coupled to each other.
  • the primary coil of a transformer T1 is connected to the first DC power supply Vcc1 from the collector of the first transistor Q1, and the secondary coil of the first transformer T1 is connected to the base input terminals of the second transistor Q2 and the third transistor Q3, and is in the middle of the coil or External taps can be drawn from other positions.
  • the grounding is used as an example.
  • One end of the second transformer T2 is connected to the coupling feedback capacitor C2, and the other end is connected to the emitter of the first transistor Q1.
  • the metal wiring indicated by the solid line is located in the substrate metal layer 1; the metal wiring indicated by the dotted line is located in the substrate metal layer 2, and the metal layers are connected by metal vias.
  • FIG. 2j is a second schematic plan view of the implementation structure of the first transformer T1 and the second transformer T2 in the embodiment of the application. As shown in FIG. 2j, the bases of the second transistor Q2 and the third transistor Q3 pass through the secondary of the first transformer T1. The coil connects capacitor C18 to ground.
  • FIG. 2k is a third schematic plan view of the implementation structure of the first transformer T1 and the second transformer T2 in the embodiment of the application; as shown in FIG. 2k, the bases of the second transistor Q2 and the third transistor Q3 no longer pass through the first transformer T1.
  • the secondary coil leads out the tap to ground.
  • the alternating voltage of the base input point B of Q1 and the alternating voltage of the collector output point C are close to a 180° phase difference; by introducing a coupling feedback circuit 20, that is, the secondary coil drawn from the base of the first transistor Q1 makes the second transformer T2 generate electromagnetic coupling, and further, at point F, a phase difference close to 180° from point C can be generated, that is, it is input with the input terminal of the first transistor Q1.
  • the signal is close to the in-phase alternating voltage.
  • the input signal strength can be greatly improved due to the in-phase superposition of the signal, which is equivalent to adding an output to the input positive feedback in the first transistor Q1 , under the condition that the gains of the first transistor Q1, the second transistor Q2 and the third transistor Q3 remain unchanged, the present application can greatly improve the gain and output power of the entire power amplifier.
  • FIG. 3a is a schematic diagram of the alternating voltage at point B of the circuit node in the embodiment of the application
  • FIG. 3b is a schematic diagram of the alternating voltage at the point C of the circuit node in the embodiment of the application
  • Schematic diagram of the voltage here, Fig. 3a, Fig. 3b and Fig. 3c all show the schematic diagram of the time domain waveform of the alternating voltage at the three points of the circuit nodes B, C and F.
  • the horizontal axis represents time
  • the unit is ms
  • the vertical axis represents the voltage value
  • the unit is V
  • the waveform diagram represents the alternating voltage of the circuit nodes B, C, and F at the frequency of 4400MHz, 4700MHz and 5000MHz, respectively. Waveform diagram.
  • FIG. 3d is a schematic diagram 1 of the alternating voltage at point C of the circuit node according to the embodiment of the application
  • FIG. 3e is a schematic diagram 2 of the alternating voltage at point C of the circuit node according to the embodiment of the application
  • FIG. 3f is the embodiment of the application.
  • Schematic diagram 3 of the alternating voltage at point C of the circuit node of the example in which, the horizontal axis represents time, the unit is ms, and the vertical axis represents the voltage value, the unit is V;
  • Figure 3d, Figure 3e and Figure 3f show that the frequency is 4400MHz, 4700MHz in turn In the case of and 5000MHz, the waveform diagram of the alternating voltage at point C of the circuit node.
  • the dotted line represents the time-domain waveform diagram before improvement
  • the solid line represents the time-domain waveform diagram after improvement
  • FIG. 4a is a schematic diagram 1 of performing gain improvement in an embodiment of the application
  • FIG. 4b is a schematic diagram 2 of performing gain improvement in an embodiment of the application
  • FIG. 4c is a schematic diagram 3 of performing gain improvement in an embodiment of the application
  • the horizontal axis represents the output power, in dBm
  • the vertical axis represents the gain of the RF power amplifier, in dB
  • Figure 4a, Figure 4b, and Figure 4c show the schematic diagrams of gain improvement at frequencies of 4400MHz, 4700MHz, and 5000MHz in turn .
  • the dotted line represents the gain waveform before the improvement
  • the solid line represents the gain waveform after the improvement
  • the present application can be well applied to the design of radio frequency power amplifiers in the sub 6GHz to FR2 millimeter wave frequency band.
  • CMOS Complementary Metal Oxide Semiconductor
  • GaAs Gallium Arsenide
  • pHEMT High Electron Mobility Transistor
  • SOI Silicon-On -Insulator
  • FIG. 4d is a second schematic diagram of the circuit structure of the push-pull RF power amplifier in the embodiment of the application, and the MOSFET process is used as an example for illustration; the push-pull RF power amplifier in FIG. 4d is based on the push-pull RF power amplifier in FIG. 2d. 4d shows the specific connection relationship between the coupling feedback circuit 20, the driving stage circuit 21 and the power output stage circuit 22 when the coupling feedback circuit 20 is connected to the driving stage circuit 21 and the power output stage circuit 22.
  • the gate G, source S and drain D of the MOSFET in FIG. 4d correspond to the base B, the emitter E and the first transistor Q1, the first transistor Q2 and the first transistor Q3 in FIG. 2d, respectively.
  • Collector C; other circuit structures are the same as in Figure 2d.
  • the primary coil of the first transformer is coupled with the secondary coil drawn from the gate of the first transistor to form a second transformer; the coupling feedback circuit includes the gate of the first transistor Outgoing secondary coil.
  • the secondary winding of the second transformer is directly connected to the ground terminal; or, in the case where the first transistor is a MOSFET, the secondary winding of the second transformer is connected to the ground terminal via the source of the first transistor.
  • the power output stage circuit includes a third transformer; in the case that the second transistor and the third transistor are MOSFETs, the primary coil of the third transformer and the secondary lead from the gate of the second transistor The coils are coupled to form a fourth transformer; the primary coil of the third transformer is coupled with the secondary coil drawn from the gate of the third transistor to form a fifth transformer; the coupling feedback circuit includes the secondary coil drawn from the gate of the second transistor and the secondary coil drawn from the gate of the third transistor. The secondary coil drawn from the gate of the three transistors.
  • the secondary winding of the fourth transformer is directly connected to the ground terminal; or, in the case where the second transistor is a MOSFET, the secondary winding of the fourth transformer is connected to the ground terminal through the source of the second transistor;
  • the secondary coil of the fifth transformer is directly connected to the ground terminal;
  • the secondary coil of the fourth transformer is connected to the ground terminal through the source of the third transistor.
  • the coupling feedback circuit and the driving stage circuit when the coupling feedback circuit and the driving stage circuit are connected, the coupling feedback circuit and the driving stage circuit are located in different metal layers, so as to realize the interlayer coupling between the metal planes.
  • the second transformer T2 that is, the secondary coil of the coupling feedback circuit and the primary coil of the driving stage circuit are located in different metal layers, so as to realize the interlayer coupling between the metal surfaces; here, the corresponding substrate stack
  • the layer structure may include two layers of metal traces or more than three layers of metal traces.
  • 5a is a schematic plan view of different transformer stack structures in an embodiment of the present application; wherein, the metal traces indicated by solid lines are located in the first metal layer of the substrate; the metal traces indicated by dashed lines are located in the second metal layer of the substrate; The metal wiring indicated by the dot-dash line is located on the third or fourth metal layer of the substrate.
  • FIG. 5b is a schematic diagram of a laminated structure in which metal traces are located on the third layer of the substrate in an embodiment of the application
  • FIG. 5c is a schematic diagram of a laminated structure in which metal traces are located in the fourth layer of the substrate in an embodiment of the application; wherein, the metal layer They are connected through metal connection holes.
  • multiple layers of metal can be used to connect through through holes to form a thick metal layer to reduce metal loss.
  • the circuit structure of the push-pull RF power amplifier proposed in the embodiment of the present application is based on the first transformer T1 in FIG. 1a, and a coupling feedback circuit 20 is introduced, wherein the coupling feedback circuit 20 includes The secondary coil and the feedback device of the second transformer T2; the feedback device in FIG. 2d is the feedback coupling capacitor C2.
  • the feedback device is any one of the following: a coupled feedback capacitor, a variable capacitor, a varactor diode, a resistor-diode series branch, an RC series branch, a resistor, and a filter. That is to say, the feedback device may be the feedback coupling capacitor C2 in FIG. 2d, or any one of a variable capacitor, a varactor diode, a resistor-diode series branch, an RC series branch, a resistor, and a filter. In some embodiments, circuit diagrams corresponding to the feedback device are shown in FIGS. 6 a to 6 j .
  • FIG. 6a is a schematic diagram of a circuit structure in which the feedback device is a variable capacitor in an embodiment of the present application. As shown in FIG. 6a, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with the variable capacitor C11 on the basis of FIG. 2d.
  • FIG. 6b is a schematic diagram of a circuit structure in which the feedback device is a varactor diode in an embodiment of the present application. As shown in FIG. 6b , the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with the varactor diode D1 on the basis of FIG. 2d .
  • FIG. 6c is a schematic diagram of the circuit structure in which the feedback device is a resistor-diode series branch in an embodiment of the present application. As shown in FIG. 6c, the circuit structure diagram is based on FIG. 2d by replacing the feedback device from the feedback coupling capacitor C2 with the resistor R1 diode. D2 series branch.
  • Fig. 6d is a schematic diagram of the circuit structure in which the feedback device is an RC series branch in an embodiment of the application. As shown in Fig. 6d, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with the R2C12 series branch on the basis of Fig. 2d .
  • FIG. 6e is a schematic diagram of a circuit structure in which the feedback device is a resistor in an embodiment of the present application. As shown in FIG. 6e, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with a resistor R3 on the basis of FIG. 2d.
  • FIG. 6f is a schematic diagram of a circuit structure in which the feedback device is a filter in an embodiment of the present application. As shown in FIG. 6f, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with a filter on the basis of FIG. 2d.
  • the filter shown in FIG. 6f may be an L-type high-pass filter, an L-type low-pass filter, a pi-type filter or other types of filters.
  • Fig. 6g is a schematic diagram 1 of the circuit structure in which the feedback device is an L-type low-pass filter according to the embodiment of the application. As shown in Fig. 6g, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with L2C13 on the basis of Fig. 2d L-type low-pass filter.
  • Fig. 6h is a schematic diagram 2 of the circuit structure in which the feedback device is an L-type high-pass filter in the embodiment of the application. As shown in Fig. 6h, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with the L3C14 on the basis of Fig. 2d L-type high-pass filter.
  • Fig. 6i is a schematic diagram of the circuit structure of the first embodiment of the application in which the feedback device is a pi filter. As shown in Fig. 6i, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with the pi of L4C15L5 on the basis of Fig. 2d type filter.
  • Fig. 6j is a schematic diagram of the second circuit structure in which the feedback device is a pi-type filter in the embodiment of the application. As shown in Fig. 6j, the circuit structure diagram replaces the feedback device from the feedback coupling capacitor C2 with the pi of C16L6C17 on the basis of Fig. 2d type filter.
  • the secondary coil of the second transformer is directly connected to the ground terminal; or, the secondary coil of the second transformer is connected to the ground terminal through the emitter of the first transistor.
  • FIG. 7a is a schematic diagram of a circuit structure in which the secondary coil of the second transformer T2 is directly connected to the ground according to an embodiment of the application
  • FIG. 7b is a schematic plan view of the secondary coil of the second transformer T2 directly connected to the ground according to an embodiment of the application; wherein , the metal traces indicated by solid lines are located in the first metal layer of the substrate; the metal traces indicated by dotted lines are located in the second metal layer of the substrate; the metal layers are connected through metal connection holes.
  • the coupling feedback circuit is configured to generate an alternating voltage at the input terminal of the first transistor; in the case that the alternating voltage is opposite to the voltage of the input terminal, the negative feedback of the input signal at the input terminal is realized.
  • FIG. 7c is a schematic plan view of the structure when the output terminal and the input terminal are negative feedback in an embodiment of the present application.
  • the metal traces indicated by solid lines are located in the first metal layer of the substrate; the metal traces indicated by dashed lines are located in the second metal layer of the substrate; the metal layers are connected through metal connection holes.
  • FIG. 8a is a schematic diagram 3 of a circuit structure of a push-pull RF power amplifier according to an embodiment of the present application, taking the HBT process as an example for illustration; the push-pull RF power amplifier in FIG. 8a is based on the push-pull RF power amplifier in FIG. 2a .
  • 8a shows the specific connection relationship between the coupling feedback circuit 20, the driving stage circuit 21 and the power output stage circuit 22 when the coupling feedback circuit 20 is connected to the driver stage circuit 21 and the power output stage circuit 22.
  • the primary coil of the third transformer is coupled with the secondary coil drawn from the base of the second transistor to form a fourth transformer T4; the primary coil of the third transformer is connected to the third transistor.
  • the secondary coils drawn from the base are coupled to form a fifth transformer T5; the coupling feedback circuit includes a secondary coil drawn from the base of the second transistor and a secondary coil drawn from the base of the third transistor.
  • the positive electrode of the secondary coil of the fourth transformer T4 is connected to the input end of the second transistor Q2, and the negative electrode is connected to the ground end; the positive electrode of the secondary coil of the fifth transformer T5 is connected to the input end of the third transistor Q3 Connect the negative pole to the ground terminal.
  • the primary coil of the third transformer T3 leads out a tap in the middle of the coil or other positions to connect to the second DC power supply Vcc2 for power supply.
  • the feedback devices included in the coupling feedback circuit 20 are a coupling feedback capacitor C8 and a coupling feedback capacitor C9; wherein, one end of the coupling feedback capacitor C8 is configured to receive the alternating voltage generated by the fourth transformer T4, and the other end is connected to the second The input end of the transistor Q2 is connected; one end of the coupling feedback capacitor C9 is configured to receive the alternating voltage generated by the fifth transformer T5, and the other end is connected to the input end of the third transistor Q3.
  • the position where the coupling feedback capacitor C8 is connected to the input end of the second transistor Q2 may be before or after the second input matching capacitor C4.
  • the position where the coupling feedback capacitor C9 is connected to the input terminal of the third transistor Q3 may be before or after the third input matching capacitor C5.
  • Figure 8a shows the case where the coupling feedback capacitor C8 and the coupling feedback capacitor C9 are connected in front of the input matching capacitor.
  • FIG. 8b is a schematic plan view of the implementation structure of different transformers in the embodiment of the application.
  • the solid line represents the wiring of the metal layer 1 and the metal ground layer
  • the dotted line represents the wiring of the metal layer 2
  • metal through holes pass between the metal layers. connection, and the metal layers are connected through metal vias.
  • the secondary coil of the fourth transformer T4 is directly connected to the ground terminal; or, the secondary coil of the fourth transformer T4 is connected to the ground terminal through the emitter of the second transistor; the secondary coil of the fifth transformer T5 It is directly connected to the ground terminal; or, the secondary coil of the fifth transformer T5 is connected to the ground terminal through the emitter of the third transistor.
  • FIG. 8a shows the secondary coil of the fourth transformer T4 and the fifth transformer T5.
  • the secondary coil of the fourth transformer T4 is grounded through the emitter of the second transistor Q2. terminal is connected, and the secondary coil of the fifth transformer T5 is connected to the ground terminal through the emitter of the third transistor Q3.
  • FIG. 8c shows the secondary coils of the fourth transformer T4 and the fifth transformer T5 are directly connected to the ground terminal;
  • FIG. 8d shows the secondary coils of the fourth transformer T4 and the fifth transformer T5 in the embodiment of the application and the ground.
  • a schematic plan view of direct connection wherein the metal traces indicated by solid lines are located in the first metal layer of the substrate; the metal traces indicated by dashed lines are located in the second metal layer of the substrate; the metal layers are connected through metal connection holes.
  • the coupling feedback circuit 20 further includes: a feedback device; one end of the feedback device is configured to receive an alternating voltage, and the other end of the feedback device is connected to the input end of the push-pull transistor.
  • the coupling feedback circuit 20 is the same as the coupling feedback circuit in the above-mentioned embodiment, which is not repeated here.
  • the coupled feedback circuit is configured to generate an alternating voltage at the input terminal of the push-pull transistor; in the case where the alternating voltage is opposite to the voltage at the input terminal, negative feedback of the input signal at the input terminal is achieved.
  • the winding direction of the secondary coil in the coupled feedback circuit can be changed; the positive electrode of the secondary coil is grounded, and the negative electrode is connected to the input end of the push-pull transistor;
  • the alternating voltage with the opposite direction of the terminal voltage realizes the negative feedback of the input signal at the input terminal.
  • the coupling feedback circuit and the power output stage circuit are located in different metal layers, so as to realize the interlayer coupling between the metal planes.
  • the secondary coil of the coupling feedback circuit and the primary coil of the power output stage circuit are located in different metal layers to realize interlayer coupling between the metal surfaces; here, the corresponding substrate stack structure may include two layers
  • the metal wiring may also include more than three layers of metal wiring; the schematic diagrams of the stacked structure of the fourth transformer T4 and the fifth transformer T5 are shown in FIG. 5b and FIG. 5c.
  • Embodiments of the present application further provide a circuit control method, which is applied to a push-pull radio frequency power amplifier, and is applied to a push-pull radio frequency power amplifier.
  • the push-pull radio frequency power amplifier includes: a coupling feedback circuit, a driver stage circuit, and a power output stage circuit; the coupling feedback circuit is connected with the driver stage circuit and/or the power output stage circuit; wherein, the circuit control method further includes:
  • An alternating voltage is generated at the input terminal of the first transistor and/or the push-pull transistor; when the alternating voltage is in the same direction as the voltage at the input terminal, the positive feedback of the input signal at the input terminal is realized;
  • the push-pull transistor refers to the second transistor and the third transistor that form a push-pull structure in the power output stage circuit.
  • circuit structure diagram of the push-pull radio frequency power amplifier proposed in the embodiment of the present application is not limited to the circuit structure described in the above-mentioned embodiment, and is also applicable to the circuit structure of other push-pull radio frequency power amplifier. Examples are not limited.

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Abstract

本申请提供了一种推挽式射频功率放大器和电路控制方法，所述推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；所述耦合反馈电路与所述驱动级电路和/或所述功率输出级电路连接；其中，所述耦合反馈电路配置为在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相同的情况下，实现所述输入端输入信号的正反馈；所述第一晶体管表示所述驱动级电路中的晶体管，所述推挽式晶体管表示所述功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。

Description

一种推挽式射频功率放大器和电路控制方法
相关申请的交叉引用
本申请基于申请号为202110129749.6、申请日为2021年01月29日的中国专利申请提出，申请人为广州慧智微电子有限公司，申请名称为“一种推挽式射频功率放大器和电路控制方法”的技术方案，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及无线通信技术，尤其涉及一种推挽式射频功率放大器和电路控制方法。
背景技术
移动通信技术已经演进至第五代，5G NR(5th-Generation New Radio)作为基于正交频分复用(Orthogonal Frequency Division Multiplexing，OFDM)的全新空口设计的全球性5G标准，也是下一代非常重要的蜂窝移动技术基础。第三代合作伙伴计划(3rd Generation Partnership Project，3GPP)针对5G NR的频率范围的定义，从FR1(Frequency range 1)(450MHz-6000MHz)到FR2(Frequency range 2)(24250MHz-52600MHz)。由于电磁波在空气中的传输衰减随频率增大而明显增高，所以5G NR进入6GHz以下(sub 6GHz)和毫米波频段时，一方面通信设备需要提供更大的发射功率以保证信号传输距离，另一方面，更高的数据传输速率要求更大的信号带宽、更复杂的调制方式，这些都对射频功率放大器提出了越来越高的技术要求，包括在高频段提供更高的增益和输出功率以保障信号覆盖范围、更低的邻道功率抑制比(Adjacent Channel Power Ratio，ACPR)以最大限度地减小频谱再生并保持调制的精确性等等。
相关技术中，为了提供足够的增益，推挽式射频功率放大器需要采用驱动级和功率输出级的级联设计。然而，两级推挽式射频功率放大器，受限于单级晶体管的增益上限，加上在sub 6GHz乃至毫米波频段，晶体管接地电感以及其本身寄生参数对增益的恶化会变得越来越明显，导致增益裕量不足的问题会越来越严重；此外，为了实现更高的增益，需要在两级推挽式射频功率放大器中再增加驱动放大管，进而，增加射频功率放大器的设计复杂度。
发明内容
本申请提供一种推挽式射频功率放大器和电路控制方法。
本申请的技术方案是这样实现的：
本申请提供一种推挽式射频功率放大器，所述推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；所述耦合反馈电路与所述驱动级电路和/或所述功率输出级电路连接；
其中，所述耦合反馈电路配置为在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相同的情况下，实现所述输入端输入信号的正反馈；所述第一晶体管表示所述驱动级电路中的晶体管，所述推挽式晶体管表示所述功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。
在一些实施例中，所述驱动级电路包括第一变压器；
在所述第一晶体管为异质结双极晶体管(Heterojunction Bipolar Transistor，HBT)的情况下，所述第一变压器的初级线圈与所述第一晶体管基极引出的次级线圈进行耦合，形成第二变压器；所述耦合反馈电路包括所述第一晶体管基极引出的次级线圈；
在所述第一晶体管为金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)的情况下，所述第一变压器的初级线圈与所述第一晶体管栅极引出的次级线圈进行耦合，形成第二变压器；所述耦合反馈电路包括所述第一晶体管栅极引出的次级线圈。
在一些实施例中，所述第二变压器的次级线圈直接与接地端连接；
或，在所述第一晶体管为HBT的情况下，所述第二变压器的次级线圈经所述第一晶体管发射极与接地端连接；
或，在所述第一晶体管为MOSFET的情况下，所述第二变压器的次级线圈经所述第一晶体管源极与接地端连接。
在一些实施例中，所述功率输出级电路包括第三变压器；
在所述第二晶体管和所述第三晶体管为HBT的情况下，所述第三变压器的初级线圈与所述第二晶体管基极引出的次级线圈进行耦合，形成第四变压器；
所述第三变压器的初级线圈与所述第三晶体管基极引出的次级线圈进行耦合，形成第五变压器；
所述耦合反馈电路包括所述第二晶体管基极引出的次级线圈和所述第三晶体管基极引出的次级线圈；
在所述第二晶体管和所述第三晶体管为MOSFET的情况下，所述第三变压器的初级线圈与所述第二晶体管栅极引出的次级线圈进行耦合，形成第四变压器；
所述第三变压器的初级线圈与所述第三晶体管栅极引出的次级线圈进行耦合，形成第五变压器；
所述耦合反馈电路包括所述第二晶体管栅极引出的次级线圈和所述第三晶体管栅极引出的次级线圈。
在一些实施例中，所述第四变压器的次级线圈直接与接地端连接；或，在所述第二晶体管为HBT的情况下，所述第四变压器的次级线圈经所述第二晶体管发射极与接地端连接；
或，在所述第二晶体管为MOSFET的情况下，所述第四变压器的次级线圈经所述第二晶体管源极与接地端连接；
所述第五变压器的次级线圈直接与接地端连接；
或，在所述第三晶体管为HBT的情况下，所述第五变压器的次级线圈经所述第三晶体管发射极与接地端连接；
或，在所述第三晶体管为MOSFET的情况下，所述第四变压器的次级线圈经所述第三晶体管源极与接地端连接。
在一些实施例中，所述耦合反馈电路还包括：反馈器件；
所述反馈器件的一端配置为接收所述交变电压，所述反馈器件的另一端与所述第一晶体管和/或所述推挽式晶体管的输入端连接。
在一些实施例中，所述反馈器件为以下任意一种：耦合反馈电容、可变电容、变容二极管、电阻二极管串联支路、RC串联支路、电阻、滤波器。
在一些实施例中，所述耦合反馈电路配置为在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相反的情况下，实现所述输入端输入信号的负反馈。
在一些实施例中，在所述耦合反馈电路和所述驱动级电路连接的情况下，所述耦合反馈电路与所述驱动级电路位于不同的金属层，实现金属面之间的层间耦合；
所述耦合反馈电路和所述功率输出级电路连接的情况下，所述耦合反馈电路与所述功率输出级电路位于不同的金属层，实现金属面之间的层间耦合。
本申请实施例还提供一种电路控制方法，应用于推挽式射频功率放大器中，应用于推挽式射频功率放大器中，所述推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；所述耦合反馈电路与所述驱动级电路和/或所述功率输出级电路连接；其中，所述方法还包括：
在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相同的情况下，实现所述输入端输入信号的正反馈；所述第一晶体管表示所述驱动级电路中的晶体管，所述推挽式晶体管表示所述功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。
本申请实施例提供了一种推挽式射频功率放大器和电路控制方法，所述推挽式射频功率放大器包括：所述推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；所述耦合反馈电路与所述驱动级电路和/或所述功率输出级电路连接；其中，所述耦合反馈电路配置为在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相同的情况下，实现所述输入端输入信号的正反馈；所述第一晶体管表示所述驱动级电路中的晶体管，所述推挽式晶体管表示所述功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。如此，通过耦合反馈电路产生的交变电压，实现输出端到输入端输入信号的正反馈，根据输入信号的正反馈进行输入信号的同相叠加，大大提高输入信号的信号强度；进而，在不增加驱动级数量的情况下，可以有效提高推挽式射频功率放大器的增益和输出功率，降低射频功率放大器的设计复杂度。
附图说明
图1a为相关技术中推挽式射频功率放大器的电路结构示意图；
图1b为相关技术中第一变压器T1实现结构的平面示意图；
图1c为相关技术中第一变压器T1衬底叠层的结构示意图；
图1d为相关技术中射频功率放大器增益随输出功率的变化关系示意图；
图2a为本申请实施例的推挽式射频功率放大器的示意图一；
图2b为本申请实施例的推挽式射频功率放大器的示意图二；
图2c为本申请实施例的推挽式射频功率放大器的示意图三；
图2d为本申请实施例的推挽式射频功率放大器的电路结构示意图一；
图2e为本申请实施例的推挽式射频功率放大器的电路结构示意图二；
图2f为本申请实施例的推挽式射频功率放大器的电路结构示意图三；
图2g为相关技术中理想变压器电磁耦合产生的感应电压和线圈极性的关系示意图一；
图2h为相关技术中理想变压器电磁耦合产生的感应电压和线圈极性的关系示意图二；
图2i为本申请实施例中第一变压器T1和第二变压器T2实现结构的平面示意图一；
图2j为本申请实施例中第一变压器T1和第二变压器T2实现结构的平面示意图二；
图2k为本申请实施例中第一变压器T1和第二变压器T2实现结构的平面示意图三；
图3a为本申请实施例中电路节点B点交变电压的示意图；
图3b为本申请实施例中电路节点C点交变电压的示意图；
图3c为本申请实施例中电路节点F点交变电压的示意图；
图3d为本申请实施例的电路节点C点交变电压的示意图一；
图3e为本申请实施例的电路节点C点交变电压的示意图二；
图3f为本申请实施例的电路节点C点交变电压的示意图三；
图4a为本申请实施例中进行增益改善的示意图一；
图4b为本申请实施例中进行增益改善的示意图二；
图4c为本申请实施例中进行增益改善的示意图三；
图4d为本申请实施例中的推挽式射频功率放大器的电路结构示意图二；
图5a为本申请实施例中不同变压器叠层结构的平面示意图；
图5b为本申请实施例中金属走线位于衬底第三层的叠层结构示意图；
图5c为本申请实施例中金属走线位于衬底第四层的叠层结构示意图；
图6a为本申请实施例中反馈器件为可变电容的电路结构示意图；
图6b为本申请实施例中反馈器件为变容二极管的电路结构示意图；
图6c为本申请实施例中反馈器件为电阻二极管串联支路的电路结构示意图；
图6d为本申请实施例中反馈器件为RC串联支路的电路结构示意图；
图6e为本申请实施例中反馈器件为电阻的电路结构示意图；
图6f为本申请实施例中反馈器件为滤波器的电路结构示意图；
图6g为本申请实施例中反馈器件为L型低通滤波器的电路结构示意图一；
图6h为本申请实施例中反馈器件为L型高通滤波器的电路结构示意图二；
图6i为本申请实施例中反馈器件为pi型滤波器的电路结构示意图一；
图6j为本申请实施例中反馈器件为pi型滤波器的电路结构示意图二；
图7a为本申请实施例的第二变压器T2的次级线圈直接与地连接的电路结构示意图；
图7b为本申请实施例的第二变压器T2的次级线圈直接与地连接的平面示意图；
图7c为本申请实施例中当输出端到输入端为负反馈时的结构的平面示意图；
图8a为本申请实施例的推挽式射频功率放大器的电路结构示意图三；
图8b为本申请实施例中不同变压器实现结构的平面示意图；
图8c为本申请实施例的第四变压器T4和第五变压器T5的次级线圈直接与接地端连接的电路结构示意图；
图8d为本申请实施例的第四变压器T4和第五变压器T5的次级线圈与地直接连接的平面示意图。
具体实施方式
以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
与非合成的单端射频功率放大器对比，典型的推挽式射频功率放大器为两路功率差分合成技术；相同的输出功率下，输出的负载线(loadline)阻抗更高(约为单端的四倍)，而且对末级共模寄生电抗较为不敏感；因而，推挽式功率放大器(Push-Pull Power Amplifier，Push-Pull PA)能提供更高的增益和输出功率，同时对偶次谐波也具有更好的抑制。
图1a为相关技术中推挽式射频功率放大器的电路结构示意图，如图1a所示，以HBT工艺为例进行说明，由于单级的增益约为10-18dB，为了提供足够的增益，需要采用驱动级电路和功率输出级电路的级联设计。这里，驱动级电路包括：第一输入匹配电容C1、第一晶体管Q1、第一变压器T1、第一旁路耦合电容C3和接地电感L1；其中，E、B和C点分别对应第一晶体管Q1的发射极、基极和集电极；L1表示接地产生的等效电感，并非驱动级电路中真实存在的电感。
功率输出级电路包括：第二输入匹配电容C4、第二晶体管Q2、第三输入匹配电容C5、第三晶体管Q3、第三变压器T3、第二旁路耦合电容C6和负载RL。其中，第一旁路耦合电容C3、第二旁路耦合电容C6可以将直流电源中的交流分量耦合到地中，起到净化直流电源的作用。
从图1a可以看出，第一输入匹配电容C1的一端配置为接收输入信号RFin，另一端与第一晶体管Q1的基极连接；驱动级偏置电流I1为第一晶体管Q1的基极提供偏置电流；第一晶体管Q1的发射极与接地端连接；第一晶体管Q1的集电极与第一变压器T1的初级线圈的一端连接，第一变压器T1的初级线圈的另 一端连接第一直流电源Vcc1进行供电，并通过旁路耦合C3电容接地。
第一变压器T1的次级线圈经第二输入匹配电容C4和第三输入匹配电容C5分别连接第二晶体管Q2和第三晶体管Q3的基极输入端，并且在线圈中间或者其他位置引出可外接抽头；这里，该抽头可以接地，也可以开路，还可以接任意负载；示例性地，图1a示出了抽头接地的情况。
第一功率级偏置电流I2为第二晶体管Q2的基极提供偏置电流；第二功率级偏置电流I3为第三晶体管Q3的基极提供偏置电流；第二晶体管Q2和第三晶体管Q3的发射极接地；第二晶体管Q2的集电极和第三晶体管Q3的集电极分别与第三变压器T3初级线圈的两个端点连接；第三变压器T3的初级线圈在线圈中间或者其他位置引出抽头连接第二直流电源Vcc2进行供电，并通过旁路耦合电容C6接地；第三变压器T3的次级线圈的一端接地，另一端与负载RL连接，输出信号RFout。
对于上述的电路结构，第三变压器T3可以实现第二晶体管Q2和第三晶体管Q3的功率合成，并将合成功率输出到负载RL，同时将阻抗匹配到应用端所需阻抗；这里，阻抗一般为50Ohm，但不限于50Ohm。第一变压器T1提供平衡端到非平衡端的功率分配和阻抗变换作用，第三变压器T3提供非平衡端到平衡端的功率合成和阻抗变换作用。
图1b为相关技术中第一变压器T1实现结构的平面示意图，如图1b所示，第一变压器T1由两个绕线电感相互耦合组成，初级线圈由第一晶体管Q1集电极开始连接第一直流电源Vcc1，次级线圈连接第二晶体管Q2和第三晶体管Q3基极输入端，并且在线圈中间或者其他位置引出可外接抽头。图1c为相关技术中第一变压器T1衬底叠层的结构示意图，如图1c所示，第一变压器T1衬底叠层包括：金属层1、金属层2和金属地层；其中，金属层1与金属层2之间通过介质层1的金属连接孔1连接；金属层2与金属地层之间通过介质层2的金属连接孔2连接。在图1b中，实线表示的金属走线位于衬底金属层1；虚线表示的金属走线位于衬底金属层2，金属层之间通过金属通孔连接。
相关技术中，由于两级推挽式射频功率放大器，受限于单级晶体管的增益上限，加上在sub 6GHz乃至毫米波频段，晶体管接地电感以及其本身寄生参数对增益的恶化会变得越来越明显，导致增益裕量不足的问题会越来越严重。图1d为相关技术中射频功率放大器增益随输出功率的变化关系示意图，其中，该变化关系曲线是基于上述图1a电路结构设计的一个n79(4400MHz-5000MHz)频段的射频功率放大器，其增益随输出功率的变化关系曲线；图1d中的横轴代表输出功率，单位为dBm，纵轴代表射频功率放大器的增益，单位为dB；实线表示在频率为4400MHz的情况下，其增益随输出功率的变化关系曲线；虚线表示在频率为4700MHz的情况下，其增益随输出功率的变化关系曲线；点划线表示在频率为5000MHz的情况下，其增益随输出功率的变化关系曲线。
从图1d可以看出，随着频率的增大，提高放大器增益的难度明显增加。为了实现30dB乃至更高的增益，此结构只能在第一晶体管Q1前面增加一级驱动放大管，但是这样一来会大大提高整个射频功率放大器的设计复杂度。
针对以上技术的缺陷，本申请实施例提供了一种推挽式射频功率放大器和电路控制方法。
基于上述记载的推挽式射频功率放大器以及应用场景，提出以下实施例。
图2a为本申请实施例的推挽式射频功率放大器的示意图一，如图2a所示，推挽式射频功率放大器包括：耦合反馈电路20、驱动级电路21和功率输出级电路22；耦合反馈电路20与驱动级电路21连接；驱动级电路与功率输出级电路22连接。
图2b为本申请实施例的推挽式射频功率放大器的示意图二；如图2b所示，推挽式射频功率放大器包括：耦合反馈电路20、驱动级电路21和功率输出级电路22；耦合反馈电路20与功率输出级电路22连接；驱动级电路与功率输出级电路22连接。
图2c为本申请实施例的推挽式射频功率放大器的示意图三；推挽式射频功率放大器包括：耦合反馈电路20、驱动级电路21和功率输出级电路22；耦合反馈电路20与驱动级电路21和功率输出级电路22连接；驱动级电路与功率输出级电路22连接。
其中，耦合反馈电路20配置为在第一晶体管Q1和/或推挽式晶体管的输入端产生交变电压；在交变电压与输入端电压方向相同的情况下，实现输入端输入信号的正反馈；第一晶体管Q1表示驱动级电路21中的晶体管，推挽式晶体管表示功率输出级电路22中形成推挽式结构的第二晶体管Q2和第三晶体管Q3。
在一种实施方式中，第一晶体管Q1和推挽式晶体管可以是一种固体半导体器件，具有检波、放大和信号调制等多种功能；例如，第一晶体管Q1可以包括：HBT或MOSFET；推挽式晶体管也可以包括：HBT或MOSFET。
在一些实施例中，耦合反馈电路20配置为产生交变电压，交变电压可以表示电压的瞬时值的大小随时间、方向的改变而改变的电压；示例性地，交变电压可以为不同幅度、不同方向的正弦交流电压；可以根据实际电路结构进行确定，本申请实施例不作限制。
本申请实施例中，驱动级电路21与功率输出级电路22进行连接，形成两级级联结构；驱动级电路21可以表示对输入信号进行放大的中间电路；即，通过放大信号使其能够驱动功率输出级电路22的第二晶体管Q2和第三晶体管Q3工作。
在一些实施例中，功率输出级电路22中形成推挽式结构的第二晶体管Q2和第三晶体管Q3可以表示两个HBT管或MOSFET管；这里，第二晶体管Q2和第三晶体管Q3各自负责正负半周的波形放大任务，在功率输出级电路22工作的情况下，两个对称的第二晶体管Q2和第三晶体管Q3每次只有一个导通，进而，可以降低导通损耗。
本申请实施例中，在耦合反馈电路20与驱动级电路21连接的情况下，如果耦合反馈电路20产生的交变电压与第一晶体管Q1的输入端电压方向相同，使得第一晶体管Q1输入端电压与交变电压同向叠加；可以实现第一晶体管Q1输出端到输入端的正反馈；进而，提高输入信号的信号强度。
本申请实施例中，在耦合反馈电路20与功率输出级电路22连接的情况下，如果耦合反馈电路20产生的交变电压与第二晶体管Q2的输入端电压方向相同，使得第二晶体管Q2输入端电压与交变电压同向叠加；可以实现第二晶体管Q2输出端到输入端的正反馈；进而，提高输入信号的信号强度；同样地，如果耦合反馈电路20产生的交变电压与第三晶体管Q3的输入端电压方向相同，使得第三晶体管Q3输入端电压与交变电压同向叠加；可以实现第三晶体管Q3输出端到输入端的正反馈；进而，提高输入信号的信号强度。
可以看出，通过实现第一晶体管Q1和/或推挽式晶体管(第二晶体管Q2、第三晶体管Q3)输出端到输入端的正反馈，可以有效提高输入信号的信号强度；如此，在不增加驱动级数量的情况下，可以有效提高推挽式射频功率放大器的增益和输出功率，降低射频功率放大器的设计复杂度。
图2d为本申请实施例的推挽式射频功率放大器的电路结构示意图一，以HBT工艺为例说明；图2d中的推挽式射频功率放大器是在图2a的推挽式射频功率放大器基础上，图2d示出了在耦合反馈电路20与驱动级电路21连接的情况下，耦合反馈电路20、驱动级电路21和功率输出级电路22之间的具体连接关系。
本申请实施例中，第一变压器T1是由第一晶体管Q1集电极引出的初级线圈与第二晶体管Q2和第三晶体管Q3的基极引出的次级线圈耦合形成的；驱动级电路21与功率输出级电路22通过第一变压器T1连接；其中，第一变压器T1既可以传递信号也可以传递功率。
可以看出，与图1a中推挽式射频功率放大器相比，第一变压器T1的初级线圈与第一晶体管Q1基极引出的次级线圈进行耦合，形成第二变压器T2；耦合反馈电路20包括第一晶体管Q1基极引出的次级线圈。即，耦合反馈电路20与驱动级电路21连接。
本申请实施例中，第二变压器T2的次级线圈的正极与第一晶体管Q1的输入端连接，负极与接地端连接；第二变压器T2的初级线圈的一端连接第一直流电源Vcc1进行供电。
这里，驱动级偏置电流I1为第一晶体管Q1的基极提供偏置电流；第一功率级偏置电流I2为第二晶体管Q2的基极提供偏置电流；第二功率级偏置电流I3为第三晶体管Q3的基极提供偏置电流。
图2e为本申请实施例的推挽式射频功率放大器的电路结构示意图二，如图2e所示，该电路结构图在图2d的基础上将第一变压器T1的次级线圈不接地。
图2f为本申请实施例的推挽式射频功率放大器的电路结构示意图三，如图2f所示，该电路结构图在图2d的基础上将第一变压器T1的次级线圈中间或者其他位置引出的抽头接电容到地。
图2d、图2e以及图2f中第一变压器T1、第二变压器T2和第三变压器T3可以为巴伦转换器等效的变压器。这里，变压器是利用电磁感应原理改变交流和电压的装置，主要构件是初级线圈、次级线圈和铁芯(磁芯)。变压器的主要功能有：电压变换、电流变换、阻抗变换、隔离、稳压等。其中，初级线圈 表示变压器的输入端，一般与直流电源连接，初级线圈从直流电源吸收能量以电磁感应的方式将能量传递给次级线圈；次级线圈表示变压器的输出端，次级线圈收到初级线圈的电磁感应后，会在次级线圈产生交变电压。
其中，对于巴伦转换器，根据耦合电感和理想变压器的理论，图2g为相关技术中理想变压器电磁耦合产生的感应电压和线圈极性的关系示意图一，图2h为相关技术中理想变压器电磁耦合产生的感应电压和线圈极性的关系示意图二；如图2g、图2h所示，T表示巴伦转换器，Ui为输入电压，Uo为感应电压，可以通过调整初级线圈、次级线圈的极性，实现跟输入电压Ui相位相同或者相反的感应电压Uo。
在一种实施方式中，耦合反馈电路20还包括：反馈器件；反馈器件的一端配置为接收交变电压，反馈器件的另一端与第一晶体管和/或推挽式晶体管的输入端连接。
本申请实施例中，反馈器件的一端与耦合反馈电路20中的次级线圈连接，另一端与第一晶体管Q1的输入端连接；进而，当耦合反馈电路在第一晶体管Q1的输入端产生交变电压时，可以通过反馈器件接收到交变电压，并将交变电压发送至第一晶体管Q1的输入端。
如图2d所示，反馈器件为耦合反馈电容C2，耦合反馈电容C2一端配置为接收第二变压器T2产生的交变电压，耦合反馈电容C2的另一端与第一晶体管Q1的输入端连接。这里，耦合反馈电容C2连接在第一晶体管Q1输入端的位置可以在第一输入匹配电容C1的前面或后面。
图2i为本申请实施例中第一变压器T1和第二变压器T2实现结构的平面示意图一，如图2i所示，第一变压器T1和第二变压器T2由两个绕线电感相互耦合组成，第一变压器T1的初级线圈由第一晶体管Q1集电极开始连接第一直流电源Vcc1，第一变压器T1的次级线圈连接第二晶体管Q2和第三晶体管Q3基极输入端，并且在线圈中间或者其他位置引出可外接抽头，此处以接地为例。第二变压器T2的一端与耦合反馈电容C2连接，另一端与第一晶体管Q1的发射极连接。其中，实线表示的金属走线位于衬底金属层1；虚线表示的金属走线位于衬底金属层2，金属层之间通过金属通孔连接。
图2j为本申请实施例中第一变压器T1和第二变压器T2实现结构的平面示意图二，如图2j所示，第二晶体管Q2和第三晶体管Q3的基极通过第一变压器T1的次级线圈连接电容C18到地。
图2k为本申请实施例中第一变压器T1和第二变压器T2实现结构的平面示意图三；如图2k所示，第二晶体管Q2和第三晶体管Q3的基极不再通过第一变压器T1的次级线圈引出抽头接地。
本申请实施例中，对于共射极连接的第一晶体管Q1，Q1基极输入B点的交变电压和集电极输出C点的交变电压是接近180°相位差的；通过引入耦合反馈电路20，即，第一晶体管Q1基极引出的次级线圈，使得第二变压器T2产生电磁耦合，进而，在F点可以产生和C点接近180°相位差、即与第一晶体管Q1输入端输入信号接近同相的交变电压，此交变电压通过耦合反馈电容C2连 接到输入端时，由于信号同相叠加就可以大大提高输入信号强度，相当于在第一晶体管Q1增加了一个输出到输入正反馈，在第一晶体管Q1、第二晶体管Q2和第三晶体管Q3增益不变的情况下，本申请可以大大提高整个功率放大器的增益和输出功率。
图3a为本申请实施例中电路节点B点交变电压的示意图；图3b为本申请实施例中电路节点C点交变电压的示意图；图3c为本申请实施例中电路节点F点交变电压的示意图；这里，图3a、图3b和图3c均表示电路节点B、C和F三点交变电压的时域波形示意图。
其中，横轴代表时间，单位为ms，纵轴代表电压值，单位为V；波形示意图表示分别在频率为4400MHz、4700MHz和5000MHz的情况下，电路节点B、C、F三点交变电压的波形示意图。
由图可见，虽然受第一晶体管Q1随频率变化的寄生参数的影响，B点和C点、C点和F点相位差并非理想180°，但是通过调节第一输入匹配电容C1,耦合反馈电容C2和第二变压器T2，可以针对不同频点实现宽带的正反馈优化。
通过本申请实施例中第二变压器T2的级间耦合和正反馈，不需要增加驱动级数目，就可以在较宽频段内实现增益和输出功率的提高。这里以n79PA为例，图3d为本申请实施例的电路节点C点交变电压的示意图一；图3e为本申请实施例的电路节点C点交变电压的示意图二；图3f为本申请实施例的电路节点C点交变电压的示意图三；其中，横轴代表时间，单位为ms，纵轴代表电压值，单位为V；图3d、图3e和图3f依次表示在频率为4400MHz、4700MHz和5000MHz的情况下，电路节点C点交变电压的波形示意图。
这里，虚线表示改进前的时域波形图，实线表示改进后的时域波形图；可以看出，采用本申请改进电路后，驱动级电路的输出增益得到了显著提升。
进一步地，图4a为本申请实施例中进行增益改善的示意图一；图4b为本申请实施例中进行增益改善的示意图二；图4c为本申请实施例中进行增益改善的示意图三；其中，横轴代表输出功率，单位为dBm，纵轴代表射频功率放大器的增益，单位为dB；图4a、图4b和图4c依次表示在频率为4400MHz、4700MHz和5000MHz的情况下，进行增益改善的示意图。
这里，虚线表示改进前的增益波形图，实线表示改进后的增益波形图；可以看出，采用本申请改进电路后，对n79频段内整体增益有显著提升，所以本申请对5G NR射频功率放大器的设计提供很好的技术支撑。
另一方面，由于第二变压器T2和传输线耦合结构具有良好的宽带特性，所以本申请可以很好地适用于sub 6GHz到FR2毫米波频段的射频功率放大器设计。
此外，本申请还适用于不同工艺，包括互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)，砷化镓(Gallium Arsenide，GaAs)，高电子迁移率晶体管(pHEMT)，硅技术(Silicon-On-Insulator，SOI)都可以很方便地运用本申请，实现高增益高功率射频功率放大器的设计。即，图2d中的第一晶体管Q1、第一晶体管Q2和第一晶体管Q3还可以是MOSFET。
图4d为本申请实施例中的推挽式射频功率放大器的电路结构示意图二，以 MOSFE工艺为例说明；图4d中的推挽式射频功率放大器是在图2d的推挽式射频功率放大器基础上，图4d示出了在耦合反馈电路20与驱动级电路21和功率输出级电路22连接的情况下，耦合反馈电路20、驱动级电路21和功率输出级电路22之间的具体连接关系。
如图4d所示，图4d中MOSFET的栅极G、源极S和漏极D分别对应图2d中第一晶体管Q1、第一晶体管Q2和第一晶体管Q3的基极B、发射极E和集电极C；其它电路结构与图2d相同。
在一些实施例中，在第一晶体管为MOSFET的情况下，第一变压器的初级线圈与第一晶体管栅极引出的次级线圈进行耦合，形成第二变压器；耦合反馈电路包括第一晶体管栅极引出的次级线圈。
在一些实施例中，第二变压器的次级线圈直接与接地端连接；或，在第一晶体管为MOSFET的情况下，第二变压器的次级线圈经第一晶体管源极与接地端连接。
在一些实施例中，功率输出级电路包括第三变压器；在在所述第二晶体管和所述第三晶体管为MOSFET的情况下，第三变压器的初级线圈与第二晶体管栅极引出的次级线圈进行耦合，形成第四变压器；第三变压器的初级线圈与第三晶体管栅极引出的次级线圈进行耦合，形成第五变压器；耦合反馈电路包括第二晶体管栅极引出的次级线圈和第三晶体管栅极引出的次级线圈。
在一些实施例中，第四变压器的次级线圈直接与接地端连接；或，在第二晶体管为MOSFET的情况下，第四变压器的次级线圈经第二晶体管源极与接地端连接；
第五变压器的次级线圈直接与接地端连接；
或，在第三晶体管为MOSFET的情况下，第四变压器的次级线圈经第三晶体管源极与接地端连接。
在一些实施例中，在耦合反馈电路和驱动级电路连接的情况下，耦合反馈电路与驱动级电路位于不同的金属层，实现金属面之间的层间耦合。
本申请实施例中，第二变压器T2，即，耦合反馈电路的次级线圈与驱动级电路的初级线圈位于不同的金属层，实现金属面之间的层间耦合；这里，相应的衬底叠层结构可以包含两层金属走线，也可以包含三层以上金属走线。图5a为本申请实施例中不同变压器叠层结构的平面示意图；其中，实线表示的金属走线位于衬底第一层金属层；虚线表示的金属走线位于衬底第二层金属层；点划线表示的金属走线位于衬底第三层或者第四层金属层。图5b为本申请实施例中金属走线位于衬底第三层的叠层结构示意图；图5c为本申请实施例中金属走线位于衬底第四层的叠层结构示意图；其中，金属层之间通过金属连接孔连接。
此外，对于本申请中的每个变压器中的初级线圈和次级线圈(耦合电感)，均可以采用多层金属通过通孔连接，形成厚金属层实现，降低金属损耗。
结合图1a和图2d可以看出，本申请实施例提出的推挽式射频功率放大器的电路结构在图1a中第一变压器T1的基础上，引入耦合反馈电路20，其中，耦合反馈电路20包括第二变压器T2的次级线圈和反馈器件；图2d中的反馈器 件为反馈耦合电容C2。
在一种实施方式中，反馈器件为以下任意一种：耦合反馈电容、可变电容、变容二极管、电阻二极管串联支路、RC串联支路、电阻、滤波器。也就是说，反馈器件可以是图2d中的反馈耦合电容C2，还可以是可变电容、变容二极管、电阻二极管串联支路、RC串联支路、电阻、滤波器中的任意一种。在一些实施例中，反馈器件对应的电路结构图如图6a至图6j所示。
图6a为本申请实施例中反馈器件为可变电容的电路结构示意图，如图6a所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为可变电容C11。
图6b为本申请实施例中反馈器件为变容二极管的电路结构示意图，如图6b所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为变容二极管D1。
图6c为本申请实施例中反馈器件为电阻二极管串联支路的电路结构示意图，如图6c所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为电阻R1二极管D2串联支路。
图6d为本申请实施例中反馈器件为RC串联支路的电路结构示意图，如图6d所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为R2C12串联支路。
图6e为本申请实施例中反馈器件为电阻的电路结构示意图，如图6e所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为电阻R3。
图6f为本申请实施例中反馈器件为滤波器的电路结构示意图，如图6f所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为滤波器。
其中，图6f中所示的滤波器可以是L型高通滤波器、L型低通滤波器、pi型滤波器或其他类型的滤波器。
图6g为本申请实施例中反馈器件为L型低通滤波器的电路结构示意图一，如图6g所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为L2C13的L型低通滤波器。
图6h为本申请实施例中反馈器件为L型高通滤波器的电路结构示意图二，如图6h所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为L3C14的L型高通滤波器。
图6i为本申请实施例中反馈器件为pi型滤波器的电路结构示意图一，如图6i所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为L4C15L5的pi型滤波器。
图6j为本申请实施例中反馈器件为pi型滤波器的电路结构示意图二，如图6j所示，该电路结构图在图2d的基础上将反馈器件从反馈耦合电容C2替换为C16L6C17的pi型滤波器。
在一种实施方式中，第二变压器的次级线圈直接与接地端连接；或，第二变压器的次级线圈经第一晶体管发射极与接地端连接。
本申请实施例中，第二变压器T2的次级线圈的接地方式有两种，可以如图 2d所示，该次级线圈经第一晶体管Q1发射极与接地端连接，也可以直接与地连接。图7a为本申请实施例的第二变压器T2的次级线圈直接与地连接的电路结构示意图；图7b为本申请实施例的第二变压器T2的次级线圈直接与地连接的平面示意图；其中，实线表示的金属走线位于衬底第一层金属层；虚线表示的金属走线位于衬底第二层金属层；金属层之间通过金属连接孔连接。
在一种实施方式中，耦合反馈电路配置为在第一晶体管的输入端产生交变电压；在交变电压与输入端电压方向相反的情况下，实现输入端输入信号的负反馈。
本申请实施例中，在第二变压器T2的次级线圈的负极与第一晶体管Q1的输入端连接，正极与接地端连接的情况下，耦合反馈电路产生的交变电压与输入端电压方向相反，进而，可以实现输入端输入信号的负反馈；通过实现负反馈，可以改善射频功率放大器的稳定性和可靠性。图7c为本申请实施例中当输出端到输入端为负反馈时的结构的平面示意图。其中，实线表示的金属走线位于衬底第一层金属层；虚线表示的金属走线位于衬底第二层金属层；金属层之间通过金属连接孔连接。
图8a为本申请实施例的推挽式射频功率放大器的电路结构示意图三，以HBT工艺为例说明；图8a中的推挽式射频功率放大器是在图2a的推挽式射频功率放大器基础上，图8a示出了在耦合反馈电路20与驱动级电路21和功率输出级电路22连接的情况下，耦合反馈电路20、驱动级电路21和功率输出级电路22之间的具体连接关系。
与上述图2d的推挽式射频功率放大器相比，第三变压器的初级线圈与第二晶体管基极引出的次级线圈进行耦合，形成第四变压器T4；第三变压器的初级线圈与第三晶体管基极引出的次级线圈进行耦合，形成第五变压器T5；耦合反馈电路包括第二晶体管基极引出的次级线圈和第三晶体管基极引出的次级线圈。
本申请实施例中，第四变压器T4的次级线圈的正极与第二晶体管Q2的输入端连接，负极与接地端连接；第五变压器T5的次级线圈的正极与第三晶体管Q3的输入端连接，负极与接地端连接。第三变压器T3的初级线圈在线圈中间或者其他位置引出抽头连接第二直流电源Vcc2进行供电。
如图8a所示，耦合反馈电路20包括的反馈器件为耦合反馈电容C8和耦合反馈电容C9；其中，耦合反馈电容C8一端配置为接收第四变压器T4产生的交变电压，另一端与第二晶体管Q2的输入端连接；耦合反馈电容C9一端配置为接收第五变压器T5产生的交变电压，另一端与第三晶体管Q3的输入端连接。
这里，耦合反馈电容C8连接在第二晶体管Q2输入端的位置可以在第二输入匹配电容C4的前面或后面。同样地，耦合反馈电容C9连接在第三晶体管Q3输入端的位置可以在第三输入匹配电容C5的前面或后面。图8a表示耦合反馈电容C8和耦合反馈电容C9连接在输入匹配电容前面的情况。
图8b为本申请实施例中不同变压器实现结构的平面示意图，如图8b所示，实线表示金属层1和金属地层走线，虚线表示金属层2走线，金属层之间通过金属通孔连接，金属层之间通过金属通孔连接。
在一种实施方式中，第四变压器T4的次级线圈直接与接地端连接；或，第四变压器T4的次级线圈经第二晶体管发射极与接地端连接；第五变压器T5的次级线圈直接与接地端连接；或，第五变压器T5的次级线圈经第三晶体管发射极与接地端连接。
本申请实施例中，第四变压器T4和第五变压器T5的次级线圈的接地方式有两种，可以如图8a所示，第四变压器T4的次级线圈经第二晶体管Q2发射极与接地端连接，第五变压器T5的次级线圈经第三晶体管Q3发射极与接地端连接。也可以如图8c所示，第四变压器T4和第五变压器T5的次级线圈直接与接地端连接；图8d为本申请实施例的第四变压器T4和第五变压器T5的次级线圈与地直接连接的平面示意图；其中，实线表示的金属走线位于衬底第一层金属层；虚线表示的金属走线位于衬底第二层金属层；金属层之间通过金属连接孔连接。
在一种实施方式中，耦合反馈电路20还包括：反馈器件；反馈器件的一端配置为接收交变电压，反馈器件的另一端与推挽式晶体管的输入端连接。
这里，耦合反馈电路20与上述实施例中的耦合反馈电路相同，这里不再累赘。
在一种实施方式中，耦合反馈电路配置为在推挽式晶体管的输入端产生交变电压；在交变电压与输入端电压方向相反的情况下，实现输入端输入信号的负反馈。
本申请实施例中，在正反馈的基础上，可以改变耦合反馈电路中次级线圈的绕线方向；将次级线圈的正极接地，负极接推挽式晶体管的输入端；进而，产生与输入端电压方向相反的交变电压，实现输入端输入信号的负反馈。通过负反馈，可以改善射频功率放大器的稳定性和可靠性。
在一种实施方式中，耦合反馈电路与功率输出级电路位于不同的金属层，实现金属面之间的层间耦合。
本申请实施例中，耦合反馈电路的次级线圈与功率输出级电路的初级线圈位于不同的金属层，实现金属面之间的层间耦合；这里，相应的衬底叠层结构可以包含两层金属走线，也可以包含三层以上金属走线；第四变压器T4和第五变压器T5叠层结构示意图如图5b和图5c所示。
本申请实施例还提供一种电路控制方法，应用于推挽式射频功率放大器中，应用于推挽式射频功率放大器中，推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；耦合反馈电路与驱动级电路和/或功率输出级电路连接；其中，电路控制方法还包括：
在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在交变电压与输入端电压方向相同的情况下，实现输入端输入信号的正反馈；第一晶体管表示驱动级电路中的晶体管，推挽式晶体管表示功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。
需要说明的是，本申请实施例中提出的推挽式射频功率放大器的电路结构图不仅限于上述实施例所记载的电路结构，还适用于其它推挽式射频功率放大 器的电路结构，本申请实施例不作限制。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种推挽式射频功率放大器，所述推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；所述耦合反馈电路与所述驱动级电路和/或所述功率输出级电路连接；
    其中，所述耦合反馈电路配置为在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相同的情况下，实现所述输入端输入信号的正反馈；所述第一晶体管表示所述驱动级电路中的晶体管，所述推挽式晶体管表示所述功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。
  2. 根据权利要求1所述的推挽式射频功率放大器，其中，所述驱动级电路包括第一变压器；
    在所述第一晶体管为异质结双极晶体管HBT的情况下，所述第一变压器的初级线圈与所述第一晶体管基极引出的次级线圈进行耦合，形成第二变压器；所述耦合反馈电路包括所述第一晶体管基极引出的次级线圈；
    在所述第一晶体管为金属-氧化物半导体场效应晶体管MOSFET的情况下，所述第一变压器的初级线圈与所述第一晶体管栅极引出的次级线圈进行耦合，形成第二变压器；所述耦合反馈电路包括所述第一晶体管栅极引出的次级线圈。
  3. 根据权利要求2所述的推挽式射频功率放大器，其中，所述第二变压器的次级线圈直接与接地端连接；
    或，在所述第一晶体管为HBT的情况下，所述第二变压器的次级线圈经所述第一晶体管发射极与接地端连接；
    或，在所述第一晶体管为MOSFET的情况下，所述第二变压器的次级线圈经所述第一晶体管源极与接地端连接。
  4. 根据权利要求1所述的推挽式射频功率放大器，其中，所述功率输出级电路包括第三变压器；
    在所述第二晶体管和所述第三晶体管为HBT的情况下，所述第三变压器的初级线圈与所述第二晶体管基极引出的次级线圈进行耦合，形成第四变压器；所述第三变压器的初级线圈与所述第三晶体管基极引出的次级线圈进行耦合，形成第五变压器；所述耦合反馈电路包括所述第二晶体管基极引出的次级线圈和所述第三晶体管基极引出的次级线圈；
    在所第二晶体管和所述第三晶体管为MOSFET的情况下，所述第三变压器的初级线圈与所述第二晶体管栅极引出的次级线圈进行耦合，形成第四变压器；所述第三变压器的初级线圈与所述第三晶体管栅极引出的次级线圈进行耦合，形成第五变压器；所述耦合反馈电路包括所述第二晶体管栅极引出的次级线圈和所述第三晶体管栅极引出的次级线圈。
  5. 根据权利要求4所述的推挽式射频功率放大器，其中，所述第四变压器的次级线圈直接与接地端连接；
    或，在所述第二晶体管为HBT的情况下，所述第四变压器的次级线圈经所 述第二晶体管发射极与接地端连接；
    或，在所述第二晶体管为MOSFET的情况下，所述第四变压器的次级线圈经所述第二晶体管源极与接地端连接；
    所述第五变压器的次级线圈直接与接地端连接；
    或，在所述第三晶体管为HBT的情况下，所述第五变压器的次级线圈经所述第三晶体管发射极与接地端连接；
    或，在所述第三晶体管为MOSFET的情况下，所述第四变压器的次级线圈经所述第三晶体管源极与接地端连接。
  6. 根据权利要求2至5任一项所述的推挽式射频功率放大器，其中，所述耦合反馈电路还包括：反馈器件；
    所述反馈器件的一端用于接收所述交变电压，所述反馈器件的另一端与所述第一晶体管和/或所述推挽式晶体管的输入端连接。
  7. 根据权利要求6所述的推挽式射频功率放大器，其中，所述反馈器件为以下任意一种：耦合反馈电容、可变电容、变容二极管、电阻二极管串联支路、RC串联支路、电阻、滤波器。
  8. 根据权利要求1所述的推挽式射频功率放大器，其中，所述耦合反馈电路配置为在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相反的情况下，实现所述输入端输入信号的负反馈。
  9. 根据权利要求1所述的推挽式射频功率放大器，其中，在所述耦合反馈电路和所述驱动级电路连接的情况下，所述耦合反馈电路与所述驱动级电路位于不同的金属层，实现金属面之间的层间耦合；
    所述耦合反馈电路和所述功率输出级电路连接的情况下，所述耦合反馈电路与所述功率输出级电路位于不同的金属层，实现金属面之间的层间耦合。
  10. 一种电路控制方法，其中，应用于推挽式射频功率放大器中，所述推挽式射频功率放大器包括：耦合反馈电路、驱动级电路和功率输出级电路；所述耦合反馈电路与所述驱动级电路和/或所述功率输出级电路连接；其中，所述方法还包括：
    在第一晶体管和/或推挽式晶体管的输入端产生交变电压；在所述交变电压与所述输入端电压方向相同的情况下，实现所述输入端输入信号的正反馈；所述第一晶体管表示所述驱动级电路中的晶体管，所述推挽式晶体管表示所述功率输出级电路中形成推挽式结构的第二晶体管和第三晶体管。
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