WO2024082739A1 - 一种高精度增量型zoom ADC架构 - Google Patents

一种高精度增量型zoom ADC架构 Download PDF

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WO2024082739A1
WO2024082739A1 PCT/CN2023/108604 CN2023108604W WO2024082739A1 WO 2024082739 A1 WO2024082739 A1 WO 2024082739A1 CN 2023108604 W CN2023108604 W CN 2023108604W WO 2024082739 A1 WO2024082739 A1 WO 2024082739A1
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incremental
adc
dsm
module
output
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PCT/CN2023/108604
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French (fr)
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刘禹延
谭年熊
洪俊杰
陈鹏鹏
林玲
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杭州万高科技股份有限公司
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Publication of WO2024082739A1 publication Critical patent/WO2024082739A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step

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  • the present invention relates to an ADC architecture, and in particular to a high-precision incremental zoom ADC architecture.
  • IADCs analog-to-digital converters
  • SQNR signal-to-quantization-noise ratio
  • Zoom ADC (zoomed analog-to-digital converter) is an architecture that combines SAR (successive approximation register) and DSM (delta-sigma modulator) (reference: Y.Chae, K.Souri and K.A.A.Makinwa, "A 6.3 ⁇ W 20bit Incremental Zoom-ADC with 6ppm INL and 1 ⁇ V Offset," IEEE JSSC, vol.48, no.12, pp.3019-3027, 2013.), which can reduce the requirements for the output swing of the op amp, making it easier to achieve low-power design.
  • the corresponding incremental zoom ADC has the advantages of IADC, so it is more suitable in many application scenarios. As shown in Figure 2, it is a traditional incremental zoom ADC architecture.
  • the subsequent incremental DSM is a FIR conversion process, similar to IADC, which causes its SQNR to lose;
  • the technical problem to be solved by the present invention is to provide a high-precision incremental zoom ADC architecture in view of the shortcomings of the prior art.
  • the present invention discloses a high-precision incremental zoom ADC architecture, including: a fine incremental DSM, a coarse quantization ADC, a residual feedforward module and an extended counting module;
  • the residual feedforward module is used to reconstruct the signal feedforward of the CIFF structure in the fine incremental DSM and reduce the output swing of the incremental zoom ADC integrator;
  • the input of the residual feedforward module is the analog input VIN of the incremental zoom ADC and the output k of the coarse quantization ADC, and the output is the feedforward signal of the CIFF structure of the fine incremental DSM;
  • the extended counting module is used to improve the signal quantization noise ratio SQNR of the incremental zoom ADC; the input of the extended counting module is the output analog voltage of the last stage integrator in the fine incremental DSM in the incremental mode in the last cycle, that is, the analog quantization error of the incremental DSM under the CIFF structure, and the output is the digital value of the quantization error of the fine incremental DSM after analog-to-digital conversion.
  • the residual feedforward module comprises:
  • An input signal transmission path a coarse quantization result establishing digital-to-analog converter DAC2, and an addition or subtraction module;
  • the input signal transmission path directly transmits the entire input signal VIN of the high-precision incremental zoom ADC;
  • the coarse quantization result establishing digital-to-analog converter DAC2 establishes the quantization result of the coarse quantization ADC;
  • the input signal VIN and the coarse quantization result established by the coarse quantization result establishing digital-to-analog converter DAC2 are subtracted through the addition or subtraction module to obtain the quantization residual of the coarse quantization ADC.
  • the quantization residual of the coarse quantization ADC namely the coarse quantization error, is used in the subsequent fine incremental DSM, added with the output of the integrator in the fine incremental DSM, and then sent to the quantizer of the fine incremental DSM to form a complete CIFF cycle.
  • the extended counting module comprises:
  • a gain module and a counting ADC module wherein the gain module amplifies the analog quantization error of the fine incremental DSM, namely the fine quantization error; the counting ADC performs analog-to-digital conversion on the amplified analog quantization error to obtain a digital value of the fine incremental DSM quantization error as the output of the extended counting module.
  • the final output of the high-precision incremental zoomADC is obtained by adding the output of the extended counting module to the original output.
  • the incremental zoom ADC architecture proposed in the present invention improves the SQNR of the incremental zoom ADC and can use an operational amplifier with a low output swing, thereby achieving high precision and low power consumption.
  • Figure 1 is a schematic diagram of the incremental zoom ADC architecture proposed in the present invention.
  • Figure 2 is a schematic diagram of the traditional incremental zoom ADC architecture.
  • Figure 3 is a circuit implementation diagram of an embodiment of the incremental zoom ADC architecture of the present invention.
  • FIG. 4 is a timing diagram of a circuit in one embodiment.
  • FIG. 5 is a schematic diagram showing a comparison of simulation results of an embodiment of the architecture of the present invention and a traditional architecture.
  • FIG. 6 is a schematic diagram showing a comparison of test results of an embodiment of the architecture of the present invention and a traditional architecture.
  • the input signal VIN is first quantized by a coarse quantization SAR ADC, and then finely quantized by a fine incremental delta-sigma modulator DSM.
  • the incremental DSM only quantizes the quantization error of the successive approximation SAR, so the requirements for the output swing of the op amp can be reduced, thereby using a low-power op amp.
  • the present invention uses a residual feedforward path to reconstruct the signal feedforward of the feedforward integrator CIFF structure, and reduces the output swing of the incremental zoom ADC integrator, thereby achieving a low-power design. Furthermore, an extended counting method is used to improve the SQNR of the incremental zoom ADC, thereby achieving high precision.
  • the present invention proposes a high-precision incremental zoom ADC architecture, and the specific scheme is as follows:
  • the digital-to-analog converter DAC2 implements residual feedforward, so that the signal feedforward path in the DSM of the CIFF architecture is established, so that the output of the second-stage integrator is the quantization error of the incremental DSM.
  • the extended count is further used to improve the signal quantization noise ratio SQNR, and the quantization error is amplified n times (2 times) and then quantized by a SAR.
  • the final result of the coarse quantization SAR, the result of the incremental DSM, and the result of the extended count SAR, these three parts are combined to form the final digital output DOUT.
  • the feedback value When the coarse SAR result k is used by DSM, the feedback value will be selected according to the BS and k of DSM.
  • the output result of the traditional incremental zoom is the output sequence of the above zoom converted through the CoI (cascade of integrators) filter, which is recorded as Dout1.
  • the extended counting principle refer to "A High-Resolution Low-Power Incremental ⁇ ADC With Extended Range for Biosensor Arrays"
  • FIG3 it is an embodiment of a specific circuit implementation of the scheme of the present invention.
  • 4b SAR is controlled by CLK SAR1 as a coarse quantizer, and the input signal is first coarsely quantized to obtain a coarse quantization result k.
  • DAC1 in the fine DSM is implemented by an array of 16 unit capacitors CS1,j, and feedback is performed using k and BS in combination, achieving the effect of zoom.
  • DAC2 in the fine DSM is implemented as a residual feedforward by a weighted CF1,j array, realizing the signal feedforward in the CIFF architecture, thereby ensuring that the fine quantization error of the DSM can be directly obtained at the output of the second-level integrator.
  • the addition (subtraction) module in the residual feedforward is combined with the addition module before the quantizer in the DSM, and is implemented by a passive capacitor adder.
  • the 4b SAR controlled by CLK SAR2 is used as an ADC for extended counting, quantizing the fine quantization error of the DSM amplified by 2 times gain, and realizing extended counting. All integrators use a fully dynamic cascoded FIA as an op amp to save power consumption.
  • the chopping technique is used in the first-stage integrator to reduce ficker noise and offset. In this second-order IADC, a fractal sequence of ⁇ +1,-1,-1,+1 ⁇ is used for chopping.
  • ADCs with coarse quantization and extended counting are not necessarily SAR ADCs
  • the op amp structure used by DSM is not unique;
  • the OTA implementing the integrator in DSM is not necessarily cascoded FIA;
  • One conversion of the incremental zoom ADC includes 256 DSM operation cycles.
  • the DSM runs at an oversampling frequency of fs, and the coarse SAR runs at a frequency of fs/4 to save power.
  • the frequency of the fractal sequence chopping is also fs/4.
  • the 2x gain stage of the extended count and the SAR ADC of the extended count are turned on only in the last cycle of each conversion, so their power consumption is negligible.
  • the simulation results show that using the architecture of this solution, the SQNR of the incremental zoom ADC is 118dB, which is about 10dB higher than that without using residual feedforward and extended count.
  • test results show that the incremental zoom ADC of this solution achieves an SNDR of 97.6dB within a 95Hz bandwidth and consumes only 0.96 ⁇ W of power, achieving high precision and extremely low power consumption.
  • the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium is capable of storing a computer program, and when the computer program is executed by the data processing unit, the invention content of a high-precision incremental zoom ADC architecture provided by the present invention and some or all of the steps in each embodiment can be executed.
  • the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
  • the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention are essentially or partly contributed to the prior art can be embodied in the form of a computer program, i.e., a software product, which can be stored in a storage medium and includes several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, a MUU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.
  • a data processing unit which can be a personal computer, a server, a single-chip microcomputer, a MUU or a network device, etc.
  • the present invention provides a concept and method of a high-precision incremental zoom ADC architecture. There are many methods and ways to implement the technical solution. The above is only a preferred implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention. All components not specified in this embodiment can be implemented using existing technologies.

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Abstract

一种高精度增量型zoom ADC架构，包括：精细的增量型DSM、粗略量化ADC、残差前馈模块以及扩展计数模块；其中，残差前馈模块用于重建精细的增量型DSM中的CIFF结构的信号前馈，减小增量型zoom ADC积分器的输出摆幅；残差前馈模块的输入为增量型zoom ADC的模拟输入VIN和粗略量化ADC的输出k，输出作为精细的增量型DSM的CIFF结构的前馈信号；扩展计数模块用于提升增量型zoom ADC的信号量化噪声比SQNR；扩展计数模块的输入为增量模式下精细的增量型DSM中最后一级积分器在最后一个周期的输出模拟电压，即CIFF结构下增量型DSM的模拟量化误差，输出为经过模数转换后的精细的增量型DSM的量化误差的数字值。

Description

一种高精度增量型zoom ADC架构 技术领域
本发明涉及一种ADC架构，特别是一种高精度增量型zoom ADC架构。
背景技术
对于许多应用，如智能传感器、生物医学信号处理和电池供电的物联网设备，需要高精度低功耗的ADC(模数转换器)。与传统DS ADC(delta-sigma模数转换器)相比，IADC(增量型模数转换器)是一个更好的选择，因为它具有低延迟，且易于复用的特征。然而，IADC的有限冲激响应(FIR)的转换模式导致它的SQNR(信号量化噪声比)会降低。
Zoom ADC(缩放式模数转换器)是一种结合SAR(successive approximation register，逐次逼近式)和DSM(delta-sigma调制器)的架构(参考：Y.Chae,K.Souri and K.A.A.Makinwa,"A 6.3μW 20bit Incremental Zoom-ADC with 6ppm INL and 1μV Offset,"IEEE JSSC,vol.48,no.12,pp.3019-3027,2013.)，可以降低对运放输出摆幅的要求，从而更易实现低功耗的设计。与之对应的增量型zoom ADC具备IADC的优势，因此在很多应用场景里更加适用。如图2所示，为传统的增量型zoom ADC架构。
传统的增量型zoom ADC存在的明显缺点：
1.输入信号经过粗量化器SAR ADC之后，后续的增量型DSM是一个FIR转换过程，类似于IADC，这导致它的SQNR有损失；
2.DSM的loop(循环)里CIFF(cascade of integrators with feed forward，前馈积分器)结构的信号前馈通路被截断，这仍会导致较大的积分器输出摆幅。
发明内容
发明目的：本发明所要解决的技术问题是针对现有技术的不足，提供一种高精度增量型zoom ADC架构。
为了解决上述技术问题，本发明公开了一种高精度增量型zoom ADC架构，包括：精细的增量型DSM、粗略量化ADC、残差前馈模块以及扩展计数模块；
其中，所述的残差前馈模块，用于重建精细的增量型DSM中的CIFF结构的信号前馈，减小增量型zoom ADC积分器的输出摆幅；残差前馈模块的输入为所述增量型zoom ADC的模拟输入VIN和粗略量化ADC的输出k，输出作为精细的增量型DSM的CIFF结构的前馈信号；
所述的扩展计数模块用于提升增量型zoom ADC的信号量化噪声比SQNR；扩展计数模块的输入为增量模式下精细的增量型DSM中最后一级积分器在最后一个周期的输出模拟电压，即所述CIFF结构下增量型DSM的模拟量化误差，输出为经过模数转换后的精细的增量型DSM的量化误差的数字值。
所述残差前馈模块，包括：
输入信号传输通路、粗量化结果建立数模转换器DAC2以及加或减法模块；输入信号传输通路直接传输整个所述高精度增量型zoom ADC的输入信号VIN；粗量化结果建立数模转换器DAC2建立粗略量化ADC的量化结果；通过加或减法模块将输入信号VIN和粗量化结果建立数模转换器DAC2建立的粗量化结果相减，得到粗量化ADC的量化残差。
所述粗量化ADC的量化残差即粗量化误差，在后续的精细的增量型DSM中使用，与精细的增量型DSM中积分器的输出进行加和，再送入精细的增量型DSM的量化器，构成完整的CIFF循环。
所述扩展计数模块，包括：
增益模块和计数ADC模块；其中，增益模块将精细的增量型DSM的模拟量化误差即细量化误差进行放大；计数ADC将放大后的模拟量化误差进行模数转换，得到精细增量型DSM量化误差的数字值，作为扩展计数模块的输出。
所述的高精度增量型zoomADC的最终输出是将所述的扩展计数模块的输出加入原输出后得到。
有益效果：
本发明提出的增量型zoom ADC架构提升了增量型zoom ADC的SQNR，同时可以使用低输出摆幅的运放。更好地实现了高精度和低功耗。
附图说明
下面结合附图和具体实施方式对本发明做更进一步的具体说明，本发明的上述和/或其他方面的优点将会变得更加清楚。
图1为本发明提出的增量型zoom ADC架构示意图。
图2为传统的增量型zoom ADC架构示意图。
图3为本发明增量型zoom ADC架构的一个实施例的电路实现示意图。
图4为一个实施例中电路的时序示意图。
图5为采用本发明架构的实施例与传统架构的仿真结果对比示意图。
图6为采用本发明架构的实施例与传统架构的测试结果对比示意图。
具体实施方式
如图2所示，传统的增量型zoom ADC采用以下方案：
输入信号VIN先通过一个粗量化的SAR ADC进行量化，后续的精细的增量型delta-sigma调制器DSM再进行细量化，增量型DSM只量化了逐次逼近SAR的量化误差，因此可以降低对运放输出摆幅的要求，从而使用低功耗的运放。
本发明使用残差前馈(residue feedforward)通路，重建前馈积分器CIFF结构的信号前馈，减小增量型zoom ADC积分器的输出摆幅，从而实现低功耗设计。更进一步，使用扩展计数(extended counting)的方式，提升增量型zoom ADC的SQNR，从而达到高精度，本发明提出的一种高精度增量型zoom ADC架构，具体方案如下：
如图1所示，数模转换器DAC2实现了残差前馈，使得CIFF架构的DSM中的信号前馈通路被建立，从而第二级积分器的输出即为增量型DSM的量化误差。进一步使用了扩展计数来提升信号量化噪声比SQNR，量化误差被放大n倍(2倍)之后再由一个SAR进行量化。最终粗量化SAR的结果、增量型DSM的结果、扩展计数SAR的结果，这三部分相结合构成了最终的数字输出DOUT。
Combine过程：
粗SAR的结果k，在被DSM使用的时候，反馈的值会根据DSM的BS和k进行选择。选择结果由over range决定，比如over range＝1，每次的反馈的值就是：如果BS＝1，反馈＝k+2；如果BS＝0，反馈＝k-1(over range＝1相当于在k～k+1的基础上上下各扩展了1个粗量化区间)。Over range保证了输入始终在DSM的参考电压之内，保证稳定性。Zoom ADC本身的输出就是BS和k的组合，即k1-1/k1+2，k2-1/k2+2，k3-1/k3+2，k4-1/k4+2，…其中ki的i表示输出序列顺序，ki-1或是ki+2是根据BS＝0或1决定的。
因此，传统增量型zoom的输出结果就是上述zoom的输出序列经过CoI(cascade of integrators)滤波器得到转换结果，记为Dout1。
本发明中增加了扩展计数，记扩展计数ADC的输出为y(归一化为-1～+1)，则扩展计数结果Dex＝y/gex*2/(a1a2M(M-1))，其中gex为扩展计数ADC前增益级的增益(图1中的2)，a1a2表示DSM中积分器系数的乘积(图1中的0.5和0.33)，M为过采样率。(扩展计数原理参考“A High-Resolution Low-Power IncrementalΣΔADC With Extended Range for Biosensor Arrays”)
最终，DOUT＝Dout1+Dex。
实施例：
如图3所示，是本发明方案的一种具体电路实现的实施例。4b SAR作为粗量化器由CLKSAR1控制，先对输入信号进行粗量化，得到粗量化结果k。然后，细DSM中DAC1由16个单位电容CS1,j阵列实现，使用k和BS结合进行反馈，达到了zoom的效果。细DSM中的DAC2作为残差前馈，由带权重的CF1,j阵列实现，实现了CIFF架构中的信号前馈，从而保证DSM的细量化误差可在第二级积分器的输出直接得到，残差前馈中的加(减)法模块和DSM中量化器前的加法模块合并，由无源电容加法器实现。由CLKSAR2控制的4b SAR作为扩展计数的ADC，量化了经过2倍增益放大的DSM的细量化误差，实现了扩展计数。所有的积分器都使用了一种全动态的cascoded FIA作为运放以节省功耗。在第一级积分器中采用了斩波技术来减少ficker噪声和offset，在该二阶IADC中，使用{+1,-1,-1,+1}的分形序列进行斩波。
本实施例中仅是举了一个能够实现的例子，其中：
1.粗量化和扩展计数的ADC不一定是SAR ADC；
2.DSM的架构不唯一；
3.DSM的阶数不唯一；
4.DSM的系数不唯一；
5.DSM的使用的运放结构不唯一；
6.扩展技术前的增益级增益不固定为2；
7.DSM中实现积分器的OTA不一定是cascoded FIA；
上述电路实现的控制时序如图4所示。增量型zoom ADC的一次转换包括了256个DSM运行周期。DSM以fs的过采样频率运行，粗SAR以fs/4的频率运行以节省功耗。分形序列斩波的频率也是fs/4。扩展计数的2倍增益级和扩展计数的SAR ADC仅在每个转换中的最后一个周期打开，因此它们的功耗是可忽略不计的。
如图5所示，仿真结果表明，使用本方案的架构，该增量型zoom ADC的SQNR＝118dB，相比于不使用残差前馈和扩展计数，SQNR提升了10dB左右。
如图6所示，测试结果表明，本方案的增量型zoom ADC在95Hz带宽内实现了97.6dB的SNDR，功耗仅为0.96μW，实现了高精度和极低功耗。
具体实现中，本申请提供计算机存储介质以及对应的数据处理单元，其中，该计算机存储介质能够存储计算机程序，所述计算机程序通过数据处理单元执行时可运行本发明提供的一种高精度增量型zoom ADC架构的发明内容以及各实施例中的部分或全部步骤。所述的存储介质可为磁碟、光盘、只读存储记忆体(read-only memory，ROM)或随机存储记忆体(random access memory，RAM)等。
本领域的技术人员可以清楚地了解到本发明实施例中的技术方案可借助计算机程序以及其对应的通用硬件平台的方式来实现。基于这样的理解，本发明实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机程序即软件产品的形式体现出来，该计算机程序软件产品可以存储在存储介质中，包括若干指令用以使得一台包含数据处理单元的设备(可以是个人计算机，服务器，单片机，MUU或者网络设备等)执行本发明各个实施例或者实施例的某些部分所述的方法。
本发明提供了一种高精度增量型zoom ADC架构的思路及方法，具体实现该技术方案的方法和途径很多，以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。本实施例中未明确的各组成部分均可用现有技术加以实现。

Claims (10)

  1. 一种高精度增量型zoom ADC架构，其特征在于，包括：精细的增量型DSM、粗略量化ADC、残差前馈模块以及扩展计数模块；
    其中，所述的残差前馈模块，用于重建精细的增量型DSM中的CIFF结构的信号前馈，减小增量型zoom ADC积分器的输出摆幅；残差前馈模块的输入为所述增量型zoom ADC的模拟输入VIN和粗略量化ADC的输出k，输出作为精细的增量型DSM的CIFF结构的前馈信号；
    所述的扩展计数模块用于提升增量型zoom ADC的信号量化噪声比SQNR；扩展计数模块的输入为增量模式下精细的增量型DSM中最后一级积分器在最后一个周期的输出模拟电压，即所述CIFF结构下增量型DSM的模拟量化误差，输出为经过模数转换后的精细的增量型DSM的量化误差的数字值。
  2. 根据权利要求1所述的一种高精度增量型zoom ADC架构，其特征在于，所述残差前馈模块，包括：
    输入信号传输通路、粗量化结果建立数模转换器DAC2以及加或减法模块；输入信号传输通路直接传输整个所述高精度增量型zoom ADC的输入信号VIN；粗量化结果建立数模转换器DAC2建立粗略量化ADC的量化结果；通过加或减法模块将输入信号VIN和粗量化结果建立数模转换器DAC2建立的粗量化结果相减，得到粗量化ADC的量化残差。
  3. 根据权利要求2所述的一种高精度增量型zoom ADC架构，其特征在于，所述粗量化ADC的量化残差即粗量化误差，在后续的精细的增量型DSM中使用，与精细的增量型DSM中积分器的输出进行加和，再送入精细的增量型DSM的量化器，构成完整的CIFF循环。
  4. 根据权利要求3所述的一种高精度增量型zoom ADC架构，其特征在于，所述扩展计数模块，包括：
    增益模块和计数ADC模块；其中，增益模块将精细的增量型DSM的模拟量化误差即细量化误差进行放大；计数ADC将放大后的模拟量化误差进行模数转换，得到精细增量型DSM量化误差的数字值，作为扩展计数模块的输出。
  5. 根据权利要求4所述的一种高精度增量型zoom ADC架构，其特征在于，所述的高精度增量型zoomADC的最终输出是将所述的扩展计数模块的输出加入原输出后得到。
  6. 根据权利要求5所述的一种高精度增量型zoom ADC架构，其特征在于，所述的残差前馈模块，由电容阵列实现。
  7. 根据权利要求6所述的一种高精度增量型zoom ADC架构，其特征在于，所述的电容阵列为带权重的电容阵列。
  8. 根据权利要求7所述的一种高精度增量型zoom ADC架构，其特征在于，所述的残差前馈模块中的加或减法模块，与精细的增量型DSM中量化器前的加法模块合并，由无源电容加法器实现。
  9. 根据权利要求8所述的一种高精度增量型zoom ADC架构，其特征在于，所述的扩展计数模块中的计数ADC模块，由奈奎斯特采样率的时钟信号CLKSAR2控制的4b SAR实现。
  10. 根据权利要求9所述的一种高精度增量型zoom ADC架构，其特征在于，所述的高精度增量型zoom ADC架构中，所有积分器使用全动态共源共栅浮动反相放大器cascoded FIA作为运放。
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