WO2024082559A1 - 占空比信号处理电路、方法、和音频信号处理设备 - Google Patents

占空比信号处理电路、方法、和音频信号处理设备 Download PDF

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Publication number
WO2024082559A1
WO2024082559A1 PCT/CN2023/085444 CN2023085444W WO2024082559A1 WO 2024082559 A1 WO2024082559 A1 WO 2024082559A1 CN 2023085444 W CN2023085444 W CN 2023085444W WO 2024082559 A1 WO2024082559 A1 WO 2024082559A1
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duty cycle
amplitude
signal
power supply
signal processing
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PCT/CN2023/085444
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English (en)
French (fr)
Inventor
程立
应豪
王涛涛
张启帆
张海军
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上海艾为电子技术股份有限公司
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Publication of WO2024082559A1 publication Critical patent/WO2024082559A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit

Definitions

  • the present application relates to the field of circuit technology, and in particular to a duty cycle signal processing circuit, method, and audio signal processing device.
  • Amplifier units such as Class D amplifiers and corresponding duty cycle signal processing circuits are important components of audio signal processing equipment.
  • Class D amplifiers can be used for the pulse width modulation process of audio signals.
  • Class D amplifiers have the characteristics of high conversion efficiency, which not only prolongs the service life of the chip power supply battery, but also reduces the heat dissipation of the chip itself.
  • For high-power amplifier chips only a small heat sink is needed or no heat sink is needed, saving chip packaging costs.
  • Class D amplifiers are getting closer and closer to the performance of traditional linear amplifiers in terms of sound quality, and are extremely popular in the audio amplifier market.
  • the output stage of this type of power amplifier unit is composed of two complementary switching power tubes. Driven by high-frequency control pulses, the power tubes work in an open state, which is consistent with the working principle of the inverter. When one switching power tube is turned on, the other switching power tube is turned off. Therefore, the switching power tube does not require static current and has a high conversion efficiency. In theory, the efficiency of this type of power amplifier unit can reach 100%, but in reality, due to the power loss of the on-resistance of the switching power tube and the charging and discharging of the LC filter at the output end of the power amplifier, the conversion efficiency of the corresponding power amplifier unit will be affected.
  • the present application provides a duty cycle signal processing circuit, method, and audio signal processing device to solve the technical problem that the traditional solution affects the conversion efficiency of the power amplifier unit.
  • a first aspect of the present application provides a duty cycle signal processing circuit, comprising an amplitude detector and an operation unit;
  • the amplitude detector is used to detect a first amplitude of the audio signal, generate a second amplitude, and send the second amplitude to the operation unit;
  • the operation unit is used to obtain the power supply voltage, perform operation processing on the second amplitude and the power supply voltage, and obtain a duty cycle control signal in which at least one parameter of the second amplitude and the power supply voltage matches.
  • the operation unit is further used to obtain a theoretical duty cycle according to preset conditions, and determine the duty cycle control signal according to the theoretical duty cycle and an expected duty cycle gear.
  • the preset condition may include an operation formula:
  • DPWM represents the theoretical duty cycle
  • VSUP represents the power supply voltage
  • Vamp_out represents the second amplitude
  • VHR represents the amplitude margin
  • the operation unit includes a comparison subunit and a transcoder; the comparison subunit is used to compare the second amplitude with multiple comparison thresholds respectively, and output the comparison results to the transcoder, and each of the comparison thresholds is determined according to the power supply voltage, the amplitude margin and the duty cycle gear, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage; the transcoder is used to transcode the comparison result to obtain the duty cycle control signal corresponding to the comparison result.
  • the comparison subunit includes a first comparator, a second comparator, a third comparator and a fourth comparator
  • the comparison threshold includes a first threshold, a second threshold, a third threshold and a fourth threshold
  • the first input terminal of the first comparator is connected to the second amplitude, the second input terminal is connected to the first threshold, and the output terminal is connected to the first input terminal of the transcoder
  • the first input terminal of the second comparator is connected to the second amplitude, the second input terminal is connected to the second threshold, and the output terminal is connected to the second input terminal of the transcoder
  • the first input terminal of the third comparator is connected to the second amplitude, the second input terminal is connected to the third threshold, and the output terminal is connected to the third input terminal of the transcoder
  • the first input terminal of the fourth comparator is connected to the second amplitude, the second input terminal is connected to the fourth threshold, and the output terminal is connected to the fourth input terminal of the transcoder.
  • the expected duty cycle gears include a first duty cycle, a second duty cycle, a third duty cycle and a fourth duty cycle;
  • VT1 represents the first threshold
  • A1 represents the first duty cycle
  • VT2 represents the second threshold
  • A2 represents the second duty cycle
  • VT3 represents the third threshold
  • A3 represents the third duty cycle
  • VT4 represents the fourth threshold
  • A4 represents the fourth duty cycle.
  • the duty cycle signal processing circuit also includes a common mode voltage control unit; the input end of the common mode voltage control unit is connected to the output end of the operation unit, and is used to perform operation processing according to the duty cycle control signal to obtain the common mode voltage corresponding to the duty cycle control signal.
  • the common-mode voltage control unit includes a voltage divider subunit and a multiplexer; the voltage divider subunit is used to perform multiple voltage division processes on the connected reference voltage to obtain voltage division signals after each voltage division process; the control end of the multiplexer is connected to the duty cycle control signal, and the corresponding voltage output channel is selected according to the duty cycle control signal to output the corresponding common-mode voltage.
  • the voltage divider subunit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; the first end of the first resistor is connected to the reference voltage, and the second end is respectively connected to the first end of the second resistor and the first input end of the multiplexer; the second end of the second resistor is respectively connected to the first end of the third resistor and the second input end of the multiplexer; the second end of the third resistor is respectively connected to the first end of the fourth resistor and the third input end of the multiplexer; the second end of the fourth resistor is respectively connected to the first end of the fifth resistor and the fourth input end of the multiplexer; the second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the fifth input end of the multiplexer; the second end of the sixth resistor is grounded.
  • the duty cycle signal processing circuit further includes an analog-to-digital converter; the analog-to-digital converter is used to obtain the electrical source voltage, after converting the power supply voltage into a digital signal, the converted power supply voltage is output to the operation unit.
  • the present application also provides a duty cycle signal processing method, which is applied to any of the above-mentioned duty cycle signal processing circuits, comprising:
  • the power supply voltage is acquired, and the second amplitude and the power supply voltage are processed by operation to obtain a duty cycle control signal in which at least one parameter of the second amplitude and the power supply voltage matches.
  • the method of performing operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: obtaining a theoretical duty cycle based on preset conditions, and determining the duty cycle control signal based on the theoretical duty cycle and an expected duty cycle gear.
  • DPWM represents the theoretical duty cycle
  • VSUP represents the power supply voltage
  • Vamp_out represents the second amplitude
  • VHR represents the amplitude margin
  • the method of performing operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: comparing the second amplitude with multiple comparison thresholds respectively, and outputting the comparison result to the transcoder, each of the comparison thresholds being determined based on the power supply voltage, the amplitude margin and the duty cycle gear, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage; transcoding the comparison result to obtain a duty cycle control signal corresponding to the comparison result.
  • the duty cycle signal processing method further includes: performing calculation processing according to the duty cycle control signal to obtain a common mode voltage corresponding to the duty cycle control signal.
  • the present application also provides an audio signal processing device, comprising an audio processing unit, a power amplifier unit, a driver, and any of the above-mentioned duty cycle signal processing circuits;
  • the audio processing unit is used to perform a first modulation process on the received audio signal to obtain a first modulation signal, and send the first modulation signal to the power amplifier unit;
  • the power amplifier unit is used to receive the first modulation signal and the common mode voltage output by the duty cycle signal processing circuit, perform a second modulation process on the common mode voltage according to the first modulation signal to obtain a second modulation signal, and send the second modulation signal to the driver;
  • the driver is used to drive the corresponding playing component according to the second modulation signal to play the audio signal.
  • the audio processing unit includes a delayer, a DSM modulator and a digital-to-analog converter; the delayer is used to delay the audio signal and output the delayed audio signal to the DSM modulator; the DSM modulator is used to perform DSM modulation on the delayed audio signal and output an initial modulated signal; the analog-to-digital converter is used to perform digital-to-analog conversion on the initial modulated signal and output the first modulated signal.
  • the power amplifier unit includes a PWM modulator; the PWM modulator is used to perform a second modulation process on the common mode voltage to obtain a second modulation signal.
  • the power amplifier unit further includes an integrator; the integrator is used to receive the first modulation signal and the common-mode voltage, filter the common-mode voltage according to the first modulation signal, and output the filtered common-mode voltage to the PWM modulator.
  • the audio signal processing device further includes a playing component, and the playing component is connected to the output end of the driver.
  • the amplitude detector can send a second amplitude corresponding to the audio signal amplitude to the operation unit, so that the operation unit performs operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage, so that the subsequent power amplifier unit such as the Class D power amplifier performs a driving operation according to the duty cycle control signal, wherein the duty cycle control signal matches at least one parameter of the second amplitude and the power supply voltage, so that the power amplifier unit can adaptively adjust the common-mode duty cycle in the power amplifier unit according to at least one parameter of the audio signal amplitude and the power supply voltage.
  • the common-mode duty cycle When the signal amplitude is low or in an idle state, the common-mode duty cycle will be correspondingly reduced, reducing the corresponding switch-on time, reducing the static power consumption loss of the on-resistance, and the power consumption loss of the LC charging and discharging, which can improve the conversion efficiency of the power amplifier unit, reduce the driving power consumption, and thus reduce the power consumption of the entire audio signal processing device without causing audio signal distortion.
  • FIG1 is a waveform diagram of the inventor's research solution
  • FIG2 is a schematic diagram of a duty cycle signal processing circuit structure according to an embodiment of the present application.
  • 3a and 3b are schematic diagrams of the structure of a computing unit according to an embodiment of the present application.
  • FIG4 is a schematic diagram of a duty cycle signal processing circuit structure according to another embodiment of the present application.
  • 5a and 5b are schematic diagrams of the structure of a common-mode voltage control unit according to an embodiment of the present application.
  • FIG6 is a schematic diagram of a duty cycle signal processing circuit structure according to another embodiment of the present application.
  • FIG7 is a schematic diagram of a duty cycle signal processing method according to an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of an audio signal processing device according to an embodiment of the present application.
  • FIG9 is a schematic structural diagram of an audio signal processing device according to another embodiment of the present application.
  • FIG. 10 a , FIG. 10 b and FIG. 10 c are schematic diagrams of waveform analysis in an embodiment of the present application.
  • BD modulation mode to encode audio input signals using pulse width modulation (such as PWM) and a triangle wave (or sawtooth) waveform generator or oscillator.
  • the BD modulation modulates the duty cycle of the difference between the output signals so that its average content corresponds to the input analog signal.
  • BD modulation provides superior audio performance (e.g., reduced pops and clicks) to a certain extent.
  • BD modulation consumes much more power than other common modulation techniques such as AD modulation.
  • BD modulation has significant common-mode content in its output.
  • the common-mode duty cycle is at or close to fifty percent (50%) because the ripple current is largest at these duty cycles.
  • the scheme is that when the level of the analog input signal is below the threshold level, the common-mode duty cycle is 50%; when the level of the analog input signal is below the threshold level, the modulator shifts the common-mode duty cycle of each of the first quantized signal and the second quantized signal so that the common-mode duty cycle is one of greater than or less than fifty percent (50%). In this way, the power consumed by the load (such as a speaker) is reduced accordingly, thereby improving the efficiency of the power amplifier to a certain extent, but the improvement effect is limited.
  • the common-mode duty cycle of the PWM (pulse width modulation) output is fixedly set to a smaller value (such as 15%), which can reduce the switch-on time and the LC charging and discharging time, reduce power consumption loss, and improve efficiency.
  • a smaller value such as 15%
  • the 15% common-mode duty cycle cannot meet the amplitude requirement of the signal modulation. It is necessary to adjust the common-mode reference voltage of the integrator by comparing the output signal of the integrator with the DC reference level to increase the duty cycle of the signal modulation, but this method will cause the class D amplifier to enter the unilateral modulation mode. As shown in the waveform of Figure 1, only one side of PWM_P and PWM_N will flip.
  • the THD (total harmonic distortion) performance of the audio signal is poor. Therefore, this scheme improves the conversion efficiency of the class D power amplifier, but entering the unilateral pulse width modulation mode will introduce more serious signal distortion, resulting in poor THD+N performance of large-signal audio signals. For example, when the signal amplitude is large, the power amplifier enters the unilateral modulation mode, which will cause the audio signal to be distorted, etc.
  • the present application generates a common-mode voltage that matches at least one parameter of the signal amplitude and the power supply voltage through a duty cycle signal processing circuit, so that the power amplifier unit can adaptively adjust the PWM common-mode duty cycle according to the audio signal amplitude and the power supply voltage.
  • the common-mode duty cycle will be reduced accordingly, reducing the switch-on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and discharging, improving the conversion efficiency, and reducing the driving power consumption, thereby reducing the power consumption of the entire audio signal processing device without causing audio signal distortion.
  • the present application provides a duty cycle signal processing circuit.
  • the duty cycle signal processing circuit includes an amplitude detector 110 and an operation unit 200.
  • the input end of the amplitude detector 110 is connected to an audio signal, and the output end is connected to a first input end of the operation unit 200.
  • the second input end of the operation unit 200 is connected to a power supply voltage, and the output end outputs a duty cycle control signal.
  • the amplitude detector 110 is used to detect a first amplitude of the audio signal, generate a second amplitude, and send the second amplitude to the operation unit 200; the operation unit 200 is used to obtain a power supply voltage, perform operation processing on the second amplitude and the power supply voltage, and obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage, so that a subsequent power amplifier unit such as a Class D power amplifier performs a driving operation according to the duty cycle control signal, so that the duty cycle control signal matches at least one parameter of the second amplitude and the power supply voltage, so that the common-mode duty cycle in the power amplifier unit can be adaptively adjusted according to at least one parameter of the amplitude of the audio signal and the power supply voltage, and when the signal When the amplitude is low or in idle state, the common-mode duty cycle will decrease accordingly, reducing the corresponding switch-on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and dischar
  • the amplitude detector 110 may perform gain processing on the obtained amplitude to determine the second amplitude.
  • the gain processing performed by the amplitude detector 110 on the amplitude may include:
  • Vamp_out Vamp_in*Gain, wherein Vamp_out represents the second amplitude, Vamp_in represents the first amplitude, the first amplitude includes the amplitude of the input audio signal, Gain represents a gain parameter, and the symbol * represents multiplication.
  • the audio signal includes a digital audio signal, and the amplitude detector 110 can detect the level amplitude of the digital audio signal to obtain the amplitude of the audio signal.
  • the operation unit 200 may include a device such as a comparator and/or a transcoder that can perform operation processing on the second amplitude and the power supply voltage to obtain a required duty cycle control signal.
  • this example can set an expected duty cycle gear, for example, the expected duty cycle gear includes 50%, 40%, 30%, 20% and 10% duty cycle gears, so that the operation unit 200 can perform operation processing on the second amplitude, the power supply voltage and the duty cycle corresponding to these expected duty cycle gears to obtain the corresponding duty cycle, which can simplify the corresponding operation process and improve the stability of the operation process.
  • the operation unit is further used to obtain a theoretical duty cycle according to a preset condition, and determine the duty cycle control signal according to the theoretical duty cycle and an expected duty cycle gear, so that the theoretical duty cycle obtained by using the preset condition matches at least one parameter of the second amplitude and the power supply voltage.
  • this embodiment can round up the theoretical duty cycle to obtain a corresponding duty cycle signal, or can select a duty cycle that is greater than or equal to and closest to the theoretical duty cycle in the expected duty cycle gear as the duty cycle control signal.
  • the amplitude margin VHR represents the margin of the maximum signal amplitude allowed in the theory of the common mode duty cycle setting relative to the actual maximum signal amplitude without distortion, which can be set by configuration or the like, for example, can be set to a value such as 1V (volt).
  • the above-mentioned operation formula of the duty cycle control signal can be used by the operation unit 200 to obtain a more accurate duty cycle control signal.
  • the operation unit 200 includes a comparison subunit 210 and a transcoder 220; the comparison subunit 210 is used to compare the second amplitude with a plurality of comparison thresholds respectively, and output the corresponding comparison results to the transcoder 220; the transcoder 220 is used to transcode the comparison results to obtain the duty cycle control signal corresponding to the comparison results.
  • Each comparison threshold is determined according to the power supply voltage VSUP, the amplitude margin VHR and the expected duty cycle gear, so that the duty cycle control signal corresponding to the comparison result matches at least one parameter of the second amplitude and the power supply voltage.
  • the comparison threshold may include n thresholds such as VT1 to VTn, and the number of the comparison thresholds may be determined according to the number of duty cycle gears to be designed; for example, if N duty cycle gears need to be set to be adjustable, N-1 comparison thresholds and N-1 corresponding comparators may be set.
  • the comparison subunit 210 includes a first comparator CMP1, a second comparator CMP2, a third comparator CMP3 and a fourth comparator CMP4, and the comparison thresholds include a first threshold VT1, a second threshold VT2, a third threshold VT3 and a fourth threshold VT4;
  • the first input terminal of the first comparator CMP1 is connected to The second amplitude Vamp_out, the second input end is connected to the first threshold VT1, and the output end is connected to the first input end of the transcoder 220;
  • the first input end of the second comparator CMP2 is connected to the second amplitude Vamp_out, the second input end is connected to the second threshold VT2, and the output end is connected to the second input end of the transcoder 220;
  • the first input end of the third comparator CMP3 is connected to the second amplitude Vamp_out, the second input end is connected to the third threshold VT3, and the output end is connected to the third input end of the transcode
  • the expected duty cycle may also include a fifth duty cycle A5.
  • the sizes of the first duty cycle A1, the second duty cycle A2, the third duty cycle A3, the fourth duty cycle A4 and the fifth duty cycle A5 may be set according to the modulation requirements of the corresponding power amplifier unit such as the Class D power amplifier.
  • the first duty cycle A1 may be set to 10%
  • the second duty cycle A2 may be set to 20%
  • the third duty cycle A3 may be set to 30%
  • the fourth duty cycle A4 may be set to 40%
  • the fifth duty cycle A5 may be set to 50%.
  • the fourth threshold VT4 is represented as the judgment threshold corresponding to the 50% gear.
  • the third threshold VT3 is represented as the judgment threshold corresponding to the 40% gear.
  • the 40% gear is selected, and the transcoder 220 outputs a duty cycle control signal corresponding to 40%.
  • the second threshold VT2 is represented as the judgment threshold corresponding to the 30% gear.
  • VT3 ⁇ Vamp_out>VT2 the 30% gear is selected, and the transcoder 220 outputs a duty cycle control signal corresponding to 30%.
  • the first threshold VT1 is represented as the judgment threshold corresponding to the 20% gear.
  • the duty cycle control signal output by the transcoder 220 can be recorded as VCM_SEL ⁇ 4:0>, and VCM_SEL ⁇ 4:0> includes five duty cycle control signals, namely VCM_SEL4, VCM_SEL3, VCM_SEL2, VCM_SEL1, and VCM_SEL0.
  • the above-mentioned duty cycle signal processing circuit also includes a common-mode voltage control unit 120; the input end of the common-mode voltage control unit 120 is connected to the output end of the operation unit 200, and is used to perform operation processing according to the duty cycle control signal to obtain the common-mode voltage corresponding to the duty cycle control signal, so as to provide the common-mode voltage to a power amplifier unit such as a Class D power amplifier, adjust the common-mode duty cycle of the Class D power amplifier unit, thereby achieving the purpose of improving conversion efficiency.
  • a power amplifier unit such as a Class D power amplifier
  • the common-mode voltage control unit 120 may include a voltage divider unit or other unit for obtaining multiple voltage levels, so as to perform voltage division processing according to factors such as expected duty cycle levels to obtain a common-mode voltage corresponding to the duty cycle control signal.
  • the common mode voltage control unit 120 includes a voltage dividing subunit 121 and a multiplexer 122; the voltage dividing subunit 121 is used to divide the connected reference voltage VDD multiple times.
  • the control end of the multiplexer 22 is connected to the duty cycle control signal, and the corresponding voltage output channel is selected according to the duty cycle control signal to output the corresponding common-mode voltage, where the common-mode voltage includes the voltage divided signal output by the corresponding voltage output channel.
  • the voltage division subunit 121 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, and the voltage division signal includes a first signal VCM_D10, a second signal VCM_D20, a third signal VCM_D30, a fourth signal VCM_D40 and a fifth signal VCM_D50;
  • the first end of the first resistor R1 is connected to the reference voltage VDD, and the second end is respectively connected to the first end of the second resistor R2 and the first input end of the multiplexer 122;
  • the second end of the second resistor R2 is respectively connected to the first end of the third resistor R3 and the second input end of the multiplexer 122;
  • the second end of the third resistor R3 is respectively connected to the first end of the fourth resistor R4 and the third input end of the multiplexer 122;
  • the second end of the fourth resistor R4 is respectively connected to
  • the multiplexer 122 may include five voltage output channels, which are connected to the duty cycle control signal VCM_SEL ⁇ 4:0>, and the corresponding voltage output channels are selected according to the above duty cycle control signal; for example, when receiving VCM_SEL4, the multiplexer 122 can select the first channel to output the first signal VCM_D10 as the common mode voltage; when receiving VCM_SEL3, the second channel can be selected to output the second signal VCM_D20 as the common mode voltage; when receiving VCM_SEL2, the third channel can be selected to output the third signal VCM_D30 as the common mode voltage; when receiving VCM_SEL1, the fourth channel can be selected to output the fourth signal VCM_D40 as the common mode voltage; when receiving VCM_SEL0, the fifth channel can be selected to output the fifth signal VCM_D50 as the common mode voltage.
  • the duty cycle signal processing circuit further includes an analog-to-digital converter 130; the analog-to-digital converter 130 is used to obtain the power supply voltage, convert the power supply voltage into a digital signal, and then output the converted power supply voltage to the operation unit 200, so that the operation unit 200 performs operation processing based on the power supply voltage in digital form, thereby improving the stability of the processing process.
  • the analog-to-digital converter 130 is used to obtain the power supply voltage, convert the power supply voltage into a digital signal, and then output the converted power supply voltage to the operation unit 200, so that the operation unit 200 performs operation processing based on the power supply voltage in digital form, thereby improving the stability of the processing process.
  • the amplitude detector 110 can send a second amplitude corresponding to the audio signal amplitude to the operation unit 200, so that the operation unit 200 performs operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage, so that the subsequent power amplifier unit such as the Class D power amplifier performs a driving operation according to the duty cycle control signal, wherein the duty cycle control signal matches at least one parameter of the second amplitude and the power supply voltage, so that the common-mode duty cycle in the power amplifier unit can be adaptively adjusted according to at least one parameter of the audio signal amplitude and the power supply voltage.
  • the common-mode duty cycle When the signal amplitude is low or in an idle state, the common-mode duty cycle will be correspondingly reduced, reducing the corresponding switch-on time, reducing the static power consumption loss of the on-resistance, and the power consumption loss of the LC charging and discharging, and can improve the conversion efficiency of the power amplifier unit.
  • the present application provides a duty cycle signal processing method, which is applied to the duty cycle signal processing circuit described in any of the above embodiments.
  • the duty cycle control signal processing method includes S310 and S320.
  • the method of performing operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: obtaining a theoretical duty cycle according to preset conditions, and determining the duty cycle control signal according to the theoretical duty cycle and an expected duty cycle gear.
  • DPWM represents the theoretical duty cycle
  • VSUP represents the power supply voltage
  • Vamp_out represents the second amplitude
  • VHR represents the amplitude margin
  • step S320 shown in FIG. 7 the method of performing operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal matching at least one parameter of the second amplitude and the power supply voltage further includes:
  • each of the comparison thresholds is determined according to the power supply voltage, the amplitude margin and the duty cycle gear, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage;
  • the comparison result is transcoded to obtain a duty cycle control signal corresponding to the comparison result.
  • the duty cycle signal processing method further includes: performing calculation processing according to the duty cycle control signal to obtain a common mode voltage corresponding to the duty cycle control signal.
  • the above-mentioned duty cycle signal processing method is applied to the duty cycle signal processing circuit described in any of the above-mentioned embodiments, and has all the beneficial effects of the duty cycle signal processing circuit described in any of the above-mentioned embodiments, which will not be repeated here.
  • the present application provides an audio signal processing device.
  • the audio signal processing device includes an audio processing unit 410 , a power amplifier unit 420 , a driver 430 , and a duty cycle signal processing circuit 500 as described in any one of the above embodiments;
  • the audio processing unit 410 is used to perform a first modulation process on the received audio signal to obtain a first modulation signal, and send the first modulation signal to the power amplifier unit 420;
  • the power amplifier unit 420 is used to receive the first modulation signal and the common mode voltage output by the duty cycle signal processing circuit 500, perform a second modulation process on the common mode voltage according to the first modulation signal to obtain a second modulation signal, and send the second modulation signal to the driver 430;
  • the driver 430 is used to drive the corresponding playing component 440 according to the second modulation signal to play the audio signal.
  • the audio processing unit 410 may include a component for transmitting and modulating audio signals, such as a DSM modulator.
  • the power amplifier unit 420 may include a class D power amplifier.
  • the driver 430 and the analog-to-digital converter 130 in the duty cycle signal processing circuit 500 are also connected to an external power supply, and the voltage of the external power supply is the power supply voltage VSUP.
  • the above-mentioned audio signal processing device adopts the duty cycle signal processing circuit 500 described in any of the above-mentioned embodiments to generate a common mode voltage.
  • the power amplifier unit 420 performs a second modulation process, so that the power amplifier unit 420 can adaptively adjust the PWM common mode duty cycle according to the audio signal amplitude and the power supply voltage.
  • the common mode duty cycle will be reduced accordingly. Small, shorten the switch opening time, reduce the static power loss of on-resistance, and the power loss of LC charging and discharging, and improve the conversion efficiency.
  • the audio processing unit 410 includes a delay 411, a DSM modulator (delta-sigma modulator) 412 and a digital-to-analog converter 413; the input end of the delay 411 is connected to an audio signal, which may include a digital audio signal, and the output end is connected to the analog-to-digital converter 413 through the DSM modulator 412.
  • a DSM modulator delta-sigma modulator
  • the delayer 411 is used to delay the audio signal and output the delayed audio signal to the DSM modulator 412; the DSM modulator 412 is used to perform DSM modulation on the delayed audio signal and output the initial modulation signal; the analog-to-digital converter 413 is used to perform digital-to-analog conversion on the initial modulation signal and output the first modulation signal.
  • the delay time of the delayer 411 can be set according to factors such as the response characteristics of the audio signal, for example, it can be set to a delay time such as 1ms (milliseconds).
  • the delayer 411 delays the audio signal, so that the duty cycle control signal in the duty cycle signal processing circuit 500 can respond to the accuracy of the audio signal and/or the power supply voltage in advance, thereby improving the corresponding modulation effect.
  • the power amplifier unit includes a PWM modulator 422; the PWM modulator 422 is used to perform a second modulation process on the common mode voltage to obtain a second modulation signal, and output the second modulation signal to the driver 430.
  • the PWM modulator 422 can be connected between the integrator 421 and the driver 430.
  • the PWM modulator 422 can be connected between the audio processing unit 410 (such as the analog-to-digital converter 413) and the driver 430, and at this time, one input end of the PWM modulator 422 can also be connected to the output end of the duty cycle signal processing circuit 500 (such as the common mode voltage control unit 120).
  • the power amplifier unit 420 also includes an integrator 421; the integrator 421 is used to receive the first modulation signal and the common-mode voltage, filter the common-mode voltage according to the first modulation signal, and output the filtered common-mode voltage to the PWM modulator 422, so that the PWM modulator 422 generates a corresponding control waveform according to the common-mode voltage, and the driver 430 performs a driving operation according to the control waveform.
  • the audio signal processing device further includes a playing component 440, which is connected to the output end of the driver 430 to play the corresponding audio signal under the drive of the driver 430.
  • the playing component 440 may include a speaker or other component for playing audio signals.
  • the inventors analyzed the working process of the PWM modulator 422 in the power amplifier unit 420 and found that the PWM modulator 422 performs the second modulation process to generate a control waveform, and the control waveform includes a PWM common-mode duty cycle. If the power supply voltage remains unchanged, the change characteristics of the PWM common-mode duty cycle with the amplitude of the audio signal can be referred to as shown in FIG10a. It can be seen from FIG10a that the power supply voltage remains unchanged.
  • the PWM common-mode duty cycle When the level (amplitude) of the input audio signal is high, the PWM common-mode duty cycle remains at 50%; when the level of the audio signal becomes lower, the common-mode duty cycle gradually decreases (for example, it becomes 40%, 30%, 20%, 10% in sequence); when the input is idle, the output duty cycle remains at 10%.
  • the change characteristics of the PWM common-mode duty cycle with the power supply voltage can be referred to as shown in FIG10b. It can be seen from FIG10b that when the amplitude of the audio signal remains unchanged, the power supply voltage becomes higher, and the PWM common-mode duty cycle is correspondingly smaller; the power supply voltage becomes lower, and the PWM common-mode duty cycle is correspondingly larger.
  • the duty cycle control signal generated by the duty cycle signal processing circuit 500 when it is detected that the power supply voltage becomes high, a certain delay is required before the common mode duty cycle becomes low, which reflects the duty cycle control signal generated by the duty cycle signal processing circuit 500.
  • the signal can provide a slow exit function; when the power supply voltage is detected to be low, the PWM common-mode duty cycle quickly increases, and the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a fast entry function.
  • the common-mode duty cycle when the level of the audio signal is detected to be low, the common-mode duty cycle will not become low until a certain delay has passed, which reflects that the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a slow exit function; when the level of the audio signal is detected to be high, the PWM common-mode duty cycle quickly increases, and the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a fast entry function.
  • the inventors also studied the traditional PWM modulation process and found that the common mode of the triangular wave of the traditional PWM modulation is the same as the common mode of the input audio signal, for example, 0.5AVDD, so the common mode duty cycle of the output signal is usually 50%.
  • the audio processing device provided in the present application can use adaptive duty cycle modulation technology to monitor the audio signal amplitude and the power supply voltage value, and judge the proportional relationship between the signal and the power supply voltage through relevant operations, so as to infer that the signal voltage will not exceed the maximum DC reference voltage of the power supply level.
  • the audio processing device using the duty cycle signal processing circuit 500 described in any of the above embodiments has the following advantages: 1. According to the audio signal amplitude and the power supply voltage, the common mode duty cycle of the power amplifier output is adaptively adjusted to reduce the power loss of the switch resistance and LC charging and discharging, improve the power amplifier efficiency, and will not cause audio signal distortion. 2. Detect the audio signal amplitude in advance to predict the output audio signal.
  • the common mode duty cycle can be adjusted to the corresponding gear in advance. 3. Detect the current power supply voltage of the power amplifier and use the power supply voltage as a reference for adjusting the common mode duty cycle, which can adapt to a wide range of power supply voltage changes. 4. Control the common mode duty cycle to adjust slowly to prevent audio signal abnormalities caused by sudden large common mode duty cycle switching. 5.
  • the comparison threshold can be flexibly configured.
  • the duty cycle signal processing circuit 500 generates a common-mode voltage that matches at least one parameter of the signal amplitude and the power supply voltage.
  • the power amplifier unit 420 can adaptively adjust the PWM common-mode duty cycle according to the audio signal amplitude and the power supply voltage. When the signal amplitude is low or in an idle state, the common-mode duty cycle will be reduced accordingly, reducing the switch-on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and discharging, improving the conversion efficiency, and reducing the driving power consumption, thereby reducing the power consumption of the entire audio signal processing device.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more features. In the description of this application, the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.

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Abstract

本申请公开一种占空比信号处理电路、方法、和音频信号处理设备；占空比信号处理电路包括：包括幅度检测器和运算单元；所述幅度检测器用于检测音频信号的第一幅度，生成第二幅度，向所述运算单元发送所述第二幅度；所述运算单元用于获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号。本申请可以提高对应功放单元的转换效率。

Description

占空比信号处理电路、方法、和音频信号处理设备
本申请要求申请日为2022年10月20日、申请号为“202211290657.7”、专利名称为“占空比信号处理电路、方法、和音频信号处理设备”的发明申请的优先权，其全部内容在此引入作为参考。
技术领域
本申请涉及电路技术领域，具体涉及一种占空比信号处理电路、方法、和音频信号处理设备。
背景技术
D类功放等功放单元以及对应的占空比信号处理电路是音频信号处理设备的重要组成部分，以D类功放为例可知，D类功放可用于音频信号的脉宽调制过程，与传统线性功放相比，D类功放具转换效率高的特点，不仅延长芯片供电电池的使用寿命，而且芯片本身的散热小，对于大功率功放芯片工作，只需要很小的散热片或者是不需要散热片，节省芯片封装成本。随着芯片制造工艺和电路设计水平的不断提高，D类功放在音质上也越来越接近传统线性功放性能，在音频功放市场上受到极大的欢迎。
D类功放这类功放单元的输出级由两个互补的开关功率管组成，在高频控制脉冲的驱动下，功率管工作在开管状态，与反相器工作原理一致，一个开关功率管导通、则另一个开关功率管关断，因此开关功率管工作不需要静态电流，具有很高的转换效率。理论上这类功放单元的效率可以达到100％，但实际由于开关功率管导通电阻的功率损耗，及功率放大器输出端LC滤波器的充放电，会影响对应功放单元的转换效率。
发明内容
鉴于此，本申请提供一种占空比信号处理电路、方法、和音频信号处理设备，以解决传统方案影响功放单元的转换效率的技术问题。
本申请第一方面提供一种占空比信号处理电路，包括幅度检测器和运算单元；
所述幅度检测器用于检测音频信号的第一幅度，生成第二幅度，向所述运算单元发送所述第二幅度；
所述运算单元用于获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号。
可选地，所述运算单元还用于依据预设条件获取理论占空比，根据所述理论占空比和预期的占空比档位确定所述占空比控制信号。
可选地，所述预设条件可以包括运算公式：
DPWM*VSUP＝Vamp_out+VHR，
其中，DPWM表示理论占空比，VSUP表示电源电压，Vamp_out表示第二幅度，VHR表示幅度余量。
可选地，所述运算单元包括比较子单元和转码器；所述比较子单元用于将所述第二幅度分别与多个比较阈值进行比较，向所述转码器输出比较结果，各个所述比较阈值分别依据所述电源电压、所述幅度余量和所述占空比档位确定，以使所述比较阈值对应的占空比控制信号匹配所述第二幅度和所述电源电压中至少一个参数；所述转码器用于对所述比较结果进行转码，以得到所述比较结果对应的占空比控制信号。
可选地，所述比较子单元包括第一比较器、第二比较器、第三比较器和第四比较器，所述比较阈值包括第一阈值、第二阈值、第三阈值和第四阈值；所述第一比较器的第一输入端接入所述第二幅度，第二输入端接入所述第一阈值，输出端连接所述转码器的第一输入端；所述第二比较器的第一输入端接入所述第二幅度，第二输入端接入所述第二阈值，输出端连接所述转码器的第二输入端；所述第三比较器的第一输入端接入所述第二幅度，第二输入端接入所述第三阈值，输出端连接所述转码器的第三输入端；所述第四比较器的第一输入端接入所述第二幅度，第二输入端接入所述第四阈值，输出端连接所述转码器的第四输入端。
可选地，预期的占空比档位包括第一占空比、第二占空比、第三占空比和第四占空比；
所述第一阈值包括：VT1＝A1×VSUP-VHR；
所述第二阈值包括：VT2＝A2×VSUP-VHR；
所述第三阈值包括：VT3＝A3×VSUP-VHR；
所述第四阈值包括：VT4＝A4×VSUP-VHR；
其中，VT1表示第一阈值，A1表示第一占空比，VT2表示第二阈值，A2表示第二占空比，VT3表示第三阈值，A3表示第三占空比，VT4表示第四阈值，A4表示第四占空比。
可选地，占空比信号处理电路还包括共模电压控制单元；所述共模电压控制单元的输入端连接所述运算单元的输出端，用于根据所述占空比控制信号进行运算处理，得到所述占空比控制信号对应的共模电压。
可选地，所述共模电压控制单元包括分压子单元和多路选通器；所述分压子单元用于对接入的参考电压进行多次分压处理，得到各次分压处理后的分压信号；所述多路选通器的控制端接入所述占空比控制信号，根据所述占空比控制信号选通对应的电压输出通道，以输出对应的共模电压。
可选地，所述分压子单元包括第一电阻、第二电阻、第三电阻、第四电阻、第五电阻和第六电阻；所述第一电阻的第一端接入所述参考电压，第二端分别连接所述第二电阻的第一端和所述多路选通器的第一输入端；所述第二电阻的第二端分别连接所述第三电阻的第一端和所述多路选通器的第二输入端；所述第三电阻的第二端分别连接所述第四电阻的第一端和所述多路选通器的第三输入端；所述第四电阻的第二端分别连接所述第五电阻的第一端和所述多路选通器的第四输入端；所述第五电阻的第二端分别连接所述第六电阻的第一端和所述多路选通器的第五输入端；所述第六电阻的第二端接地。
可选地，占空比信号处理电路还包括模数转换器；所述模数转换器用于获取所述电 源电压，将所述电源电压转换为数字信号后，将转换后的所述电源电压输出至所述运算单元。
本申请还提供一种占空比信号处理方法，应用于上述任一种占空比信号处理电路，包括：
检测音频信号的第一幅度，生成第二幅度；
获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号。
可选地，所述对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号的方法进一步包括：依据预设条件获取理论占空比，根据所述理论占空比和预期的占空比档位确定所述占空比控制信号。
可选地，所述预设条件可以包括运算公式：
DPWM*VSUP＝Vamp_out+VHR，
其中，DPWM表示理论占空比，VSUP表示电源电压，Vamp_out表示第二幅度，VHR表示幅度余量。
可选地，所述对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号的方法进一步包括：将所述第二幅度分别与多个比较阈值进行比较，向所述转码器输出比较结果，各个所述比较阈值分别依据所述电源电压、所述幅度余量和所述占空比档位确定，以使所述比较阈值对应的占空比控制信号匹配所述第二幅度和所述电源电压中至少一个参数；对所述比较结果进行转码，以得到所述比较结果对应的占空比控制信号。
可选地，占空比信号处理方法，还包括：根据所述占空比控制信号进行运算处理，得到所述占空比控制信号对应的共模电压。
本申请还提供一种音频信号处理设备，包括音频处理单元、功放单元、驱动器和上述任一种占空比信号处理电路；
所述音频处理单元用于对接入的音频信号进行第一调制处理，得到第一调制信号，向所述功放单元发送所述第一调制信号；
所述功放单元用于接收所述第一调制信号和占空比信号处理电路输出的共模电压，根据所述第一调制信号对所述共模电压进行第二调制处理，得到第二调制信号，向所述驱动器发送所述第二调制信号；
所述驱动器用于根据所述第二调制信号驱动对应的播放组件，以播放所述音频信号。
可选地，所述音频处理单元包括延迟器、DSM调制器和数模转换器；所述延迟器用于对所述音频信号进行延迟处理，向所述DSM调制器输出延迟后的音频信号；所述DSM调制器用于对所述延迟后的音频信号进行DSM调制，输出初始调制信号；所述模数转换器用于对所述初始调制信号进行数模转换，输出所述第一调制信号。
可选地，所述功放单元包括PWM调制器；所述PWM调制器用于对所述共模电压进行第二调制处理，得到第二调制信号。
可选地，所述功放单元还包括积分器；所述积分器用于接收所述第一调制信号和所述共模电压，根据所述第一调制信号对所述共模电压进行滤波处理，向所述PWM调制器输出滤波后的共模电压。
可选地，音频信号处理设备还包括播放组件，所述播放组件连接所述驱动器的输出端。
本申请提供的占空比信号处理电路、方法、和音频信号处理设备中，幅度检测器可以向运算单元发送音频信号幅度对应的第二幅度，使运算单元对第二幅度和电源电压进行运算处理，得到第二幅度和电源电压中至少一个参数匹配的占空比控制信号，以在后续D类功放等功放单元依据该占空比控制信号进行驱动作业，其中占空比控制信号匹配第二幅度和电源电压中至少一个参数，这样功放单元可以根据音频信号的幅度和电源电压中的至少一个参数自适应调节功放单元中的共模占空比，当信号幅度较低或空闲状态时，共模占空比会对应减小，减少对应开关开启时间，降低导通电阻的静态功耗损失、以及其中LC充放电的功耗损失，可以提升功放单元的转换效率，降低驱动功耗，从而降低整个音频信号处理设备的功耗，且不会导致音频信号失真。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是发明人研究方案涉及的波形图；
图2是本申请一实施例的占空比信号处理电路结构示意图；
图3a和图3b是本申请一实施例的运算单元结构示意图；
图4是本申请另一实施例的占空比信号处理电路结构示意图；
图5a和图5b是本申请一实施例的共模电压控制单元结构示意图；
图6是本申请另一实施例的占空比信号处理电路结构示意图；
图7是本申请一实施例的占空比信号处理方法流程示意图；
图8是本申请一实施例的音频信号处理设备结构示意图；
图9是本申请另一实施例的音频信号处理设备结构示意图；
图10a、图10b和图10c是本申请一实施例中波形分析示意图。
具体实施方式
发明人对采样D类功放这类功放单元的音频处理设备进行研究，发现有的方案采用BD调制模式，利用脉冲宽度调制(如PWM)与三角波(或锯齿)波形发生器或振荡器来对音频输入信号进行编码。其中BD调制对输出信号之差的占空比进行调制，以使得其平均内容对应于输入模拟信号。BD调制在一定程度上提供优越的音频性能(例如，减少的爆音与嘀哒声)。然而，当使用低通LC滤波器时，无(或具有低电平的)音频信号的 BD调制比其他常见调制技术(如AD调制)的功耗要高得多。BD调制在其输出中具有显著的共模内容。因此，共模占空比、电感器电流纹波和功耗彼此之间存在相关性。当共模占空比为或接近百分之五十(50％)时功耗最高，因为纹波电流在这些占空比下最大。该方案是当模拟输入信号的电平低于阈值电平时，共模占空比为50％；当模拟输入信号的电平低于阈值电平时，该调制器使该第一量化信号和该第二量化信号中的每一个的共模占空比发生移位，以使得该共模占空比为大于或小于百分之五十(50％)中的一者。采用这种方式，负载(如扬声器)所消耗的功率相应减少，从而在一定程度上提高了功率放大器的效率，然而提升效果有限。
发明人还发现有的方案中，PWM(脉冲宽度调制)输出的共模占空比固定设置为一个较小的值(比如15％)，可以减少开关开启时间和LC充放电时间，降低功耗损失，提高效率。但是当音频信号幅度较大时，15％的共模占空比无法满足信号调制的幅度要求，它需要通过比较积分器的输出信号与直流参考电平，来调节积分器的共模参考电压，增大信号调制的占空比，但这种方式会使得D类放大器进入单边调制模式，如图1所示波形，PWM_P和PWM_N只有一边会翻转，这种情况下音频信号的THD(总谐波失真)性能较差。因而该方案提升D类功放的转换效率，但进入单边脉宽调制模式会引入比较严重的信号失真，导致大信号音频信号THD+N性能差，例如在信号幅度较大的情况下，功放进入单边调制模式，会导致音频信号失真等等。
针对上述问题，本申请通过占空比信号处理电路产生匹配信号幅度和供电电压中至少一个参数的共模电压，使功放单元能够根据音频信号幅度和电源电压自适应调节PWM共模占空比，当信号幅度较低或空闲状态时，共模占空比会对应减小，减少开关开启时间，降低导通电阻的静态功耗损失、以及LC充放电的功耗损失，提升转换效率，降低驱动功耗，从而降低整个音频信号处理设备的功耗，且不会导致音频信号失真。
下面结合附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而非全部实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。在不冲突的情况下，下述各个实施例及其技术特征可以相互组合。
本申请第一方面提供一种占空比信号处理电路，参考图2所示，上述占空比信号处理电路包括幅度检测器110和运算单元200；幅度检测器110的输入端接入音频信号，输出端连接运算单元200的第一输入端，运算单元200的第二输入端接入电源电压，输出端输出占空比控制信号。
具体地，所述幅度检测器110用于检测音频信号的第一幅度，生成第二幅度，向所述运算单元200发送所述第二幅度；所述运算单元200用于获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号，以在后续D类功放等功放单元依据该占空比控制信号进行驱动作业，使占空比控制信号匹配第二幅度和电源电压中至少一个参数，这样可以根据音频信号的幅度和电源电压中的至少一个参数自适应调节功放单元中的共模占空比，当信号 幅度较低或空闲状态时，共模占空比会对应减小，减少对应开关开启时间，降低导通电阻的静态功耗损失、以及其中LC充放电的功耗损失，可以提升功放单元的转换效率。
在一个示例中，幅度检测器110可以从在检测音频信号的第一幅度之后，可以对所得幅度进行增益处理，以确定第二幅度。可选地，幅度检测器110对幅度进行的增益处理可以包括：
Vamp_out＝Vamp_in*Gain，其中Vamp_out表示第二幅度，Vamp_in表示第一幅度，第一幅度包括输入的音频信号的幅度，Gain表示增益参数，符号*表示相乘。可选地，音频信号包括数字音频信号，幅度检测器110可以检测数字音频信号的电平幅度，以得到音频信号的幅度。
在一个示例中，运算单元200可以包括比较器和/或转码器等能够对第二幅度和电源电压进行运算处理，获得所需占空比控制信号的器件。可选地，本示例可以设定预期的占空比档位，例如预期的占空比档位包括50％、40％、30％、20％和10％等占空比档位，这样运算单元200可以对第二幅度、电源电压和这些预期占空比档位对应的占空比进行运算处理，获得对应占空比，能够简化对应运算过程，提高运算过程的稳定性。
在一个实施例中，所述运算单元还用于依据预设条件获取理论占空比，根据所述理论占空比和预期的占空比档位确定所述占空比控制信号，以使采用预设条件得到的理论占空比匹配第二幅度和电源电压中至少一个参数。可选地，本实施例可以对理论占空比进行向上取整，得到对应的占空比信号，也可以在预期的占空比档位中，选择大于或等于，且最接近理论占空比的一档占空比作为占空比控制信号。
可选地，所述预设条件包括的运算公式为：DPWM*VSUP＝Vamp_out+VHR，其中，DPWM表示理论占空比，VSUP表示电源电压，Vamp_out表示第二幅度，VHR表示幅度余量，幅度余量VHR表征共模占空比设定的理论中可允许最大信号幅度相对于实际不失真的最大信号幅度的余量，可以通过配置等方式设定，例如可以设定为1V(伏特)等值。上述占空比控制信号的运算公式可供运算单元200获取更为准确的占空比控制信号。
在一个实施例中，参考图3a和图3b所示，所述运算单元200包括比较子单元210和转码器220；所述比较子单元210用于将所述第二幅度分别与多个比较阈值进行比较，向所述转码器220输出对应的比较结果；所述转码器220用于对所述比较结果进行转码，以得到所述比较结果对应的占空比控制信号。其中各个比较阈值分别依据所述电源电压VSUP、所述幅度余量VHR和预期的占空比档位确定，以使所述比较结果对应的占空比控制信号匹配所述第二幅度和所述电源电压中至少一个参数。可选地，如图3a所示，比较阈值可以包括VT1至VTn等n个阈值，比较阈值的个数可以根据所需设计的占空比挡位个数确定；例如需要设定N个占空比挡位可调，则可以设定N-1个比较阈值，及N-1个对应的比较器等等。
在一个示例中，参考图3b所示，所述比较子单元210包括第一比较器CMP1、第二比较器CMP2、第三比较器CMP3和第四比较器CMP4，所述比较阈值包括第一阈值VT1、第二阈值VT2、第三阈值VT3和第四阈值VT4；所述第一比较器CMP1的第一输入端接入 所述第二幅度Vamp_out，第二输入端接入所述第一阈值VT1，输出端连接所述转码器220的第一输入端；所述第二比较器CMP2的第一输入端接入所述第二幅度Vamp_out，第二输入端接入所述第二阈值VT2，输出端连接所述转码器220的第二输入端；所述第三比较器CMP3的第一输入端接入所述第二幅度Vamp_out，第二输入端接入所述第三阈值VT3，输出端连接所述转码器220的第三输入端；所述第四比较器CMP4的第一输入端接入所述第二幅度Vamp_out，第二输入端接入所述第四阈值VT4，输出端连接所述转码器220的第四输入端。
具体地，预期的占空比包括第一占空比A1、第二占空比A2、第三占空比A3和第四占空比A4这四档占空比；相应地，第一阈值包括：VT1＝A1×VSUP-VHR；第二阈值包括：VT2＝A2×VSUP-VHR；第三阈值包括：VT3＝A3×VSUP-VHR；第四阈值包括：VT4＝A4×VSUP-VHR；其中，VT1表示第一阈值，A1表示第一占空比，VT2表示第二阈值，A2表示第二占空比，VT3表示第三阈值，A3表示第三占空比，VT4表示第四阈值，A4表示第四占空比。
可选地，预期的占空比还可以包括第五占空比A5这一档占空比。第一占空比A1、第二占空比A2、第三占空比A3、第四占空比A4和第五占空比A5的大小可以依据对应D类功放等功放单元的调制需求设定，例如可以将第一占空比A1设为10％，第二占空比A2设为20％，第三占空比A3设为30％，第四占空比A4设为40％，第五占空比A5设为50％。此时，第四阈值VT4表示为50％档位对应的判断阈值，当Vamp_out>VT4时，选择50％档位，转码器220输出50％对应的占空比控制信号(如占空比为50％的指示信号等等)。第三阈值VT3表示为40％档位对应的判断阈值，当VT4≥Vamp_out>VT3时，选择40％档位，转码器220输出40％对应的占空比控制信号。第二阈值VT2表示为30％档位对应的判断阈值，当VT3≥Vamp_out>VT2时，选择30％档位，转码器220输出30％对应的占空比控制信号。第一阈值VT1表示为20％档位对应的判断阈值，当VT2≥Vamp_out>VT1时，选择20％档位，转码器220输出20％对应的占空比控制信号，Vamp_out≤VT1时，选择10％档位，转码器220输出10％对应的占空比控制信号。相应地，如图3b所示，转码器220输出的占空比控制信号可以记为VCM_SEL<4:0>，VCM_SEL<4:0>包括VCM_SEL4、VCM_SEL3、VCM_SEL2、VCM_SEL1和VCM_SEL0共五档占空比控制信号。
在一个实施例中，参考图4所示，上述占空比信号处理电路还包括共模电压控制单元120；所述共模电压控制单元120的输入端连接所述运算单元200的输出端，用于根据所述占空比控制信号进行运算处理，得到所述占空比控制信号对应的共模电压，以将该共模电压提供至D类功放等功放单元，调节D类功放单元的共模占空比，从而达到提升转换效率的目的。
可选地，共模电压控制单元120可以包括分压子单元等用于得到多档电压的单元，以依据预期的占空比档位等因素进行分压处理，得到占空比控制信号对应的共模电压。
在一个示例中，参考图5a和图5b所示，所述共模电压控制单元120包括分压子单元121和多路选通器122；所述分压子单元121用于对接入的参考电压VDD进行多次分 压处理，得到各次分压处理后的分压信号，如图5b所示VCM_D10至VCM_D50；所述多路选通器22的控制端接入所述占空比控制信号，根据所述占空比控制信号选通对应的电压输出通道，以输出对应的共模电压，这里共模电压包括对应电压输出通道输出的分压信号。
具体地，参考图5b所示，所述分压子单元121包括第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5和第六电阻R6，所述分压信号包括第一信号VCM_D10、第二信号VCM_D20、第三信号VCM_D30、第四信号VCM_D40和第五信号VCM_D50；所述第一电阻R1的第一端接入所述参考电压VDD，第二端分别连接所述第二电阻R2的第一端和所述多路选通器122的第一输入端；所述第二电阻R2的第二端分别连接所述第三电阻R3的第一端和所述多路选通器122的第二输入端；所述第三电阻R3的第二端分别连接所述第四电阻R4的第一端和所述多路选通器122的第三输入端；所述第四电阻R4的第二端分别连接所述第五电阻R5的第一端和所述多路选通器122的第四输入端；所述第五电阻R5的第二端分别连接所述第六电阻R6的第一端和所述多路选通器122的第五输入端；所述第六电阻R6的第二端接地。其中，多路选通器122可以包括五路电压输出通道，接入占空比控制信号VCM_SEL<4:0>，根据上述占空比控制信号选通对应的电压输出通道；例如多路选通器122可以在接收VCM_SEL4时，选通第一通道，以输出第一信号VCM_D10作为共模电压；在接收VCM_SEL3时，选通第二通道，以输出第二信号VCM_D20作为共模电压；在接收VCM_SEL2时，选通第三通道，以输出第三信号VCM_D30作为共模电压；在接收VCM_SEL1时，选通第四通道，以输出第四信号VCM_D40作为共模电压；在接收VCM_SEL0时，选通第五通道，以输出第五信号VCM_D50作为共模电压。
在一个实施例中，参考图6所示，上述占空比信号处理电路还包括模数转换器130；所述模数转换器130用于获取所述电源电压，将所述电源电压转换为数字信号后，将转换后的所述电源电压输出至所述运算单元200，以使运算单元200依据数字形式的电源电压进行运算处理，提高处理过程的稳定性。
以上音频信号处理设备中，幅度检测器110可以向运算单元200发送音频信号幅度对应的第二幅度，使运算单元200对第二幅度和电源电压进行运算处理，得到第二幅度和电源电压中至少一个参数匹配的占空比控制信号，以在后续D类功放等功放单元依据该占空比控制信号进行驱动作业，其中占空比控制信号匹配第二幅度和电源电压中至少一个参数，这样可以根据音频信号的幅度和电源电压中的至少一个参数自适应调节功放单元中的共模占空比，当信号幅度较低或空闲状态时，共模占空比会对应减小，减少对应开关开启时间，降低导通电阻的静态功耗损失、以及其中LC充放电的功耗损失，可以提升功放单元的转换效率。
本申请在第二方面提供一种占空比信号处理方法，应用于上述任一实施例所述的占空比信号处理电路，参考图7所示，所述占空比控制信号处理方法包括S310和S320。
S310，检测音频信号的第一幅度，生成第二幅度；
S320，获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第 二幅度和所述电源电压中至少一个参数匹配的占空比控制信号。
在一个实施例中，所述对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号的方法进一步包括：依据预设条件获取理论占空比，根据所述理论占空比和预期的占空比档位确定所述占空比控制信号。
可选地，所述预设条件包括运算公式：
DPWM*VSUP＝Vamp_out+VHR，
其中，DPWM表示理论占空比，VSUP表示电源电压，Vamp_out表示第二幅度，VHR表示幅度余量。
在一个实施例中，图7所示步骤S320中，所述对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号的方法进一步包括：
将所述第二幅度分别与多个比较阈值进行比较，向所述转码器输出比较结果，各个所述比较阈值分别依据所述电源电压、所述幅度余量和所述占空比档位确定，以使所述比较阈值对应的占空比控制信号匹配所述第二幅度和所述电源电压中至少一个参数；
对所述比较结果进行转码，以得到所述比较结果对应的占空比控制信号。
在一个实施例中，上述占空比信号处理方法，还包括：根据所述占空比控制信号进行运算处理，得到所述占空比控制信号对应的共模电压。
上述占空比信号处理方法应用于上述任一实施例所述的占空比信号处理电路，具有上述任一实施例所述的占空比信号处理电路的所有有益效果，在此不再赘述。
本申请在第三方面提供一种音频信号处理设备，参考图8所示，上述音频信号处理设备包括音频处理单元410、功放单元420、驱动器430和上述任一实施例所述的占空比信号处理电路500；
所述音频处理单元410用于对接入的音频信号进行第一调制处理，得到第一调制信号，向所述功放单元420发送所述第一调制信号；
所述功放单元420用于接收所述第一调制信号和占空比信号处理电路500输出的共模电压，根据所述第一调制信号对所述共模电压进行第二调制处理，得到第二调制信号，向所述驱动器430发送所述第二调制信号；
所述驱动器430用于根据所述第二调制信号驱动对应的播放组件440，以播放所述音频信号。
可选地，音频处理单元410可以包括DSM调制器等用于传输和调制音频信号的组件。功放单元420可以包括D类功率放大器。可选地，驱动器430和占空比信号处理电路500中的模数转换器130还连接外供电源，外供电源的电压为电源电压VSUP。
上述音频信号处理设备采用上述任一实施例所述的占空比信号处理电路500产生共模电压功放单元420进行第二调制处理，使功放单元420能够根据音频信号幅度和电源电压自适应调节PWM共模占空比，当信号幅度较低或空闲状态时，共模占空比会对应减 小，减少开关开启时间，降低导通电阻的静态功耗损失、以及LC充放电的功耗损失，提升转换效率。
在一个实施例中，参考图9所示，所述音频处理单元410包括延迟器411、DSM调制器(三角积分调制器)412和数模转换器413；延迟器411的输入端接入音频信号，该音频信号可以包括数字音频信号，输出端通过DSM调制器412连接模数转换器413。
所述延迟器411用于对所述音频信号进行延迟处理，向所述DSM调制器412输出延迟后的音频信号；所述DSM调制器412用于对所述延迟后的音频信号进行DSM调制，输出初始调制信号；所述模数转换器413用于对所述初始调制信号进行数模转换，输出所述第一调制信号。可选地，延迟器411的延迟时间可以根据音频信号的响应特征等因素设定，比如可以设置为1ms(毫秒)等延迟时间。延迟器411对音频信号进行延迟处理，可以使占空比信号处理电路500中的占空比控制信号提前应对音频信号和/或电源电压的准确性，提高相应调制效果。
在一个实施例中，参考图9所示，所述功放单元包括PWM调制器422；所述PWM调制器422用于对所述共模电压进行第二调制处理，得到第二调制信号，向所述驱动器430输出所述第二调制信号。可选地，如图9所示，若功放单元包括积分器421，PWM调制器422可以连接在积分器421和驱动器430之间。若功放单元不包括积分器411，PWM调制器422可以连接在音频处理单元410(如模数转换器413)和驱动器430之间，此时PWM调制器422的一个输入端还可以连接占空比信号处理电路500(如共模电压控制单元120)的输出端。
可选地，如图9所示，所述功放单元420还包括积分器421；所述积分器421用于接收所述第一调制信号和所述共模电压，根据所述第一调制信号对所述共模电压进行滤波处理，向所述PWM调制器422输出滤波后的共模电压，以使PWM调制器422根据共模电压产生对应的控制波形，使驱动器430根据控制波形进行驱动作业。
在一个示例中，上述音频信号处理设备还包括播放组件440，所述播放组件440连接所述驱动器430的输出端，以在驱动器430的驱动下播放对应音频信号。可选地播放组件440可以包括扬声器等用于播放音频信号的组件。
在一个示例中，发明人对功放单元420中PWM调制器422的工作过程进行分析，发现PWM调制器422进行第二调制处理生成控制波形，控制波形包括PWM共模占空比。若供电电压不变，PWM共模占空比随音频信号幅度的变化特征可以参考图10a所示，从图10a可以看出，供电电压保持不变，当输入的音频信号的电平(幅度)较高时，PWM共模占空比保持在50％；当音频信号的电平变低时，共模占空比逐渐降低(例如依次变为40％、30％、20％、10％)；当输入空闲时，输出占空比保持为10％。若音频信号幅度不变，PWM共模占空比随供电电压的变化特征可以参考图10b所示，从图10b可以看出，当音频信号幅度不变的情况下，电源电压变高，PWM共模占空比对应变小；电源电压变低，PWM共模占空比对应变大。特别地，如图10b所示，当检测到电源电压变高时，需要经过一定延迟后，共模占空比才会变低，体现上述占空比信号处理电路500产生的占空比控制信 号能够提供慢退出的功能；当检测到电源电压变低时，PWM共模占空比快速变高，上述占空比信号处理电路500产生的占空比控制信号能够提供快速进入的功能。如图10a所示，当检测到音频信号的电平变低时，需要经过一定延迟后，共模占空比才会变低，体现上述占空比信号处理电路500产生的占空比控制信号能够提供慢退出的功能；当检测到音频信号的电平变高时，PWM共模占空比快速变高，上述占空比信号处理电路500产生的占空比控制信号能够提供快速进入的功能。发明人还对传统PWM调制过程进行研究，发现传统PWM调制的三角波的共模与输入的音频信号共模相同，例如为0.5AVDD，因此输出信号的共模占空比通常为50％，为了改变输出共模信号占空比，就必须改变信号的直流参考电平，如图10c所示，当对应共模电压VC升高时，静态输出信号占空比显著降低，其中三角波幅度VOSC＝0.5*AVDD±0.058*AVCC，共模输出信号占空比D为：
其中，表示三角波幅度VOSC的最高值，表示三角波幅度VOSC的最低值。上式给出了静态输出信号占空比与直流参考电平的关系，该直流参考电平的产生电路如下。图中VH和VL即为三角波的峰值，运放钳制1/2*AVDD作为VH和VL的中间值，通过电阻分压，得到10％、20％、30％、40％、50％所对应的积分器共模电平。而本申请提供的音频处理设备能够采用自适应占空比调制技术通过对音频信号幅值及供电电源电压值进行监测，经过相关运算判断该信号下与电源电压的比例关系，从而推断使信号电压不会超过电源电平的最大直流参考电压。经过对比分析，发明人发现采用上述任一实施例所述的占空比信号处理电路500的音频处理设备具有如下优势：1、根据音频信号幅度和电源电压，自适应调节功放输出的共模占空比，降低开关电阻及LC充放电的功耗损失，提高功放效率，且不会导致音频信号失真。2、提前检测音频信号幅度，可预测输出音频信号，当预测到音频信号幅度变大，可提前调节共模占空比至对应档位。3、检测当前的功放电源电压，并将电源电压作为共模占空比调节的一个参考量，可以适应宽范围的电源电压变化。4、控制共模占空比缓慢调节，防止突然出现较大的共模占空比切换导致的音频信号异常。5、比较阈值可以灵活配置。
上述音频信号处理设备中，占空比信号处理电路500产生匹配信号幅度和供电电压中至少一个参数的共模电压，功放单元420能够根据音频信号幅度和电源电压自适应调节PWM共模占空比，当信号幅度较低或空闲状态时，共模占空比会对应减小，减少开关开启时间，降低导通电阻的静态功耗损失、以及LC充放电的功耗损失，提升转换效率，降低驱动功耗，从而降低整个音频信号处理设备的功耗。
尽管已经相对于一个或多个实现方式示出并描述了本申请，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本申请包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示)，即使在结构上与执行本文所示的本说明书的示范 性实现方式中的功能的公开结构不等同。
即，以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。
另外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了使本领域任何技术人员能够实现和使用本申请，本申请给出了以上描述。在以上描述中，为了解释的目的而列出了各个细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实施例中，不会对公知的过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。

Claims (20)

  1. 一种占空比信号处理电路，包括幅度检测器和运算单元；
    所述幅度检测器用于检测音频信号的第一幅度，生成第二幅度，向所述运算单元发送所述第二幅度；
    所述运算单元用于获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号。
  2. 根据权利要求1所述的占空比信号处理电路，所述运算单元依据预设条件获取理论占空比，根据所述理论占空比和预期的占空比档位确定所述占空比控制信号。
  3. 根据权利要求2所述的占空比信号处理电路，其中，所述预设条件包括运算公式：
    DPWM*VSUP＝Vamp_out+VHR，
    其中，DPWM表示理论占空比，VSUP表示电源电压，Vamp_out表示第二幅度，VHR表示幅度余量。
  4. 根据权利要求2所述的占空比信号处理电路，其中，所述运算单元包括比较子单元和转码器；
    所述比较子单元用于将所述第二幅度分别与多个比较阈值进行比较，向所述转码器输出比较结果，各个所述比较阈值分别依据所述电源电压、所述幅度余量和所述占空比档位确定，以使所述比较阈值对应的占空比控制信号匹配所述第二幅度和所述电源电压中至少一个参数；
    所述转码器用于对所述比较结果进行转码，以得到所述比较结果对应的占空比控制信号。
  5. 根据权利要求4所述的占空比信号处理电路，其中，所述比较子单元包括第一比较器、第二比较器、第三比较器和第四比较器，所述比较阈值包括第一阈值、第二阈值、第三阈值和第四阈值；
    所述第一比较器的第一输入端接入所述第二幅度，第二输入端接入所述第一阈值，输出端连接所述转码器的第一输入端；
    所述第二比较器的第一输入端接入所述第二幅度，第二输入端接入所述第二阈值，输出端连接所述转码器的第二输入端；
    所述第三比较器的第一输入端接入所述第二幅度，第二输入端接入所述第三阈值，输出端连接所述转码器的第三输入端；
    所述第四比较器的第一输入端接入所述第二幅度，第二输入端接入所述第四阈值，输出端连接所述转码器的第四输入端。
  6. 根据权利要求4所述的占空比信号处理电路，其中，预期的占空比档位包括第一占空比、第二占空比、第三占空比和第四占空比；
    所述第一阈值包括：VT1＝A1×VSUP-VHR；
    所述第二阈值包括：VT2＝A2×VSUP-VHR；
    所述第三阈值包括：VT3＝A3×VSUP-VHR；
    所述第四阈值包括：VT4＝A4×VSUP-VHR；
    其中，VT1表示第一阈值，A1表示第一占空比，VT2表示第二阈值，A2表示第二占空比，VT3表示第三阈值，A3表示第三占空比，VT4表示第四阈值，A4表示第四占空比。
  7. 根据权利要求1所述的占空比信号处理电路，其中，还包括共模电压控制单元；所述共模电压控制单元的输入端连接所述运算单元的输出端，用于根据所述占空比控制信号进行运算处理，得到所述占空比控制信号对应的共模电压。
  8. 根据权利要求7所述的占空比信号处理电路，其中，所述共模电压控制单元包括分压子单元和多路选通器；
    所述分压子单元用于对接入的参考电压进行多次分压处理，得到各次分压处理后的分压信号；
    所述多路选通器的控制端接入所述占空比控制信号，根据所述占空比控制信号选通对应的电压输出通道，以输出对应的共模电压。
  9. 根据权利要求8所述的占空比信号处理电路，其中，所述分压子单元包括第一电阻、第二电阻、第三电阻、第四电阻、第五电阻和第六电阻；
    所述第一电阻的第一端接入所述参考电压，第二端分别连接所述第二电阻的第一端和所述多路选通器的第一输入端；所述第二电阻的第二端分别连接所述第三电阻的第一端和所述多路选通器的第二输入端；所述第三电阻的第二端分别连接所述第四电阻的第一端和所述多路选通器的第三输入端；所述第四电阻的第二端分别连接所述第五电阻的第一端和所述多路选通器的第四输入端；所述第五电阻的第二端分别连接所述第六电阻的第一端和所述多路选通器的第五输入端；所述第六电阻的第二端接地。
  10. 根据权利要求1所述的占空比信号处理电路，其中，还包括模数转换器；所述模数转换器用于获取所述电源电压，将所述电源电压转换为数字信号后，将转换后的所述电源电压输出至所述运算单元。
  11. 一种占空比信号处理方法，其中，应用于权利要求1至8任一项所述的占空比信号处理电路，包括：
    检测音频信号的第一幅度，生成第二幅度；
    获取电源电压，对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号。
  12. 根据权利要求11所述的占空比信号处理方法，其中，所述对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号的方法进一步包括：
    依据预设条件获取理论占空比，根据所述理论占空比和预期的占空比档位确定所述占空比控制信号，所述运算公式用于表征所述理论占空比、所述电源电压和所述第二幅度之间的关系。
  13. 根据权利要求12所述的占空比信号处理方法，其中，所述预设条件包括运算公式：
    DPWM*VSUP＝Vamp_out+VHR，
    其中，DPWM表示理论占空比，VSUP表示电源电压，Vamp_out表示第二幅度，VHR表示幅度余量。
  14. 根据权利要求11所述的占空比信号处理方法，其中，所述对所述第二幅度和所述电源电压进行运算处理，得到所述第二幅度和所述电源电压中至少一个参数匹配的占空比控制信号的方法进一步包括：
    将所述第二幅度分别与多个比较阈值进行比较，向所述转码器输出比较结果，各个所述比较阈值分别依据所述电源电压、所述幅度余量和所述占空比档位确定，以使所述比较阈值对应的占空比控制信号匹配所述第二幅度和所述电源电压中至少一个参数；
    对所述比较结果进行转码，以得到所述比较结果对应的占空比控制信号。
  15. 根据权利要求11所述的占空比信号处理方法，其中，还包括：
    根据所述占空比控制信号进行运算处理，得到所述占空比控制信号对应的共模电压。
  16. 一种音频信号处理设备，其中，包括音频处理单元、功放单元、驱动器和权利要求1至10任一项所述的占空比信号处理电路；
    所述音频处理单元用于对接入的音频信号进行第一调制处理，得到第一调制信号，向所述功放单元发送所述第一调制信号；
    所述功放单元用于接收所述第一调制信号和占空比信号处理电路输出的共模电压，根据所述第一调制信号对所述共模电压进行第二调制处理，得到第二调制信号，向所述驱动器发送所述第二调制信号；
    所述驱动器用于根据所述第二调制信号驱动对应的播放组件，以播放所述音频信号。
  17. 根据权利要求16所述的音频信号处理设备，其中，所述音频处理单元包括延迟器、DSM调制器和数模转换器；
    所述延迟器用于对所述音频信号进行延迟处理，向所述DSM调制器输出延迟后的音频信号；
    所述DSM调制器用于对所述延迟后的音频信号进行DSM调制，输出初始调制信号；
    所述模数转换器用于对所述初始调制信号进行数模转换，输出所述第一调制信号。
  18. 根据权利要求16所述的音频信号处理设备，其中，所述功放单元包括PWM调制器；所述PWM调制器用于对所述共模电压进行第二调制处理，得到第二调制信号。
  19. 根据权利要求18所述的音频信号处理设备，其中，所述功放单元还包括积分器；所述积分器用于接收所述第一调制信号和所述共模电压，根据所述第一调制信号对所述共模电压进行滤波处理，向所述PWM调制器输出滤波后的共模电压。
  20. 根据权利要求16所述的音频信号处理设备，其中，还包括播放组件，所述播放组件连接所述驱动器的输出端。
PCT/CN2023/085444 2022-10-20 2023-03-31 占空比信号处理电路、方法、和音频信号处理设备 WO2024082559A1 (zh)

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