WO2024082527A1 - 一种延迟锁相环和存储器 - Google Patents

一种延迟锁相环和存储器 Download PDF

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Publication number
WO2024082527A1
WO2024082527A1 PCT/CN2023/081158 CN2023081158W WO2024082527A1 WO 2024082527 A1 WO2024082527 A1 WO 2024082527A1 CN 2023081158 W CN2023081158 W CN 2023081158W WO 2024082527 A1 WO2024082527 A1 WO 2024082527A1
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Prior art keywords
signal
delay
switch tube
clock signal
output
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PCT/CN2023/081158
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English (en)
French (fr)
Inventor
张雪艳
郑载勲
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长鑫存储技术有限公司
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Publication of WO2024082527A1 publication Critical patent/WO2024082527A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present disclosure relates to, but is not limited to, a delay locked loop and a memory.
  • the delay locked loop needs to use a delay line to transmit a four-phase clock signal (i.e., a clock signal with four phases that are 90 degrees apart in sequence) in order to complete the subsequent data sampling process.
  • a four-phase clock signal i.e., a clock signal with four phases that are 90 degrees apart in sequence
  • the operating parameters of the delay line need to be adjusted and locked.
  • the use of a time-to-digital converter can speed up the adjustment of the delay line.
  • the time-to-digital converter may have bit errors, which in turn has an adverse effect on the delay line adjustment and increases the locking time of the delay locked loop.
  • an embodiment of the present disclosure provides a delay locked loop, the delay locked loop comprising a first signal path and a time digital converter, the time digital converter comprising a detection module and a conversion module; wherein,
  • the first signal path includes a first delay line configured to receive a reference clock signal and output a feedback clock signal; wherein a delay parameter of the first delay line is controlled by a coarse adjustment control code;
  • the detection module is configured to receive the reference clock signal and the feedback clock signal; output a work indication signal based on a phase difference between the reference clock signal and the feedback clock signal; wherein, when the phase difference is greater than or equal to a first threshold, the work indication signal generates a pulse, and the pulse width indicates the magnitude of the phase difference; when the phase difference is less than the first threshold, the level state of the work indication signal remains unchanged;
  • the conversion module is configured to receive the work instruction signal, convert the pulse width of the work instruction signal, and output the initial value of the coarse adjustment control code.
  • the detection module includes: a pulse generation module, configured to receive the reference clock signal and the feedback clock signal, and output a phase pulse signal; wherein the phase pulse signal has one pulse, and the pulse width indicates the phase difference between the reference clock signal and the feedback clock signal; a control module, configured to receive the phase pulse signal, the reference clock signal and the feedback clock signal; when the phase difference between the reference clock signal and the feedback clock signal is greater than or equal to the first threshold, the phase pulse signal is transmitted and processed, and the work indication signal is output; when the phase difference is less than the first threshold, the phase pulse signal is shielded so that the level state of the work indication signal remains unchanged.
  • control module includes: a comparison module, configured to receive the reference clock signal and the feedback clock signal, and output a comparison signal based on the phase difference between the reference clock signal and the feedback clock signal; wherein, if the phase difference is greater than or equal to the first threshold, the comparison signal is in a first state; if the phase difference is less than the first threshold, the comparison signal is in a second state; a logic module, configured to receive the comparison signal and the phase pulse signal, perform logical operations on the comparison signal and the phase pulse signal, and output the work indication signal.
  • the first state is a high level state
  • the second state is a low level state
  • the logic module includes a first AND gate, a first input end of the first AND gate receives the comparison signal, a second input end of the first AND gate receives the phase pulse signal, and an output end of the first AND gate outputs the work indication signal.
  • the comparison module includes two delay modules, two level comparators and an operator; wherein the first delay module is configured to receive the reference clock signal, delay the reference clock signal, and output a reference delay signal, and the delay between the reference clock signal and the reference delay signal is the first threshold; the second delay module is configured to receive the feedback clock signal, delay the feedback clock signal, and output a feedback delay signal, and the delay between the feedback clock signal and the feedback delay signal is the first threshold; the first level comparator is configured to receive the reference clock signal and the feedback delay signal, compare the rising edge of the reference clock signal with the rising edge of the feedback delay signal, and output a first result signal; wherein, if the If the reference clock signal is ahead of the feedback delay signal, the first result signal is in the third state; if the reference clock signal lags behind the feedback delay signal, the first result signal is in the fourth state; the second level comparator is configured to receive the feedback clock signal and the reference delay signal, compare the rising edge of the reference delay signal with the rising edge of the feedback clock signal, and output a
  • the delay module includes a first NAND gate and a second NAND gate; wherein, the first input end of the first NAND gate forms the input end of the delay module, the first input end of the second NAND gate is connected to the output end of the first NAND gate, the second input end of the first NAND gate and the second input end of the second NAND gate both receive a first power supply signal, and the output end of the second NAND gate forms the output end of the delay module.
  • the level comparator includes a comparison unit, a latch unit and a first NOT gate; wherein the comparison unit includes a first output terminal and a second output terminal, and is configured to receive a first input signal and a second input signal; when the first input signal is in a high level state, the first input signal and the second input signal are compared in level, and the first output terminal and the second output terminal are charged and discharged according to the comparison result to compare the rising edge of the first input signal and the rising edge of the second input signal; the latch unit includes a first input terminal, a second input terminal and an output terminal, the first input terminal of the latch unit is connected to the first output terminal of the comparison unit, the second input terminal of the latch unit is connected to the second output terminal of the comparison unit, and the output terminal of the comparison unit is connected to the input terminal of the first NOT gate; wherein, for the first level comparator, the first input signal refers to the reference clock signal, the second input signal refers to the feedback delay signal, and the output terminal of the first NOT gate is used to
  • the comparison unit includes a cross-coupling component, a pre-charging component, an input component, a control component and an equalizing component; wherein the cross-coupling component includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; the control end of the first switch tube, the control end of the second switch tube, the second end of the third switch tube and the first end of the fourth switch tube are connected to the first output end, the control end of the third switch tube, the control end of the fourth switch tube, the second end of the first switch tube and the first end of the second switch tube are connected to the second output end, the first end of the first switch tube receives a second power supply signal, and the first end of the third switch tube receives a third power supply signal; the pre-charging component includes a fifth switch tube, a sixth switch tube and a seventh switch tube; the control end of the fifth switch tube, the control end of the sixth switch tube and the control end of the seventh switch tube all receive the first input signal, the first end of
  • the first switch tube, the third switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eleventh switch tube are all P-type field effect tubes
  • the second switch tube, the fourth switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all N-type field effect tubes.
  • the latch unit includes a third NAND gate and a fourth NAND gate; wherein, the first input end of the third NAND gate constitutes the first input end of the latch unit, the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, and the third input end of the third NAND gate receives a reset signal; the first input end of the fourth NAND gate constitutes the second input end of the latch unit, and the second input end of the fourth NAND gate is connected to the output end of the third NAND gate.
  • the third state is a high level state
  • the fourth state is a low level state
  • the operator includes a second AND gate and a second NOT gate, the first input end of the second AND gate receives the first result signal, the second input end of the second AND gate receives the second result signal, the output end of the second AND gate is connected to the input end of the second NOT gate, and the second NOT gate is used to output the comparison signal.
  • the pulse generation module includes a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, and a third AND gate; wherein the clock end of the first trigger, the clock end of the second trigger, and the clock end of the third trigger all receive the feedback clock signal; the input end of the first trigger receives a phase-locked start signal, the positive phase output end of the first trigger is connected to the input end of the second trigger, the positive phase output end of the second trigger is connected to the input end of the third trigger, and the positive phase output end of the third trigger is connected to the first input end of the third AND gate; the clock end of the fourth trigger, the clock end of the fifth trigger, and the clock end of the sixth trigger all receive the reference clock signal; the input end of the fourth trigger is connected to the inverting output end of the first trigger, the positive phase output end of the fourth trigger is connected to the input end of the fifth trigger, and the positive phase output end of the fifth trigger is connected to the input end of the sixth trigger; the positive
  • the first delay line includes a coarse adjustment delay line; wherein, the first delay line is further configured to adjust the working state of the coarse adjustment delay line through the coarse adjustment control code to achieve adjustment of the delay parameters; wherein, the coarse adjustment delay line includes n+1 first delay units connected in series, and the delay of the first delay unit is the first threshold; the coarse adjustment control code includes n+1-bit sub-signals, and the i-th first delay unit receives the i-th sub-signal of the coarse adjustment control code, and n is a natural number.
  • the conversion module includes n+1 second delay units connected in series and n+1 seventh triggers; wherein, the input end of the first second delay unit receives the work indication signal, and the output end of the i-th second delay unit is connected to the input end of the i+1-th second delay unit; the input end of the i-th seventh trigger is connected to the output end of the i-th second delay unit, the clock end of the i-th seventh trigger receives the inverted signal of the work indication signal, and the positive output end of the i-th seventh trigger outputs the i-th bit sub-signal of the coarse adjustment control code; the delay of the second delay unit is the first threshold.
  • the delay locked loop also includes a clock processing module and multiple second delay lines, the clock processing module is connected to the first delay line and multiple second delay lines, the first delay line and the second delay line have the same structure, and the delay parameter of the second delay line is controlled by the coarse adjustment control code; wherein, the clock processing module is configured to receive an initial clock signal, and output multiple phase-splitting clock signals based on the initial clock signal; wherein, the reference clock signal is one of the phase-splitting clock signals; the second delay line is configured to receive one of the phase-splitting clock signals, delay transmission and adjust the received phase-splitting clock signal, and output a target clock signal; wherein, the target clock signal is used for data sampling processing after transmission.
  • an embodiment of the present disclosure provides a memory, wherein the memory includes a delay locked loop as described in the first aspect.
  • FIG1 is a schematic diagram of the structure of a delay phase-locked loop provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of an application scenario of a delay phase-locked loop provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of the structure of another delay-locked loop provided by an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a partial structure of a delay-locked loop provided by an embodiment of the present disclosure.
  • FIG5 is a first schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure.
  • FIG6 is a second schematic diagram of a partial structure of a delay-locked loop provided in an embodiment of the present disclosure.
  • FIG7 is a second signal timing diagram provided by an embodiment of the present disclosure.
  • FIG8 is a third schematic diagram of a partial structure of a delay-locked loop provided by an embodiment of the present disclosure.
  • FIG9 is a fourth schematic diagram of a partial structure of a delay-locked loop provided in an embodiment of the present disclosure.
  • FIG10 is a third signal timing diagram provided by an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of the structure of another delay-locked loop provided in an embodiment of the present disclosure.
  • FIG12 is a fourth signal timing diagram provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Double Data Rate SDRAM (DDR)
  • LPDDR Low Power DDR
  • the initial clock signal from the outside will be divided internally and divided into four-phase clock signals.
  • the four-phase clock signals are respectively sent to the delay locked loop for phase synchronization and locking.
  • the adjusted four-phase clock signal is used to sample and select the output of the data signal DQ after transmission.
  • the delay locked loop includes a first delay line and multiple second delay lines (generally 4).
  • the second delay line is used to adjust and transmit the four-phase clock signal.
  • the first delay line is used to copy the processing process of the second delay line, and the transmission result of the first delay line is used as the basis for adjusting the working parameters of all delay lines.
  • the structures of the first delay line and the second delay line are the same, both including a coarse delay line, a fine delay line, a duty cycle adjustment module and other parts.
  • the delay locked loop is locked after the steps of coarse delay adjustment, fine delay adjustment, and duty cycle adjustment.
  • the disclosed embodiment mainly relates to the process of coarse delay adjustment, specifically, the delay parameter of the coarse adjustment delay line in the first delay line/the second delay line is adjusted by a coarse adjustment control code.
  • the initial value of the coarse adjustment control code can be determined by a time digital converter.
  • the time digital converter receives a reference clock signal and a feedback clock signal, the reference clock signal refers to the input signal of the first delay line, and the feedback clock signal is used to simulate the waveform of the reference clock signal after being transmitted by a delay phase-locked loop; then, the time digital converter converts the phase pulse signal (whose pulse width indicates the phase difference between the reference clock signal and the feedback clock signal) into the initial value of the coarse adjustment control code.
  • the time digital converter generally realizes transcoding through a trigger (DFF), but when the pulse of the phase pulse signal is too narrow, the time digital converter is in a metastable state and an error code problem occurs. At this time, the initial value of the coarse adjustment control code obtained by conversion is wrong, which prolongs the locking time of the delay phase-locked loop.
  • DFF trigger
  • the initial value of the coarse adjustment control code obtained by conversion is wrong, which prolongs the locking time of the delay phase-locked loop.
  • the embodiment of the present disclosure provides a delay phase-locked loop, when the phase difference between the reference clock signal and the feedback clock signal is small,
  • the time digital converter does not need to work, which can improve the bit error problem, speed up the locking speed of the delay phase-locked loop, and improve the performance of the delay phase-locked loop.
  • FIG1 shows a schematic diagram of the structure of a delay locked loop 10 provided by the embodiment of the present disclosure.
  • the delay locked loop 10 includes a first signal path 11 and a time-to-digital converter 12, and the time-to-digital converter 12 includes a detection module 121 and a conversion module 122; wherein,
  • the first signal path 11 includes a first delay line 111 configured to receive a reference clock signal and output a feedback clock signal; wherein a delay parameter of the first delay line 111 is controlled by a coarse adjustment control code;
  • the detection module 121 is configured to receive a reference clock signal and a feedback clock signal; based on the phase difference between the reference clock signal and the feedback clock signal, output a work indication signal; wherein, when the phase difference is greater than or equal to a first threshold, the work indication signal generates a pulse, and the pulse width indicates the magnitude of the phase difference; when the phase difference is less than the first threshold, the level state of the work indication signal remains unchanged;
  • the conversion module 122 is configured to receive the work instruction signal, convert the pulse width of the work instruction signal, and output the initial value of the coarse adjustment control code.
  • the delay locked loop 10 of the embodiment of the present disclosure can be applied to but not limited to memories, such as DRAM, SDRAM, DDR, LPDDR, etc.
  • the phase locking of the clock signal can be achieved by the delay locked loop 10 provided by the embodiment of the present disclosure.
  • the reference clock signal is used for data sampling processing after being adjusted by the delay locked loop 10 and transmitted by the corresponding signal path
  • the feedback clock signal is used to simulate the signal waveform (corresponding to the reference clock signal) for data sampling processing.
  • the feedback clock signal and the reference clock signal need to be aligned within the allowable error range to achieve correct sampling of the data.
  • alignment means: the clock period of the feedback clock signal and the reference clock signal is the same, the rising edge of the feedback clock signal and the reference clock signal are consistent, and the falling edge of the feedback clock signal and the reference clock signal are consistent.
  • the work indication signal when the phase difference between the reference clock signal and the feedback clock signal is greater than or equal to the first threshold, the work indication signal has a pulse, and the conversion module 122 converts the pulse width of the work indication signal into the initial value of the coarse adjustment control code, that is, the coarse adjustment control code is adjusted with the initial value output by the time digital converter 12 as the starting point, thereby accelerating the adjustment process of the coarse adjustment control code.
  • the conversion module 122 will not work, and the coarse adjustment control code will not be assigned an initial value by the time digital converter 12, thereby avoiding the time digital converter 12 from being in a metastable state and outputting an erroneous code value when the phase difference of the input signal is small, avoiding adverse effects on the adjustment process of the coarse adjustment control code, and preventing the additional extension of the lock time of the delay locked loop, thereby improving the working performance of the delay locked loop.
  • the first threshold can be determined according to the actual application scenario.
  • the first threshold is the delay adjustment granularity of the coarse control code.
  • the delay adjustment granularity of the coarse control code refers to: the delay adjustment amount of the first delay line 111 when the coarse control code is adjusted in the smallest unit.
  • FIG. 2 shows a schematic diagram of an application scenario of the delay locked loop 10.
  • the delay locked loop 10 also includes a clock processing module 13 and a plurality of second delay lines (FIG. 2 shows four second delay lines as an example), and the clock processing module 13 is connected to the first delay line 111 and the plurality of second delay lines.
  • the first delay line 111 and all the second delay lines have the same structure, and the delay parameters of the first delay line 111 and all the second delay lines are controlled by the aforementioned coarse adjustment control code.
  • the clock processing module 13 is configured to receive an initial clock signal, and based on the initial clock signal, output a plurality of phase-splitting clock signals (e.g., clk0, clk90, clk180, and clk270 in FIG. 2 ); wherein the reference clock signal is one of the phase-splitting clock signals.
  • the second delay line is configured to receive a phase-splitting clock signal, delay transmission and adjust the received phase-splitting clock signal, and output a target clock signal (i.e., CLK_0, CLK_90, CLK_180, or CLK_270 in FIG. 2 ). wherein the target clock signal is used for data sampling processing after being transmitted through the signal path.
  • the output end of the second delay line is connected to the data selection module through a corresponding signal path, that is, the four target clock signals (i.e., CLK_0, CLK_90, CLK_180, and CLK_270 in FIG. 2 ) are connected to the data selection module through the corresponding signal path.
  • the data selection module After the signal is transmitted through the signal path, it reaches the data selection module, which will also receive the data signal DQ and use the received target clock signal to sample the data signal DQ and select and output it.
  • the waveforms of clk0 and CLK_0 after being transmitted through the signal path are consistent, the waveforms of clk90 and CLK_90 after being transmitted through the signal path are consistent, the waveforms of clk180 and CLK_180 after being transmitted through the signal path are consistent, and the waveforms of clk270 and CLK_270 after being transmitted through the signal path are consistent.
  • the reference clock signal refers to the first phase-split clock signal clk0
  • the feedback clock signal is used to simulate the waveform of CLK_0 when it is transmitted to the data selection module.
  • the delay phase-locked loop 10 needs to simulate the delay of the "second delay line + signal path" through the first signal path 11 to achieve feedback adjustment.
  • the first signal path 11 also includes a delay simulation module 112; wherein the first delay line 111 is configured to receive a reference clock signal, delay transmission and adjust the reference clock signal, and output a first target signal; the delay simulation module 112 is connected to the first delay line 111, and is configured to delay transmission of the first target signal and output a feedback clock signal.
  • the first delay line 111 is used to replicate the delay of the second delay line, and the delay simulation module is used to replicate the delay of the signal path.
  • the phase difference between the feedback clock signal and the reference clock signal can reflect whether the delay parameter of the first delay line 111 is appropriate, and the phase difference is also the basis for adjusting the delay parameter.
  • the signal in the first signal path 11 can be processed by frequency division, thereby reducing the update frequency of the delay line adjustment signal, avoiding signal jitter caused by signal glitches, and reducing power consumption.
  • the detection module 121 includes:
  • the pulse generating module 21 is configured to receive a reference clock signal REF_CLK and a feedback clock signal FB_CLK, and output a phase pulse signal Diff Pulse; wherein the phase pulse signal Diff Pulse has one pulse, and the pulse width indicates the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK;
  • the control module 22 is configured to receive a phase pulse signal Diff Pulse, a reference clock signal REF_CLK and a feedback clock signal FB_CLK; when the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is greater than or equal to a first threshold, the phase pulse signal Diff Pulse is transmitted and processed, and a working indication signal is output; when the phase difference is less than the first threshold, the phase pulse signal Diff Pulse is shielded so that the level state of the working indication signal remains unchanged.
  • control module 22 can decide to transmit backward or shield the phase pulse signal Diff Pulse, thereby determining whether the time-to-digital converter 12 performs transcoding, and can avoid bit error problems when the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is small.
  • the pulse generating module 21 includes a first trigger 211, a second trigger 212, a third trigger 213, a fourth trigger 214, a fifth trigger 215, a sixth trigger 216, and a third AND gate 217; wherein the clock end of the first trigger 211, the clock end of the second trigger 212, and the clock end of the third trigger 213 all receive the feedback clock signal FB_CLK; the input end of the first trigger 211 receives the phase-locked start signal FCL start flag, the positive phase output end of the first trigger 211 is connected to the input end of the second trigger 212, and the positive phase output end of the second trigger 212 is connected to the input end of the third trigger 213.
  • the positive phase output terminal of the third trigger 213 is connected to the first input terminal of the third AND gate 217; the clock terminal of the fourth trigger 214, the clock terminal of the fifth trigger 215 and the clock terminal of the sixth trigger 216 all receive the reference clock signal REF_CLK; the input terminal of the fourth trigger 214 is connected to the inverting output terminal of the first trigger 211, the positive phase output terminal of the fourth trigger 214 is connected to the input terminal of the fifth trigger 215, the positive phase output terminal of the fifth trigger 215 is connected to the input terminal of the sixth trigger 216; the positive phase output terminal of the sixth trigger 216 is connected to the second input terminal of the third AND gate 217; the output terminal of the third AND gate 217 outputs the phase pulse signal Diff Pulse.
  • the triggers involved in the embodiments of the present disclosure are all D-type triggers (DFFs), whose functions are: at the rising edge of the signal at the clock end, the signal at the input end is sampled to obtain the signal at the positive output end (Q), and the signal at the negative output end (Q) is sampled.
  • DFFs D-type triggers
  • the signal at the positive phase output terminal (Q) and the signal at the positive phase output terminal (Q) are a pair of anti-phase signals.
  • phase-locked start signal FCL start flag indicates whether the pulse generating module 21 is working, and also indicates whether the delay phase-locked loop 10 enters the locking step.
  • FIG5 it shows a schematic diagram of the signal timing of the pulse generating module 21 .
  • the output of the pulse generating module 21 maintains a low level state; after the phase-locked start signal FCL start flag is at a high level, the output signal FB_clk align1st of the first flip-flop 211, the output signal FB_clk align 2nd of the second flip-flop 212, and the output signal FB_clk align 3rd of the third flip-flop 213 are flipped to a high level in sequence, and their rising edges are aligned with the rising edge of the feedback clock signal FB_CLK in sequence; at the same time, the output signal REF_clk align 1st of the fourth flip-flop 214, the output signal REF_clk align 2nd of the fifth flip-flop 215, and the output signal REF_clk align 3rd of the sixth flip-flop 216 are flipped to a low level in sequence, and their falling edges are aligned with the rising edge of the reference clock
  • phase pulse signal Diff Pulse is obtained through an AND operation of FB_clk align 3 rd and REF_clk align 3 rd , which indicates the phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK.
  • the first to sixth flip-flops 211 to 216 all have a reset terminal for receiving a reset signal RST to implement a reset process.
  • control module 22 includes:
  • the comparison module 221 is configured to receive a reference clock signal REF_CLK and a feedback clock signal FB_CLK, and output a comparison signal DL_PDT based on a phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK; wherein if the phase difference is greater than or equal to a first threshold, the comparison signal DL_PDT is in a first state; if the phase difference is less than the first threshold, the comparison signal DL_PDT is in a second state;
  • the logic module 222 is configured to receive the comparison signal DL_PDT and the phase pulse signal Diff Pulse, perform logic operations on the comparison signal DL_PDT and the phase pulse signal Diff Pulse, and output a work indication signal.
  • the first state is a low level state
  • the second state is a high level state
  • the logic module includes a first AND gate, the first input end of the first AND gate receives the inverted signal of the comparison signal, the second input end of the first AND gate receives the phase pulse signal, and the output end of the first AND gate outputs a work indication signal.
  • the first state is a high level state
  • the second state is a low level state
  • the logic module includes a first AND gate, the first input end of the first AND gate receives the comparison signal, the second input end of the first AND gate receives the phase pulse signal, and the output end of the first AND gate outputs the work indication signal, and the following description is based on this case.
  • the comparison module 221 includes two delay modules ( 31 , 32 ), two level comparators ( 33 , 34 ) and an operator 35 ; wherein,
  • the first delay module 31 is configured to receive a reference clock signal REF_CLK, delay the reference clock signal REF_CLK, and output a reference delay signal REF_CLK_2g, wherein the delay between the reference clock signal REF_CLK and the reference delay signal REF_CLK_2g is a first threshold;
  • the second delay module 32 is configured to receive the feedback clock signal FB_CLK, delay the feedback clock signal FB_CLK, and output a feedback delay signal FB_CLK_2g, wherein the delay between the feedback clock signal FB_CLK and the feedback delay signal FB_CLK_2g is a first threshold;
  • the first level comparator 33 is configured to receive the reference clock signal REF_CLK and the feedback delay signal FB_CLK_2g, compare the rising edge of the reference clock signal REF_CLK with the rising edge of the feedback delay signal FB_CLK_2g, and output a first result signal PD_OUT1; wherein, if the reference clock signal REF_CLK is ahead of the feedback delay signal FB_CLK_2g, the first result signal PD_OUT1 is in the third state; if the reference clock signal REF_CLK lags behind the feedback delay signal FB_CLK_2g, the first result signal PD_OUT1 is in the fourth state;
  • the second level comparator 34 is configured to receive the feedback clock signal FB_CLK and the reference delay signal REF_CLK_2g, compare the rising edge of the reference delay signal REF_CLK_2g with the rising edge of the feedback clock signal FB_CLK, and output a second result signal PD_OUT2; wherein, if the feedback clock signal FB_CLK is ahead of the reference delay signal REF_CLK_2g, the second result signal PD_OUT2 is in the third state; if the feedback clock signal FB_CLK lags behind the reference delay signal REF_CLK_2g, the second result signal PD_OUT2 is in the fourth state;
  • the operator 35 is configured to receive the first result signal PD_OUT1 and the second result signal PD_OUT2 , perform a logic operation on the first result signal PD_OUT1 and the second result signal PD_OUT2 , and output a comparison signal DL_PDT.
  • the third state and the fourth state are different and can be set according to the actual application scenario.
  • the third state is a high level state and the fourth state is a low level state as an example for explanation in the following embodiments of the present disclosure. Understand accordingly.
  • the delay adjustment granularity of the coarse control code is the delay value of 2 NAND gates, that is, the first threshold can be the delay value of 2 NAND gates, expressed as 2g.
  • FIG7 it shows a schematic diagram of the signal timing of the comparison module 221. In conjunction with FIG7 , three cases are described:
  • Case 1 The reference clock signal REF_CLK lags behind the feedback clock signal FB_CLK, and the phase difference is greater than or equal to the first threshold 2g.
  • the reference clock signal REF_CLK lags behind the feedback delay signal FB_CLK_2g, and the feedback clock signal FB_CLK leads the reference delay signal REF_CLK_2g, as shown in (a) of FIG. 7 , at this time, the first result signal PD_OUT1 is in a low level state, and the second result signal PD_OUT1 is in a high level state.
  • Case 2 (not shown in FIG. 7 ): the reference clock signal REF_CLK is ahead of the feedback clock signal FB_CLK, and the phase difference is greater than or equal to the first threshold 2g. At this time, the reference clock signal REF_CLK is ahead of the feedback delay signal FB_CLK_2g, and the feedback clock signal FB_CLK lags behind the reference delay signal REF_CLK_2g. At this time, the first result signal PD_OUT1 is in a high level state, and the second result signal PD_OUT1 is in a low level state.
  • Case 3 The phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is less than the first threshold 2g, then the reference clock signal REF_CLK leads the feedback delay signal FB_CLK_2g, and the feedback clock signal FB_CLK leads the reference delay signal REF_CLK_2g.
  • the first result signal PD_OUT1 and the second result signal PD_OUT2 are both in high level state.
  • the first result signal PD_OUT1 and the second result signal PD_OUT2 have a low level; if the phase difference is less than the first threshold 2g, the first result signal PD_OUT1 and the second result signal PD_OUT2 both change to a high level.
  • the operator 35 includes a second AND gate 351 and a second NOT gate 352, the first input end of the second AND gate 351 receives the first result signal PD_OUT1, the second input end of the second AND gate 351 receives the second result signal PD_OUT2, the output end of the second AND gate 351 is connected to the input end of the second NOT gate 352, and the second NOT gate 352 is used to output the comparison signal DL_PDT.
  • the comparison signal DL_PDT is in the first state (high level); as shown in (b) of FIG. 7 , if the phase difference is less than the first threshold value 2g, the comparison signal DL_PDT is in the second state (low level).
  • OUT indicates the output of the second AND gate 351.
  • the delay module and the level comparator in the comparison module 221 are described in detail below.
  • the delay module includes a first NAND gate 311 and a second NAND gate 312; wherein the first input end of the first NAND gate 311 forms the input end of the delay module, the first input end of the second NAND gate 312 is connected to the output end of the first NAND gate 311, the second input end of the first NAND gate 311 and the second input end of the second NAND gate 312 both receive the first power supply signal VDD, and the output end of the second NAND gate 312 forms the output end of the delay module.
  • the level comparator includes a comparison unit 41 , a latch unit 43 and a first NOT gate 45 ; wherein,
  • the comparison unit 41 includes a first output terminal and a second output terminal, and is configured to receive a first input signal XCLK and a second input signal CLK, and compare the first input signal XCLK and the second input signal CLK when the first input signal XCLK is in a high level state, and charge and discharge the first output terminal and the second output terminal according to the comparison result, so as to compare the rising edge of the first input signal XCLK and the rising edge of the second input signal CLK;
  • the latch unit 43 includes a first input terminal, a second input terminal and an output terminal.
  • the first input terminal of the latch unit 43 is connected to the first output terminal of the comparison unit 41
  • the second input terminal of the latch unit 43 is connected to the second output terminal of the comparison unit 41
  • the output terminal of the comparison unit 41 is connected to the input terminal of the first NOT gate 45.
  • the first input signal XCLK refers to the reference clock signal REF_CLK
  • the second input signal CLK refers to the feedback delay signal FB_CLK_2g
  • the output end of the first NOT gate 45 is used to output the first result signal PD_OUT1
  • the first input signal XCLK refers to the feedback clock signal FB_CLK
  • the second input signal CLK refers to the reference delay signal REF_CLK_2g
  • the output end of the first NOT gate 45 is used to output the second result signal PD_OUT2.
  • the comparison unit 41 can compare the first input signal XCLK with the second output signal only when the first input signal XCLK is in a high level state.
  • the latch unit 43 may be an SR latch composed of two NAND gates (as shown in FIG. 9 ), or the latch unit 43 may be an SR latch composed of two NOR gates.
  • a possible structure of the comparison unit 41 is provided below.
  • the comparison unit 41 includes a cross-coupling component, a pre-charging component, an input component, a control component and a balancing component; wherein the cross-coupling component includes a first switch tube 401, a second switch tube 402, a third switch tube 403 and a fourth switch tube 404; the control end of the first switch tube 401, the control end of the second switch tube 402, the second end of the third switch tube 403 and the first end of the fourth switch tube 404 are connected to the first output end, and the control end of the third switch tube 403, the control end of the fourth switch tube 404, the second end of the first switch tube 401, the second end of the second switch tube 402, the second end of the third switch tube 403 and the first end of the fourth switch tube 404 are connected to the first output end.
  • the cross-coupling component includes a first switch tube 401, a second switch tube 402, a third switch tube 403 and a fourth switch tube 404; the control end of the first switch tube 401, the control end of
  • the first end of the first switch tube 402 is connected to the second output end, the first end of the first switch tube 401 receives the second power supply signal, and the first end of the third switch tube 403 receives the third power supply signal;
  • the pre-charging component includes a fifth switch tube 405, a sixth switch tube 406 and a seventh switch tube 407;
  • the control end of the fifth switch tube 405, the control end of the sixth switch tube 406 and the control end of the seventh switch tube 407 all receive the first input signal XCLK, the first end of the fifth switch tube 405 receives the fourth power supply signal, the first end of the sixth switch tube 406 receives the fifth power supply signal, and the fifth switch tube 405 receives the fourth power supply signal.
  • the second end of the seventh switch tube 407 is connected to the first output end, the second end of the sixth switch tube 406 and the second end of the seventh switch tube 407 are connected to the second output end;
  • the input component includes an eighth switch tube 408 and a ninth switch tube 409, the control end of the eighth switch tube 408 receives the first input signal XCLK, the control end of the ninth switch tube 409 receives the second input signal CLK, the first end of the eighth switch tube 408 is connected to the second end of the second switch tube 402, and the first end of the ninth switch tube 409 is connected to the second end of the fourth switch tube 404;
  • the equalizing component includes a tenth switch tube 410, the control end of the tenth switch tube 410 receives the first input signal, the first end of the tenth switch tube 410 is connected to the second end of the eighth switch tube 408 and the second end of the ninth switch tube 409, and the second end of the tenth switch tube 410 is connected to the ground signal;
  • first switch tube 401, the third switch tube 403, the fifth switch tube 405, the sixth switch tube 406, the seventh switch tube 407 and the eleventh switch tube 411 are all P-type field effect tubes
  • the second switch tube 402, the fourth switch tube 404, the eighth switch tube 408, the ninth switch tube 409 and the tenth switch tube 410 are all N-type field effect tubes.
  • Other situations can be adaptively understood.
  • the comparison unit 41 is not turned on as a whole, and the first output terminal and the second output terminal are charged to a high level by the pre-charge component and cannot reflect the level comparison result of the input signal; on the contrary, only when the first input signal XCLK is in a high level state, the first output terminal and the second output terminal will reflect the level comparison result of the input signal, that is, the comparison unit 41 can perform the signal comparison function.
  • the latch unit 43 includes a third NAND gate 431 and a fourth NAND gate 432; wherein, the first input end of the third NAND gate 431 constitutes the first input end of the latch unit 43, the second input end of the third NAND gate 431 is connected to the output end of the fourth NAND gate 432, and the third input end of the third NAND gate 431 receives the reset signal LRSTB; the first input end of the fourth NAND gate 432 constitutes the second input end of the latch unit 43, and the second input end of the fourth NAND gate 432 is connected to the output end of the third NAND gate 431.
  • the output terminal when the first input terminal and the second input terminal are both high level, the output terminal will maintain the previous level state unchanged; when the first input terminal is high level and the second input terminal is low level, the output terminal is low level; when the first input terminal is low level and the second input terminal is high level, the output terminal is high level; when the first input terminal is low level and the second input terminal is low level, the state of the output terminal is uncertain, and in principle this situation will not occur.
  • the reset signal LRSTB is used to reset the latch unit 43. Specifically, if the reset signal LRSTB is at a low level, the output terminal of the third NAND gate 431 is at a high level, that is, the latch unit 43 is reset to a high level.
  • the output signal of the latch unit 43 is called the intermediate signal
  • the output signal of the first inverter 45 is called the result signal PD_OUT. Due to the effect of the reset signal LRSTB, the intermediate signal is initially at a high level, and the result signal PD_OUT is initially at a low level.
  • the pre-charge component and the equalization component are turned on, but the control component is not turned on, that is, the comparison unit does not enter the comparison state, and the potentials of the first output terminal and the second output terminal are pulled to a high level by the pre-charge component.
  • the tenth switch tube 410 is turned on to put the comparison unit into operation, the cross-coupling component, the eighth switch tube 408 and the tenth switch tube 410 are turned on, and the ninth switch tube 409 is not turned on at this time.
  • the potential of the second output terminal is gradually lower than the potential of the first output terminal. After the difference of the cross-coupling component is amplified, the first output terminal outputs a high-level signal and the second output terminal outputs a low-level signal, so that the intermediate signal becomes a low level, and the result signal PD_OUT becomes a high level.
  • phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is greater than or equal to the first threshold 2g, then one of the first result signal PD_OUT1 and the second result signal PD_OUT2 must be in a low level state, and the comparison result signal DL_PDT is a high level. If the above phase difference is less than the first threshold 2g, then both the first result signal PD_OUT1 and the second result signal PD_OUT2 become high level states, and the comparison result signal DL_PDT becomes a low level.
  • an even number of inverters may be provided on the connection path between the comparison unit 41 and the latch unit 43 to achieve delay matching and drive enhancement between signals.
  • the embodiment of the present disclosure provides a delay phase-locked loop.
  • the time-to-digital converter does not need to work, which can improve the bit error problem, speed up the locking speed of the delay phase-locked loop, and improve the performance of the delay phase-locked loop.
  • the first delay line 111 comprises a coarse delay line
  • the first delay line 111 is further configured to adjust the working state of the coarse delay line through a coarse adjustment control code to adjust the delay parameter.
  • the coarse delay line includes n+1 first delay units connected in series, and the delay of the first delay unit is the first threshold, which is also the delay value of the aforementioned delay module.
  • the coarse adjustment control code includes an n+1-bit sub-signal, which can be expressed as Q ⁇ n:1>; the i-th first delay unit receives the i-th sub-signal Q ⁇ i-1> of the coarse adjustment control code.
  • the output signal of the coarse adjustment delay line can be controlled to be output from the first delay unit at a specific position, thereby controlling the delay parameter of the coarse adjustment delay line.
  • the conversion module 122 includes n+1 second delay units 51 and n+1 seventh delay units 52 connected in series. Trigger 52; wherein, the input end of the first second delay unit 51 receives the work indication signal, the output end of the i-th second delay unit 51 is connected to the input end of the i+1-th second delay unit 51; the input end of the i-th seventh trigger 52 is connected to the output end of the i-th second delay unit 51, the clock end of the i-th seventh trigger 52 receives the inverted signal of the work indication signal, and the positive phase output end of the i-th seventh trigger 52 outputs the i-th bit sub-signal of the coarse adjustment control code; the delay of the second delay unit 51 is the first threshold.
  • D0 0 refers to the input signal of the first seventh trigger 52
  • D0 1 refers to the input signal of the second seventh trigger 52
  • D0 n refers to the input signal of the n+1th seventh trigger 52.
  • D0 n are sampled at the falling edge of the work indication signal (i.e., the rising edge of the inverted signal of the work indication signal), and Q0 (high level), Q1 (high level), Q2 (high level), Q3 (high level), Q4 (low level), Q5 (low level) ... Qn (low level) are obtained in sequence, and Q0, Q1, Q2, Q3, Q4, Q5 ... Qn together constitute the coarse adjustment control code Q ⁇ n:1>.
  • the processing process of the coarse adjustment delay line can be simulated by n+1 second delay units 51 connected in series, and the output signal of each second delay unit 51 is sampled by n+1 seventh triggers 52 to obtain the coarse adjustment control code.
  • the time-to-digital converter generates a digital code (used as the initial value of the coarse control code) using the phase difference between the reference clock signal and the feedback clock signal, and this digital code is generated by a trigger.
  • a digital code used as the initial value of the coarse control code
  • the pulse of the phase pulse signal is too narrow, and the time-to-digital converter will have a code error problem, which will lead to a coarse delay line (CDL) locking error, which brings a heavy burden to the adjustment process and prolongs the locking process of the delay-locked loop.
  • CDL coarse delay line
  • the phase difference between the reference clock signal and the feedback clock signal is detected by a detection module, and when the phase difference is small, the time-to-digital converter is controlled not to perform transcoding processing, so as to avoid an unexpected increase in the locking time of the delay-locked loop.
  • a schematic diagram of the structure of a memory 50 provided by the present disclosure is shown.
  • the memory 50 at least includes the delay locked loop 10 mentioned above.

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Abstract

本公开实施例提供了一种延迟锁相环和存储器，在开始工作时，延迟锁相环确定参考时钟信号和反馈时钟信号之间的相位差，若相位差较大，则将相位差转换为粗调控制码的初始值；若相位差较小，则不进行转换。

Description

一种延迟锁相环和存储器
相关申请的交叉引用
本公开要求在2022年10月21日提交中国专利局、申请号为202211295105.5、申请名称为“一种延迟锁相环和存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种延迟锁相环和存储器。
背景技术
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，延迟锁相环需要利用延迟线对四相位时钟信号(即4个相位依次相差90度的时钟信号)进行传输，以便后续完成数据采样处理。然而，在延迟锁相环的工作过程中，需要对延迟线的工作参数进行调节和锁定，利用时间数字转换器可以加快延迟线调节的速度。然而，时间数字转换器在某些情况下会出现误码问题，反而为延迟线调节带来不利影响，增加了延迟锁相环的锁定时间。
发明内容
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种延迟锁相环，所述延迟锁相环包括第一信号路径和时间数字转换器，所述时间数字转换器包括检测模块和转换模块；其中，
所述第一信号路径，包括第一延迟线，配置为接收参考时钟信号，输出反馈时钟信号；其中，所述第一延迟线的延迟参数受到粗调控制码的控制；
所述检测模块，配置为接收所述参考时钟信号和所述反馈时钟信号；基于所述参考时钟信号和所述反馈时钟信号之间的相位差，输出工作指示信号；其中，在所述相位差大于等于第一阈值的情况下，所述工作指示信号产生一个脉冲，且脉冲宽度指示所述相位差的大小；在所述相位差小于所述第一阈值的情况下，所述工作指示信号的电平状态保持不变；
所述转换模块，配置为接收所述工作指示信号，对所述工作指示信号的脉冲宽度进行转换，输出所述粗调控制码的初始值。
在一些实施例中，所述检测模块包括：脉冲产生模块，配置为接收所述参考时钟信号和所述反馈时钟信号，输出相位脉冲信号；其中，所述相位脉冲信号存在一个脉冲，且脉冲宽度指示所述参考时钟信号和所述反馈时钟信号之间的相位差；控制模块，配置为接收所述相位脉冲信号、所述参考时钟信号和所述反馈时钟信号；在所述参考时钟信号和所述反馈时钟信号的相位差大于等于所述第一阈值的情况下，对所述相位脉冲信号进行传输处理，输出所述工作指示信号；在所述相位差小于所述第一阈值的情况下，对所述相位脉冲信号进行屏蔽处理，以使得所述工作指示信号的电平状态保持不变。
在一些实施例中，所述控制模块包括：比较模块，配置为接收所述参考时钟信号和所述反馈时钟信号，基于所述参考时钟信号和所述反馈时钟信号的相位差，输出比较信号；其中，若所述相位差大于等于所述第一阈值，则所述比较信号为第一状态；若所述相位差小于第一阈值，则所述比较信号为第二状态；逻辑模块，配置为接收所述比较信号和所述相位脉冲信号，对所述比较信号和所述相位脉冲信号进行逻辑运算，输出所述工作指示信号。
在一些实施例中，所述第一状态为高电平状态，所述第二状态为低电平状态；所述逻辑模块包括第一与门，所述第一与门的第一输入端接收所述比较信号，所述第一与门的第二输入端接收所述相位脉冲信号，所述第一与门的输出端输出所述工作指示信号。
在一些实施例中，所述比较模块包括2个延迟模块、2个电平比较器和运算器；其中，第1个所述延迟模块，配置为接收所述参考时钟信号，对所述参考时钟信号进行延迟处理，输出参考延迟信号，且所述参考时钟信号和所述参考延迟信号之间的延迟为所述第一阈值；第2个所述延迟模块，配置为接收所述反馈时钟信号，对所述反馈时钟信号进行延迟处理，输出反馈延迟信号，且所述反馈时钟信号和所述反馈延迟信号之间的延迟为所述第一阈值；第1个所述电平比较器，配置为接收所述参考时钟信号和所述反馈延迟信号，对所述参考时钟信号的上升沿和所述反馈延迟信号的上升沿进行比较，输出第一结果信号；其中，若所述参考时钟信号超前于所述反馈延迟信号，则所述第一结果信号为第三状态；若所述参考时钟信号滞后于所述反馈延迟信号，则所述第一结果信号为第四状态；第2个所述电平比较器，配置为接收所述反馈时钟信号和所述参考延迟信号，对所述参考延迟信号的上升沿和所述反馈时钟信号的上升沿进行比较，输出第二结果信号；其中，若所述反馈时钟信号超前于所述参考延迟信号则所述第二结果信号为第三状态；若反馈时钟信号滞后于所述参考延迟信号，则所述第二结果信号为第四状态；运算器，配置为接收所述第一结果信号和所述第二结果信号，对所述第一结果信号和所述第二结果信号进行逻辑运算，输出所述比较信号。
在一些实施例中，所述延迟模块包括第一与非门和第二与非门；其中，所述第一与非门的第一输入端形成所述延迟模块的输入端，所述第二与非门的第一输入端与所述第一与非门的输出端连接，所述第一与非门的第二输入端、所述第二与非门的第二输入端均接收第一电源信号，所述第二与非门的输出端形成所述延迟模块的输出端。
在一些实施例中，所述电平比较器包括比较单元、锁存单元和第一非门；其中，所述比较单元包括第一输出端和第二输出端，配置为接收第一输入信号和第二输入信号；在所述第一输入信号为高电平状态的情况下，对所述第一输入信号和所述第二输入信号进行电平比较，并根据比较结果对第一输出端和第二输出端进行充放电处理，以比较所述第一输入信号的上升沿和所述第二输入信号的上升沿；所述锁存单元包括第一输入端、第二输入端和输出端，所述锁存单元的第一输入端与所述比较单元的第一输出端连接，所述锁存单元的第二输入端与所述比较单元的第二输出端连接，所述比较单元的输出端与第一非门的输入端连接；其中，对于第1个所述电平比较器，第一输入信号是指所述参考时钟信号，所述第二输入信号是指所述反馈延迟信号，所述第一非门的输出端用于输出所述第一结果信号；对于第2个所述电平比较器，所述第一输入信号是指反馈时钟信号，所述第二输入信号是指参考延迟信号，所述第一非门的输出端用于输出所述第二结果信号。
在一些实施例中，所述比较单元包括交叉耦合组件、预充组件、输入组件、控制组件和均衡组件；其中，交叉耦合组件包括第一开关管、第二开关管、第三开关管、第四开关管；所述第一开关管的控制端、所述第二开关管的控制端、所述第三开关管的第二端、所述第四开关管的第一端与所述第一输出端连接，所述第三开关管的控制端、所述第四开关管的控制端、所述第一开关管的第二端、所述第二开关管的第一端与所述第二输出端连接，所述第一开关管的第一端接收第二电源信号，所述第三开关管的第一端接收第三电源信号；所述预充组件包括第五开关管、第六开关管和第七开关管；所述第五开关管的控制端、所述第六开关管的控制端和所述第七开关管的控制端均接收所述第一输入信号，所述第五开关管的第一端接收第四电源信号，所述第六开关管的第一端接收第五电源信号，所述第五开关管的第二端、所述第七开关管的第一端与所述第一输出端连接，所述第六开关管的第二端、所述第七开关管的第二端与所述第二输出端连接；所述输入组件包括第八开关管和第九开关管，所述第八开关管的控制端接收所述第一输入信号，所述第九开关管的控制端接收所述第二输入信号，所述第八开关管的第一端与所述第二开关管的第二端连接，所述第九开关管的第一端与所述第四开关管的第二端连接；所述控制组件包括第十开关管，所述第十开关管的控制端接收所述第一输入信号，所述第十开关管的第一端与所述第八开关管的第二端、所述第九开关管的第二端连接，所述第十开关管的第二端与地信号连接；所述均衡组件包括第十一开关管，所述第十一开关管的控制端接收所述第一输入信号，所述第十一开关管的第一端与所述第四开 关管的第二端连接，所述第十一开关管的第二端与所述第二开关管的第二端连接。
在一些实施例中，所述第一开关管、所述第三开关管、所述第五开关管、所述第六开关管、所述第七开关管和所述第十一开关管均为P型场效应管，所述第二开关管、所述第四开关管、所述第八开关管、所述第九开关管和所述第十开关管均为N型场效应管。
在一些实施例中，所述锁存单元包括第三与非门和第四与非门；其中，所述第三与非门的第一输入端构成所述锁存单元的第一输入端，所述第三与非门的第二输入端和所述第四与非门的输出端连接，所述第三与非门的第三输入端接收复位信号；所述第四与非门的第一输入端构成所述锁存单元的第二输入端，所述第四与非门的第二输入端和所述第三与非门的输出端连接。
在一些实施例中，所述第三状态为高电平状态，所述第四状态为低电平状态；所述运算器包括第二与门和第二非门，所述第二与门的第一输入端接收所述第一结果信号，所述第二与门的第二输入端所述第二结果信号，所述第二与门的输出端和所述第二非门的输入端连接，所述第二非门用于输出所述比较信号。
在一些实施例中，所述脉冲产生模块包括第一触发器、第二触发器、第三触发器、第四触发器、第五触发器和第六触发器、第三与门；其中，所述第一触发器的时钟端、所述第二触发器的时钟端和所述第三触发器的时钟端均接收所述反馈时钟信号；所述第一触发器的输入端接收锁相开启信号，所述第一触发器的正相输出端与所述第二触发器的输入端连接，所述第二触发器的正相输出端与所述第三触发器的输入端连接，所述第三触发器的正相输出端和所述第三与门的第一输入端连接；所述第四触发器的时钟端、所述第五触发器的时钟端和所述第六触发器的时钟端均接收所述参考时钟信号；所述第四触发器的输入端与所述第一触发器的反相输出端连接，所述第四触发器的正相输出端与所述第五触发器的输入端连接，所述第五触发器的正相输出端和所述第六触发器的输入端连接；所述第六触发器的正相输出端和所述第三与门的第二输入端连接；所述第三与门的输出端输出所述相位脉冲信号。
在一些实施例中，所述第一延迟线包括粗调延迟线；其中，所述第一延迟线，还配置为通过所述粗调控制码调整所述粗调延迟线的工作状态，以实现延迟参数的调整；其中，所述粗调延迟线包括n+1个串联的第一延迟单元，所述第一延迟单元的延迟是所述第一阈值；所述粗调控制码包括n+1位子信号，第i个所述第一延迟单元接收所述粗调控制码的第i位子信号，n为自然数。
在一些实施例中，所述转换模块包括n+1个串联的第二延迟单元和n+1个第七触发器；其中，第1个所述第二延迟单元的输入端接收所述工作指示信号，第i个所述第二延迟单元的输出端与第i+1个所述第二延迟单元的输入端连接；第i个所述第七触发器的输入端与第i个所述第二延迟单元的输出端连接，第i个所述第七触发器的时钟端接收所述工作指示信号的反相信号，第i个所述第七触发器的正相输出端输出粗调控制码的第i位子信号；所述第二延迟单元的延迟是所述第一阈值。
在一些实施例中，所述延迟锁相环还包括时钟处理模块和多个第二延迟线，所述时钟处理模块与所述第一延迟线、多个所述第二延迟线均连接，所述第一延迟线和所述第二延迟线的结构相同，所述第二延迟线的延迟参数受到所述粗调控制码的控制；其中，所述时钟处理模块，配置为接收初始时钟信号，基于所述初始时钟信号，输出多个分相时钟信号；其中，所述参考时钟信号是其中一个所述分相时钟信号；所述第二延迟线，配置为接收一个所述分相时钟信号，对所接收的分相时钟信号进行延迟传输及调整处理，输出一个目标时钟信号；其中，所述目标时钟信号经过传输后用于数据采样处理。
第二方面，本公开实施例提供了一种存储器，所述存储器包括如第一方面所述的延迟锁相环。
附图说明
图1为本公开实施例提供的一种延迟锁相环的结构示意图；
图2为本公开实施例提供的一种延迟锁相环的应用场景示意图；
图3为本公开实施例提供的另一种延迟锁相环的结构示意图；
图4为本公开实施例提供的一种延迟锁相环的局部结构示意图一；
图5为本公开实施例提供的一种信号时序示意图一；
图6为本公开实施例提供的一种延迟锁相环的局部结构示意图二；
图7为本公开实施例提供的一种信号时序示意图二；
图8为本公开实施例提供的一种延迟锁相环的局部结构示意图三；
图9为本公开实施例提供的一种延迟锁相环的局部结构示意图四；
图10为本公开实施例提供的一种信号时序示意图三；
图11为本公开实施例提供的又一种延迟锁相环的结构示意图；
图12为本公开实施例提供的一种信号时序示意图四；
图13为本公开实施例提供的一种存储器的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
动态随机存取存储器(Dynamic Random Access Memory，DRAM)；
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)；
双倍数据速率内存(Double Data Rate SDRAM，DDR)；
低功率DDR(Low Power DDR，LPDDR)。
以DRAM为例，来自于外部的初始时钟信号在内部会分频且分为四相位时钟信号，四相位时钟信号分别送入延迟锁相环进行相位同步及锁定，调整后的四相位时钟信号经过传输后用于对数据信号DQ进行采样及选择输出。延迟锁相环包括第一延迟线和多个第二延迟线(一般为4条)，第二延迟线用于实现四相位时钟信号的调整及传输，第一延迟线用于复制第二延迟线的处理过程，且第一延迟线的传输结果作为所有延迟线的工作参数的调整依据。在这里，第一延迟线和第二延迟线的结构是相同的，均包括粗调延迟线、细调延迟线、占空比调节模块等部分。延迟锁相环在经过延迟粗调、延迟细调、占空比调整等步骤后实现锁定。
本公开实施例主要涉及延迟粗调这一过程，具体是通过粗调控制码来调整第一延迟线/第二延迟线中的粗调延迟线的延迟参数。在延迟粗调的步骤中，可以通过时间数字转换器确定粗调控制码的初始值。具体来说，时间数字转换器接收参考时钟信号和反馈时钟信号，参考时钟信号是指第一延迟线的输入信号，反馈时钟信号用于模拟参考时钟信号经过延迟锁相环传输后的波形；然后，时间数字转换器将相位脉冲信号(其脉冲宽度指示参考时钟信号和反馈时钟信号之间的相位差)转换为粗调控制码的初始值。目前，时间数字转换器一般通过触发器(DFF)实现转码，但是在相位脉冲信号的脉冲过窄时，时间数字转换器处于亚稳态而出现误码问题，此时转换得到的粗调控制码的初始值是错误的，反而延长了延迟锁相环的锁定时间。
本公开实施例提供了一种延迟锁相环，在参考时钟信号和反馈时钟信号的相位差较小时， 时间数字转换器无需工作，能够改善误码问题，加快延迟锁相环的锁定速度，提高延迟锁相环的性能。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图1，其示出了本公开实施例提供的一种延迟锁相环10的结构示意图。如图1所示，延迟锁相环10包括第一信号路径11和时间数字转换器12，时间数字转换器12包括检测模块121和转换模块122；其中，
第一信号路径11，包括第一延迟线111，配置为接收参考时钟信号，输出反馈时钟信号；其中，第一延迟线111的延迟参数受到粗调控制码的控制；
检测模块121，配置为接收参考时钟信号和反馈时钟信号；基于参考时钟信号和反馈时钟信号之间的相位差，输出工作指示信号；其中，在上述相位差大于等于第一阈值的情况下，工作指示信号产生一个脉冲，且脉冲宽度指示上述相位差的大小；在上述相位差小于第一阈值的情况下，工作指示信号的电平状态保持不变；
转换模块122，配置为接收工作指示信号，对工作指示信号的脉冲宽度进行转换，输出粗调控制码的初始值。
需要说明的是，本公开实施例的延迟锁相环10可以应用但不限于存储器，例如DRAM、SDRAM、DDR、LPDDR等。另外，在其他模拟电路/数字电路中，均可通过本公开实施例提供的延迟锁相环10实现时钟信号的相位锁定。
在这里，参考时钟信号经过延迟锁相环10的调整及相应信号路径的传输后用于进行数据采样处理，而反馈时钟信号用于模拟(参考时钟信号对应的)用于进行数据采样处理的信号波形。应理解，反馈时钟信号与参考时钟信号需要在误差允许的范围内处于对齐状态，从而实现数据的正确采样。在这里，“对齐”是指：反馈时钟信号和参考时钟信号的时钟周期相同，反馈时钟信号和参考时钟信号的上升沿一致，反馈时钟信号和参考时钟信号的下降沿一致。
在本公开实施例中，在参考时钟信号和反馈时钟信号的相位差大于等于第一阈值的情况下，工作指示信号存在脉冲，转换模块122将工作指示信号的脉冲宽度转码为粗调控制码的初始值，即粗调控制码以时间数字转换器12输出的初始值为起点进行调整，从而加快粗调控制码的调整进程。反之，在参考时钟信号和反馈时钟信号的相位差小于第一阈值的情况下，工作指示信号不存在脉冲，转换模块122并不会工作，粗调控制码不会被时间数字转换器12赋予初始值，从而避免时间数字转换器12在输入信号相位差较小的情况下处于亚稳态而输出错误码值，避免为粗调控制码的调整过程带来不利影响，防止额外延长延迟锁相环的锁定时间，从而提高了延迟锁相环的工作性能。
还需要说明的是，第一阈值可以根据实际应用场景进行确定。示例性的，第一阈值为粗调控制码的延迟调整粒度。粗调控制码的延迟调整粒度是指：在粗调控制码进行最小单位的调整时，第一延迟线111的延迟调整量。
在一些实施例中，请参见图2，其示出了延迟锁相环10的应用场景示意。如图2所示，延迟锁相环10还包括时钟处理模块13和多个第二延迟线(图2以4个第二延迟线为例进行示出)，时钟处理模块13与第一延迟线111、多个第二延迟线均连接。在这里，第一延迟线111和所有的第二延迟线的结构相同，且第一延迟线111、所有第二延迟线的延迟参数均受到前述的粗调控制码的控制。
在这里，时钟处理模块13，配置为接收初始时钟信号，基于初始时钟信号，输出多个分相时钟信号(例如图2中的clk0、clk90、clk180和clk270)；其中，参考时钟信号是其中一个分相时钟信号。第二延迟线，配置为接收一个分相时钟信号，对所接收的分相时钟信号进行延迟传输及调整处理，输出一个目标时钟信号(即图2中的CLK_0、CLK_90、CLK_180或CLK_270)。其中，目标时钟信号经过信号路径的传输后用于数据采样处理。
需要说明的是，如图2所示，第二延迟线的输出端通过相应的信号路径连接到数据选择模块，即4个目标时钟信号(即图2中的CLK_0、CLK_90、CLK_180和CLK_270)在经过 信号路径的传输后到达数据选择模块，数据选择模块还会接收数据信号DQ，并利用所接收到的目标时钟信号对数据信号DQ进行采样及选择输出处理。
在理想状态下，clk0与CLK_0经过信号路径传输后的波形一致，clk90与CLK_90经过信号路径传输后的波形一致，clk180与CLK_180经过信号路径传输后的波形一致，clk270与CLK_270经过信号路径传输后的波形一致。以图2为例，参考时钟信号是指第1个分相时钟信号clk0，反馈时钟信号用于模拟CLK_0传输到数据选择模块时的波形。换句话说，延迟锁相环10需要通过第一信号路径11模拟“第二延迟线+信号路径”的延迟，从而实现反馈调整。
因此，在一些实施例中，如图2所示，第一信号路径11还包括延迟模拟模块112；其中，第一延迟线111，配置为接收参考时钟信号，对参考时钟信号进行延迟传输及调整处理，输出第一目标信号；延迟模拟模块112，与第一延迟线111连接，配置为对第一目标信号进行延迟传输，输出反馈时钟信号。
需要说明的是，以图2为例，第一延迟线111用于复制第二延迟线的延时，延迟模拟模块用于复制信号路径的延时。这样，反馈时钟信号和参考时钟信号的相位差能够体现第一延迟线111的延迟参数是否合适，而且该相位差也是延迟参数的调整依据。
特别地，在延迟锁相环10进入稳定工作状态之后，第一信号路径11中的信号可以进行分频处理，从而降低延迟线调整信号的更新频次，避免信号毛刺带来的信号抖动，同时降低电力消耗。
在一些实施例中，如图3所示，检测模块121包括：
脉冲产生模块21，配置为接收参考时钟信号REF_CLK和反馈时钟信号FB_CLK，输出相位脉冲信号Diff Pulse；其中，相位脉冲信号Diff Pulse存在一个脉冲，且脉冲宽度指示参考时钟信号REF_CLK和反馈时钟信号FB_CLK之间的相位差；
控制模块22，配置为接收相位脉冲信号Diff Pulse、参考时钟信号REF_CLK和反馈时钟信号FB_CLK；在参考时钟信号REF_CLK和反馈时钟信号FB_CLK的相位差大于等于第一阈值的情况下，对相位脉冲信号Diff Pulse进行传输处理，输出工作指示信号；在相位差小于第一阈值的情况下，对相位脉冲信号Diff Pulse进行屏蔽处理，以使得所述工作指示信号的电平状态保持不变。
这样，控制模块22可以决定向后传输或者屏蔽相位脉冲信号Diff Pulse，从而决定时间数字转换器12是否进行转码，能够在参考时钟信号REF_CLK和反馈时钟信号FB_CLK的相位差较小时避免误码问题。
在一些实施例中，如图4所示，脉冲产生模块21包括第一触发器211、第二触发器212、第三触发器213、第四触发器214、第五触发器215和第六触发器216、第三与门217；其中，第一触发器211的时钟端、第二触发器212的时钟端和第三触发器213的时钟端均接收反馈时钟信号FB_CLK；第一触发器211的输入端接收锁相开启信号FCL start flag，第一触发器211的正相输出端与第二触发器212的输入端连接，第二触发器212的正相输出端与第三触发器213的输入端连接，第三触发器213的正相输出端和第三与门217的第一输入端连接；第四触发器214的时钟端、第五触发器215的时钟端和第六触发器216的时钟端均接收参考时钟信号REF_CLK；第四触发器214的输入端与第一触发器211的反相输出端连接，第四触发器214的正相输出端与第五触发器215的输入端连接，第五触发器215的正相输出端和第六触发器216的输入端连接；第六触发器216的正相输出端和第三与门217的第二输入端连接；第三与门217的输出端输出相位脉冲信号Diff Pulse。
需要说明的是，本公开实施例涉及的触发器均为D型触发器(DFF)，其功能为：在时钟端的信号上升沿，对输入端的信号进行采样得到正相输出端(Q)的信号，反相输出端的信号与正相输出端(Q)的信号为一对反相信号。
需要说明的是，锁相开启信号FCL start flag指示脉冲产生模块21是否工作，也指示延时锁相环10是否进入锁定步骤。参见图5，其示出了脉冲产生模块21的信号时序示意图。 如图5所示，在锁相开启信号FCL start flag为低电平时，脉冲产生模块21的输出保持低电平状态；在锁相开启信号FCL start flag为高电平后，第一触发器211的输出信号FB_clk align1st、第二触发器212的输出信号FB_clk align 2nd、第三触发器213的输出信号FB_clk align 3rd依次翻转为高电平，且其上升沿依次与反馈时钟信号FB_CLK的上升沿对齐；同时，第四触发器214的输出信号REF_clk align 1st、第五触发器215的输出信号REF_clk align 2nd、第六触发器216的输出信号REF_clk align 3rd依次翻转为低电平，且其下降沿依次与参考时钟信号REF_CLK的上升沿对齐。这样，FB_clk align 3rd和REF_clk align 3rd经过与运算结果得到相位脉冲信号Diff Pulse，其指示了反馈时钟信号FB_CLK和参考时钟信号REF_CLK的相位差。
如图4所示，第一触发器211～第六触发器216均具有复位端，用于接收复位信号RST，实现复位处理。
在一些实施例中，如图3所示，控制模块22包括：
比较模块221，配置为接收参考时钟信号REF_CLK和反馈时钟信号FB_CLK，基于参考时钟信号REF_CLK和反馈时钟信号FB_CLK的相位差，输出比较信号DL_PDT；其中，若上述相位差大于等于第一阈值，则比较信号DL_PDT为第一状态；若上述相位差小于第一阈值，则比较信号DL_PDT为第二状态；
逻辑模块222，配置为接收比较信号DL_PDT和相位脉冲信号Diff Pulse，对比较信号DL_PDT和相位脉冲信号Diff Pulse进行逻辑运算，输出工作指示信号。
需要说明的是，在第一种实现方式中，第一状态为低电平状态，第二状态为高电平状态；逻辑模块包括第一与门，第一与门的第一输入端接收比较信号的反相信号，第一与门的第二输入端接收相位脉冲信号，第一与门的输出端输出工作指示信号。或者，在第二种实现方式中，第一状态为高电平状态，第二状态为低电平状态；逻辑模块包括第一与门，第一与门的第一输入端接收比较信号，第一与门的第二输入端接收相位脉冲信号，第一与门的输出端输出工作指示信号，后续均以此种情况进行说明。
在一些实施例中，如图6所示，比较模块221包括2个延迟模块(31、32)、2个电平比较器(33、34)和运算器35；其中，
第1个延迟模块31，配置为接收参考时钟信号REF_CLK，对参考时钟信号REF_CLK进行延迟处理，输出参考延迟信号REF_CLK_2g，且参考时钟信号REF_CLK和参考延迟信号REF_CLK_2g之间的延迟为第一阈值；
第2个延迟模块32，配置为接收反馈时钟信号FB_CLK，对反馈时钟信号FB_CLK进行延迟处理，输出反馈延迟信号FB_CLK_2g，且反馈时钟信号FB_CLK和反馈延迟信号FB_CLK_2g之间的延迟为第一阈值；
第1个电平比较器33，配置为接收参考时钟信号REF_CLK和反馈延迟信号FB_CLK_2g，对参考时钟信号REF_CLK的上升沿和反馈延迟信号FB_CLK_2g的上升沿进行比较，输出第一结果信号PD_OUT1；其中，若参考时钟信号REF_CLK超前于反馈延迟信号FB_CLK_2g，则第一结果信号PD_OUT1为第三状态；若参考时钟信号REF_CLK滞后于反馈延迟信号FB_CLK_2g，则第一结果信号PD_OUT1为第四状态；
第2个电平比较器34，配置为接收反馈时钟信号FB_CLK和参考延迟信号REF_CLK_2g，对参考延迟信号REF_CLK_2g的上升沿和反馈时钟信号FB_CLK的上升沿进行比较，输出第二结果信号PD_OUT2；其中，若反馈时钟信号FB_CLK超前于参考延迟信号REF_CLK_2g则第二结果信号PD_OUT2为第三状态；若反馈时钟信号FB_CLK滞后于参考延迟信号REF_CLK_2g，则第二结果信号PD_OUT2为第四状态；
运算器35，配置为接收第一结果信号PD_OUT1和第二结果信号PD_OUT2，对第一结果信号PD_OUT1和第二结果信号PD_OUT2进行逻辑运算，输出比较信号DL_PDT。
需要说明的是，第三状态和第四状态不同，具体可以根据实际应用场景进行设定。本公开实施例后续以第三状态为高电平状态，第四状态为低电平状态为例进行说明，其他情况可 进行相应理解。
还需要说明的是，根据行业常见情况，粗调控制码的延迟调整粒度为2个与非门的延迟值，即第一阈值可以取2个与非门的延迟值，表示为2g。
参见图7，其示出了比较模块221的信号时序示意图。结合图7，分为三种情况进行说明：
情况一：参考时钟信号REF_CLK滞后于反馈时钟信号FB_CLK，且相位差大于等于第一阈值2g。此时，参考时钟信号REF_CLK滞后于反馈延迟信号FB_CLK_2g，反馈时钟信号FB_CLK超前于参考延迟信号REF_CLK_2g，如图7中的(a)所示，此时第一结果信号PD_OUT1为低电平状态，第二结果信号PD_OUT1为高电平状态。
情况二(该种情况图7未示出)：参考时钟信号REF_CLK超前于反馈时钟信号FB_CLK，且相位差大于等于第一阈值2g。此时，参考时钟信号REF_CLK超前于反馈延迟信号FB_CLK_2g，反馈时钟信号FB_CLK滞后于参考延迟信号REF_CLK_2g，此时第一结果信号PD_OUT1为高电平状态，第二结果信号PD_OUT1为低电平状态。
情况三：参考时钟信号REF_CLK和反馈时钟信号FB_CLK的相位差小于第一阈值2g，那么参考时钟信号REF_CLK超前于反馈延迟信号FB_CLK_2g，且反馈时钟信号FB_CLK超前于参考延迟信号REF_CLK_2g。第一结果信号PD_OUT1和第二结果信号PD_OUT2均为高电平状态。
这样，如果上述相位差大于等于第一阈值2g，第一结果信号PD_OUT1和第二结果信号PD_OUT2中存在低电平；如果上述相位差小于第一阈值2g，第一结果信号PD_OUT1和第二结果信号PD_OUT2均变化为高电平。
相应的，如图6所示，运算器35包括第二与门351和第二非门352，第二与门351的第一输入端接收第一结果信号PD_OUT1，第二与门351的第二输入端第二结果信号PD_OUT2，第二与门351的输出端和第二非门352的输入端连接，第二非门352用于输出比较信号DL_PDT。
这样，如图7中的(a)所示，如果上述相位差大于等于第一阈值2g，比较信号DL_PDT处于第一状态(高电平)；如图7中的(b)所示，如果上述相位差小于第一阈值2g，比较信号DL_PDT处于第二状态(低电平)。特别地，在图7中，OUT指示第二与门351的输出。
以下对比较模块221中的延迟模块和电平比较器进行具体说明。
需要说明的是，延迟模块的结构也是粗调延迟线中的最小结构单元。示例性的，如图8所示，延迟模块包括第一与非门311和第二与非门312；其中，第一与非门311的第一输入端形成延迟模块的输入端，第二与非门312的第一输入端与第一与非门311的输出端连接，第一与非门311的第二输入端、第二与非门312的第二输入端均接收第一电源信号VDD，第二与非门312的输出端形成延迟模块的输出端。
需要说明的是，结合图6和图8可以看出，对于第1个延迟模块31，其输入端接收参考时钟信号REF_CLK，其输出端输出参考延迟信号REF_CLK_2g。对于第2个延迟模块32，其输入端接收反馈时钟信号FB_CLK，其输出端输出反馈延迟信号FB_CLK_2g。
在一种实施例中，如图9所示，电平比较器包括比较单元41、锁存单元43和第一非门45；其中，
比较单元41包括第一输出端和第二输出端，配置为接收第一输入信号XCLK和第二输入信号CLK，在第一输入信号XCLK为高电平状态的情况下，对第一输入信号XCLK和第二输入信号CLK进行电平比较，并根据比较结果对第一输出端和第二输出端进行充放电处理，以比较第一输入信号XCLK的上升沿和第二输入信号CLK的上升沿；
锁存单元43包括第一输入端、第二输入端和输出端，锁存单元43的第一输入端与比较单元41的第一输出端连接，锁存单元43的第二输入端与比较单元41的第二输出端连接，比较单元41的输出端与第一非门45的输入端连接。
需要说明的是，对于第1个电平比较器，第一输入信号XCLK是指参考时钟信号 REF_CLK，第二输入信号CLK是指反馈延迟信号FB_CLK_2g，第一非门45的输出端用于输出第一结果信号PD_OUT1；对于第2个电平比较器，第一输入信号XCLK是指反馈时钟信号FB_CLK，第二输入信号CLK是指参考延迟信号REF_CLK_2g，第一非门45的输出端用于输出第二结果信号PD_OUT2。
需要说明的是，仅在第一输入信号XCLK为高电平状态的情况下，比较单元41才能够对第一输入信号XCLK和第二输出信号进行比较。
还需要说明的是，锁存单元43可以是由2个与非门构成的SR锁存器(如图9所示)，或者，锁存单元43还可以是由2个或非门构成的SR锁存器。
以下提供比较单元41的一种可行结构。
如图9所示，比较单元41包括交叉耦合组件、预充组件、输入组件、控制组件和均衡组件；其中，交叉耦合组件包括第一开关管401、第二开关管402、第三开关管403、第四开关管404；第一开关管401的控制端、第二开关管402的控制端、第三开关管403的第二端、第四开关管404的第一端与第一输出端连接，第三开关管403的控制端、第四开关管404的控制端、第一开关管401的第二端、第二开关管402的第一端与第二输出端连接，第一开关管401的第一端接收第二电源信号，第三开关管403的第一端接收第三电源信号；预充组件包括第五开关管405、第六开关管406和第七开关管407；第五开关管405的控制端、第六开关管406的控制端和第七开关管407的控制端均接收第一输入信号XCLK，第五开关管405的第一端接收第四电源信号，第六开关管406的第一端接收第五电源信号，第五开关管405的第二端、第七开关管407的第一端与第一输出端连接，第六开关管406的第二端、第七开关管407的第二端与第二输出端连接；输入组件包括第八开关管408和第九开关管409，第八开关管408的控制端接收第一输入信号XCLK，第九开关管409的控制端接收第二输入信号CLK，第八开关管408的第一端与第二开关管402的第二端连接，第九开关管409的第一端与第四开关管404的第二端连接；控制组件包括第十开关管410，第十开关管410的控制端接收第一输入信号，第十开关管410的第一端与第八开关管408的第二端、第九开关管409的第二端连接，第十开关管410的第二端与地信号连接；均衡组件包括第十一开关管411，第十一开关管411的控制端接收第一输入信号XCLK，第十一开关管411的第一端与第四开关管404的第二端连接，第十一开关管411的第二端与第二开关管402的第二端连接。在这里，上述的第一电源信号～第五电源信号可以为同一个信号。
需要说明的是，第一开关管401、第三开关管403、第五开关管405、第六开关管406、第七开关管407和第十一开关管411均为P型场效应管，第二开关管402、第四开关管404、第八开关管408、第九开关管409、第十开关管410均为N型场效应管。其他情况可进行适应性理解。
需要说明的是，如果第一输入信号XCLK为低电平状态，此时第十开关管410不导通，所以比较单元41整体是不导通的，第一输出端和第二输出端被预充组件充电至高电平，并不能反映输入信号的电平比较结果；反之，仅在第一输入信号XCLK为高电平状态时，第一输出端和第二输出端才会反映输入信号的电平比较结果，即比较单元41才能够执行信号比较功能。
相应的，如图9所示，锁存单元43包括第三与非门431和第四与非门432；其中，第三与非门431的第一输入端构成锁存单元43的第一输入端，第三与非门431的第二输入端和第四与非门432的输出端连接，第三与非门431的第三输入端接收复位信号LRSTB；第四与非门432的第一输入端构成锁存单元43的第二输入端，第四与非门432的第二输入端和第三与非门431的输出端连接。
需要说明的是，在第一输入端和第二输入端均为高电平时，输出端将保持之前的电平状态不变；在第一输入端为高电平，第二输入端为低电平时，输出端为低电平；在第一输入端为低电平，第二输入端为高电平时，输出端为高电平；在第一输入端为低电平，第二输入端为低电平的时候，输出端的状态不定，原则上不出现这种情况。
另外，复位信号LRSTB用于对锁存单元43进行复位。具体的，若复位信号LRSTB为低电平，则第三与非门431的输出端为高电平，即锁存单元43被复位为高电平。
以下对电平比较器的工作原理进行说明。为了方便，将锁存单元43的输出信号称为中间信号，将第一非门45的输出信号称为结果信号PD_OUT。由于复位信号LRSTB的作用，中间信号初始为高电平，结果信号PD_OUT初始为低电平。
首先，在第一输入信号XCLK为低电平时，预充组件和均衡组件导通，但是控制组件不导通，即比较单元并未进入比较状态，第一输出端和第二输出端的电位均被预充组件拉至高电平。
其次，需要分情况说明：(1)如图10的(a)所示，在第一输入信号XCLK的上升沿滞后于第二输入信号CLK的情况下，在第一输入信号XCLK的上升沿后，第十开关管410导通使比较单元41进入比较状态，交叉耦合组件、第八开关管408、第九开关管409和第十开关管410均导通，第一输出端和第二输出端处于相同的电平状态，此时交叉耦合组件无法进行差异放大，锁存单元43始终为信号保持状态，从而中间信号为高电平，比较信号DL_PDT为低电平。另外，在第二输入信号CLK的下降沿之后，由于第九开关管409的关闭，第一输出端和第二输出端可能会产生电位差异，但很快第一输入信号XCLK的下降沿也会来临，这导致第五开关管405、第六开关管406、第七开关管407和第十一开关管411均导通，第一输出端和第二输出端的电位差还未进行足够放大就已经被充电为高电平状态，因此不会导致中间信号和结果信号PD_OUT的翻转。(2)如图10的(b)所示，在第一输入信号XCLK的上升沿超前于第二输入信号CLK的情况下，在第一输入信号XCLK的上升沿后，第十开关管410导通使比较单元进入工作状态，交叉耦合组件、第八开关管408和第十开关管410导通，此时第九开关管409还未导通，第二输出端的电位逐渐低于第一输出端的电位，在交叉耦合组件的差异放大后，第一输出端输出高电平信号，第二输出端输出低电平信号，从而中间信号变为低电平，结果信号PD_OUT变为高电平。
这样，如图7中的(a)所示，如果参考时钟信号REF_CLK与反馈时钟信号FB_CLK之间的相位差大于等于第一阈值2g，那么第一结果信号PD_OUT1和第二结果信号PD_OUT2中必定存在一个为低电平状态，比较结果信号DL_PDT为高电平。如果上述相位差小于第一阈值2g，那么第一结果信号PD_OUT1和第二结果信号PD_OUT2均变为高电平状态，比较结果信号DL_PDT变为低电平。
还需要说明的是，如图9所示，在比较单元41和锁存单元43的连接路径上可以设置偶数个反相器，以实现信号之间的延迟匹配和驱动增强。
从以上可以看出，本公开实施例提供了一种延迟锁相环，在参考时钟信号和反馈时钟信号的相位差较小时，时间数字转换器无需工作，能够改善误码问题，加快延迟锁相环的锁定速度，提高延迟锁相环的性能。
在一些实施例中，第一延迟线111包括粗调延迟线；其中，
第一延迟线111，还配置为通过粗调控制码调整粗调延迟线的工作状态，以实现延迟参数的调整。其中，粗调延迟线包括n+1个串联的第一延迟单元，第一延迟单元的延迟是第一阈值，也是前述的延迟模块的延迟值。
粗调控制码包括n+1位子信号，可以表示为Q<n:1>；第i个第一延迟单元接收粗调控制码的第i位子信号Q<i-1>。
需要说明的是，根据粗调控制码的具体取值，可以控制粗调延迟线的输出信号从特定位置处的第一延迟单元后输出，从而控制粗调延迟线的延迟参数。例如，如果粗调控制码Q<n:1>＝111000……0，那么粗调延迟线的输出信号是从第3个第一延迟单元后进行输出的，即粗调延迟线能够提供3×(第一阈值2g)的延迟；如果粗调控制码Q<n:1>＝1111100……0，那么粗调延迟线的输出信号是从第5个第一延迟单元后进行输出的，即粗调延迟线能够提供5×(第一阈值2g)的延迟。
相应的，如图11所示，转换模块122包括n+1个串联的第二延迟单元51和n+1个第七 触发器52；其中，第1个第二延迟单元51的输入端接收工作指示信号，第i个第二延迟单元51的输出端与第i+1个第二延迟单元51的输入端连接；第i个第七触发器52的输入端与第i个第二延迟单元51的输出端连接，第i个第七触发器52的时钟端接收工作指示信号的反相信号，第i个第七触发器52的正相输出端输出粗调控制码的第i位子信号；第二延迟单元51的延迟是第一阈值。
需要说明的是，参见图12，其示出了转换模块122的信号时序示意图。在图12中，D00是指第1个第七触发器52的输入信号，D01是指第2个第七触发器52的输入信号……D0n是指第n+1个第七触发器52的输入信号。这样，在工作指示信号的下降沿(即工作指示信号的反相信号的上升沿)对D00、D01、D02、D03、D04、D05……D0n进行采样，依次得到Q0(高电平)、Q1(高电平)、Q2(高电平)、Q3(高电平)、Q4(低电平)、Q5(低电平)……Qn(低电平)，Q0、Q1、Q2、Q3、Q4、Q5……Qn共同组成粗调控制码Q<n:1>。
这样，通过n+1个串联的第二延迟单元51可以模拟粗调延迟线的处理过程，通过n+1个第七触发器52采样每一第二延迟单元51的输出信号，从而获得粗调控制码。
综上所述，对于延迟锁相环来说，时间数字转换器利用参考时钟信号和反馈时钟信号之间的相位差产生数字码(用于作为粗调控制码的初始值)，这种数字码是通过触发器产生的。然而，如果参考时钟信号和反馈时钟信号之间的相位差较小，相位脉冲信号的脉冲过窄，此时时间数字转换器会出现误码问题，进而导致粗调延迟线(CDL)锁定错误，为调整过程带来沉重负担，反而延长了延迟锁相环的锁定过程。在本公开实施例中，通过检测模块来检测参考时钟信号和反馈时钟信号之间的相位差，在相位差较小时控制时间数字转换器不进行转码处理，避免延迟锁相环的锁定时间意外增加。
在本公开的另一实施例中，参见图13，其示出了本公开实施例提供的一种存储器50组成结构示意图。如图13所示，存储器50至少包括前述的延迟锁相环10。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种延迟锁相环，所述延迟锁相环包括第一信号路径(11)和时间数字转换器(12)，所述时间数字转换器(12)包括检测模块(121)和逻辑模块(122)；其中，
    所述第一信号路径(11)，包括第一延迟线(111)，配置为接收参考时钟信号，输出反馈时钟信号；其中，所述第一延迟线(111)的延迟参数受到粗调控制码的控制；
    所述检测模块(121)，配置为接收所述参考时钟信号和所述反馈时钟信号；基于所述参考时钟信号和所述反馈时钟信号之间的相位差，输出工作指示信号；其中，在所述相位差大于等于第一阈值的情况下，所述工作指示信号产生一个脉冲，且脉冲宽度指示所述相位差的大小；在所述相位差小于所述第一阈值的情况下，所述工作指示信号的电平状态保持不变；
    所述逻辑模块(122)，配置为接收所述工作指示信号，对所述工作指示信号的脉冲宽度进行转换，输出所述粗调控制码的初始值。
  2. 根据权利要求1所述的延迟锁相环，其中，所述检测模块(121)包括：
    脉冲产生模块(21)，配置为接收所述参考时钟信号和所述反馈时钟信号，输出相位脉冲信号；其中，所述相位脉冲信号存在一个脉冲，且脉冲宽度指示所述参考时钟信号和所述反馈时钟信号之间的相位差；
    控制模块(22)，配置为接收所述相位脉冲信号、所述参考时钟信号和所述反馈时钟信号；在所述参考时钟信号和所述反馈时钟信号的相位差大于等于所述第一阈值的情况下，对所述相位脉冲信号进行传输处理，输出所述工作指示信号；在所述相位差小于所述第一阈值的情况下，对所述相位脉冲信号进行屏蔽处理，以使得所述工作指示信号的电平状态保持不变。
  3. 根据权利要求2所述的延迟锁相环，其中，所述控制模块(22)包括：
    比较模块(221)，配置为接收所述参考时钟信号和所述反馈时钟信号，基于所述参考时钟信号和所述反馈时钟信号的相位差，输出比较信号；其中，若所述相位差大于等于所述第一阈值，则所述比较信号为第一状态；若所述相位差小于第一阈值，则所述比较信号为第二状态；
    逻辑模块(222)，配置为接收所述比较信号和所述相位脉冲信号，对所述比较信号和所述相位脉冲信号进行逻辑运算，输出所述工作指示信号。
  4. 根据权利要求3所述的延迟锁相环，其中，所述第一状态为高电平状态，所述第二状态为低电平状态；
    所述逻辑模块(222)包括第一与门，所述第一与门的第一输入端接收所述比较信号，所述第一与门的第二输入端接收所述相位脉冲信号，所述第一与门的输出端输出所述工作指示信号。
  5. 根据权利要求3或4所述的延迟锁相环，其中，所述比较模块(221)包括2个延迟模块(31/32)、2个电平比较器(31/34)和运算器(35)；
    第1个所述延迟模块(31)，配置为接收所述参考时钟信号，对所述参考时 钟信号进行延迟处理，输出参考延迟信号，且所述参考时钟信号和所述参考延迟信号之间的延迟为所述第一阈值；
    第2个所述延迟模块(32)，配置为接收所述反馈时钟信号，对所述反馈时钟信号进行延迟处理，输出反馈延迟信号，且所述反馈时钟信号和所述反馈延迟信号之间的延迟为所述第一阈值；
    第1个所述电平比较器(33)，配置为接收所述参考时钟信号和所述反馈延迟信号，对所述参考时钟信号的上升沿和所述反馈延迟信号的上升沿进行比较，输出第一结果信号；其中，若所述参考时钟信号超前于所述反馈延迟信号，则所述第一结果信号为第三状态；若所述参考时钟信号滞后于所述反馈延迟信号，则所述第一结果信号为第四状态；
    第2个所述电平比较器(34)，配置为接收所述反馈时钟信号和所述参考延迟信号，对所述参考延迟信号的上升沿和所述反馈时钟信号的上升沿进行比较，输出第二结果信号；其中，若所述反馈时钟信号超前于所述参考延迟信号则所述第二结果信号为第三状态；若反馈时钟信号滞后于所述参考延迟信号，则所述第二结果信号为第四状态；
    运算器(35)，配置为接收所述第一结果信号和所述第二结果信号，对所述第一结果信号和所述第二结果信号进行逻辑运算，输出所述比较信号。
  6. 根据权利要求5所述的延迟锁相环，其中，所述延迟模块(31/32)包括第一与非门(311)和第二与非门(312)；
    所述第一与非门(311)的第一输入端形成所述延迟模块的输入端，所述第二与非门(312)的第一输入端与所述第一与非门(311)的输出端连接，所述第一与非门(311)的第二输入端、所述第二与非门(312)的第二输入端均接收第一电源信号，所述第二与非门(312)的输出端形成所述延迟模块的输出端。
  7. 根据权利要求5或6所述的延迟锁相环，其中，所述电平比较器(33/34)包括比较单元(41)、锁存单元(43)和第一非门(45)；
    所述比较单元(41)包括第一输出端和第二输出端，配置为接收第一输入信号和第二输入信号；在所述第一输入信号为高电平状态的情况下，对所述第一输入信号和所述第二输入信号进行电平比较，并根据比较结果对第一输出端和第二输出端进行充放电处理，以比较所述第一输入信号的上升沿和所述第二输入信号的上升沿；
    所述锁存单元(43)包括第一输入端、第二输入端和输出端，所述锁存单元(43)的第一输入端与所述比较单元(41)的第一输出端连接，所述锁存单元(43)的第二输入端与所述比较单元(41)的第二输出端连接，所述比较单元(41)的输出端与第一非门(45)的输入端连接；
    其中，对于第1个所述电平比较器(33)，第一输入信号是指所述参考时钟信号，所述第二输入信号是指所述反馈延迟信号，所述第一非门(45)的输出端用于输出所述第一结果信号；对于第2个所述电平比较器(34)，所述第一输入信号是指反馈时钟信号，所述第二输入信号是指参考延迟信号，所述第一非门(45)的输出端用于输出所述第二结果信号。
  8. 根据权利要求7所述的延迟锁相环，其中，所述比较单元(41)包括交 叉耦合组件、预充组件、输入组件、控制组件和均衡组件；
    交叉耦合组件包括第一开关管(401)、第二开关管(402)、第三开关管(403)、第四开关管(404)；所述第一开关管(401)的控制端、所述第二开关管(402)的控制端、所述第三开关管(403)的第二端、所述第四开关管(404)的第一端与所述第一输出端连接，所述第三开关管(403)的控制端、所述第四开关管(404)的控制端、所述第一开关管(401)的第二端、所述第二开关管(402)的第一端与所述第二输出端连接，所述第一开关管(401)的第一端接收第二电源信号，所述第三开关管(403)的第一端接收第三电源信号；
    所述预充组件包括第五开关管(405)、第六开关管(406)和第七开关管(407)；所述第五开关管(405)的控制端、所述第六开关管(406)的控制端和所述第七开关管(407)的控制端均接收所述第一输入信号，所述第五开关管(405)的第一端接收第四电源信号，所述第六开关管(406)的第一端接收第五电源信号，所述第五开关管(405)的第二端、所述第七开关管(407)的第一端与所述第一输出端连接，所述第六开关管(406)的第二端、所述第七开关管(407)的第二端与所述第二输出端连接；
    所述输入组件包括第八开关管(408)和第九开关管(409)，所述第八开关管(408)的控制端接收所述第一输入信号，所述第九开关管(409)的控制端接收所述第二输入信号，所述第八开关管(408)的第一端与所述第二开关管(402)的第二端连接，所述第九开关管(409)的第一端与所述第四开关管(404)的第二端连接；
    所述控制组件包括第十开关管(410)，所述第十开关管(410)的控制端接收所述第一输入信号，所述第十开关管(410)的第一端与所述第八开关管(408)的第二端、所述第九开关管(409)的第二端连接，所述第十开关管(410)的第二端与地信号连接；
    所述均衡组件包括第十一开关管(411)，所述第十一开关管(411)的控制端接收所述第一输入信号，所述第十一开关管(411)的第一端与所述第四开关管(404)的第二端连接，所述第十一开关管(411)的第二端与所述第二开关管(402)的第二端连接。
  9. 根据权利要求8所述的延迟锁相环，其中，所述第一开关管(401)、所述第三开关管(403)、所述第五开关管(405)、所述第六开关管(406)、所述第七开关管(407)和所述第十一开关管(411)均为P型场效应管，所述第二开关管(402)、所述第四开关管(404)、所述第八开关管(408)、所述第九开关管(409)和所述第十开关管(410)均为N型场效应管。
  10. 根据权利要求7、8或9任一项所述的延迟锁相环，其中，所述锁存单元(43)包括第三与非门(431)和第四与非门(432)；
    所述第三与非门(431)的第一输入端构成所述锁存单元(43)的第一输入端，所述第三与非门(431)的第二输入端和所述第四与非门(432)的输出端连接，所述第三与非门(431)的第三输入端接收复位信号；所述第四与非门(432)的第一输入端构成所述锁存单元(43)的第二输入端，所述第四与非门(432)的第二输入端和所述第三与非门(431)的输出端连接。
  11. 根据权利要求5-10任一项所述的延迟锁相环，其中，所述第三状态为高电平状态，所述第四状态为低电平状态；
    所述运算器(35)包括第二与门(351)和第二非门(352)，所述第二与门(351)的第一输入端接收所述第一结果信号，所述第二与门(351)的第二输入端所述第二结果信号，所述第二与门(351)的输出端和所述第二非门(352)的输入端连接，所述第二非门(352)用于输出所述比较信号。
  12. 根据权利要求2-11任一项所述的延迟锁相环，其中，所述脉冲产生模块(21)包括第一触发器(211)、第二触发器(212)、第三触发器(213)、第四触发器(214)、第五触发器(215)和第六触发器(216)、第三与门(217)；
    所述第一触发器(211)的时钟端、所述第二触发器(212)的时钟端和所述第三触发器(213)的时钟端均接收所述反馈时钟信号；所述第一触发器(211)的输入端接收锁相开启信号，所述第一触发器(211)的正相输出端与所述第二触发器(212)的输入端连接，所述第二触发器(212)的正相输出端与所述第三触发器(213)的输入端连接，所述第三触发器(213)的正相输出端和所述第三与门(217)的第一输入端连接；
    所述第四触发器(214)的时钟端、所述第五触发器(215)的时钟端和所述第六触发器(216)的时钟端均接收所述参考时钟信号；所述第四触发器(214)的输入端与所述第一触发器(211)的反相输出端连接，所述第四触发器(214)的正相输出端与所述第五触发器(215)的输入端连接，所述第五触发器(215)的正相输出端和所述第六触发器(216)的输入端连接；所述第六触发器(216)的正相输出端和所述第三与门(217)的第二输入端连接；
    所述第三与门(217)的输出端输出所述相位脉冲信号。
  13. 根据权利要求1-12任一项所述的延迟锁相环，其中，所述第一延迟线(111)包括粗调延迟线；
    所述第一延迟线(111)，还配置为通过所述粗调控制码调整所述粗调延迟线的工作状态，以实现延迟参数的调整；
    其中，所述粗调延迟线包括n+1个串联的第一延迟单元，所述第一延迟单元的延迟是所述第一阈值；所述粗调控制码包括n+1位子信号，第i个所述第一延迟单元接收所述粗调控制码的第i位子信号，n为自然数。
  14. 根据权利要求13所述的延迟锁相环，其中，所述逻辑模块(122)包括n+1个串联的第二延迟单元(51)和n+1个第七触发器(52)；
    第1个所述第二延迟单元(51)的输入端接收所述工作指示信号，第i个所述第二延迟单元(51)的输出端与第i+1个所述第二延迟单元(51)的输入端连接；第i个所述第七触发器(52)的输入端与第i个所述第二延迟单元(51)的输出端连接，第i个所述第七触发器(52)的时钟端接收所述工作指示信号的反相信号，第i个所述第七触发器(52)的正相输出端输出粗调控制码的第i位子信号；
    所述第二延迟单元(51)的延迟是所述第一阈值。
  15. 根据权利要求14所述的延迟锁相环，其中，所述延迟锁相环还包括时钟处理模块(13)和多个第二延迟线，所述时钟处理模块(13)与所述第一延 迟线(111)、多个所述第二延迟线均连接，所述第一延迟线(111)和所述第二延迟线的结构相同，所述第二延迟线的延迟参数受到所述粗调控制码的控制；
    所述时钟处理模块(13)，配置为接收初始时钟信号，基于所述初始时钟信号，输出多个分相时钟信号；其中，所述参考时钟信号是其中一个所述分相时钟信号；
    所述第二延迟线，配置为接收一个所述分相时钟信号，对所接收的分相时钟信号进行延迟传输及调整处理，输出一个目标时钟信号；其中，所述目标时钟信号经过传输后用于数据采样处理。
  16. 一种存储器，所述存储器包括如权利要求1-15任一项所述的延迟锁相环。
PCT/CN2023/081158 2022-10-21 2023-03-13 一种延迟锁相环和存储器 WO2024082527A1 (zh)

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