WO2024082074A1 - 一种微发光二极管及其显示装置 - Google Patents

一种微发光二极管及其显示装置 Download PDF

Info

Publication number
WO2024082074A1
WO2024082074A1 PCT/CN2022/110617 CN2022110617W WO2024082074A1 WO 2024082074 A1 WO2024082074 A1 WO 2024082074A1 CN 2022110617 W CN2022110617 W CN 2022110617W WO 2024082074 A1 WO2024082074 A1 WO 2024082074A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
metal
emitting diode
metal electrode
Prior art date
Application number
PCT/CN2022/110617
Other languages
English (en)
French (fr)
Inventor
叶雪萍
夏德玲
李佳恩
吴政
Original Assignee
泉州三安半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 泉州三安半导体科技有限公司 filed Critical 泉州三安半导体科技有限公司
Priority to PCT/CN2022/110617 priority Critical patent/WO2024082074A1/zh
Publication of WO2024082074A1 publication Critical patent/WO2024082074A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present invention belongs to the field of semiconductor manufacturing, and in particular relates to a micro light emitting diode and a display device.
  • Micro LED is a next-generation display light source that is currently being hotly researched. It has the advantages of low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, low energy consumption, and long life. In addition, its power consumption is about 10% of LCD and 50% of OLED. Compared with OLED, which is also self-luminous, the brightness is many times higher, and the resolution can reach a high pixel density. These obvious advantages of mLED make it likely to replace the current OLED and LCD and become the light source for the next generation of displays. mLED cannot be mass-produced at present because there are still many technical difficulties to be overcome. One of the important technical difficulties is how to improve the transfer yield. The present invention proposes a feasible solution to this problem, through which the transfer of mLED with a high yield can be achieved.
  • micro-LED substrate needs to be peeled off and relies on the semiconductor material support of the semiconductor layer sequence, after the semiconductor layer sequence is further thinned or removed, it is difficult to complete large-scale transfer through conventional structures and maintain a high transfer yield due to its fragility.
  • the present invention provides a micro light emitting diode, which has a semiconductor layer sequence, wherein the semiconductor layer sequence includes a front side and a back side which are arranged opposite to each other, wherein the semiconductor layer sequence includes: a first type semiconductor layer, a second type semiconductor layer and an active layer therebetween, wherein the back side of the semiconductor layer sequence has a groove, wherein the groove penetrates the second type semiconductor layer and the active layer to expose the first type semiconductor layer, and in order to ensure that the first type semiconductor layer is exposed, a portion of the first type semiconductor layer is usually removed;
  • a first metal electrode and a second metal electrode are arranged on the back side of the semiconductor layer sequence.
  • the back side of the semiconductor layer sequence includes a first mesa in the groove, a second mesa and a groove therebetween. Sidewall,
  • the first metal electrode is disposed on the first table surface, and the second metal electrode is disposed on the second table surface.
  • the first metal electrode is electrically connected to the first type semiconductor layer
  • the second metal electrode is electrically connected to the second type semiconductor layer
  • the first type semiconductor layer is a support layer. When viewed from above, the support layer is rectangular.
  • the distance from at least part of the groove to the front side of the semiconductor layer sequence is no more than 4 microns, that is, the thickness of the first type semiconductor layer in the groove is no more than 4 microns, for example, the distance is 1 micron to 4 microns.
  • the semiconductor layer sequence is at least partially penetrated by the groove
  • the first metal electrode extends along the long side direction of the support layer, and the extension covers from the side wall of the groove to the second table surface, so as to reinforce the stress concentration area where the thickness of the semiconductor layer sequence changes significantly.
  • a dielectric passivation layer is arranged between the first metal electrode and the first mesa, and between the first metal electrode and the side wall of the groove.
  • the coverage width of the first metal electrode on the second mesa exceeds 20% of the length of the short side, thereby ensuring sufficient holding force.
  • the ratio of the long side to the short side of the support layer is 1.5 to 5, and the support layer matches this narrow and long design to provide a holding force.
  • the support layer matches this narrow and long design to provide a holding force.
  • the manufacturing process includes a substrate stripping process, the front side of the semiconductor layer sequence is exposed, there is no supporting substrate, and the front side of the semiconductor layer sequence is a first type semiconductor layer or an undoped semiconductor layer, and the front side of the semiconductor layer sequence is at least partially removed.
  • the front side of the semiconductor layer sequence has a patterned or roughened surface.
  • the above-mentioned removal may bring about an improvement in optical performance, such as control of light type, but may cause some damage or hidden dangers to the front side of the first type semiconductor layer, that is, the supporting layer.
  • the front side of the semiconductor layer sequence is covered with an insulating protective layer, and the front side of the insulating protective layer is exposed.
  • the thickness of the insulating protective layer is 2000 angstroms to 10000 angstroms, which assists in supporting the patterned or roughened surface and provides holding force on the front side.
  • the material of the insulating protection layer includes: silicon dioxide, silicon nitride, titanium oxide or aluminum oxide.
  • the micro light emitting diode described in the present invention refers to a light emitting diode chip with a size of less than 100 ⁇ m ⁇ 150 ⁇ m after production or the support substrate is removed.
  • the first metal electrode includes multiple layers of metal, the first metal layer of the first metal electrode is in contact with the back side, the deformation modulus of the first metal layer is not less than 100 GPa, and the thickness of the first metal layer is 30 angstroms to 1000 angstroms.
  • the high deformation modulus of the first metal layer is utilized to ensure that the semiconductor layer sequence is prevented from being cut off when subjected to shear force and torque.
  • the first metal layer includes ruthenium, rhodium or chromium.
  • the first metal electrode includes multiple layers of metal, the first metal layer of the first metal electrode contacts the back side of the light-emitting diode, the deformation modulus of the first metal layer is not less than 100 GPa, the thickness of the first metal layer is 10 angstroms to 30 angstroms, and the front side of the semiconductor layer sequence is covered with an insulating protective layer, the thickness of the insulating protective layer is 2000 angstroms to 5000 angstroms, and through the combined reinforcement design, the thickness of the first metal layer is reduced, thereby reducing the absorption of radiation by the first metal.
  • the first metal electrode includes a first metal layer, a second metal layer and a third metal layer in sequence
  • the second metal layer is in direct contact with the first metal layer and the third metal layer respectively
  • the deformation modulus of the first metal layer and the third metal layer is greater than that of the second metal layer
  • the deformation modulus of the first metal layer and the third metal layer is not less than 100 GPa
  • the sum of the thickness of the first metal layer and the third metal layer is 30 angstroms to 1000 angstroms
  • the first metal layer and the third metal layer jointly provide a holding force.
  • the third metal layer is ruthenium, rhodium or chromium.
  • the second metal layer is a metal reflective layer
  • the material of the second metal layer is aluminum or silver, which not only ensures the reliability of the product but also improves the brightness of the product.
  • the above-mentioned soft metal is used as the metal reflective layer, and the thickness of the second metal layer is 10 angstroms to 2000 angstroms.
  • the thickness of the second metal reflective layer is limited. If the thickness of the soft metal exceeds 2000 angstroms, the reliability of the device may be reduced. Because the second metal layer has reflective property requirements, a thickness less than 10 angstroms is difficult to provide effective reflection contribution.
  • the present invention is preferably applicable to a chip structure in which the groove area is 25% to 60% of the area of the first type semiconductor layer on the top projection plane. If it is less than 25%, there is basically no problem of support layer breakage during the transfer process due to the relatively small torque. If it exceeds 60%, the loss of light-emitting area is too large.
  • the first metal electrode comprises a plurality of metal layers, wherein the The total thickness of the metal layer with a variable modulus of not less than 100 GPa is 30 angstroms to 1000 angstroms, providing sufficient supporting force for the first metal electrode.
  • the material of the semiconductor layer sequence is a gallium nitride series or an aluminum gallium indium phosphide series, and the thickness of the first type semiconductor layer in the groove is not greater than 4 microns.
  • the difference in size between the first metal electrode area on the second table and the second metal electrode area on the second table is no more than 30%, thereby improving the stability of the bonding force during package bonding, reducing the shear torque, and improving the transfer yield.
  • the present invention also provides a micro light emitting diode, comprising a semiconductor layer sequence, the semiconductor layer sequence comprising a front side and a back side arranged opposite to each other, the semiconductor layer sequence comprising: a first type semiconductor layer, a second type semiconductor layer and an active layer therebetween, the back side of the semiconductor layer sequence having a groove,
  • a first metal electrode and a second metal electrode are arranged on the back side of the semiconductor layer sequence.
  • the back side of the semiconductor layer sequence includes a first mesa in the groove, a second mesa and a groove sidewall located therebetween, the groove penetrates the second mesa to the first type semiconductor layer, and a portion of the second type semiconductor layer is removed;
  • the first metal electrode is disposed on the first table surface, and the second metal electrode is disposed on the second table surface.
  • the first metal electrode is electrically connected to the first type semiconductor layer
  • the second metal electrode is electrically connected to the second type semiconductor layer
  • the first type semiconductor layer is a support layer. When viewed from above, the support layer is rectangular.
  • the distance from at least part of the groove to the front side of the semiconductor layer sequence is no more than 4 microns, that is, the thickness of the first type semiconductor layer in the groove is no more than 4 microns, for example, the distance is 1 micron to 4 microns.
  • the area of the groove is 25% to 60% of the area of the first type semiconductor layer.
  • the first metal electrode extends along the long side direction of the support layer, and the extension covers from the side wall of the groove to the second table surface, so as to reinforce the stress concentration area where the thickness of the semiconductor layer sequence changes significantly.
  • a dielectric passivation layer is arranged between the first metal electrode and the first mesa, and between the first metal electrode and the side wall of the groove.
  • a display device comprises a substrate and any one of the above-mentioned micro-light emitting diodes.
  • the beneficial effects of the present invention include, but are not limited to, improving the reliability of micro-LEDs, reducing or avoiding the cutting of the support layer, and improving the overall yield of the product.
  • Figures 1 and 2 are schematic diagrams of the structure of the existing transfer process
  • 3 and 4 are respectively a cross-sectional structural schematic diagram and a three-dimensional structural schematic diagram of the first embodiment of the present invention
  • FIG5 is a cross-sectional view of a second embodiment of the present invention.
  • FIG6 is a schematic cross-sectional view of a third embodiment of the present invention and an enlarged schematic view of a first metal electrode
  • FIG7 is a schematic cross-sectional view of the first metal electrode stack according to the fourth embodiment of the present invention.
  • FIG8 is a schematic cross-sectional view of the first metal electrode stack according to the fifth embodiment of the present invention.
  • FIGS. 9 and 10 are schematic cross-sectional views of a sixth embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional view of the seventh embodiment of the present invention.
  • 100 micro-light-emitting diode
  • 110 semiconductor layer sequence
  • 111 first type semiconductor layer
  • 113 active layer
  • 120 supporting layer
  • 200 imprinting
  • 310 first metal electrode; 311, first metal layer; 312, second metal layer; 313, third metal layer; 314, fourth metal layer; 331, platinum layer; 332, bonding metal layer
  • 320 second metal electrode
  • 400 dielectric passivation layer
  • 500 insulating protection layer
  • PD horizontal projection plane of long side.
  • the size of the micro-LED 100 is within 100 ⁇ m ⁇ 150 ⁇ m.
  • Ultra-thin and/or small devices need to be picked up and placed through lamination and stamping.
  • the design of the present invention allows the selection and application of these ultra-thin, fragile and/or small devices without causing damage to the chip itself.
  • micro-transfer printing allows arrays of micro-scale, high-performance devices to be definitively assembled and integrated on non-native substrates.
  • micro-transfer printing is similar to using a rubber stamp to transfer fluid-based ink from an ink pad to paper.
  • the "ink” is composed of high-performance solid-state semiconductor devices and the "paper” can be a substrate containing circuit boards, films, plastics, or other semiconductors.
  • the micro-transfer printing process utilizes a designed elastomeric stamp 200 coupled to a high-precision controlled motion print head to selectively pick up and print large arrays of micro-scale devices on a non-native destination substrate.
  • the micro-LED 100 is prone to fracture C1 at the side wall S1 of the first groove and the first table M1.
  • a micro-light-emitting diode is provided in the first embodiment of the present invention, including a semiconductor layer sequence 110, wherein the semiconductor layer sequence 110 includes a front side and a back side that are arranged oppositely, that is, the upper surface of the semiconductor layer sequence 110 away from the first metal electrode 310 and the second metal electrode 320 is the front side, and the lower surface of the semiconductor layer sequence 110 close to the first metal electrode 310 and the second metal electrode 320 is the back side.
  • the semiconductor layer sequence 110 includes: a first-type semiconductor layer 111, a second-type semiconductor layer 112, and an active layer 113 therebetween.
  • the material of the semiconductor layer sequence 110 is a gallium nitride series or an aluminum gallium indium phosphide series.
  • the semiconductor layer sequence 110 generates electrons generated by the first-type semiconductor layer 111 and holes generated by the second-type semiconductor layer 112, and then recombines and excites light. After the substrate removal process, the front side of the semiconductor layer sequence 110 is exposed.
  • the back side of the semiconductor layer sequence 110 has a first groove G1 of a Mesa table.
  • the first groove G1 is used to set a current injection window to the first type semiconductor layer 111.
  • the first groove G1 sequentially penetrates the second type semiconductor layer 112, the active layer 113 and part of the first type semiconductor layer 111, and exposes the first type semiconductor layer 111. Since the first type semiconductor layer 111 has a large thickness, a part of the first type semiconductor layer 111 can be used as a support layer 120.
  • the semiconductor layer sequence 110 is at least partially penetrated by the first groove G1. It is particularly suitable for the horizontal projection plane PD1 of the long side L1.
  • the length D1 of the penetration area of the semiconductor layer sequence 110 is 25% to 60% of the length of the long side L1. Since a large range of the semiconductor layer sequence 110 is removed in the lateral direction, it is more suitable for the design of the first metal electrode 310 of this embodiment.
  • a first metal electrode 310 and a second metal electrode 320 are arranged on the back side of the semiconductor layer sequence 110, and the first metal electrode 310 and the second metal electrode 320 are used to connect to an external circuit.
  • the back side of the semiconductor layer sequence 110 includes a first table M1, a first table M1 in a first groove G1, and a first groove sidewall S1 located therebetween, wherein the first metal electrode 310 is arranged on the first table M1, and the first table M1 is located on the bottom surface of the first groove G1, and the second metal electrode 320 is arranged on the second table M2, the first metal electrode 310 is directly connected to the first type semiconductor layer 111, and the second metal electrode 320 is electrically connected to the second type semiconductor layer 112, for example, the second metal electrode 320 is connected to the second type semiconductor layer 112 through a transparent current spreading layer (not indicated in the figure in this embodiment).
  • the first type semiconductor layer 111 is a support layer 120, which provides support for the semiconductor layer sequence 110. From the top projection direction, the support layer 120 is generally rectangular, and the length ratio of the long side L1 to the short side of the support layer 120 is 1.5 to 5. In the vertical direction, the distance from at least part of the first groove G1 to the front side of the semiconductor layer sequence 110 is not greater than 4 microns, that is, the thickness of the first type semiconductor layer 111 in at least part of the first groove G1 is not greater than 4 microns, for example, the thickness of the first type semiconductor layer 111 in at least part of the first groove G1 is 1 micron to 4 microns. In the top projection plane, the area of the first groove G1 is 25% to 60% of the area of the first type semiconductor layer 111, and the area here refers to the area of the first groove G1 area alone, excluding the boundary area of the second mesa M2.
  • the first metal electrode 310 extends along the long side L1 of the support layer 120, and the extension covers the first groove sidewall S1 to the second table M2.
  • the first metal electrode 310 includes multiple metal layers, wherein the total thickness of the metal layer with a deformation modulus of not less than 100 GPa is 30 angstroms to 1000 angstroms.
  • the first metal electrode 310 and the second mesa M2 are connected to each other, and the first metal electrode 310 and the first groove sidewall S 1, a dielectric passivation layer 400 is arranged between the first metal electrode 310 and the second table M2, and the dielectric passivation layer 400 is used to electrically isolate the first metal electrode 310 and the second table M2.
  • the material of the dielectric passivation layer 400 includes silicon oxide, silicon nitride or a distributed Bragg reflector DBR. As an example, if the material of the dielectric passivation layer 400 is silicon dioxide, the thickness of the dielectric passivation layer 400 is 1000 angstroms to 10000 angstroms.
  • the first metal electrode 310 and the second table M2 are connected. From the short side projection surface, the coverage width D2 of the first metal electrode 310 on the second table M2 exceeds 20% of the length of the short side L2, for example, the coverage width D2 is 20% to 90% of the length of the short side L2.
  • the first metal electrode 310 includes multiple metal layers, the first metal layer 311 of the first metal electrode 310 contacts the back side, the deformation modulus of the first metal layer 311 is not less than 100 GPa, and the thickness of the first metal layer 311 is 30 angstroms to 1000 angstroms.
  • the first metal layer 311 includes ruthenium, rhodium or chromium.
  • the front side of the semiconductor layer sequence is a first type semiconductor layer 111 or an undoped semiconductor layer, and the front side of the semiconductor layer sequence 110 is at least partially removed.
  • the front side of the semiconductor layer sequence 110 has a patterned or roughened surface.
  • the roughened surface is provided to increase the light output from the front side and reduce the total surface reflection.
  • the commonly used method includes removing part of the semiconductor material on the front side of the semiconductor layer sequence with an etching solution to form a roughened second groove G2 on the surface. After roughening, there is a region with a thickness of no more than 4 microns in the longitudinal direction in the first type semiconductor layer 111, for example, the thickness at the junction of the first mesa M1 and the second mesa M2 is 1 micron to 4 microns.
  • the front side of the semiconductor layer sequence 110 is covered with an insulating protective layer 500, which is exposed, and in this embodiment is completely exposed, and the thickness of the insulating protective layer 500 is 2000 angstroms to 10000 angstroms.
  • the insulating protective layer 500 is independently provided in the micro-LED, the probability of fracture anomaly can be reduced, but it is still difficult to avoid fracture anomaly.
  • the first metal electrode 310 includes multiple layers of metal, the first metal layer of the first metal electrode 310 (not shown in the figure of this embodiment) is in contact with the back side, the deformation modulus of the first metal layer is not less than 100 GPa, the thickness of the first metal layer is 10 angstroms to 30 angstroms, and the front side of the semiconductor layer sequence 110 is covered with an insulating protective layer 500, and the thickness of the insulating protective layer 500 is 2000 angstroms to 10000 angstroms, which can reduce the thickness requirement of the first metal layer and help to improve the flexibility of electrode thickness design, such as reducing the light absorption of the first metal layer.
  • the laminated metal of the first metal electrode 310 is further designed.
  • the laminated metal material is mainly The relative position relationship between the stacked metals is explained.
  • the first metal electrode 310 includes a first metal layer 311 in contact with the back side of the semiconductor layer sequence.
  • a platinum layer 331 and a bonding metal layer 332 are arranged on the first metal layer 311, wherein the material of the bonding metal layer 332 includes gold, and the thickness of the platinum layer 331 is 300 angstroms to 1000 angstroms.
  • the deformation modulus of platinum is slightly lower than that of the first metal layer 311, with the thickness, it also has the basis for providing reliable supporting force.
  • the thickness of the platinum layer 331 used in this embodiment is 500 angstroms.
  • the first metal layer 311 extends along the long side L1 of the support layer 120 (first type semiconductor layer), and the extension covers from the first groove sidewall S1 to the second mesa M2.
  • the deformation modulus of the first metal layer 311 is not less than 100 GPa, the thickness of the first metal layer 311 is 30 angstroms to 100 angstroms, and the thickness of the first metal layer 311 in this embodiment is 50 angstroms.
  • the first metal layer 311 extends along the long side L1 of the support layer 120, and the extension covers from the first groove sidewall S1 to the second mesa M2. From the horizontal projection plane of the short side L2, the first metal layer 311 covers the second mesa M2 with a width exceeding 20% of the length of the short side L2.
  • the semiconductor layer sequence 110 is at least partially penetrated by the first groove G1.
  • the penetrated area of the semiconductor layer sequence 110 is 25% to 60% of the length of the long side L1. Since a large area is removed in the lateral direction of the semiconductor layer sequence 110, it is more suitable for the design of the first metal electrode 310 of this embodiment.
  • the laminated metal of the first metal electrode 310 is further designed.
  • the first metal electrode 310 includes a first metal layer 311, a second metal layer 312 and a third metal layer 313 in sequence. From the process point of view, the second metal layer 312 is located between the first metal layer 311 and the third metal layer 313, and the second metal layer 312 is directly in contact with the first metal layer 311 and the third metal layer 313 respectively.
  • the deformation modulus of the first metal layer 311 and the third metal layer 313 is greater than that of the second metal layer 312.
  • the deformation modulus of the first metal layer 311 and the third metal layer 313 is not less than 100 GPa.
  • the present embodiment preferably designs the sum of the thickness of the first metal layer 311 and the third metal layer 313 to be 30 angstroms to 100 angstroms.
  • the third metal layer 313 is ruthenium, rhodium or chromium.
  • the thickness of the first metal layer 311 is 10 angstroms to 30 angstroms
  • the thickness of the third metal layer 313 is 20 angstroms to 70 angstroms.
  • the second metal layer 312 is configured as a metal reflective layer.
  • the material of the second metal layer 312 is aluminum or silver.
  • the thickness of the second metal layer 312 is 10 angstroms to 5000 angstroms.
  • the laminated metal of the first metal electrode 310 is further designed.
  • the laminated metal materials and the relative positional relationship between the laminated metals are mainly described.
  • the first metal electrode 310 sequentially includes a first metal layer 311, a platinum layer 331, a bonding metal layer 332 and a fourth metal layer 314.
  • the first metal layer 311 includes ruthenium, rhodium or chromium, with a thickness of 40 angstroms to 60 angstroms
  • the platinum layer 331 is platinum, with a thickness of 100 angstroms to 1000 angstroms
  • the bonding metal layer 332 is gold, with a thickness of 100 angstroms to 1000 angstroms
  • the fourth metal layer 314 includes titanium, nickel, tin, silver or copper.
  • the present invention is also applicable to the design of thin support layer 120.
  • the thickness of support layer 120 is usually greater than 4 microns.
  • the thickness of sapphire is usually greater than 50 microns.
  • the present embodiment does not adopt the support substrate design. Since the support substrate is peeled off and the semiconductor layer sequence 110 is penetrated from the side of the projection plane of the long side L1, there are stress concentration areas and stress defect areas in the entire semiconductor layer sequence 110, that is, there are stress defects at the intersection line of the first mesa M1 and the second mesa M2.
  • the thickness of the first type semiconductor layer 111 of the first mesa M1 is 1 micron to 4 microns.
  • the semiconductor layer sequence 110 is at least partially penetrated by the first groove G1. It is particularly suitable for the horizontal projection plane of the long side L1.
  • the penetration area of the semiconductor layer sequence 110 is 25% to 60% of the length of the long side L1. Since it is removed in a large range in the side direction of the semiconductor layer sequence 110, it is more suitable for the design of the first metal electrode 310 of this embodiment. Even if the front side of the first type semiconductor layer 111 is not roughened or patterned, it may still break under pressure, and the overall structure is not stable.
  • the first groove opening does not penetrate the horizontal projection plane of the long side alone, and the length of the first groove on the short side is 30% to 80% of the length of the short side, but the support layer 120 is further thinned to less than 3 microns, and the first metal electrode 310 extends along the long side L1 direction of the support layer 120, and the extension covers from the side wall S1 of the first groove to the second table M2.
  • the first metal electrode 310 includes multiple layers of metal, wherein the total thickness of the metal layer with a deformation modulus of not less than 100 GPa is 30 angstroms to 1000 angstroms.
  • the first metal electrode 310 extends along the long side L1 of the support layer 120, and the extension covers the first groove sidewall S1 to the second table M2.
  • the first metal electrode 310 includes multiple layers of metal.
  • the first metal layer 311 of the first metal electrode 310 contacts the back side.
  • the deformation modulus of the first metal layer 311 is not less than 100 GPa, and the thickness of the first metal layer 311 is 30 angstroms to 1000 angstroms.
  • the first metal Layer 311 includes ruthenium, rhodium or chromium.
  • the first metal electrode 310 includes a first metal layer 311, a second metal layer 312 and a third metal layer 313 in sequence. From the process technology point of view, the second metal layer 312 is located between the first metal layer 311 and the third metal layer 313, and the second metal layer 312 is in direct contact with the first metal layer 311 and the third metal layer 313 respectively, wherein the deformation modulus of the first metal layer 311 and the third metal layer 313 is greater than that of the second metal layer 312. From the hardness point of view, the deformation modulus of the first metal layer 311 and the third metal layer 313 is not less than 100 GPa. In order to ensure reliability, the present embodiment preferably designs the sum of the thickness of the first metal layer 311 and the third metal layer 313 to be 30 angstroms to 100 angstroms.
  • any one of the embodiments 1 to 5 except for the roughening of the front side is adopted, such as the design of the first metal electrode 310 and/or the design of the insulating protective layer 500, to strengthen the structure itself.
  • the thickness of the insulating protective layer 500 is 2000 angstroms to 5000 angstroms, which can reduce the thickness requirement of the first metal layer 311, which is conducive to improving the flexibility of the electrode thickness design, such as reducing the light absorption of the first metal layer 311.
  • the thickness of the insulating protective layer 500 can also be designed to be 5000 angstroms to 10000 angstroms, so that the design of the first metal layer 311 is not required, and soft metal can be used in the first metal layer 311 to improve the strength of the chip structure.
  • a display device comprising a substrate 600 and a plurality of micro-LEDs 100 .
  • the substrate 600 and the plurality of micro-LEDs 100 are connected via wires or conductive pads 610 , and the micro-LEDs 100 are any one of the above embodiments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

一种微发光二极管，具有半导体层序列，半导体层序列的背侧设置有第一金属电极和第二金属电极，半导体层序列的背侧包括凹槽内的第一台面、第二台面和位于两者之间的凹槽侧壁，第一金属电极设置在第一台面上，其中第一类型半导体层为支撑层，凹槽底面至半导体层序列正侧的距离不大于4微米，在支撑层长边的水平投影面上，半导体层序列至少有局部被凹槽贯穿，第一金属电极沿着支撑层的长边方向延伸，且所述延伸从凹槽侧壁覆盖到第二台面上，提升微发光二极管结构强度。

Description

一种微发光二极管及其显示装置 技术领域
本发明属于半导体制造领域，具体涉及微发光二极管及显示装置。
背景技术
微型LED(mLED)是目前热门研究的下一代显示器光源。它具有低功耗、高亮度、超高分辨率与色彩饱和度、响应速度快、能耗低、寿命长灯优点。此外，它的功率消耗量约为LCD的10％，OLED的50％。而与同样是自发光的OLED相比较，亮度高了多倍，且分辨率可以达到高像素密度。mLED这些明显的优势，使得它有望取代现在的OLED和LCD，成为下一代显示器的光源。mLED目前还无法量产，是因为目前还有许多技术难题需要攻克，其中一个重要的技术难题就是如何提高转移良率。而本发明就是针对此问题提出一种可行的解决方案，通过此方案可以实现高良率的mLED的转移。
发明概述
技术问题
问题的解决方案
技术解决方案
针对由于微发光二极管衬底需要剥离，依靠半导体层序列的半导体材料支撑，在半导体层序列进一步减薄设计或者移除设计后，大批量转移时因为脆弱很难通过常规结构完成且保持高的转移良率。
本发明提供了一种微发光二极管，具有半导体层序列，半导体层序列包括相对设置的正侧和背侧，半导体层序列包括：第一类型半导体层、第二类型半导体层和两者之间的有源层，半导体层序列的背侧具有凹槽，凹槽贯穿第二类型半导体层、有源层，露出第一类型半导体层，为了保证露出第一类型半导体层，通常会移除部分第一类型半导体层；
半导体层序列的背侧设置有第一金属电极和第二金属电极，
半导体层序列的背侧包括凹槽内的第一台面、第二台面和位于两者之间的凹槽 侧壁，
第一金属电极设置在第一台面，第二金属电极设置在第二台面，
第一金属电极与第一类型半导体层电连接，
第二金属电极与第二类型半导体层电连接，
其中第一类型半导体层为支撑层，从俯视方向上看，支撑层为长方形，至少部分凹槽至半导体层序列正侧的距离不大于4微米，即凹槽内第一类型半导体层厚度不大于4微米，例如距离为1微米至4微米。
支撑层长边的水平投影面上，半导体层序列至少有局部被凹槽贯穿，
第一金属电极沿着支撑层的长边方向延伸，且所述延伸从凹槽侧壁覆盖到第二台面上，对半导体层序列厚度显著变化的应力集中区进行加固。
第一金属电极和第一台面之间，以及第一金属电极与凹槽侧壁之间设置有介质钝化层。
根据本发明，优选的，短边的水平投影面看，第一金属电极在第二台面的覆盖面宽度超过短边长度的20％，保证足够的固持力。
根据本发明，优选的，适用于支撑层的长边和短边的比例大为1.5至5，支撑层匹配该种狭长设计，提供固持力。综合考虑支撑层最小厚度以及长、短边比例小于1.5时，受力时支撑层断裂概率小，而支撑层长边和短边比例大于5时，由于力矩增大，支撑层断裂概率显著增加。
根据本发明，优选的，制作过程中包括衬底剥离工艺，半导体层序列的正侧露出，没有支撑衬底，且半导体层序列的正侧为第一类型半导体层或者未掺杂半导体层，半导体层序列的正侧至少部分被移除。
根据本发明，优选的，半导体层序列的正侧具有图案化或者粗糙化表面。
根据本发明，优选的，上述移除，可能会带来光性能的提升，例如光型的控制，但对第一类型半导体层的正侧，即支撑层造成一些损伤或者隐患，半导体层序列的正侧覆盖有绝缘保护层，绝缘保护层的正侧露出，绝缘保护层的厚度为2000埃至10000埃，在图案化或者粗化表面辅助进行支撑，提供正侧的固持力。
根据本发明，优选的，绝缘保护层的材料包括：二氧化硅、氮化硅、氧化钛或者氧化铝。
本发明所述的微发光二极管，指的是尺寸为100μm×150μm以内的生产或支撑衬底去除的发光二极管芯片。
根据本发明，优选的，第一金属电极包括复数层金属，第一金属电极的第一金属层与背侧接触，第一金属层的形变模量不小于100GPa，第一金属层的厚度为30埃至1000埃，利用第一金属层的高形变模量保证，半导体层序列受到剪切力力矩时，避免被切断。
根据本发明，优选的，第一金属层包括钌、铑或者铬。
根据本发明，优选的，第一金属电极包括复数层金属，第一金属电极的第一金属层与发光二极管的背侧接触，第一金属层的形变模量不小于100GPa，第一金属层的厚度为10埃至30埃，半导体层序列的正侧覆盖有绝缘保护层，绝缘保护层的厚度为2000埃至5000埃，通过组合式加固设计，降低第一金属层的厚度，减少第一金属对辐射的吸收。
在本发明的一些实施方式中，优选的，第一金属电极依次包括第一金属层、第二金属层和第三金属层，第二金属层分别与第一金属层、第三金属层直接接触，第一金属层和第三金属层的形变模量大于第二金属层，第一金属层和第三金属层的形变模量不小于100GPa，第一金属层和第三金属层的厚度和为30埃至1000埃，第一金属层和第三金属层共同提供固持力。
在该些实施方式中，优选的，第三金属层为钌、铑或者铬。
在该些实施方式中，优选的，第二金属层为金属反射层，第二金属层的材料为铝或者银，既保证了产品的可靠性，又提升了产品的亮度。
在该些实施方式中，优选的，采用上述软性金属作为金属反射层，则第二金属层的厚度为10埃至2000埃，限制第二金属反射层的厚度，如果软性金属厚度超过2000埃，有可能降低器件的可靠性，因为对第二金属层具有反射特性要求，厚度小于10埃难以提供有效反射贡献。
根据本发明，优选的，适用于在俯视投影面上，凹槽面积为第一类型半导体层面积的25％至60％的芯片结构，小于25％，由于力矩比较小则基本不存在转移过程中支撑层断裂的问题，超过60％则发光区面积损失过大。
在本发明的一些实施方式中，优选的，第一金属电极包括复数层金属，其中形 变模量不小于100GPa的金属层的总厚度为30埃至1000埃，提供第一金属电极足够的支持力。
在本发明的一些实施方式中，优选的，半导体层序列的材料为氮化镓系列或者铝镓铟磷系列，凹槽内第一类型半导体层厚度不大于4微米。
根据本发明，优选的，第二台面上的第一金属电极面积与第二台面上的第二金属金属电极面积大小差异不大于30％，提升封装键合时，键合力的稳定性，降低切力力矩，提升转移良率。
本发明还提供了一种微发光二极管，具有半导体层序列，半导体层序列包括相对设置的正侧和背侧，半导体层序列包括：第一类型半导体层、第二类型半导体层和两者之间的有源层，半导体层序列的背侧具有凹槽，
半导体层序列的背侧设置有第一金属电极和第二金属电极，
半导体层序列的背侧包括凹槽内的第一台面、第二台面和位于两者之间的凹槽侧壁，凹槽贯穿第二台面至第一类型半导体层，且第二类型半导体层部分被移除；
第一金属电极设置在第一台面，第二金属电极设置在第二台面，
第一金属电极与第一类型半导体层电连接，
第二金属电极与第二类型半导体层电连接，
其中第一类型半导体层为支撑层，从俯视方向上看，支撑层为长方形，至少部分凹槽至半导体层序列正侧的距离不大于4微米，即凹槽内第一类型半导体层厚度不大于4微米，例如距离为1微米至4微米。
在俯视投影面上，凹槽面积为第一类型半导体层面积的25％至60％。
第一金属电极沿着支撑层的长边方向延伸，且所述延伸从凹槽侧壁覆盖到第二台面上，对半导体层序列厚度显著变化的应力集中区进行加固。
第一金属电极和第一台面之间，以及第一金属电极与凹槽侧壁之间设置有介质钝化层。
一种显示装置，包括基板以及上述任意一种微发光二极管。
发明的有益效果
有益效果
本发明的有益效果包括但不限于，提升微发光二极管的可靠性，减少或避免支撑层被切断，以及提升产品整体良率。
对附图的简要说明
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1和图2：现有转移工艺的结构示意图；
图3和图4：分别为本发明第一个实施例的剖视结构示意图和立体结构示意图；
图5：为本发明第二个实施例的剖视结构示意图；
图6：为本发明第三个实施例的剖视结构示意图和第一金属电极的放大示意图；
图7：为本发明第四个实施例的第一金属电极叠层剖视结构示意图；
图8：为本发明第五个实施例的第一金属电极叠层剖视结构示意图；
图9和图10：分别为本发明第六个实施例的剖视结构示意图；
图11：为本发明第七个实施例的剖视结构示意图。
图中标识：100、微发光二极管；110、半导体层序列；111、第一类型半导体层；112、第二类型半导体层；113、有源层；120、支撑层；200、压印；310、第一金属电极；311、第一金属层；312、第二金属层；313、第三金属层；314、第四金属层；331、铂层；332、键合金属层；320、第二金属电极；400、介质钝化层；500、绝缘保护层；C1、断裂；D1、D2、长度；G1、第一凹槽；G2、第二凹槽；L1、长边；L2、短边；M1、第一台面；M2、第二台面；S1、第一凹槽侧壁；PD1、长边的水平投影面。
发明实施例
本发明的实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中 的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
为了更好的实施本发明的技术，说明本发明涉及的转移流程，对现有转移工艺简单进行描述。
参看图1，在常规MicroLED转移制程中，例如高像素的显示芯片制程中，微发光二极管100的尺寸为100μm×150μm以内。需经过压膜压印的，拾取和放置超薄和/或小型装置。本发明的设计，使得微转贴印刷允许这些超薄、易碎及/或小型装置的选择及应用而不会导致对芯片自身的损坏。
微转贴印刷的巨量转移方式允许将微尺度、高性能装置阵列决定性地组装及集成于非原生衬底上。在其最简单实施例中，微转贴印刷类似于使用橡胶压印器以将基于流体的墨水从印台转贴到纸上。然而，在微转贴印刷中，“墨水”是由高性能固态半导体装置组成且“纸”可为包含电路板、胶膜、塑料或者其它半导体的衬底。微转贴印刷工艺利用与高精度控制动作印刷头耦合的经设计弹性体压印200以选择性地将大阵列的微尺度装置拾取且印刷于非原生目的地衬底上。
参看图2，在巨量转移过程中，存在压印200对微发光二极管100的挤压和印刷，当微发光二极管100远离压印200的一侧存在表面第一凹槽G1，例如半导体层序列110的N型窗口层设置有第一凹槽G1，特别是微发光二极管靠近压印200的一侧还经过减薄、粗化或者图形化蚀刻移除时，微发光二极管100易在第一凹槽侧壁S1与第一台面M1处出现断裂C1。
参看图3和图4，在本发明的第一个实施例中提供了一种微发光二极管，包括半导体层序列110，半导体层序列110包括相对设置的正侧和背侧，即半导体层序列110远离第一金属电极310和第二金属电极320一侧的上表面为正侧，半导体层序列110靠近第一金属电极310和第二金属电极320一侧的下表面为背侧，半导体层序列110包括：第一类型半导体层111、第二类型半导体层112和两者之间的有源层113，在本实施例中，半导体层序列110的材料为氮化镓系列或者铝镓铟磷系列。在一个具体的实施例中，半导体层序列110通过产生第一类型半导体层111产生的电子和第二类型半导体层112产生的空穴，进行复合激发出光。经过衬底移除工艺，半导体层序列110的正侧露出。
半导体层序列110的背侧具有Mesa台面的第一凹槽G1，在本实施例中图形化的 第一凹槽G1用于设置向第一类型半导体层111的电流注入窗口，第一凹槽G1依次贯穿第二类型半导体层112、有源层113和部分第一类型半导体层111，并露出第一类型半导体层111。由于第一类型半导体层111具有较大的厚度，因此第一类型半导体层111的一部分可以作为支撑层120，在支撑层120长边L1的水平投影面PD1上，半导体层序列110至少有局部被第一凹槽G1贯穿。特别适用于长边L1的水平投影面PD1上，半导体层序列110贯穿区域的长度D1为长边L1长度的25％至60％，由于在半导体层序列110侧向上大范围的被移除，因此更适用于本实施例的第一金属电极310设计。
在半导体层序列110的背侧设置有第一金属电极310和第二金属电极320，第一金属电极310和第二金属电极320用于与外部电路连接，半导体层序列110的背侧包括第一台面M1、第一凹槽G1内的第一台面M1和位于两者之间的第一凹槽侧壁S1，其中第一金属电极310设置在第一台面M1上，第一台面M1位于第一凹槽G1的底面，第二金属电极320设置在第二台面M2上，第一金属电极310与第一类型半导体层111直接连接，第二金属电极320与第二类型半导体层112电连接，例如第二金属电极320通过透明电流扩展层(本实施例未在图中标识)与第二类型半导体层112连接。
其中第一类型半导体层111为支撑层120，对半导体层序列110提供支撑，从俯视投影方向上看，支撑层120大体为长方形，支撑层120的长边L1和短边的长度比例为1.5至5，在竖直方向上，至少部分第一凹槽G1至半导体层序列110正侧的距离不大于4微米，即至少部分第一凹槽G1内第一类型半导体层111厚度不大于4微米，例如至少部分第一凹槽G1内第一类型半导体层111厚度为1微米至4微米。在俯视投影面上，第一凹槽G1面积为第一类型半导体层111面积的25％至60％，这里的面积指的是单独整块第一凹槽G1区域的面积，不包括第二台面M2的边界区域。
第一金属电极310沿着支撑层120的长边L1方向延伸，且所述延伸从第一凹槽侧壁S1覆盖到第二台面M2上，第一金属电极310包括复数层金属，其中形变模量不小于100GPa的金属层的总厚度为30埃至1000埃。
第一金属电极310和第二台面M2之间，以及第一金属电极310与第一凹槽侧壁S 1之间设置有介质钝化层400，依托介质钝化层400将第一金属电极310和第二台面M2电隔离，介质钝化层400的材料包括氧化硅、氮化硅或者为分布布拉格反射镜DBR，作为示例的如果介质钝化层400的材料为二氧化硅，则介质钝化层400的厚度为1000埃至10000埃，将第一金属电极310和第二台面M2，从短边投影面看，第一金属电极310在第二台面M2的覆盖面宽度D2超过短边L2长度的20％，例如覆盖面宽度D2为短边L2长度的20％至90％。
第一金属电极310包括复数层金属，第一金属电极310的第一金属层311与背侧接触，第一金属层311的形变模量不小于100GPa，第一金属层311的厚度为30埃至1000埃。第一金属层311包括钌、铑或者铬。
参看图5，在本发明的第二个实施例中，半导体层序列的正侧为第一类型半导体层111或者未掺杂半导体层，半导体层序列110的正侧至少部分被移除。
半导体层序列110的正侧具有图案化或者粗糙化表面，作为示例的为了增加正侧出光而设置粗化表面减少表面全反射，通常采用的方式包括，蚀刻液移除部分半导体层序列正侧半导体材料，在表面形成粗糙化的第二凹槽G2。粗化后第一类型半导体层111中在纵向上存在厚度不大于4微米的区域，例如在第一台面M1和第二台面M2的交界出厚度为1微米至4微米。
半导体层序列110的正侧覆盖有绝缘保护层500，绝缘保护层500露出，在本实施例中为完全露出，绝缘保护层500的厚度为2000埃至10000埃。根据本实施例，在微发光二极管中独立设置绝缘保护层500虽然有机会降低断裂异常概率，但依然难以避免断裂异常。
在本实施例中在正侧覆盖绝缘保护层500的基础上，结合第一金属电极310强化设计，第一金属电极310包括复数层金属，第一金属电极310的第一金属层(此实施例图中未画出)与背侧接触，第一金属层的形变模量不小于100GPa，第一金属层的厚度为10埃至30埃，半导体层序列110的正侧覆盖有绝缘保护层500，绝缘保护层500的厚度为2000埃至10000埃，可降低第一金属层厚度需求，有利于提升电极厚度设计的灵活性，例如减少第一金属层吸光。
参看图6，在本发明的第三个实施例中，在实施例1和实施例2的基础上，进一步对第一金属电极310的叠层金属做出设计，在本实施例中主要对叠层金属材料 以及叠层金属之间的相对位置关系进行阐述，第一金属电极310包括跟半导体层序列背侧接触的第一金属层311，第一金属层311上设置铂层331和键合金属层332，其中键合金属层332的材料包括金，铂层331的厚度为300埃至1000埃，虽然铂的形变模量略低于第一金属层311，在厚度加持下，也具有提供可靠支撑力的基础，本实施例采用的铂层331厚度为500埃。
在本实施例中，第一金属层311沿着支撑层120(第一类型半导体层)的长边L1方向延伸，且所述延伸从第一凹槽侧壁S1覆盖到第二台面M2上，第一金属层311的形变模量不小于100GPa，第一金属层311的厚度为30埃至100埃，本实施例第一金属层311的厚度为50埃，第一金属层311沿着支撑层120的长边L1方向延伸，且所述延伸从第一凹槽侧壁S1覆盖到第二台面M2上。在短边L2的水平投影面看，第一金属层311在第二台面M2覆盖面宽度超过短边L2长度的20％。
在支撑层120长边L1的水平投影面上，半导体层序列110至少有局部被第一凹槽G1贯穿。特别适用于长边L1的水平投影面PD1上，半导体层序列110的贯穿区域为长边L1长度的25％至60％，由于在半导体层序列110侧向上大范围的被移除，因此更适用于本实施例的第一金属电极310设计。
参看图7，在本发明的第四个实施例中，在实施例1和实施例2的基础上，进一步对第一金属电极310的叠层金属做出设计，在本实施例中主要对叠层金属材料以及叠层金属之间的相对位置关系进行阐述，第一金属电极310依次包括第一金属层311、第二金属层312和第三金属层313，从制程工艺看，第二金属层312位于第一金属层311和第三金属层313之间，第二金属层312分别与第一金属层311、第三金属层313直接接触，其中第一金属层311和第三金属层313的形变模量大于第二金属层312，从硬度上看，第一金属层311和第三金属层313的形变模量不小于100GPa，为了保证可靠性，本实施例优选设计第一金属层311和第三金属层313的厚度和为30埃至100埃。其中第三金属层313为钌、铑或者铬。在本实施例中，第一金属层311厚度为10埃至30埃，第三金属层313厚度为20埃至70埃。
在本实施例中，为了提供微发光二极管的外量子效率，第二金属层312设置为金属反射层，第二金属层312的材料为铝或者银，第二金属层312的厚度为10埃至5000埃。
参看图8，在本发明的第五个实施例中，在实施例1和实施例2的基础上，进一步对第一金属电极310的叠层金属做出设计，在本实施例中主要对叠层金属材料以及叠层金属之间的相对位置关系进行阐述，第一金属电极310依次包括第一金属层311、铂层331、键合金属层332和第四金属层314。其中第一金属层311包括钌、铑或者铬，厚度为40埃至60埃，铂层331为铂，厚度为100埃至1000埃，键合金属层332为金，厚度为100埃至1000埃，第四金属层314包括钛、镍、锡、银或者铜。
参看图9和图10，在本发明的第六个实施例中，即使不采用粗化，本发明也适用于支撑层120厚度较薄的设计。在现有芯片技术中，支撑层120厚度通常会大于4微米，例如常规尺寸芯片如果采用蓝宝石，通常会蓝宝石厚度会大于50微米。作为相反的设计，本实施例未采用支撑衬底设计，由于支撑衬底被剥离，且半导体层序列110从长边L1投影面的侧向上被贯穿，在整个半导体层序列110存在应力集中区域和应力缺陷区域，即在第一台面M1和第二台面M2的相贯线存在应力缺陷，在本实施例中，第一台面M1的第一类型半导体层111厚度为1微米至4微米。半导体层序列110至少有局部被第一凹槽G1贯穿。特别适用于长边L1的水平投影面上，半导体层序列110的贯穿区域为长边L1长度的25％至60％，由于在半导体层序列110侧向上大范围的被移除，因此更适用于本实施例的第一金属电极310设计。即使第一类型半导体层111正侧不采用粗化或者图形化，受压条件下也可能出现破裂，整体结构稳固性不佳。
在本实施例中，第一凹槽开口不单独贯穿长边的水平投影面，在第一凹槽在短边的长度为短边长度的30％至80％，但支撑层120进一步减薄至3微米以下，第一金属电极310沿着支撑层120的长边L1方向延伸，且所述延伸从第一凹槽侧壁S1覆盖到第二台面M2上，第一金属电极310包括复数层金属，其中形变模量不小于100GPa的金属层的总厚度为30埃至1000埃。
在本实施例的另一种实施方式中，第一金属电极310沿着支撑层120的长边L1方向延伸，且所述延伸从第一凹槽侧壁S1覆盖到第二台面M2上，第一金属电极310包括复数层金属，第一金属电极310的第一金属层311与背侧接触，第一金属层311的形变模量不小于100GPa，第一金属层311的厚度为30埃至1000埃。第一金属 层311包括钌、铑或者铬。
在本实施例的另一种实施方式中，第一金属电极310依次包括第一金属层311、第二金属层312和第三金属层313，从制程工艺看，第二金属层312位于第一金属层311和第三金属层313之间，第二金属层312分别与第一金属层311、第三金属层313直接接触，其中第一金属层311和第三金属层313的形变模量大于第二金属层312，从硬度上看，第一金属层311和第三金属层313的形变模量不小于100GPa，为了保证可靠性，本实施例优选设计第一金属层311和第三金属层313的厚度和为30埃至100埃。
在本实施例中，采用实施例1至实施例5中任意一种的除正侧粗化外的实施方式，例如第一金属电极310设计和/或绝缘保护层500设计，对结构本身进行强化。以绝缘保护层500设计为例，绝缘保护层500的厚度为2000埃至5000埃，可降低第一金属层311厚度需求，有利于提升电极厚度设计的灵活性，例如减少第一金属层311吸光。也可以设计绝缘保护层500的厚度为5000埃至10000埃，则可不借助第一金属层311的设计，可在第一金属层311采用软质金属，对芯片结构强度进行改善。
参看图11，在本发明的第七个实施例中，提出一种显示装置，具有基板600和复数颗微发光二极管100，基板600和复数颗微发光二极管100，通过导线或者导电焊盘610连接，微发光二极管100为上述实施例中任意一种。
以上所述仅为本发明创造的较佳实施例而已，并不用以限制本发明创造，凡在本发明创造的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明创造的保护范围之内。

Claims (22)

  1. 一种微发光二极管，具有半导体层序列，半导体层序列包括相对设置的正侧和背侧，半导体层序列包括：第一类型半导体层、第二类型半导体层和两者之间的有源层，半导体层序列的背侧具有凹槽，凹槽贯穿第二类型半导体层、有源层并露出第一类型半导体层，
    半导体层序列的背侧设置有第一金属电极和第二金属电极，
    半导体层序列的背侧包括凹槽内的第一台面、第二台面和位于两者之间的凹槽侧壁，
    第一金属电极设置在第一台面上，第二金属电极设置在第二台面上，
    第一金属电极与第一类型半导体层电连接，
    第二金属电极与第二类型半导体层电连接，
    其特征在于，其中第一类型半导体层为支撑层，从俯视方向上看，支撑层为长方形，在竖直方向上，至少部分凹槽底面至半导体层序列正侧的距离不大于4微米，
    在支撑层长边的水平投影面上，半导体层序列至少有局部被凹槽贯穿，
    第一金属电极沿着支撑层的长边方向延伸，且所述延伸从凹槽侧壁覆盖到第二台面上，
    第一金属电极和第二台面之间，以及第一金属电极与凹槽侧壁之间设置有介质钝化层。
  2. 根据权利要求1所述的一种微发光二极管，其特征在于，短边的水平投影面看，第一金属电极在第二台面的覆盖面宽度超过短边长度的20％。
  3. 根据权利要求2所述的一种微发光二极管，其特征在于，第一金属电极在第二台面的覆盖面宽度为短边长度的20％至90％。
  4. 根据权利要求1所述的一种微发光二极管，其特征在于，支撑层的 长边和短边的比例为1.5至5。
  5. 根据权利要求1所述的一种微发光二极管，其特征在于，经过衬底移除工艺，半导体层序列的正侧露出，且半导体层序列的正侧为第一类型半导体层或者未掺杂半导体层，半导体层序列的正侧至少部分被移除。
  6. 根据权利要求5所述的一种微发光二极管，其特征在于，半导体层序列的正侧具有图案化或者粗糙化表面。
  7. 根据权利要求1所述的一种微发光二极管，其特征在于，半导体层序列的正侧覆盖有绝缘保护层，绝缘保护层的正侧露出，绝缘保护层的厚度为2000埃至10000埃。
  8. 根据权利要求7所述的一种微发光二极管，其特征在于，绝缘保护层的材料包括二氧化硅、氮化硅、氧化钛或者氧化铝。
  9. 根据权利要求1所述的一种微发光二极管，其特征在于，微发光二极管的尺寸为100μm×150μm以内。
  10. 根据权利要求1所述的一种微发光二极管，其特征在于，第一金属电极包括复数层金属，第一金属电极的第一金属层与背侧接触，第一金属层的形变模量不小于100GPa，第一金属层的厚度为30埃至1000埃。
  11. 根据权利要求10所述的一种微发光二极管，其特征在于，第一金属层包括钌、铑或者铬。
  12. 根据权利要求1所述的一种微发光二极管，其特征在于，第一金属电极包括复数层金属，第一金属电极的第一金属层设置在微发光二极管的背侧，第一金属层的形变模量不小于100GPa，第一金属层的厚度为10埃至30埃，半导体层序列的正侧覆盖有绝缘保护层，绝缘保护层的厚度为2000埃至10000埃。
  13. 根据权利要求1所述的一种微发光二极管，其特征在于，第一金属电极依次包括第一金属层、第二金属层和第三金属层，第二金属层分别与第一金属层、第三金属层直接接触，第一金属层和第三 金属层的形变模量大于第二金属层，第一金属层和第三金属层的形变模量不小于100GPa，第一金属层和第三金属层的厚度和为30埃至1000埃。
  14. 根据权利要求13所述的一种微发光二极管，其特征在于，第三金属层为钌、铑或者铬。
  15. 根据权利要求13所述的一种微发光二极管，其特征在于，第二金属层为金属反射层，第二金属层的材料为铝或者银。
  16. 根据权利要求15所述的一种微发光二极管，其特征在于，第二金属层的厚度为10埃至2000埃。
  17. 根据权利要求1所述的一种微发光二极管，其特征在于，在俯视投影面上，凹槽面积为第一类型半导体层面积的25％至60％。
  18. 根据权利要求1所述的一种微发光二极管，其特征在于，第一金属电极包括复数层金属，其中形变模量不小于100GPa的金属层的总厚度为30埃至1000埃。
  19. 根据权利要求1所述的一种微发光二极管，其特征在于，半导体层序列的材料为氮化镓系列或者铝镓铟磷系列，至少部分凹槽内第一类型半导体层厚度为1微米至4微米。
  20. 根据权利要求1所述的一种微发光二极管，其特征在于，第二台面上的第一金属电极面积与第二台面上的第二金属电极面积大小差异不大于30％。
  21. 根据权利要求1所述的一种微发光二极管，其特征在于，长边的水平投影面上，半导体层序列的贯穿区域长度为长边长度的25％至60％。
  22. 一种显示装置，包括基板，其特征在于，包括权利要求1至权利要求21中任意一项所述的一种微发光二极管。
PCT/CN2022/110617 2022-10-21 2022-10-21 一种微发光二极管及其显示装置 WO2024082074A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/110617 WO2024082074A1 (zh) 2022-10-21 2022-10-21 一种微发光二极管及其显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/110617 WO2024082074A1 (zh) 2022-10-21 2022-10-21 一种微发光二极管及其显示装置

Publications (1)

Publication Number Publication Date
WO2024082074A1 true WO2024082074A1 (zh) 2024-04-25

Family

ID=90736559

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/110617 WO2024082074A1 (zh) 2022-10-21 2022-10-21 一种微发光二极管及其显示装置

Country Status (1)

Country Link
WO (1) WO2024082074A1 (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130049051A1 (en) * 2011-08-30 2013-02-28 Epistar Corporation Light-emitting device
CN105895758A (zh) * 2014-10-23 2016-08-24 北京中科天顺信息技术有限公司 发光二极管、发光二极管模块及其制作方法
CN106229400A (zh) * 2016-09-23 2016-12-14 厦门市三安光电科技有限公司 一种发光二极管及其制作方法
CN213184332U (zh) * 2020-06-09 2021-05-11 山西中科潞安紫外光电科技有限公司 一种倒装紫外发光二极管芯片
CN112909136A (zh) * 2019-11-19 2021-06-04 成都辰显光电有限公司 发光二极管、显示面板、显示装置及制备方法
CN113488569A (zh) * 2021-06-23 2021-10-08 山西中科潞安紫外光电科技有限公司 一种倒装结构发光二极管芯片及其制备方法
CN114188454A (zh) * 2021-12-03 2022-03-15 厦门市三安光电科技有限公司 紫外发光二极管及发光装置
CN114824000A (zh) * 2022-03-18 2022-07-29 华灿光电（浙江）有限公司 反极性红光发光二极管芯片及其制备方法
CN115020567A (zh) * 2022-04-18 2022-09-06 泉州三安半导体科技有限公司 发光二极管及发光装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130049051A1 (en) * 2011-08-30 2013-02-28 Epistar Corporation Light-emitting device
CN105895758A (zh) * 2014-10-23 2016-08-24 北京中科天顺信息技术有限公司 发光二极管、发光二极管模块及其制作方法
CN106229400A (zh) * 2016-09-23 2016-12-14 厦门市三安光电科技有限公司 一种发光二极管及其制作方法
CN112909136A (zh) * 2019-11-19 2021-06-04 成都辰显光电有限公司 发光二极管、显示面板、显示装置及制备方法
CN213184332U (zh) * 2020-06-09 2021-05-11 山西中科潞安紫外光电科技有限公司 一种倒装紫外发光二极管芯片
CN113488569A (zh) * 2021-06-23 2021-10-08 山西中科潞安紫外光电科技有限公司 一种倒装结构发光二极管芯片及其制备方法
CN114188454A (zh) * 2021-12-03 2022-03-15 厦门市三安光电科技有限公司 紫外发光二极管及发光装置
CN114824000A (zh) * 2022-03-18 2022-07-29 华灿光电（浙江）有限公司 反极性红光发光二极管芯片及其制备方法
CN115020567A (zh) * 2022-04-18 2022-09-06 泉州三安半导体科技有限公司 发光二极管及发光装置

Similar Documents

Publication Publication Date Title
US10903397B2 (en) Light emitting device package
EP3079171B1 (en) Transfer system comprising a transfer head of semiconductor light emitting device, and method of transferring semiconductor light emitting device
US7067340B1 (en) Flip-chip light emitting diode and fabricating method thereof
US20170345801A1 (en) Display apparatus and fabricating method thereof
JP4097510B2 (ja) 半導体装置の製造方法
US8847267B2 (en) Light emitting diode with metal piles and multi-passivation layers and its manufacturing method
CN112768484B (zh) 发光二极管及其制作方法
WO2021087686A1 (zh) 发光二极管及其制作方法
JP5148336B2 (ja) 発光ダイオードチップおよびその製造方法
KR100878326B1 (ko) 칩스케일 패키징 발광소자 및 그의 제조방법
JP2009032882A (ja) 半導体発光素子及び半導体発光素子製造方法
WO2016000458A1 (zh) 发光二极管
JP2013008817A (ja) 半導体発光素子及びその製造方法
JP2008218878A (ja) ＧａＮ系ＬＥＤ素子および発光装置
WO2023071910A1 (zh) Micro-LED芯片结构及其制作方法
CN111129062B (zh) Led显示模组、led显示屏及制作方法
CN115528154A (zh) 倒装发光二极管和发光装置
KR20010088929A (ko) AlGaInN계 반도체 LED 소자 및 그 제조 방법
KR20050014343A (ko) 반도체 발광 소자
JP2014207327A (ja) 半導体発光素子
US6809345B2 (en) Semiconductor light emitting element and semiconductor light emitting device
CN210897328U (zh) 发光二极管芯片及发光模块
JP2005302803A (ja) 窒化物半導体発光素子およびその製造方法
WO2024082074A1 (zh) 一种微发光二极管及其显示装置
CN110828629B (zh) 一种倒装led芯片及其制作方法