WO2024078102A1 - 存储芯片、存储设备和电子设备 - Google Patents

存储芯片、存储设备和电子设备 Download PDF

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Publication number
WO2024078102A1
WO2024078102A1 PCT/CN2023/110919 CN2023110919W WO2024078102A1 WO 2024078102 A1 WO2024078102 A1 WO 2024078102A1 CN 2023110919 W CN2023110919 W CN 2023110919W WO 2024078102 A1 WO2024078102 A1 WO 2024078102A1
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Prior art keywords
memory
storage
electrode
sub
units
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PCT/CN2023/110919
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English (en)
French (fr)
Inventor
吴全潭
李响
陈一峰
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华为技术有限公司
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Publication of WO2024078102A1 publication Critical patent/WO2024078102A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a memory chip, a memory device and an electronic device.
  • Memory chips are the main medium for storing data in computers, and storage capacity is one of the key indicators of memory chip performance.
  • the capacity of memory chips is generally increased by optimizing the operation mode or the storage array architecture.
  • the increase in the number of stacked layers in current memory chips makes it more difficult to manufacture and mass produce.
  • the negative benefits of the increase in the number of stacked layers are greater than the positive benefits of the increase in storage density, the cost performance of memory chips is not high.
  • the embodiments of the present application provide a memory chip, a memory device and an electronic device.
  • the multiple memory sub-units in the embodiments of the present application are memory structures that can be manufactured separately, which reduces the manufacturing difficulty of the memory chip and facilitates mass production.
  • an embodiment of the present application provides a memory chip.
  • the memory chip includes a plurality of memory cells, each of the plurality of memory cells includes a substrate and a plurality of memory sub-units, the plurality of memory sub-units are stacked on the substrate, each of the memory sub-units includes a memory layer and an insulating layer alternately stacked, and a first electrode penetrating the memory layer and the insulating layer, the memory layer includes a memory part for storing data and a second electrode, the first electrode is electrically connected to the memory parts of all the memory layers of the memory sub-unit, and the first electrode and the second electrode are used to connect to a peripheral circuit to control the access of data in the memory part through the peripheral circuit.
  • the number of memory sub-units of the present application is at least two.
  • the number of storage layers of each storage sub-unit may be one, two or three layers, etc.
  • at least two storage layers at least two storage layers are spaced apart and stacked on a substrate, an insulating layer is provided between the storage layer and the substrate, and an insulating layer is provided between two adjacent storage layers.
  • the number of layers of the memory chip is usually increased. As the number of layers of the memory chip increases, the difficulty of manufacturing the memory chip will increase, especially for electrodes that need to run through multiple storage layers. The manufacturing difficulty is even greater.
  • the multi-layer storage unit is divided into multiple storage sub-units, and each storage sub-unit is a separately manufactured storage structure, which reduces the difficulty of the manufacturing process and facilitates mass production.
  • the multi-layer structure of the memory chip is decomposed into multiple storage sub-units that can be manufactured separately, and the number of layer structures of each storage sub-unit is less than the total number of layer structures of the memory chip. This will effectively reduce the difficulty of etching the storage layer and the insulating layer, and reduce the difficulty of depositing the electrode.
  • the first electrodes of the plurality of storage sub-units of each storage unit are not connected to each other, and the peripheral circuit controls the access to data in the plurality of storage sub-units respectively.
  • the plurality of storage sub-units can be controlled separately to access data independently.
  • the insulating layer exists between two adjacent storage sub-units in the plurality of storage sub-units.
  • the insulating layer isolates the first electrodes of the two adjacent storage sub-units, so that the first electrodes of the two adjacent storage sub-units are not connected to each other, so that the two adjacent storage sub-units are two independent storage structures that can be manufactured separately, which is conducive to reducing the difficulty of the manufacturing process of the memory chip.
  • the first electrodes of the plurality of storage sub-units of each storage unit are connected to each other, and the peripheral circuit controls the access to data in the plurality of storage sub-units as a whole.
  • the plurality of storage sub-units can be uniformly controlled to access data.
  • a buffer layer is provided between the first electrode and the storage unit.
  • the material of the buffer layer may be carbon, and the embodiment of the present application does not limit the material of the buffer layer.
  • the buffer layer may prevent the material of the first electrode from diffusing with the material of the storage unit, and may also increase the interface contact. The provision of the buffer layer is conducive to improving the storage performance of the memory chip.
  • the gating layer between the first electrode and the storage unit.
  • the gating layer may be located outside the first electrode.
  • the gating layer acts as a switch to read and write required information according to user needs.
  • the storage part is made of a self-selectable material.
  • the storage part can be a memory chip made of a self-selectable material that integrates selectable and storage properties, so that a separate selectable layer does not need to be provided, simplifying the manufacturing process.
  • each of the storage sub-units includes a hole that penetrates the storage layer and the insulating layer, and the first electrode is formed in the hole.
  • another storage sub-unit is manufactured on the manufactured storage sub-unit.
  • Each storage sub-unit includes a hole for depositing the first electrode.
  • the number of layers of the storage layer of each storage sub-unit is less than or equal to 32.
  • the number of layers of the storage layer is greater than 32, the number of layers of the storage layer is too many, and the size of each storage sub-unit is thick, which is not conducive to the deposition of the storage part and the first electrode in terms of process.
  • the memory chip is divided into multiple independent memory sub-units, which reduces the process difficulty of memory chip manufacturing. Each memory sub-unit can be manufactured separately, with fewer layers, and the manufacturing process difficulty is reduced. Multiple memory sub-units can be stacked to increase the storage capacity of the memory chip.
  • the material of the storage unit is one of a phase change material, an oxide, a resistive material, a ferroelectric material, and a magnetic storage material.
  • the phase change material may be a chalcogenide compound, and the phase change material may also be a Sb (antimony) element, a Ge-Te (germanium-tellurium) binary compound, a Ge-Sb (germanium-antimony) binary compound, a Sb-Te (antimony-tellurium) binary compound, a Bi-Te (bismuth-tellurium) binary compound, an In-Se (indium-selenium) binary compound, a Ge-Sb-Te (germanium-antimony-tellurium) ternary compound, a Ge-Bi-Te (germanium-bismuth-tellurium) ternary compound, a Ge-Sb-Bi-Te (germanium-antimony-bismuth-tellurium) quaternary compound,
  • the oxide may be silicon oxide, etc.
  • the resistive material may be binary metal oxide, bismuth telluride, HfO2 (hafnium dioxide) or SiO2 (silicon dioxide), etc.
  • the ferroelectric material may be lead zirconium titanium, aluminum oxide or HfZrO (hafnium zirconium oxide), etc.
  • the magnetic storage material may be hexagonal ferrite, iron fluoride, FeO (iron oxide) or CoO (cobalt oxide), etc.
  • Phase change materials are used to obtain phase change memory chips, oxides are used to obtain three-dimensional flash memory chips, resistive materials are used to obtain resistive memory chips, ferroelectric materials are used to obtain ferroelectric memory chips, or magnetic storage materials are used to obtain magnetoresistive memory chips.
  • the materials of the storage parts of different storage subunits may be the same or different.
  • the storage parts of the multiple storage subunits are made of different materials.
  • Each storage subunit in the implementation of the present application is an independent storage structure and can be manufactured separately, which is convenient for depositing storage parts of different materials, so that the multiple storage subunits are storage structures with different access mechanisms.
  • Multiple storage subunits are stacked together to form a storage chip with multiple storage advantages.
  • the storage part of a storage subunit can use phase change material to obtain a storage subunit with phase change storage advantages
  • the storage part of another storage subunit can use resistive material to obtain a storage subunit with resistive storage advantages, which is conducive to obtaining a storage chip with good comprehensive performance, and the storage material can be flexibly configured as needed.
  • the present application provides a storage device, comprising a peripheral circuit and the storage chip described in any one of the embodiments of the first aspect, wherein the peripheral circuit is used to control access to data in the storage chip.
  • the present application provides an electronic device, comprising a processor and a storage device as described in any one of the embodiments of the second aspect, wherein the processor is used to read data from the storage device or write data into a storage chip of the storage device.
  • FIG1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • FIG2 is a simplified schematic diagram of a memory chip provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the internal structure of a memory chip provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the internal structure of another memory chip provided in an embodiment of the present application.
  • FIG5 is a schematic structural diagram of a substrate and a storage subunit provided in an embodiment of the present application.
  • FIG6 is a schematic structural diagram of a storage subunit from another perspective provided in an embodiment of the present application.
  • FIG7 is a flow chart of manufacturing a memory chip provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a structure in which an insulating layer and a second electrode are deposited on a substrate according to an embodiment of the present application;
  • FIG9 is a schematic diagram of a structure for forming a hole provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of a structure for forming a concave portion provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a deposition storage unit and a first electrode provided in an embodiment of the present application;
  • FIG. 12 is a schematic diagram of a structure for forming a connection portion provided in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the structure of an electronic device 100.
  • the electronic device 100 may be a laptop computer, a tablet computer, a mobile phone, a wearable device, a server, a computer, and the like. In the embodiments of the present application, the electronic device 100 is described as a mobile phone.
  • the electronic device 100 may include a processor 10 and a storage device 11, and the processor 10 is used to read data from the storage device 11 or write data to the storage device 11.
  • the storage device 11 may include a peripheral circuit 12 and a storage chip 20.
  • the peripheral circuit 12 is used to control the access of data in the storage chip 20.
  • FIG1 merely schematically shows the position and structure of the processor 10 , the peripheral circuit 12 , and the memory chip 20 .
  • the processor 10 , the peripheral circuit 12 , and the memory chip 20 may be located at other positions of the electronic device 100 , and this application does not limit this.
  • the electronic device 100 also includes one or more structures such as a housing 101, a display screen 102, a front camera 103 and a battery 104.
  • the display screen 102 is fixed to the housing 101, and the display screen 102 is used to display images to meet the user's usage needs.
  • the display screen 102 may include a display layer and a touch layer covering the display layer, and the touch layer can be used for the user to perform touch operations.
  • the touch layer can be a transparent glass cover, plastic or other materials with good light transmittance.
  • the display layer can be a liquid crystal display screen, or an organic light emitting diode display screen, etc.
  • the display layer may include a display area and a non-display area, and the non-display area is located on one side of the display area, or is surrounded by the periphery of the display area, wherein in some electronic devices, the non-display area may not be provided.
  • the front camera 103 is used to take pictures or videos to achieve the shooting needs of the electronic device 100.
  • the battery 104 is located inside the electronic device 100 and is used to power the electronic device 100.
  • the processor 10 and the battery 104 are both located on the side where the non-display surface of the display screen 102 is located.
  • the electronic device 100 includes a rear camera (not shown in FIG. 1 ) for taking pictures or videos.
  • the housing 101 of the electronic device 100 may also be provided with an earphone jack and the like.
  • FIG. 1 is only a schematic diagram of the structure of an electronic device 100 , and the present application does not limit the structure of the electronic device 100 .
  • FIG. 2 is a simplified schematic diagram of the structure of the memory chip 20
  • FIG. 3 is a schematic diagram of the internal structure of the memory chip 20.
  • the memory chip 20 may include a plurality of memory cells 210, and the plurality of memory cells 210 may be understood as at least two memory cells 210, and the plurality of memory cells 210 may be arranged in an array to form the memory chip 20.
  • Each memory cell 210 includes a substrate 21 and a plurality of memory sub-units 22, and FIG. 2 and FIG. 3 take three memory sub-units 22 as an example.
  • the plurality of memory sub-units 22 may be understood as at least two memory sub-units 22.
  • the plurality of memory sub-units 22 are sequentially stacked on the same side of the substrate 21.
  • each storage subunit 22 includes a storage layer 220 and an insulating layer 224 alternately stacked, and a first electrode 221 penetrating the storage layer 220 and the insulating layer 224.
  • the storage layer 220 includes a second electrode 222 and a storage portion 223 for storing data
  • the first electrode 221 is electrically connected to the storage portions 223 of all storage layers 220 of the storage subunit 22, and the first electrode 221 and the second electrode 222 are used to connect to the peripheral circuit 12 so as to control the access of data in the storage portion 223 through the peripheral circuit 12.
  • first electrode 221 and the second electrode 222 are arranged crosswise, and the storage unit 223 is located at the intersection between the first electrode 221 and the second electrode 222.
  • the crosswise arrangement of the first electrode 221 and the second electrode 222 can be understood as the first electrode 221 and the second electrode 222 are not parallel.
  • the first electrode 221 can be perpendicular to the second electrode 222, and the storage unit 223 is located at the vertical intersection between the first electrode 221 and the second electrode 222.
  • the first electrode 221 and the second electrode 222 may also be non-perpendicular.
  • At least one storage layer 220 and at least two insulating layers 224 are alternately stacked on the substrate 21.
  • the storage layer 220 is one layer
  • the storage layer 220 is located between two insulating layers 224.
  • one insulating layer 224 is located between the storage layer 220 and the substrate 21, and the remaining insulating layers 224 are located between two adjacent storage layers 220, so that the two adjacent storage layers 220 are insulated.
  • the number of layers of the storage layer 220 can be one layer, two layers, three layers, four layers, or five layers, etc., and the number of stacked layers of the storage layer 220 is not limited in the embodiment of the present application.
  • the number of layers of the memory chip 20 is usually increased (i.e., the number of stacked memory layers 220 and the number of insulating layers 224 are increased). As the number of layers of the memory chip 20 increases, the difficulty of manufacturing the memory chip 20 increases.
  • the multiple storage sub-units 22 of the embodiment of the present application are multiple independent storage sub-units that can be manufactured separately, which reduces the difficulty of manufacturing the multi-layer memory chip. The difficulty of depositing the storage part 223 and the difficulty of depositing the first electrode 221 are reduced, and mass production is facilitated.
  • the memory chip 20 has 128 layers, that is, the memory chip 20 includes 128 layers of memory layers 220 stacked with the substrate 21.
  • this hole is used to deposit the first electrode
  • This continuous hole is usually a narrow and long hole. The more layers this continuous hole passes through, the longer the size of the hole.
  • each memory sub-unit 22 can include 32 layers.
  • the number of layers of each memory sub-unit 22 is less than the total number of layers of the memory chip 20.
  • the length of the hole for depositing the first electrode of each memory sub-unit 22 is reduced, which is convenient for depositing the first electrode and for depositing the memory part 223 in the recess. Different memory sub-units 22 are made separately.
  • one memory sub-unit 22 After one memory sub-unit 22 is made, it is stacked, deposited, and another memory sub-unit 22 is made. They do not affect each other, which reduces the difficulty of making the memory chip 20. And because the manufacturing process is simple, multiple memory sub-units 22 can be superimposed as needed, effectively increasing the storage capacity of the memory chip 20.
  • the memory chip 20 in the embodiment of the present application is divided into a plurality of memory sub-units 22, each memory sub-unit 22 has a small number of layers, and the deposition of the memory portion 223 and the deposition of the first electrode 221 can be deposited by using existing mature technologies, without the need to develop new deposition processes.
  • the memory chip 20 is divided into a plurality of memory sub-units 22, the number of memory layers 220 in each memory sub-unit 22 is reduced, so that the path of signal transmission is short and the signal transmission speed is substantially the same.
  • the first electrodes 221 of the multiple storage sub-units 22 of each storage unit 210 are not connected to each other, and the peripheral circuit 12 controls the access to the data in the multiple storage sub-units 22 respectively. That is, the first electrodes 221 of the multiple storage sub-units 22 of each storage unit 210 are not conductive and are two independent electrodes.
  • the multiple storage sub-units 22 are multiple storage structures that can be controlled independently.
  • the large-sized electrodes are divided into multiple independent electrodes (i.e., multiple first electrodes 221), so that the multiple storage sub-units 22 are multiple independent storage sub-units that can be manufactured separately, which is conducive to reducing the difficulty of manufacturing the memory chip 20.
  • an insulating layer 224 is provided between two adjacent storage sub-units 22 in the plurality of storage sub-units 22, so that the first electrodes 221 of the plurality of storage sub-units 22 of each storage unit 210 are insulated, that is, not interconnected, and the plurality of storage sub-units 22 are separated into a plurality of independent storage structures that can be manufactured separately, thereby reducing the difficulty of the manufacturing process of the storage chip 20.
  • the storage subunit 22 includes a bit line 229, which is located on a side of the first electrode 221 away from the substrate 21 and is electrically connected to the first electrode 221.
  • the bit line 229 is used to electrically connect the peripheral circuit 12.
  • the bit line 229 and the first electrode 221 can be electrically connected through a connecting portion 2290.
  • the second electrode 222 can be a word line.
  • the bit line 229, the connecting portion 2290 and the first electrode 221 are all conductive materials and can be regarded as a whole and are conductive to each other.
  • the spacing L1 between the bit line 229 of a storage subunit 22 and the first electrode 221 of the adjacent storage subunit 22 is greater than or equal to 50 nm.
  • the spacing L1 between the bit line 229 of a storage subunit 22 and the first electrode 221 of the adjacent storage subunit 22 may be 60 nm, 70 nm, 80 nm or 100 nm, etc.
  • the safety distance between the bit line 229 of a storage subunit 22 and the first electrode 221 of the adjacent storage subunit 22 is set by limiting the spacing between the bit line 229 of a storage subunit 22 and the first electrode 221 of the adjacent storage subunit 22, so as to prevent the insulating layer between the bit line 229 of a storage subunit 22 and the first electrode 221 of the adjacent storage subunit 22 from being broken down and turned on after a voltage is applied to the bit line 229 and the first electrode 221 of two adjacent storage subunits 22, thereby affecting the information access of the storage subunit 22 and causing information access confusion.
  • the spacing between the bit line 229 of a storage sub-unit 22 and the first electrode 221 of an adjacent storage sub-unit 22 is less than 50 nm, the spacing between the bit line 229 of a storage sub-unit 22 and the first electrode 221 of an adjacent storage sub-unit 22 is too small, and the structure between the bit line 229 of a storage sub-unit 22 and the first electrode 221 of an adjacent storage sub-unit 22 is easily broken down after voltage is applied.
  • the spacing between the bit line 229 of a storage sub-unit 22 and the first electrode 221 of an adjacent storage sub-unit 22 may also be less than 50 nm.
  • FIG. 4 is a schematic diagram of the structure of another memory chip 20.
  • the first electrodes 221 of the multiple memory sub-units 22 of each memory cell 210 are connected to each other, and the peripheral circuit 12 controls the access of data in the multiple memory sub-units 22 as a whole.
  • the multiple memory sub-units 22 are uniformly controlled.
  • the number of layers of the storage layer 220 of the storage subunit 22 far from the substrate 21 may be set to be smaller than the number of layers of the storage layer 220 of the storage subunit 22 close to the substrate 21.
  • the surface of each storage subunit 22 far from the substrate 21 may be There is an unevenness problem.
  • the stacking of multiple storage sub-units 22 makes the structure of the storage sub-unit 22 farther away from the substrate 21 more uneven. Even if the degree of unevenness can be reduced by mechanical flattening during the manufacturing process, it cannot be completely eliminated.
  • the embodiment of the present application reduces the number of layers of the storage sub-units 220 away from the substrate 21 by setting the number of layers of the storage layer 220 of the storage sub-unit 22 away from the substrate 21 to be smaller than the number of layers of the storage layer 220 of the storage sub-unit 22 close to the substrate 21, thereby avoiding that the storage layer of the memory chip 20 is mainly concentrated in the uneven storage sub-units away from the substrate 21, which affects the performance and structural stability of the memory chip 20.
  • the number of storage layers 220 of multiple storage sub-units 22 can be reduced successively, or some storage sub-units 22 can have the same number of layers while some storage sub-units 22 can have a reduced number of layers.
  • the specific number can be adjusted according to demand and performance, and this application does not limit this.
  • Each storage subunit 22 includes a hole 225, the hole 225 passes through the storage layer 220 and the insulating layer 224, and the first electrode 221 is formed in the hole 225.
  • the hole 225 can be obtained by etching the storage layer 220 and the insulating layer 224.
  • the hole 225 can pass through multiple storage layers 220 and multiple insulating layers 224.
  • the number of layers of the storage layer 220 of each storage subunit 22 is less than or equal to 32, which is conducive to avoiding too many layers of the storage layer 220 of each storage subunit 22, resulting in a thicker size of each storage subunit 22, which is not conducive to the deposition of the storage part 223 and the first electrode 221 in terms of process.
  • the embodiment of the present application divides the memory chip 20 into a plurality of independent memory sub-units 22, which reduces the process difficulty of manufacturing the memory chip 20.
  • Each memory sub-unit 22 can be manufactured separately, with fewer layers, and the manufacturing process difficulty is reduced.
  • Multiple memory sub-units 22 can be stacked to increase the storage capacity of the memory chip 20.
  • the number of memory layers 220 can also be greater than 32.
  • the number of memory layers 220 can be 64.
  • the material of the storage unit 223 may be a phase change material, an oxide, a resistive material, a ferroelectric material, or a magnetic storage material.
  • the phase change material may be a chalcogenide compound, and the phase change material may also be a Sb (antimony) element, a Ge-Te (germanium-tellurium) binary compound, a Ge-Sb (germanium-antimony) binary compound, a Sb-Te (antimony-tellurium) binary compound, a Bi-Te (bismuth-tellurium) binary compound, an In-Se (indium-selenium) binary compound, a Ge-Sb-Te (germanium-antimony-tellurium) ternary compound, a Ge-Bi-Te (germanium-bismuth-tellurium) ternary compound, a Ge-Sb-Bi-Te (germanium-antimony-bismuth-tellurium) quaternary compound, or any one or more
  • the oxide may be silicon oxide, etc.
  • the resistive material may be a binary metal oxide, bismuth telluride, HfO2 (hafnium dioxide) or SiO2 (silicon dioxide), etc.
  • the ferroelectric material may be lead zirconium titanium, aluminum oxide, or HfZrO (hafnium zirconium oxide), etc.
  • the magnetic storage material may be hexagonal ferrite, ferric fluoride, FeO (iron oxide) or CoO (cobalt oxide), etc. This application does not limit the specific materials used for phase change materials, oxides, resistive materials, ferroelectric materials, and magnetic storage materials.
  • the materials of the storage parts 223 of the multiple storage subunits 22 can be the same or different.
  • a phase change material can be used to obtain a phase change memory chip, which has the advantages of non-volatility, fast read and write speed, long life, stable storage, low power consumption, etc.
  • an oxide can be used to obtain a three-dimensional flash memory chip, which has the advantages of non-volatility, fast read and write speed, faster processing of larger workloads, small size, and durability
  • a resistive memory chip made of a resistive material can be used, which has the advantages of non-volatility, low operating voltage, low power consumption, and resistance to erasure
  • a ferroelectric material can be used to obtain a ferroelectric memory chip, which has the advantages of non-volatility, high durability, high-speed read and write, etc.
  • a magnetic storage material can be used to obtain a magnetoresistive memory chip, which has non-volatility, high capacity density and service life.
  • the storage parts 223 of the multiple storage subunits 22 can use different storage materials to obtain the storage chip 20.
  • the multiple storage subunits 22 in the embodiment of the present application are multiple independent storage structures, which can be made separately, so as to facilitate the deposition of storage parts 223 of different materials, so that the multiple storage subunits 22 are storage structures with different access mechanisms, and the multiple storage subunits 22 are stacked together to form a storage chip 20 with multiple storage advantages.
  • the storage part 223 of one storage subunit 22 can use phase change material to obtain a storage subunit 22 with phase change storage advantages
  • the storage part 223 of another storage subunit 22 can use resistive material to obtain a storage subunit 22 with resistive storage advantages, which is conducive to obtaining a storage chip 20 with good comprehensive performance, and the storage material can be flexibly configured as needed.
  • the storage parts 223 of at least two storage subunits 22 can be set to have different materials.
  • the storage subunit 22 includes a buffer layer 227, the buffer layer 227 is located at the periphery of the first electrode 221, and the buffer layer 227 is located between the first electrode 221 and the storage portion 223.
  • the material of the buffer layer 227 can be carbon, and the buffer layer 227 can prevent the material of the first electrode 221 from diffusing with the material of the storage portion 223, and can also increase the interface contact.
  • the provision of the buffer layer 227 is conducive to improving the storage performance.
  • FIG. 5 is a schematic diagram of the structure of a substrate 21 and a storage subunit 22.
  • FIG. 5 only schematically shows one storage subunit 22. It can be understood that the number of storage subunits 22 in the embodiment of the present application is at least two.
  • the storage subunit 22 also includes a gate
  • the gate layer 228 is located between the first electrode 221 and the storage part 223, and the gate layer 228 is also located between the buffer layer 227 and the first electrode 221.
  • the gate layer 228 acts as a switch to read and write information according to user needs.
  • the storage unit 223 may be a storage chip composed of a self-selectable storage material that integrates select properties and storage properties, so there is no need to set up a separate select layer.
  • FIG. 6 is a schematic diagram of the structure of a storage subunit 22 from another perspective.
  • the bit line 229 is provided with a first contact hole 2291, and the first contact hole 2291 is used to electrically connect to a peripheral circuit.
  • the first contact hole 2291 can be located at the edge of the bit line 229 to facilitate wiring to achieve electrical connection between the peripheral circuit and the bit line 229.
  • the second electrode 222 includes a second contact hole 2221, and the second contact hole 2221 can be located at the edge of the second electrode 222, and the second contact hole 2221 is used to connect to a peripheral circuit.
  • the present application provides a method for manufacturing a memory chip 20, as shown in FIG. 7, which is a flow chart of manufacturing the memory chip 20.
  • the method for manufacturing the memory chip 20 in one embodiment specifically includes the following steps:
  • the substrate 21 may be a substrate made of polycrystalline silicon, single crystal silicon, sapphire, aluminum nitride or glass.
  • the substrate 21 may be a rigid substrate or a flexible substrate. The present application does not limit the material of the substrate 21 and it may be selected as needed.
  • the storage subunit 22 includes a storage layer 220 and an insulating layer 224 that are alternately stacked, and a first electrode 221 that penetrates the storage layer 220 and the insulating layer 224.
  • the storage layer 220 includes a storage part 223 for storing data and a second electrode 222.
  • the first electrode 221 is electrically connected to the storage part 223 of all storage layers 220 of the storage subunit 22.
  • the first electrode 221 and the second electrode 222 are used to connect to the peripheral circuit 12 to control the access of data in the storage part 223 through the peripheral circuit 12.
  • each storage sub-unit 22 includes a storage layer 220 and an insulating layer 224 that are alternately stacked, and a first electrode 221 that penetrates the storage layer 220 and the insulating layer 224.
  • the storage layer 220 includes a storage part 223 for storing data and a second electrode 222.
  • the first electrode 221 is electrically connected to the storage part 223 of all storage layers 220 of the storage sub-unit 22.
  • the first electrode 221 and the second electrode 222 are used to connect to the peripheral circuit 12 to control the access of data in the storage part 223 through the peripheral circuit 12.
  • the first electrodes 221 of the multiple storage sub-units 22 of each storage unit 210 may or may not be conductive to each other.
  • the example in which the first electrodes 221 of the multiple storage sub-units 22 of each storage unit 210 may or may not be conductive to each other is used for description.
  • a storage sub-unit 22 can be first deposited on a substrate 21 to produce a storage sub-unit 22, and then another storage sub-unit 22 can be produced on the produced storage sub-unit 22.
  • the production of the two storage sub-units 22 does not affect each other.
  • the two storage sub-units 22 are produced independently, which can avoid the increase in the difficulty of the deposition process as the number of layers increases.
  • a method for manufacturing a storage subunit 22 specifically includes the following steps:
  • Figure 8 is a schematic diagram of the structure in which an insulating layer 224 and a second electrode 222 are deposited on a substrate 21.
  • the number of second electrodes 222 is four layers as an example.
  • the insulating layer 224 and the second electrode 222 are alternately stacked on the substrate 21.
  • the insulating layer 224 and the second electrode 222 can be deposited by chemical vapor deposition or other deposition methods, which is not limited in the present application.
  • the insulating layer 224 can be silicon dioxide, and the second electrode 222 can be tungsten or tin. However, the present application does not limit the material of the insulating layer 224 and the second electrode 222.
  • An insulating layer 224 is provided between the second electrode 222 and the substrate 21, and an insulating layer 224 is provided between adjacent second electrodes 222.
  • FIG. 9 is a schematic diagram of a structure for forming a hole 225.
  • the layer structure formed by the insulating layer 224 and the second electrode 222 can be etched to form a hole 225.
  • the number of holes 225 can be multiple, and the present application takes one hole 225 as an example.
  • the hole 225 penetrates the multi-layer insulating layer 224 and the multi-layer second electrode 222, and a gap can be provided between the hole 225 and the substrate 21, that is, the hole 225 does not penetrate the insulating layer 224 that is in direct contact with the substrate 21.
  • FIG10 is a schematic diagram of a structure for forming a recess 226.
  • a portion of the second electrode 222 may be removed by an etch-back process to form the recess 226.
  • the recess 226 is formed at one end of the second electrode 222 facing the hole 225.
  • FIG. 11 is a schematic diagram of the structure of depositing the storage part 223 and the first electrode 221.
  • the storage part 223 is deposited in the concave part 226, and the buffer layer 227, the gating layer 228 and the first electrode 221 are sequentially deposited in the hole 225, and the buffer layer 227 is located outside the gating layer 228.
  • the storage part 223 can be a self-selectable storage material integrating gating characteristics and storage characteristics, or the gating layer 228 may not be provided.
  • An insulating material is deposited on the insulating layer 224 farthest from the substrate 21, and the thickness of the insulating layer 224 is increased, so that the surface of the insulating layer 224 farthest from the substrate 21 that is away from the substrate covers the first electrode 221.
  • FIG12 is a schematic diagram of a structure for forming a connection portion 2290.
  • a first through hole 31 is provided on the uppermost insulating layer 224, and an electrode material such as tungsten is deposited in the first through hole 31 to form the connection portion 2290, and insulating material is continuously deposited to form a second through hole 32, and an electrode material such as tungsten is deposited in the second through hole 32 to form a bit line 229.
  • the steps of manufacturing another memory subunit 22 on a memory subunit 22 include: depositing an insulating layer 224 on a manufactured memory subunit 22, and a second electrode 222 on the insulating layer 224, and multiple layers of insulating layers 224 and multiple layers of second electrodes 222 can be alternately stacked and deposited on the manufactured memory subunit 22. Etching the insulating layer 224 and the second electrode 222 to form a hole 225 and a recess 226. Depositing the memory unit 223 in the recess 226, and depositing the first electrode 221 in the hole 225.
  • Another storage subunit 22 refers to the steps of manufacturing the storage subunit in Figures 3, 5 and 8 to 12, which will not be repeated here. Multiple storage subunits can be stacked according to the above manufacturing steps to form a multi-layer storage chip 20 with large storage capacity.
  • the present application deposits the storage unit 223 in the recess 226 and the first electrode 221 in the hole 225. If the number of layers of the storage layer 220 is large, the depth of the hole 225 is large, and the difficulty of depositing the storage unit 223 in the recess 226 of the multi-layer storage layer 220 increases. The difficulty of depositing the first electrode 221 in the hole 225 with a large depth also increases. This is also the case in the entire memory chip 20. If the present application does not divide the memory chip 20 into multiple independent memory sub-units, the manufacturing difficulty increases when a multi-layer structure is used to increase the storage capacity of the memory chip 20. The multiple memory sub-units in the embodiment of the present application can be manufactured separately, which reduces the process difficulty of manufacturing the memory chip 20 and facilitates mass production while ensuring a large storage capacity.

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Abstract

本申请涉及存储芯片、存储设备和电子设备。存储芯片（20）包括多个存储单元（210），每个存储单元（210）包括衬底（21）和多个存储子单元（22），多个存储子单元（22）层叠设置于衬底（21）上，每个存储子单元（22）包括交替层叠设置的存储层（220）及绝缘层（224），及贯穿存储层（220）与绝缘层（224）的第一电极（221），存储层（220）包括存储数据的存储部（223）及第二电极（222），第一电极（221）与存储子单元（22）的所有存储层（220）的存储部（223）电连接，第一电极（221）及第二电极（222）用于连接外围电路，以通过外围电路控制存储部中的数据的存取。本申请的多个存储子单元可以为独立的能够单独制作的结构，减小了存储芯片的制作难度。

Description

存储芯片、存储设备和电子设备
本申请要求于2022年10月11日提交中国专利局、申请号为202211239471.9、申请名称为“存储芯片、存储设备和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种存储芯片、存储设备和电子设备。
背景技术
随着数据存储技术的迅猛发展，用户对存储性价比的要求也越来越高。存储芯片是计算机中数据存放的主要介质，存储容量是存储芯片性能的关键指标之一。
存储芯片的容量提升一般是通过优化操作方式或对存储阵列架构进行优化来实现的。目前的存储芯片中堆叠层数增多导致制作难度增大且难以量产，当堆叠层数增多带来的负收益大于存储密度增加带来的正收益时，存储芯片的性价比不高。
因此，有必要提供一种新型的存储芯片，能够满足存储容量大、制作难度低、易于量产的需求。
发明内容
本申请实施例提供一种存储芯片、存储设备和电子设备。本申请实施例的多个存储子单元为可以单独制作的存储结构，减小了存储芯片的制作难度，易于量产。
第一方面，本申请实施例提供一种存储芯片。存储芯片包括多个存储单元，所述多个存储单元中的每个存储单元包括衬底和多个存储子单元，所述多个存储子单元层叠设置于所述衬底上，每个所述存储子单元包括交替层叠设置的存储层及绝缘层，及贯穿所述存储层与所述绝缘层的第一电极，所述存储层包括存储数据的存储部及第二电极，所述第一电极与所述存储子单元的所有存储层的存储部电连接，所述第一电极及所述第二电极用于连接外围电路，以通过所述外围电路控制所述存储部中的数据的存取。可以理解地，本申请的存储子单元的数量至少为两个。
本申请实施方式中，每个存储子单元的存储层的层数可以为一层、两层或三层等，存储层为至少两层时，至少两层存储层间隔且层叠于衬底，存储层与衬底之间设有绝缘层，相邻的两个存储层之间设有绝缘层。
为了增大存储芯片的存储容量，通常会增大存储芯片的层数，随着存储芯片的层数的增多，存储芯片制作的工艺难度会增大，尤其是对于需要贯穿多个存储层的电极，制作难度更大。本申请实施方式中将多层存储单元分成多个存储子单元，各个存储子单元为单独制作的存储结构，制作工艺难度减小、易于量产。将存储芯片的多层结构分解为可以单独制作的多个存储子单元，每个存储子单元的层结构数量均少于存储芯片总共的层结构数量，这样将有效减少对存储层和绝缘层刻蚀的难工艺度，降低沉积电极的工艺难度。
一种可能的实施方式中，所述每个存储单元的所述多个存储子单元的所述第一电极彼此不导通，所述外围电路分别对所述多个存储子单元中的数据的存取进行控制。在本申请实施方式中，多个存储子单元可以单独控制，独立的进行数据的存取。
一种可能的实施方式中，所述多个存储子单元中相邻的两个所述存储子单元之间存在所述绝缘层。绝缘层将相邻的两个存储子单元的第一电极隔离，使得相邻的两个存储子单元的第一电极之间互不连通，使得相邻的两个存储子单元为两个独立的可以单独制作的存储结构，有利于降低存储芯片的制作工艺难度。
一种可能的实施方式中，所述每个存储单元的多个存储子单元的第一电极彼此导通，所述外围电路将所述多个存储子单元作为一个整体对其中的数据的存取进行控制。本申请实施方式中，多个存储子单元可以受到统一的控制，进行数据的存取。
一种可能的实施方式中，所述第一电极与所述存储部之间存在缓冲层。缓冲层的材质可以为碳，本申请实施例对缓冲层的材质不做限定。缓冲层可以防止第一电极的材料与存储部的材料发生扩散，也可以增加界面接触，缓冲层的设置有利于提高存储芯片的存储性能。
一种可能的实施方式中，所述第一电极与所述存储部之间存在选通层。选通层可以位于第一电极的外侧。选通层起到开关的作用，根据用户需求读写所需的信息。
一种可能的实施方式中，所述存储部为自选通材料。存储部可以采用集选通特性与存储特性为一体的自选通材料组成的存储芯片，这样不用单独设置选通层，简化制作工艺。
一种可能的实施方式中，所述每个存储子单元包括贯穿所述存储层与绝缘层的孔，所述第一电极形成在所述孔中。在本申请实施方式中，一个存储子单元制作完成后，在制作完成的存储子单元上制作另一个存储子单元。每个存储子单元都包括沉积第一电极的孔。
一种可能的实施方式中，所述每个存储子单元的所述存储层的层数小于等于32。存储层的层数大于32时，存储层的层数过多，每个存储子单元的尺寸较厚，在工艺上不利于沉积存储部和第一电极。本申请实施方式中将存储芯片分为多个独立的存储子单元，降低了存储芯片制作的工艺难度，每个存储子单元可以单独制作，层数较少，制作工艺难度降低。多个存储子单元可以叠加，以增加存储芯片的存储容量。
一种可能的实施方式中，所述存储部的材质为相变材料、氧化物、阻变材料、铁电材料、磁存储材料中的一种。示例性地，相变材料可以为硫系化合物，相变材料还可以为Sb(锑)单质、Ge-Te(锗-碲)二元化合物、Ge-Sb(锗-锑)二元化合物、Sb-Te(锑-碲)二元化合物、Bi-Te(铋-碲)二元化合物、In-Se(铟-硒)二元化合物、Ge-Sb-Te(锗-锑-碲)三元化合物、Ge-Bi-Te(锗-铋-碲)三元化合物、Ge-Sb-Bi-Te(锗-锑-铋-碲)四元化合物，或者它们经元素掺杂形成的化合物中化学式不同的任意一种或多种。氧化物可以为氧化硅等，阻变材料可以为二元金属氧化物、碲化铋、HfO2(二氧化铪)或SiO2(二氧化硅)等，铁电材料可以为铅锆钛、氧化铝或HfZrO(氧化铪锆)等，磁存储材料可以为六方铁氧体、氟化铁、FeO(氧化铁)或CoO(氧化钴)等。采用相变材料得到相变存储芯片、采用氧化物得到立体闪存存储芯片、采用阻变材料阻变存储芯片、采用铁电材料得到铁电存储芯片或者采用磁存储材料得到磁阻存储芯片等。不同的存储子单元的存储部的材质可以相同也可以不同。
一种可能的实施方式中，所述多个存储子单元的所述存储部的材质不同。本申请实施方式中的每个存储子单元都是独立的存储结构，可以单独制作，便于沉积不同材质的存储部，使得多个存储子单元为存取机理不同的存储结构。多个存储子单元叠加在一起形成具有多种存储优势的存储芯片。示例性地，一个存储子单元的存储部可以采用相变材料以得到具有相变存储优势的存储子单元，另一个存储子单元的存储部可以采用阻变材料以得到具有阻变存储优势的存储子单元，有利于得到综合性能良好的存储芯片，且可以根据需要灵活配置存储材料。
第二方面，本申请提供一种存储设备，包括外围电路及第一方面中任一种实施方式所述的存储芯片，所述外围电路用于控制所述存储芯片中的数据的存取。
第三方面，本申请提供一种电子设备，包括处理器和第二方面中任一种实施方式所述的存储设备，所述处理器用于从所述存储设备中读取数据或者将数据写入所述存储设备存储芯片。
附图说明
为了更清楚地说明本发明实施例或背景技术中的技术方案，下面将对本发明实施例或背景技术中所需要使用的附图进行说明。
图1是本申请实施方式提供的一种电子设备的结构示意图；
图2是本申请实施方式提供的一种存储芯片的简化结构示意图；
图3是本申请实施方式提供的一种存储芯片的内部结构示意图；
图4是本申请实施方式提供的另一种存储芯片的内部结构示意图；
图5是本申请实施方式提供的一种衬底和存储子单元的结构示意图；
图6是本申请实施方式提供的一种存储子单元另一视角的结构示意图；
图7是本申请实施方式提供的一种存储芯片制作的流程图；
图8是本申请实施方式提供的一种在衬底上沉积绝缘层和第二电极的结构示意图；
图9是本申请实施方式提供的一种形成孔的结构示意图；
图10是本申请实施方式提供的一种形成凹部的结构示意图；
图11是本申请实施方式提供的一种沉积存储部及第一电极的结构示意图；
图12是本申请实施方式提供的一种形成连接部的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，图1是一种电子设备100的结构示意图。电子设备100可以为笔记本电脑、平板电脑、手机、可穿戴设备、服务器、计算机等产品。在本申请的实施例中，以电子设备100是手机为例进行描写。电子设备100可以包括处理器10和存储设备11，处理器10用于从存储设备11中读取数据或者将数据写入存储设备11。存储设备11可以包括外围电路12和存储芯片20。外围电路12用于控制存储芯片20中的数据的存取。
图1只是示意性的表示处理器10、外围电路12和存储芯片20的位置和结构，处理器10、外围电路12和存储芯片20可以位于电子设备100的其他位置，本申请对此不做限定。
电子设备100还包括壳体101、显示屏幕102、前置摄像头103和电池104等结构中的一个或多个。显示屏幕102固定至壳体101，显示屏幕102用于显示图像，满足用户的使用需求。显示屏幕102可以包括显示层和覆盖在显示层上的触摸层，触摸层可以供用户进行触摸操作，触摸层可以为透明玻璃盖板、塑料或者其他透光性好的材料。显示层可以为液晶显示屏，或者有机发光二极管显示屏等。显示层可包括显示区和非显示区，非显示区位于显示区的一侧，或者围设于显示区的外围，其中，在一些电子设备中，可以不设置非显示区。前置摄像头103用于拍摄图片或视频，实现电子设备100的拍摄需求。电池104位于电子设备100的内部，用于为电子设备100供电。处理器10和电池104均位于显示屏幕102的非显示面所在的一侧。
在一些实施方式中，电子设备100包括后置摄像头(图1未示)，用于拍摄图片或视频。电子设备100的壳体101上还可以设有耳机插口等。
需要说明的是，图1只是示意性的表示一种电子设备100的结构示意图，本申请对电子设备100的结构不作限定。
如图1、图2和图3所示，图2为存储芯片20的简化结构示意图，图3为存储芯片20的内部结构示意图。存储芯片20可以包括多个存储单元210，多个存储单元210可以理解为至少两个存储单元210，多个存储单元210可以呈阵列排布形成存储芯片20。每个存储单元210包括衬底21和多个存储子单元22，图2和图3以三个存储子单元22为例。多个存储子单元22可以理解为至少两个存储子单元22。多个存储子单元22依次层叠于衬底21的同一侧。
参阅图3，每个存储子单元22包括交替层叠设置的存储层220及绝缘层224，及贯穿存储层220与绝缘层224的第一电极221。存储层220包括第二电极222和用于存储数据的存储部223，第一电极221与存储子单元22的所有存储层220的存储部223电连接，第一电极221及第二电极222用于连接外围电路12，以通过外围电路12控制存储部223中的数据的存取。
可以理解地，第一电极221与第二电极222交叉设置，存储部223位于第一电极221和第二电极222之间的交叉处。第一电极221与第二电极222交叉设置可以理解为第一电极221和第二电极222不平行，示例性地，第一电极221可以垂直于第二电极222，存储部223位于第一电极221和第二电极222之间的垂直交叉处。其他实施方式中，第一电极221和第二电极222也可以不垂直。
本申请实施例中至少一个存储层220与至少两个绝缘层224交替层叠于衬底21。存储层220为一层时，存储层220位于两层绝缘层224之间。存储层220为至少两层时，其中一个绝缘层224位于存储层220与衬底21之间，其余的绝缘层224位于相邻的两个存储层220之间，以使相邻的两个存储层220之间绝缘。存储层220的层数可以为一层、两层、三层、四层或者五层等，本申请实施例中对存储层220的层叠数量不限。
为了增大存储芯片20的存储容量，通常会增大存储芯片20的层数(即层叠的存储层220的数量增多、绝缘层224的数量增多)，随着存储芯片20的层数的增多，存储芯片20制作的工艺难度会增大。本申请实施例的多个存储子单元22为多个可以单独制作的独立的存储子单元，减小了多层存储芯片的制作工艺难度， 使得存储部223的沉积难度减小，第一电极221的沉积难度减小，易于量产。
示例性地，以存储芯片20为128层为例，即存储芯片20包括128层与衬底21层叠的存储层220。现有技术中，需要通过刻蚀等工艺刻蚀能够贯穿128层的一个连续的孔(这个孔用于沉积第一电极)，还要通过这个连续的孔，在128层的每层的第二电极上刻蚀能够沉积存储部的凹部。这个连续的孔通常为既窄又长的孔，这个连续的孔穿过的层数越多，孔的尺寸越长，这样在既窄又长的孔内刻蚀能够沉积存储部的凹部、在这个孔内沉积第一电极、通过这个孔在凹部沉积存储部时，工艺难度增大，且制作良率低。本申请实施例可以将128层的存储芯片20分为多个存储子单元，以四个存储子单元为例，每个存储子单元22可以包括32层，每个存储子单元22的层数均少于存储芯片20的总层数，每个存储子单元22用于沉积第一电极的孔的长度减小，便于沉积第一电极，且便于在凹部内沉积存储部223。不同的存储子单元22单独制作，一个存储子单元22制作完成再堆叠、沉积、制作另一个存储子单元22，互不影响，减小了存储芯片20的制作难度。且由于制作工艺简单，可以根据需要进行多个存储子单元22的叠加，有效增加存储芯片20的存储容量。
本申请实施例中的存储芯片20分为多个存储子单元22，每个存储子单元22的层数较少，沉积存储部223及沉积第一电极221可以选择现有成熟的技术沉积，无需开发新的沉积工艺。此外，由于将存储芯片20分为多个存储子单元22，每个存储子单元22内的存储层220的数量减少，使得信号传输的路径短，信号传输速度基本一致。
在一些实施例中，参阅图3，每个存储单元210的多个存储子单元22的第一电极221彼此不导通，外围电路12分别对多个存储子单元22中的数据的存取进行控制。即每个存储单元210的多个存储子单元22的第一电极221之间是不导电的，是独立的两个电极。多个存储子单元22为多个可以独立控制的存储结构。本申请实施例中通过设置每个存储单元210的多个存储子单元22的第一电极221互不连通，将大尺寸的电极分为独立的多个电极(即多个第一电极221)，使得多个存储子单元22为多个可以单独制作的独立的存储子单元，有利于减小存储芯片20的制作难度。
示例性地，多个存储子单元22中相邻的两个存储子单元22之间设有绝缘层224。以使每个存储单元210的多个存储子单元22的第一电极221之间是绝缘的，即互不连通，将多个存储子单元22分离为多个独立的可以单独制作的存储结构，存储芯片20的制作工艺难度降低。
在一些实施例中，存储子单元22包括位线229，位线229位于第一电极221背离衬底21的一侧，且与第一电极221电连接，位线229用于电连接外围电路12。示例性地，位线229和第一电极221可以通过连接部2290电连接。第二电极222可以为字线。位线229、连接部2290和第一电极221均为导电材料，可以看作为一个整体，是彼此导通的。
参阅图3，一些实施例中，一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的间距L1大于等于50nm。示例性地，一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的间距L1可以为60nm、70nm、80nm或100nm等。本申请实施例通过限定一个存储子单元22的位线229与相邻的存储子单元22的第一电极221的间距设定一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的安全距离，防止相邻两个存储子单元22的位线229和第一电极221上施加电压后，一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的绝缘层被击穿导通，影响存储子单元22的信息存取，导致信息存取混乱。一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的间距小于50nm时，一个存储子单元22的位线229与相邻的存储子单元22的第一电极221的间距过小，施加电压之后容易导致一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的结构被击穿。其他实施方式中，只要一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间不会被击穿，一个存储子单元22的位线229与相邻的存储子单元22的第一电极221之间的间距也可以小于50nm。
在一些实施例中，参阅图4，图4为另一种存储芯片20的结构示意图。每个存储单元210的多个存储子单元22的第一电极221彼此导通，外围电路12将多个存储子单元22作为一个整体对其中的数据的存取进行控制。多个存储子单元22受到统一的控制。
一些实施例中，可以设置远离衬底21的存储子单元22的存储层220的层数小于靠近衬底21的存储子单元22的存储层220的层数。在存储子单元22制作的过程中，每个存储子单元22远离衬底21的表面会 存在不平整的问题，多个存储子单元22叠加使得越远离衬底21的存储子单元22的结构越不平整，即使在制作的过程中可以通过机械平坦化处理减小不平整的程度，但是并不能完全消除。本申请实施方式通过设置远离衬底21的存储子单元22的存储层220的层数小于靠近衬底21的存储子单元22的存储层220的层数，减少远离衬底21的存储子单元的层数，避免存储芯片20的存储层主要集中在不平整的远离衬底21的存储子单元，影响存储芯片20的性能和结构稳定性。
在一些实施例中，多个存储子单元22的存储层220数量可以依次减少，或者也可以有些存储子单元22的层数相同，有些存储子单元22的层数减少，具体可以根据需求及性能调整，本申请对此不做限定。
每个存储子单元22包括孔225，孔225贯穿存储层220和绝缘层224，第一电极221形成于孔225中。孔225可以通过在存储层220和绝缘层224上刻蚀得到。存储层220的数量为多个及绝缘层224的数量为多个时，孔225可以穿过多个存储层220和多个绝缘层224。
每个存储子单元22的层数越多，制作难度越大。示例性的，每个存储子单元22的存储层220的数量越多，在多个存储层220和多个绝缘层224中刻蚀形成容纳第一电极221的孔225的难度越大，刻蚀形成容纳存储部223的凹部226的难度也较大，沉积存储部223、第一电极221的难度增大。在一些实施例中，每个存储子单元22的存储层220的层数小于等于32，有利于避免每个存储子单元22的存储层220的层数过多，导致每个存储子单元22的尺寸较厚，在工艺上不利于沉积存储部223和第一电极221。
本申请实施例将存储芯片20分为独立的多个存储子单元22，降低了存储芯片20制作的工艺难度，每个存储子单元22可以单独制作，层数较少，制作工艺难度降低。多个存储子单元22可以叠加，以增加存储芯片20的存储容量。其他实施方式中，存储层220的数量也可以大于32，示例性地，存储层220的数量可以为64。
存储部223的材质可以为相变材料、氧化物、阻变材料、铁电材料、磁存储材料中的一种。示例性地，相变材料可以为硫系化合物，相变材料还可以为Sb(锑)单质、Ge-Te(锗-碲)二元化合物、Ge-Sb(锗-锑)二元化合物、Sb-Te(锑-碲)二元化合物、Bi-Te(铋-碲)二元化合物、In-Se(铟-硒)二元化合物、Ge-Sb-Te(锗-锑-碲)三元化合物、Ge-Bi-Te(锗-铋-碲)三元化合物、Ge-Sb-Bi-Te(锗-锑-铋-碲)四元化合物，或者它们经元素掺杂形成的化合物中化学式不同的任意一种或多种。氧化物可以为氧化硅等，阻变材料可以为二元金属氧化物、碲化铋、HfO2(二氧化铪)或SiO2(二氧化硅)等，铁电材料可以为铅锆钛、氧化铝、或HfZrO(氧化铪锆)等，磁存储材料可以为六方铁氧体、氟化铁、FeO(氧化铁)或CoO(氧化钴)等，本申请对相变材料、氧化物、阻变材料、铁电材料、磁存储材料的具体采用的材料不做限定。
多个存储子单元22的存储部223的材质可以相同也可以不同。比如可以采用相变材料得到相变存储芯片，相变存储芯片具有非易失性、读写速度快、寿命长、存储稳定、功耗低等优势；可以采用氧化物得到立体闪存存储芯片，闪存存储芯片具有非易失性、读写速度快、可以更快地处理更大的工作负载、体积小、耐用等优势；可以采用阻变材料阻变存储芯片，阻变存储芯片具有非易失性、低操作电压、低功耗、耐擦写等优势；可以采用铁电材料得到铁电存储芯片，铁电存储芯片具有非易失性、高耐久性、高速读写等优势，或者采用磁存储材料得到磁阻存储芯片，磁阻存储芯片具有非易失性、高容量密度及使用寿命。
多个存储子单元22的存储部223可以采用不同的存储材料，以得到存储芯片20。本申请实施方式中的多个存储子单元22是多个独立的存储结构，可以单独制作，便于沉积不同材质的存储部223，使得多个存储子单元22为存取机理不同的存储结构，多个存储子单元22叠加在一起形成具有多种存储优势的存储芯片20。示例性地，一个存储子单元22的存储部223可以采用相变材料以得到具有相变存储优势的存储子单元22，另一个存储子单元22的存储部223可以采用阻变材料以得到具有阻变存储优势的存储子单元22，有利于得到综合性能良好的存储芯片20，且可以根据需要灵活配置存储材料。本申请实施方式中，可以设置至少两个存储子单元22的存储部223的材质不同。
一些实施例中，参阅图3和图4，存储子单元22包括缓冲层227，缓冲层227位于第一电极221的外围，且缓冲层227位于第一电极221和存储部223之间。缓冲层227的材质可以为碳，缓冲层227可以防止第一电极221的材料与存储部223的材料发生扩散，也可以增加界面接触，缓冲层227的设置有利于提高存储性能。
如图5所示，图5为一种衬底21和存储子单元22的结构示意图。图5只是示意性的表示了一个存储子单元22，可以理解地，本申请实施例中的存储子单元22的数量至少为两个。存储子单元22还包括选通 层228，选通层228位于第一电极221和存储部223之间，选通层228也位于缓冲层227和第一电极221之间。选通层228起到开关的作用，根据用户需求读写信息。
一些实施例中，存储部223可以采用集选通特性与存储特性为一体的自选通存储材料组成的存储芯片，这样不用单独设置选通层。
如图6所示，图6为一种存储子单元22另一视角的结构示意图。位线229设有第一接触孔2291，第一接触孔2291用于电连接外围电路。第一接触孔2291可以位于位线229的边缘位置，便于布线，以实现外围电路与位线229的电连接。第二电极222包括第二接触孔2221，第二接触孔2221可以位于第二电极222的边缘，第二接触孔2221用于连接外围电路。
本申请提供一种存储芯片20的制作方法，如图7所示，图7为存储芯片20制作的流程图，一种实施方式中的存储芯片20的制作方法具体包括以下步骤：
S10、提供衬底21。
参阅图3，衬底21可以为多晶硅、单晶硅、蓝宝石、氮化铝或玻璃等材质的衬底，衬底21可以为刚性衬底也可以为柔性衬底，本申请对衬底21的材质不做限定，可以根据需要选取。
S20、在衬底21上制作一个存储子单元22。
参阅图3，存储子单元22包括交替层叠设置的存储层220及绝缘层224，及贯穿存储层220与绝缘层224的第一电极221，存储层220包括存储数据的存储部223及第二电极222，第一电极221与存储子单元22的所有存储层220的存储部223电连接，第一电极221及第二电极222用于连接外围电路12，以通过外围电路12控制存储部223中的数据的存取。
S30、在制作完成的一个存储子单元22上制作另一个存储子单元22。
参阅图3，每个存储子单元22均包括交替层叠设置的存储层220及绝缘层224，及贯穿存储层220与绝缘层224的第一电极221，存储层220包括存储数据的存储部223及第二电极222，第一电极221与存储子单元22的所有存储层220的存储部223电连接，第一电极221及第二电极222用于连接外围电路12，以通过外围电路12控制存储部223中的数据的存取。
每个存储单元210的多个存储子单元22的第一电极221可以彼此不导通，也可以彼此不导通，本申请实施例中以每个存储单元210的多个存储子单元22的第一电极221可以彼此不导通为例介绍。
本申请实施方式可以先在衬底21上沉积制作一个存储子单元22，然后在制作完成的一个存储子单元22上制作另一个存储子单元22，两个存储子单元22的制作互不影响，两个存储子单元22独立制作，可以避免随着层数增多沉积工艺的难度增大。
一种实施方式中的一个存储子单元22的制作方法具体包括以下步骤：
如图8所示，图8为在衬底21上沉积绝缘层224和第二电极222的结构示意图。本申请实施例中以第二电极222的数量为四层为例。在衬底21上交替层叠绝缘层224和第二电极222。绝缘层224和第二电极222可以采用化学气相沉积，也可以采用其它沉积方式，本申请对此不作限定。绝缘层224可以为二氧化硅，第二电极222可以为钨或锡，然而，本申请对绝缘层224和第二电极222的材质不做限定。第二电极222与衬底21之间设有绝缘层224，相邻的第二电极222之间设有绝缘层224。
如图9所示，图9为形成孔225的结构示意图。本申请实施例中可以刻蚀绝缘层224及第二电极222形成的层结构，以形成孔225。孔225的数量可以为多个，本申请以其中一个孔225为例。孔225贯穿多层的绝缘层224和多层的第二电极222，孔225与衬底21之间可以设有间距，也即孔225并没贯穿与衬底21直接接触的绝缘层224。
如图10所示，图10为形成凹部226的结构示意图。本申请实施例中可以通过回刻工艺去除部分的第二电极222形成凹部226。示例性地，在第二电极222朝向孔225的一端形成凹部226。
如图11所示，图11为沉积存储部223及第一电极221的结构示意图。在凹部226内沉积存储部223，在孔225内依次沉积缓冲层227、选通层228和第一电极221，缓冲层227位于选通层228的外侧。在一些实施例中，存储部223可以为集选通特性与存储特性为一体的自选通存储材料，也可以不设置选通层228。在最远离衬底21的绝缘层224上再沉积绝缘材料，增加绝缘层224的厚度，使得最远离衬底21的绝缘层224背离衬底的表面覆盖第一电极221。
如图12和图5所示，图12为形成连接部2290的结构示意图。在最上层的绝缘层224上设置通过第一通孔31，并在第一通孔31内沉积钨等电极材料形成连接部2290，继续沉积绝缘材料，并形成第二通孔32，在第二通孔32内沉积钨等电极材料，形成位线229。
参阅图3、图5及图8至图12，在一个存储子单元22上制作另一个存储子单元22的步骤包括：在一个制作完成的存储子单元22上沉积绝缘层224，在绝缘层224上第二电极222，多层的绝缘层224和多层的第二电极222可以交替层叠沉积于已经制作完成的存储子单元22。对绝缘层224和第二电极222进行刻蚀处理，形成孔225和凹部226。沉积存储部223于凹部226，沉积第一电极221于孔225。
另一个存储子单元22其他具体的制作的步骤参阅图3、图5及图8至图12中的存储子单元制作的步骤，这里不再赘述。多个存储子单元以上述制作步骤堆叠即可形成多层的、大存储容量的存储芯片20。
本申请在凹部226内沉积存储部223，在孔225内沉积第一电极221，如果存储层220的层数较多，那么孔225的深度较大，在多层存储层220的凹部226中沉积存储部223的难度增大，在深度较大的孔225沉积第一电极221的难度也增大，在整个存储芯片20中也是这样，如果没有本申请将存储芯片20分为多个独立的存储子单元，为了增大存储芯片20的存储容量采用多层结构时，制作难度增大。本申请实施例中的多个存储子单元可以单独制作，在保证大存储容量的基础上，减少了存储芯片20制作的工艺难度、易于量产。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种存储芯片，包括多个存储单元，其特征在于，所述多个存储单元中的每个存储单元包括衬底和多个存储子单元，所述多个存储子单元层叠设置于所述衬底上，所述多个存储子单元中的每个存储子单元包括交替层叠设置的存储层及绝缘层，及贯穿所述存储层与所述绝缘层的第一电极，所述存储层包括存储数据的存储部及第二电极，所述第一电极与所述存储子单元的所有存储层的存储部电连接，所述第一电极及所述第二电极用于连接外围电路，以通过所述外围电路控制所述存储部中的数据的存取。
  2. 如权利要求1所述的存储芯片，其特征在于，所述每个存储单元的所述多个存储子单元的所述第一电极彼此不导通，所述外围电路分别对所述多个存储子单元中的数据的存取进行控制。
  3. 如权利要求2所述的存储芯片，其特征在于，所述多个存储子单元中相邻的两个所述存储子单元之间存在所述绝缘层。
  4. 如权利要求1所述的存储芯片，其特征在于，所述每个存储单元的多个存储子单元的第一电极彼此导通，所述外围电路将所述多个存储子单元作为一个整体对其中的数据的存取进行控制。
  5. 如权利要求1至4任意一项所述的存储芯片，其特征在于，所述第一电极与所述存储部之间存在缓冲层。
  6. 如权利要求1至5任意一项所述的存储芯片，其特征在于，所述第一电极与所述存储部之间存在选通层。
  7. 如权利要求1至5任意一项所述的存储芯片，其特征在于，所述存储部为自选通材料。
  8. 如权利要求1至5任意一项所述的存储芯片，其特征在于，所述每个存储子单元包括贯穿所述存储层与绝缘层的孔，所述第一电极形成在所述孔中。
  9. 如权利要求1至8任意一项所述的存储芯片，其特征在于，所述每个存储子单元的所述存储层的层数小于等于32。
  10. 如权利要求1至9任意一项所述的存储芯片，其特征在于，所述多个存储子单元的所述存储部的材质不同。
  11. 一种存储设备，其特征在于，包括外围电路及权利要求1至10任意一项所述的存储芯片，所述外围电路用于控制所述存储芯片中的数据的存取。
  12. 一种电子设备，其特征在于，包括处理器和如权利要求11所述的存储设备，所述处理器用于从所述存储设备中读取数据或者将数据写入所述存储设备存储芯片。
PCT/CN2023/110919 2022-10-11 2023-08-03 存储芯片、存储设备和电子设备 WO2024078102A1 (zh)

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