WO2024077826A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024077826A1
WO2024077826A1 PCT/CN2023/076162 CN2023076162W WO2024077826A1 WO 2024077826 A1 WO2024077826 A1 WO 2024077826A1 CN 2023076162 W CN2023076162 W CN 2023076162W WO 2024077826 A1 WO2024077826 A1 WO 2024077826A1
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Prior art keywords
bit line
target
layer
pillar
sacrificial
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PCT/CN2023/076162
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English (en)
French (fr)
Inventor
郑孟晟
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长鑫存储技术有限公司
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Publication of WO2024077826A1 publication Critical patent/WO2024077826A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure and a method for preparing the same.
  • the size of the parasitic capacitance is positively correlated with the size of the dielectric constant of the isolation material, thereby reducing the impact of the parasitic capacitance between the bit lines on the device.
  • a stacked structure of nitride, oxide, and nitride is used.
  • the process of the stacked structure is complicated and will occupy the volume of the device.
  • the thickness of the isolation layer continues to shrink, and the effect of reducing parasitic capacitance is also weakened, which in turn leads to reduced electrical stability of the conductor device and reduced product yield.
  • a semiconductor structure and a method for manufacturing the same are provided.
  • one aspect of the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate, which includes an active area; forming a target bit line column on the top of the substrate, the target bit line column is electrically connected to the active area directly below it; forming a target bit line protection layer covering the outer surface of the target bit line column, the target bit line protection layer is located inside the side wall portion of the target bit line column and has a target gap.
  • forming a target bit line protection layer covering the outer surface of a target bit line column includes: forming a target sacrificial column, the target bit line column and the target sacrificial column are arranged alternately, there is a spacing groove between adjacent target bit line columns and target sacrificial columns, and the top surface of the target sacrificial column is higher than the top surface of the target bit line column; using a preset atomic layer deposition process to form a first sub-protective layer, the first sub-protective layer covers the outer surface of the target sacrificial column, the outer surface of the target bit line column, and the bottom surface of the spacing groove; using a preset chemical vapor deposition process to form a second sub-protective layer in the spacing groove, the top surface of the second sub-protective layer is not lower than the top surface of the target sub-protective layer, the portion of the first sub-protective layer located on the top surface of the target bit line column constitutes the target sub-protective layer, and the
  • the top surface of the substrate has a groove
  • the target bit line pillar is located on the surface of the active area exposed by the groove
  • forming the target sacrificial pillar includes: forming the target sacrificial pillars on the top surface of the substrate on opposite sides of the groove.
  • forming a target bit line pillar on the top of the substrate includes: forming an initial bit line pillar on the surface of the active area in the groove; depositing an initial protective layer, the initial protective layer covering the outer surface of the initial bit line pillar and the exposed top surface of the substrate; the portion of the initial protective layer located on the outer surface of the initial bit line pillar and the initial bit line pillar constitute the target bit line pillar.
  • forming target sacrificial pillars on the top surface of the substrate on opposite sides of the groove includes: forming a sacrificial layer with a flush top surface, the sacrificial layer covering the outer surface of the target sacrificial bit line pillars and filling the gaps between adjacent target bit line pillars; forming an initial patterned mask on the top surface of the sacrificial layer; etching the top of the sacrificial layer based on the initial patterned mask until the top surface of the target bit line pillars is exposed, and the remaining initial patterned mask and the sacrificial layer higher than the target bit line pillars constitute the target patterned mask; etching the remaining sacrificial layer along the thickness direction of the substrate based on the target patterned mask until the initial protective layer located on the top surface of the substrate is exposed, and the remaining sacrificial layer constitutes the target sacrificial pillars.
  • forming an initial patterned mask on the top surface of the sacrificial layer includes: forming A first mask layer; forming a graphic mask layer on the top surface of the first mask layer, wherein the graphic mask layer has an opening pattern, and the orthographic projection of the target bit line column on the top surface of the sacrificial layer is located inside the orthographic projection of the opening pattern on the top surface of the sacrificial layer; forming a first dielectric layer filled with the opening pattern, wherein the top surface of the first dielectric layer is higher than the top surface of the graphic mask layer; the first dielectric layer, the graphic mask layer and the first mask layer constitute an initial graphic mask.
  • the remaining initial patterned mask is removed.
  • a material of the first dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination thereof.
  • the top surface of the substrate between adjacent grooves is covered with an insulating protection layer; an initial bit line column is formed on the surface of the active area in the groove; the initial bit line column is formed on the surface of the active area in the groove, including: forming a bit line contact material layer that fills the groove and covers the insulating protection layer; forming a metal barrier layer, a bit line material layer, a protection material layer and a bit line mask layer stacked in sequence along the thickness direction of the substrate on the top surface of the bit line contact material layer, the metal barrier layer is adjacent to the bit line contact material layer; etching the protection material layer, the bit line material layer, the metal barrier layer and the bit line contact material layer along the thickness direction based on the bit line mask, and the remaining bit line contact material layer, the remaining metal barrier layer, the remaining bit line material layer and the remaining protection material layer constitute the initial bit line column.
  • the preset atomic layer deposition process includes at least one of the following features: the deposition rate range includes: 0.5 angstroms/second to 2 angstroms/second per second; the pressure range includes: 0.1 torr-50 torr; the temperature range includes: 25°C-600°C; the oxygen flow range includes: 0.1L-10L; the silane includes: di(isopropylamino)silane, bis(tert-butylamino)silane, bis(diethylamino)silane or a combination thereof.
  • the temperature range of the preset chemical vapor deposition process includes: 600°C-900°C.
  • the width of the spacing trenches is 5 nm-50 nm.
  • the target gap comprises an air gap.
  • the width of the initial bit line pillar is 1/2-1/3 of the width of the groove.
  • the material of the first mask layer includes silicon oxynitride, spin-on hard mask, spin-on carbon, or a combination thereof.
  • another aspect of the present disclosure provides a semiconductor structure, including a substrate, a target bit line pillar, a target bit line protection layer and a target gap;
  • the substrate includes an active area;
  • the target bit line pillar is located on the top of the substrate and is electrically connected to the active area directly below it;
  • the target bit line protection layer covers the outer surface of the target bit line pillar;
  • the target bit line protection layer is located inside the side wall portion of the target bit line pillar and has a target gap.
  • a top surface of the substrate has a recess
  • the target bit line pillar is located on a surface of the active region exposed by the recess.
  • the target gap comprises an air gap.
  • the target bit line pillar includes an initial bit line pillar and an initial bit line protection layer; the initial bit line pillar is located on the surface of the active area in the groove; and the initial bit line protection layer covers the outer surface of the initial bit line pillar.
  • the width of the initial bit line pillar is 1/2-1/3 of the width of the groove.
  • a target bit line column, a target bit line protection layer and a target gap are sequentially formed so that the target bit line protection layer is located inside the side wall portion of the target bit line column and has a target gap, thereby reducing the dielectric constant of the semiconductor structure, reducing the parasitic capacitance between the bit lines, improving the reliability and stability of the semiconductor device, and improving the yield of the product.
  • FIG1 is a schematic diagram of a process for preparing a semiconductor structure in an embodiment of the present disclosure
  • FIGS. 2a to 2c are schematic cross-sectional views of the structure obtained in step S20 of the method for preparing a semiconductor structure in one embodiment of the present disclosure
  • FIG3 is a schematic diagram of a process for preparing a semiconductor structure in another embodiment of the present disclosure.
  • 4a to 5c are schematic diagrams of cross-sectional structures obtained in step S30 of a method for preparing a semiconductor structure in an embodiment of the present disclosure.
  • the resistance-capacitance (RC) delay associated with the interconnection of conductive materials has become an important factor limiting the speed of semiconductor devices.
  • the distance between adjacent bit lines continues to decrease, resulting in an increase in parasitic effects.
  • the parasitic capacitance of the bit line increases the resistance-capacitance (RC) delay electrical stress of the semiconductor device, which in turn reduces the reliability and stability of the conductor device and reduces the product yield.
  • the present disclosure aims to provide a semiconductor structure and a method for preparing the same, which can at least reduce the parasitic capacitance generated by the shortened distance between bit lines in the semiconductor manufacturing process, and improve the reliability, stability and yield of the semiconductor structure.
  • a method for preparing a semiconductor structure includes:
  • Step S10 providing a substrate 10 including an active region 11;
  • Step S20 forming a target bit line pillar 100 on the top of the substrate 10, wherein the target bit line pillar 100 is electrically connected to the active region 11 directly below it;
  • Step S30 forming a target bit line protection layer 300 covering the outer surface of the target bit line pillar 100 .
  • the target bit line protection layer 300 is located inside the sidewall portion of the target bit line pillar 100 and has a target gap 321 .
  • a substrate 10 is provided, and the substrate 10 includes an active area 11.
  • a target bit line column 100 is formed on the top side of the substrate 10 away from the active area 11, and the target bit line column 100 is electrically connected to the active area 11 directly below it.
  • a target bit line protection layer 300 is formed to cover the outer surface of the target bit line column 100, and the target bit line protection layer 300 is located inside the sidewall portion of the target bit line column 100 and has a target gap 321.
  • the dielectric constant of the semiconductor structure is reduced, thereby reducing the parasitic capacitance between adjacent bit lines, and improving the reliability, stability and product yield of the semiconductor device.
  • the substrate 10 in step S10 may be made of semiconductor material, insulating material, conductive material or any combination thereof.
  • the substrate 10 may be a single-layer structure or a multi-layer structure. Structure.
  • the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the substrate 10 may be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator.
  • SOI silicon on insulator
  • P-type ions may be implanted into the substrate 10 by an ion implantation process to form a first type doped well region (not shown), and the P-type ions may include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF 2 ) ions and indium (In) ions.
  • a shallow trench isolation structure may be formed in the substrate 10.
  • the shallow trench isolation structure may isolate a plurality of active regions 11 arranged at intervals in the substrate 10.
  • the active region 11 may be formed by injecting N-type ions; correspondingly, in an embodiment where the silicon substrate includes an N-type substrate, the active region 11 may be formed by injecting P-type ions.
  • the active region may be a P-type active region or an N-type active region.
  • the P-type active region may form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) device, and the N-type active region may form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) device.
  • the N-type impurity ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.
  • the top surface of the substrate 10 between adjacent grooves 101 is covered with an insulating protection layer 102 ; and initial bit line pillars 110 are formed on the surface of the active region 11 in the groove 101 .
  • Figures 2a to 2b Please continue to refer to Figures 2a to 2b.
  • the initial bit line pillar 110 is formed on the surface of the active area 11 in the groove 101, including: forming a bit line contact material layer 111 that fills the groove 101 and covers the insulating protection layer 102; forming a metal barrier layer 112, a bit line material layer 113, a protection material layer 114 and a bit line mask 115 stacked in sequence along the thickness direction of the substrate 10 on the top surface of the bit line contact material layer 111, and the metal barrier layer 112 is adjacent to the bit line contact material layer 111; etching the protection material layer 114, the bit line material layer 113, the metal barrier layer 112 and the bit line contact material layer 111 along the thickness direction based on the bit line mask 115, and the remaining bit line contact material layer 111, the remaining metal barrier layer 112, the remaining bit line material layer 113 and the remaining protection material layer 114 constitute the initial bit line pillar 110, and the thickness direction of the substrate 10 can be the OY direction.
  • the material of the bit line contact material layer 111 may include polysilicon; the materials of the insulating protection layer 102 and the metal barrier layer 112 may include silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof, for example, tantalum nitride or titanium nitride and have good blocking capability; the material of the bit line material layer 113 may include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride or a combination thereof, for example, ruthenium, tungsten, gold or silver are all low-resistance metals, which can further reduce the resistance of the bit line material layer 113 and improve the operating speed of the device.
  • the width d of the initial bit line pillar 110 can be set according to the width D of the groove 101.
  • the width d of the initial bit line pillar 110 can be set in the range of 1/2D to 1/3D.
  • d can be set to 1/2D, 5/12D or 1/3D, etc., so as to further reduce the connection impedance and improve product performance.
  • forming a target bit line pillar 100 on the top of the substrate 10 includes: forming an initial bit line pillar 110 on the surface of the active region 11 in the groove 101; depositing an initial protection layer 120, the initial protection layer 120 covers the outer surface of the initial bit line pillar 110 and the exposed top surface of the substrate 10; the portion of the initial protection layer 120 located on the outer surface of the initial bit line pillar 110 and the initial bit line pillar 110 constitute the target bit line pillar 100.
  • the initial protection layer 120 covers the target bit line pillar 100, which can prevent the conductive material in the target bit line pillar 100 from being oxidized, thereby reducing the failure frequency of the device.
  • an atomic layer deposition process can be used to form the initial protective layer 120. Since the atomic layer deposition process has excellent conformality and uniformity when depositing on a three-dimensional complex surface, a uniform initial protective layer 120 can be formed on the outer surface of the initial bit line pillar 110 and the exposed top surface of the substrate 10, thereby improving the step coverage and conformal coverage, further avoiding oxidation of the conductive material in the target bit line pillar 100, and extending the mean time between failures.
  • the top surface of the substrate 10 has a groove 101 .
  • the target bit line pillar 100 is located on the surface of the active area 11 exposed by the groove 101 .
  • Forming the target sacrificial pillar 200 includes: The target sacrificial pillars 200 are formed on the top surfaces of the substrates 10 on both sides, and the target bit line pillars 100 are located in the grooves 101 to reduce the connection impedance and improve the product performance.
  • forming the target sacrificial pillars 200 on the top surfaces of the substrate 10 on opposite sides of the groove 101 includes: forming a sacrificial layer 210 with a flush top surface, the sacrificial layer 210 covers the outer surface of the target sacrificial bit line pillars, and fills the gaps between adjacent target bit line pillars 100; forming an initial patterned mask 220 on the top surface of the sacrificial layer 210; referring to FIG.
  • the thickness direction of the substrate 10 may be the OY direction, until the initial protective layer 120 located on the top surface of the substrate 10 is exposed.
  • the remaining sacrificial layer 210 constitutes the target sacrificial column 200.
  • the method of etching the sacrificial layer 210 includes wet etching and/or dry etching.
  • the sacrificial layer 210 may be etched using a plasma etching process.
  • Plasma etching refers to the use of a high-frequency glow discharge reaction to activate the reaction gas into active particles, such as from or free radicals. These active particles diffuse to the etched site to react with the etched material to form volatile products that are removed to achieve the purpose of etching.
  • the etching gas may include one or more of NF 3 , CF 3 , HF, and CHF 4 , thereby increasing the etching rate.
  • forming an initial patterned mask plate 220 on the top surface of the sacrificial layer 210 includes: forming a first mask layer 221 on the top surface of the sacrificial layer 210; forming a patterned mask layer 222 on the top surface of the first mask layer 221, wherein the patterned mask layer 222 has an opening pattern, and the orthographic projection of the target bit line pillar 100 on the top surface of the sacrificial layer 210 is located inside the orthographic projection of the opening pattern on the top surface of the sacrificial layer 210; forming a first dielectric layer 223 filled with the opening pattern, wherein the top surface of the first dielectric layer 223 is higher than the top surface of the patterned mask layer 222; the first dielectric layer 223, the patterned mask layer 222 and the first mask layer 221 constitute the initial patterned mask plate 220.
  • the material of the first dielectric layer 223 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride or a combination thereof to meet the actual needs of various application scenarios.
  • the material of the first mask layer 221 includes silicon oxynitride, spin-on hard mask, spin-on carbon, or a combination thereof.
  • spin-on carbon is a polymer solution containing high carbon, which has good filling properties, can reduce the generation of outgassing, and improve thermal stability and planarization performance.
  • the width d of the initial bit line pillar 110 can be set according to the width D of the groove 101.
  • the width d of the initial bit line pillar 110 can be set in the range of 1/2D to 1/3D.
  • d can be set to 1/2D, 5/12D or 1/3D, etc., so as to further reduce the connection impedance and improve product performance.
  • the remaining initial patterned mask 220 is removed to expose the top surface of the target sacrificial pillar 200.
  • the material of the initial patterned mask 220 may include photoresist or hard mask, etc.
  • the removal method may include ashing and wet cleaning; for the initial patterned mask 220 composed of hard mask such as silicon dioxide, the removal method includes wet etching and/or dry etching.
  • the initial patterned mask 220 may be etched by a laser etching process.
  • the laser etching process is to irradiate the surface of the etched part with a high-energy laser beam to melt or vaporize it, forming a groove of a certain depth to achieve the purpose of etching the material.
  • the use of the laser etching process can improve the yield and stability of the product, and realize one-time molding of different graphics and different angles, without consumables, pollution, and low cost.
  • the method for preparing a semiconductor structure, step S30: forming a target bit line protection layer 300 covering the outer surface of the target bit line pillar 100, the target bit line protection layer 300 being located inside the sidewall portion of the target bit line pillar 100 and having a target gap 321, further comprises:
  • Step S31 forming target sacrificial pillars 200, target bit line pillars 100 and target sacrificial pillars 200 are arranged alternately, adjacent target bit line pillars 100 and target sacrificial pillars 200 have spacing grooves 12 between them, and the top surface of the target sacrificial pillars 200 is higher than the top surface of the target bit line pillars 100;
  • Step S32 using a preset atomic layer deposition process to form a first sub-protection layer 310, the first sub-protection layer 310 covers the outer surface of the target sacrificial pillar 200, the outer surface of the target bit line pillar 100, and the bottom surface of the spacing trench 12;
  • Step S33 forming a second sub-protection layer 320 in the spacing groove 12 by a preset chemical vapor deposition process, wherein the top surface of the second sub-protection layer 320 is not lower than the top surface of the target sub-protection layer 311, the portion of the first sub-protection layer 310 located on the top surface of the target bit line pillar 100 constitutes the target sub-protection layer 311, and the second sub-protection layer 320 has a target gap 321;
  • Step S34 removing the portion of the first sub-protection layer 310 located on the outer surface of the target sacrificial pillar 200 and the target sacrificial pillar 200 , and the remaining first sub-protection layer 310 and the second sub-protection layer 320 constitute the target bit line protection layer 300 .
  • a first sub-protective layer 310 is formed by a preset atomic layer deposition process.
  • the first sub-protective layer 310 covers the outer surface of the target sacrificial pillar 200, the outer surface of the target bit line pillar 100, and the bottom surface of the spacing groove 12.
  • Atomic layer deposition is a technique for forming a deposited film by alternately passing a gas phase precursor pulse into a reactor and chemically adsorbing and reacting on a deposition substrate. When the precursor reaches the surface of the deposition substrate, it will chemically adsorb on the surface and react on the surface.
  • the surface reaction of atomic layer deposition is self-limiting.
  • the desired structure is formed by continuously repeating the self-limiting reaction in atomic layer deposition.
  • the precursor material may include a non-metallic precursor material and/or a metallic precursor material.
  • non-metal precursors include halides (SiCl 4 or AlCl 3 , etc.), nitrides (NH 3 , (CH 3 )NH 2 or BuNH 2 , etc.)
  • metal precursors include alkyl precursors (Ga(CH 3 ) 3 or Mg(C 2 H 5 ) 2 ), ⁇ -diketone precursors (La(thd) 3 or Ca(thd) 2 ), alkoxide precursors (Ta(OC 2 H 5 ) 5 or Zr[(OC)(CH 3 ) 3 ] 4 ) or alkylamine and silanamine-based precursors (Ti[N(C 2 H 5 CH 3 ) 2 ] 4 or Pr[N(SiMe 3 ) 2 ] 3 ) etc.; Traditional solution chemical deposition technology and physical deposition technology
  • atomic layer deposition technology is based on surface self-limitation and self-saturated adsorption reaction, so it has surface control.
  • the prepared structure has excellent three-dimensional conformality and large-area uniformity, and is more adaptable to complex high aspect ratio surface deposition processes.
  • the atomic layer deposition process can produce a smooth surface morphology that fits the filling layer tightly, thereby reducing the stress generated by the deposition process, for example
  • the atomic layer deposition low-fluorine tungsten technology can reduce the stress by one order of magnitude (GPa to hMPa), the fluorine content by 99%, and the resistivity by 30%.
  • the atomic layer deposition process is used to form the first sub-protective layer 310 to achieve uniform coverage of the outer surface of the target sacrificial column 200, the outer surface of the target bit line column 100, and the bottom surface of the spacing groove 12, so that the conformality, uniformity and step coverage of the deposition process of the first sub-protective layer 310 are improved, and the difficulty of the subsequent process of forming the gap is reduced.
  • a second sub-protection layer 320 is formed in the spacing groove 12 by a preset chemical vapor deposition process.
  • the top surface of the second sub-protection layer 320 is higher than the top surface of the target sub-protection layer 311, or is flush with the top surface of the target sub-protection layer 311.
  • the portion of the first sub-protection layer 310 located on the top surface of the target bit line pillar 100 constitutes the target sub-protection layer 311.
  • the second sub-protection layer 320 has a target gap 321.
  • Chemical vapor deposition is a technology that allows gaseous substances to chemically react on the surface of a solid and deposit on the surface to form a stable structure. Due to the fast chemical reaction speed, the gaseous substances have already chemically reacted to produce solid substances before reaching the solid surface. Therefore, according to the characteristics of the chemical vapor deposition process itself, when the chemical vapor deposition process is used to deposit on a surface with steps, the thickness from the bottom to the top of the step gradually increases. It gradually increases until it is closed at the top opening.
  • the thickness of the second sub-protective layer 320 deposited on the surfaces of both sides of the spacing groove 12 gradually increases from bottom to top along the OY direction. There is an opening portion that is not deposited in the spacing groove 12. It is closed until it is deposited to the top surface opening of the target bit line column 100 to form the second sub-protective layer 320 with the target gap 321 inside, thereby reducing the dielectric constant of the semiconductor structure and reducing the parasitic capacitance between the bit lines.
  • the sealing efficiency and the concentration of the medium with low dielectric constant in the target gap 321 are improved, and the parasitic capacitance between the bit lines is further reduced, thereby improving the reliability, stability and yield of the semiconductor device.
  • step S34 the portion of the first sub-protection layer 310 located on the outer surface of the target sacrificial pillar 200 and the target sacrificial pillar 200 are removed, and the remaining first sub-protection layer 310 and the second sub-protection layer 320 constitute the target bit line protection layer 300; the portion of the first sub-protection layer 310 located on the outer surface of the target sacrificial pillar 200 and the target sacrificial pillar 200 can be removed by an etching process.
  • the etching process includes a dry etching process and/or a wet etching process, and the dry etching process includes but is not limited to one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP).
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • HDP high concentration plasma etching
  • the target gap 321 is formed in the target protection layer to reduce the dielectric constant, thereby reducing the parasitic capacitance between the bit lines.
  • the deposition rate of the atomic layer deposition process can be set to a range of 0.5 angstroms per second to 2 angstroms per second, for example, the deposition rate of the atomic layer deposition process can be set to 0.5 angstroms per second, 0.8 angstroms per second, 1.1 angstroms per second, 1.4 angstroms per second, 1.7 angstroms per second, or 2 angstroms per second.
  • the pressure of the atomic layer deposition process can be set to a range of 0.1 torr to 50 torr, for example, the pressure of the atomic layer deposition process can be set to 0.1 torr, 0.5 torr, 2.5 torr, 12.5 torr, or 50 torr.
  • the temperature of the atomic layer deposition process can be set to a range of 25°C-600°C, for example, the temperature of the atomic layer deposition process can be set to 25°C, 140°C, 255°C, 370°C, 485°C, or 600°C.
  • the flow rate of oxygen in the atomic layer deposition process can be set to a range of 0.1L to 10L, for example, the flow rate of oxygen in the atomic layer deposition process can be set to 0.1L, 0.5L, 1L, 5L, or 10L.
  • the precursor material of the atomic layer deposition process may include silane, for example, the silane includes: di(isopropylamino)silane, bis(tert-butylamino)silane, bis(diethylamino)silane or a combination thereof.
  • the silane includes: di(isopropylamino)silane, bis(tert-butylamino)silane, bis(diethylamino)silane or a combination thereof.
  • the temperature range of the chemical vapor deposition process can be set to include 600°C to 900°C.
  • the temperature of the chemical vapor deposition process can be set to 600°C, 700°C, 800°C or 900°C, etc., so as to improve the adaptability to deposition of different structures and materials, and accurately and controllably reduce the parasitic capacitance between the bit lines, thereby further improving the reliability and stability of the semiconductor device.
  • the width of the spacing groove 12 ranges from 5 nm to 50 nm.
  • the width of the spacing groove 12 can be set to 5 nm, 20 nm, 35 nm or 50 nm, etc., so as to adapt to semiconductor device processes of different sizes.
  • the target gap 321 includes an air gap. Since the magnitude of the parasitic capacitance is positively correlated with the magnitude of the dielectric constant, in order to reduce the parasitic capacitance between the bit lines, a material with a smaller dielectric constant needs to be selected as the gap material between the bit lines. Therefore, air with a dielectric constant of 1 can be used as the gap to further reduce the parasitic capacitance between the bit lines.
  • steps or stages 3 may include a plurality of steps or a plurality of stages, these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.
  • a semiconductor structure including a substrate 10, a target bit line pillar 100, a target bit line protection layer 300 and a target gap 321; the substrate 10 includes an active region 11; the target bit line pillar 100 is located on the top of the substrate 10 and is electrically connected to the active region 11 directly below it; the target bit line protection layer 300 covers the outer surface of the target bit line pillar 100; the target bit line protection layer 300 is located inside the sidewall portion of the target bit line pillar 100 and has a target gap 321.
  • the target bit line pillar 100 By sequentially forming the substrate 10, the target bit line pillar 100, the target bit line protection layer 300 and the target gap 321, the target bit line pillar 100 has a target gap 321 inside the sidewall portion, thereby reducing the dielectric constant of the semiconductor structure, reducing the parasitic capacitance between the bit lines, improving the reliability and stability of the semiconductor device, and improving the yield of the product.
  • the semiconductor structure further includes a groove 101, and the groove 101 is located in the substrate 10
  • the target bit line pillar 100 is located on the surface of the active area 11 exposed by the groove 101, thereby reducing the connection impedance and improving the product performance.
  • the target bit line pillar 100 includes an initial bit line pillar 110 and an initial bit line protection layer (not shown in the figure); the initial bit line pillar 110 is located on the surface of the active area 11 in the groove 101; the initial bit line protection layer covers the outer surface of the initial bit line pillar 110, which can prevent the conductive material in the target bit line pillar 100 from being oxidized and reduce the failure frequency of the device.
  • the semiconductor structure further includes an insulating protection layer 102, which covers the top surface of the substrate 10 between adjacent grooves 101;
  • the initial bit line pillar 110 includes a bit line contact material layer 111, a metal barrier layer 112, a bit line material layer 113 and a protection material layer 114;
  • the bit line contact material layer 111 fills the groove 101 and covers the insulating protection layer 102;
  • the metal barrier layer 112, the bit line material layer 113, the protection material layer 114 and the bit line mask 115 are sequentially arranged on the top surface of the bit line contact material layer 111 along the thickness direction of the substrate 10, and the metal barrier layer 112 and the bit line contact material layer 111 are connected to each other.
  • the thickness direction of the substrate 10 can be an OY direction;
  • the material of the bit line contact material layer 111 can include polysilicon;
  • the material of the insulating protection layer 102 or the metal barrier layer 112 can include silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof, for example, tantalum nitride or titanium nitride, and has good blocking ability;
  • the material of the bit line material layer 113 can include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride or a combination thereof, for example, ruthenium, tungsten, gold or silver are all low-resistance metals, which can further reduce the resistance of the bit line material layer 113 and improve the operating speed of the device.
  • the width d of the initial bit line pillar 110 can be set according to the width D of the groove 101.
  • the width d of the initial bit line pillar 110 can be set in the range of 1/2D to 1/3D.
  • d can be set to 1/2D, 5/12D or 1/3D.
  • the target gap 321 includes an air gap. Since the magnitude of the parasitic capacitance is positively correlated with the magnitude of the dielectric constant, in order to reduce the parasitic capacitance between the bit lines, a material with a smaller dielectric constant needs to be selected as the gap material between the bit lines. Therefore, air with a dielectric constant of 1 can be used as the gap to further reduce the parasitic capacitance between the bit lines.
  • the semiconductor structure further includes a target bit line protection layer 300, the target bit line protection layer 300 covers the outer surface of the target bit line pillar 100, and the target gap 321 is located inside the sidewall portion of the target bit line protection layer 300 located at the target bit line pillar 100; in some embodiments, the target bit line protection layer 300 includes a first sub-protection layer 310 and a second sub-protection layer 320; the first sub-protection layer 310 covers the outer surface of the target bit line pillar 100 and the bottom surface of the spacing groove 12, and the first sub-protection layer 310 can be formed by a preset atomic layer deposition process, and the atomic layer deposition is A technique in which a gaseous precursor pulse is alternately introduced into a reactor and chemically adsorbed and reacted on a deposition substrate to form a deposited film.
  • atomic layer deposition When the precursor reaches the surface of the deposition substrate, it chemically adsorbs and reacts on the surface.
  • the surface reaction of atomic layer deposition is self-limiting.
  • Traditional solution chemical deposition techniques and physical deposition techniques such as sputtering or evaporation have poor deposition effects on the surface of three-dimensional complex structures due to the lack of surface control or the presence of sputtering shadow areas.
  • atomic layer deposition is based on surface self-limitation and self-saturated adsorption reactions, thus having surface controllability, and the prepared structure has excellent
  • the unique three-dimensional conformality and large-area uniformity have stronger adaptability to the surface deposition support of complex high aspect ratio.
  • the first sub-protection layer 310 is formed by the atomic layer deposition process to achieve uniform coverage of the outer surface of the target sacrificial column 200, the outer surface of the target bit line column 100 and the bottom surface of the spacing groove 12, so that the conformality, uniformity and step coverage of the deposition process of the first sub-protection layer 310 are improved, and the difficulty of the subsequent process of forming the gap is reduced; the top surface of the second sub-protection layer 320 is not lower than the top surface of the target sub-protection layer 311, and the second sub-protection layer 320 has the target
  • the gap 321 can be formed by a preset chemical vapor deposition process in the spacing groove 12, and the second sub-protection layer 320 has a target gap 321.
  • the gaseous substance has already reacted chemically to produce solid substances before reaching the solid surface. Therefore, according to the characteristics of the chemical vapor deposition process itself, in the process of forming the second sub-protection layer 320 by the chemical vapor deposition process and forming the target gap 321 inside the second sub-protection layer 320, the thickness of the second sub-protection layer 320 deposited on the surfaces of the spacing groove 12 increases from the bottom to the top along the OY direction.
  • the top surface of the target sacrificial column 200 is higher than the top surface of the target bit line column 100, the sealing efficiency and the concentration of the medium with a low dielectric constant in the target gap 321 are improved, thereby further reducing the parasitic capacitance between the bit lines, improving the reliability and stability of the semiconductor device, and improving the yield of the product.
  • the first sub-protective layer 310 is formed by an atomic layer deposition process.
  • the deposition rate of the atomic layer deposition process can be set to include: 0.5 angstroms per second to 2 angstroms per second.
  • the deposition rate of the atomic layer deposition process can be set to 0.5 angstroms per second, 0.8 angstroms per second, 1.1 angstroms per second, 1.4 angstroms per second, 1.7 angstroms per second, or 2 angstroms per second;
  • the atomic layer deposition process pressure can be set to include: 0.1 torr to 50 torr, for example, the atomic layer deposition process pressure can be set to 0.1 torr, 0.5 torr, 2.5 torr, 12.5 torr, etc.
  • the range of the atomic layer deposition process temperature can be set to include: 25°C-600°C, for example, the atomic layer deposition process temperature can be set to 25°C, 140°C, 255°C, 370°C, 485°C or 600°C, etc.
  • the range of the flow rate of oxygen in the atomic layer deposition process can be set to include: 0.1L to 10L, for example, the flow rate of oxygen in the atomic layer deposition process can be set to 0.1L, 0.5L, 1L, 5L or 10L, etc.
  • the precursor material of the atomic layer deposition process can include silane, for example, the silane includes: di(isopropylamino)silane, bis(tert-butylamino)silane, bis(diethylamino)silane or a combination thereof.
  • the second sub-protective layer 320 is formed by a chemical vapor deposition process, and the temperature range of the chemical vapor deposition process can be set to include 600°C to 900°C, for example, the temperature of the chemical vapor deposition process can be set to 600°C, 700°C, 800°C or 900°C, etc.
  • the adaptability to deposition of different structures and materials is improved, and the parasitic capacitance between bit lines is accurately and controllably reduced, thereby further improving the reliability and stability of semiconductor devices.

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Abstract

本公开涉及一种半导体结构及其制备方法，半导体结构制备方法包括：提供衬底，其内包括有源区；于衬底的顶部形成目标位线立柱，目标位线立柱与其正下方的有源区电连接；形成覆盖目标位线立柱的外表面的目标位线保护层，目标位线保护层位于目标位线立柱的侧壁部分的内部具有目标间隙。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开要求于2022年10月12日提交中国专利局、申请号为2022112472775、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路设计及制造技术领域，特别涉及半导体结构及其制备方法。
背景技术
随着集成电路制造工艺的不断发展，半导体器件的集成度不断提高，相邻位线之间的距离不断减小，导致产生的寄生效应增强，位线之间的寄生电容使得半导体器件的电应力增大，从而使得半导体器件的可靠性及稳定性降低。
传统的半导体制程中，通过在位线的表面覆盖具有低介电常数的隔离材料，寄生电容的大小与隔离材料的介电常数的大小呈正相关，从而降低位线之间的寄生电容对器件造成的影响，例如采用氮化物、氧化物、氮化物的叠层结构，但是叠层结构的制程复杂，且会占用器件的体积，随着半导体器件尺寸的不断微缩，隔离层的厚度不断缩小，降低寄生电容的效果也随之减弱，进而导致导体器件的电稳定性降低，产品良率下降。
发明内容
根据本公开的各种实施例，提供一种半导体结构及其制备方法。
根据一些实施例，本公开的一方面提供一种半导体结构制备方法，包括：提供衬底，其内包括有源区；于衬底的顶部形成目标位线立柱，目标位线立柱与其正下方的有源区电连接；形成覆盖目标位线立柱的外表面的目标位线保护层，目标位线保护层位于目标位线立柱的侧壁部分的内部具有目标间隙。
根据一些实施例，形成覆盖目标位线立柱的外表面的目标位线保护层包括：形成目标牺牲立柱，目标位线立柱与目标牺牲立柱交替排布，相邻的目标位线立柱与目标牺牲立柱之间具有间隔沟槽，目标牺牲立柱的顶面高于目标位线立柱的顶面；采用预设原子层沉积工艺形成第一子保护层，第一子保护层覆盖目标牺牲立柱的外表面、目标位线立柱的外表面，及间隔沟槽的底面；采用预设化学气相沉积工艺于间隔沟槽内形成第二子保护层，第二子保护层的顶面不低于目标子保护层的顶面，第一子保护层位于目标位线立柱的顶面的部分构成目标子保护层，第二子保护层内具有目标间隙；去除第一子保护层位于目标牺牲立柱外表面的部分及目标牺牲立柱，剩余的第一子保护层及第二子保护层构成目标位线保护层。
根据一些实施例，衬底的顶面具有凹槽，目标位线立柱位于凹槽暴露的有源区表面；形成目标牺牲立柱包括：于凹槽相对两侧的衬底的顶面均形成目标牺牲立柱。
根据一些实施例，于衬底的顶部形成目标位线立柱包括：于凹槽内有源区表面形成初始位线立柱；沉积初始保护层，初始保护层覆盖初始位线立柱的外表面及衬底的裸露的顶面；初始保护层位于初始位线立柱的外表面的部分及初始位线立柱构成目标位线立柱。
根据一些实施例，于凹槽相对两侧的衬底的顶面均形成目标牺牲立柱包括：形成顶面齐平的牺牲层，牺牲层覆盖目标牺牲位线立柱的外表面，以及填充满相邻的目标位线立柱之间的间隙；于牺牲层的顶面形成初始图形化掩膜版；基于初始图形化掩膜版刻蚀牺牲层的顶部，至暴露出目标位线立柱的顶面，剩余的初始图形化掩膜版及高于目标位线立柱的牺牲层构成目标图形化掩膜版；基于目标图形化掩膜版沿衬底的厚度方向刻蚀剩余的牺牲层，至暴露出位于衬底的顶面的初始保护层，剩余的牺牲层构成目标牺牲立柱。
根据一些实施例，于牺牲层的顶面形成初始图形化掩膜版包括：于牺牲层的顶面形成 第一掩膜层；于第一掩膜层的顶面形成图形化掩膜层，图形化掩膜层内具有开口图形，目标位线立柱在牺牲层的顶面的正投影，位于开口图形在牺牲层的顶面的正投影的内部；形成填充满开口图形的第一介质层，第一介质层的顶面高于图形化掩膜层的顶面；第一介质层、图形化掩膜层及第一掩膜层构成初始图形化掩膜版。
根据一些实施例，在形成目标牺牲立柱之后，及形成第一子保护层之前，去除剩余的初始图形化掩膜版。
根据一些实施例，第一介质层的材料包括：氧化硅、氮化硅、氮氧化硅、氮碳化硅或其组合。
根据一些实施例，相邻的凹槽之间的衬底的顶面覆盖有绝缘保护层；于凹槽内有源区表面形成初始位线立柱；于凹槽内有源区表面形成初始位线立包括：形成填充满凹槽并覆盖绝缘保护层的位线接触材料层；于位线接触材料层的顶面形成沿衬底的厚度方向依次叠置的金属阻挡层、位线材料层、保护材料层及位线掩膜版，金属阻挡层与位线接触材料层相邻；基于位线掩膜版沿厚度方向刻蚀保护材料层、位线材料层、金属阻挡层及位线接触材料层，剩余的位线接触材料层、剩余的金属阻挡层、剩余的位线材料层及剩余的保护材料层构成初始位线立柱。
根据一些实施例，预设原子层沉积工艺包括如下特征中至少一个：沉积速率范围包括：0.5埃/秒-每秒2埃/秒；压力范围包括：0.1torr-50torr；温度范围包括：25℃-600℃；氧气流量范围包括：0.1L-10L；硅烷包括：二(异丙氨基)硅烷、双(叔丁基氨基)硅烷、双(二乙氨基)硅烷或其组合。
根据一些实施例，预设化学气相沉积工艺的温度范围包括：600℃-900℃。
根据一些实施例，间隔沟槽的宽度为5nm-50nm。
根据一些实施例，目标间隙包括空气间隙。
根据一些实施例，初始位线立柱的宽度为凹槽的宽度的1/2-1/3。
根据一些实施例，第一掩膜层的材料包括：氮氧化硅、硬掩膜上旋体、旋涂碳或其组合。
根据一些实施例，本公开的又一方面提供一种半导体结构，包括衬底、目标位线立柱、目标位线保护层及目标间隙；衬底内包括有源区；目标位线立柱位于衬底的顶部且与其正下方的有源区电连接；目标位线保护层覆盖目标位线立柱的外表面；目标位线保护层位于目标位线立柱的侧壁部分的内部具有目标间隙。
根据一些实施例，衬底的顶面具有凹槽，目标位线立柱位于凹槽暴露的有源区表面。
根据一些实施例，目标间隙包括空气间隙。
根据一些实施例，目标位线立柱包括初始位线立柱及初始位线保护层；初始位线立柱位于凹槽内有源区表面；初始位线保护层覆盖初始位线立柱的外表面。
根据一些实施例，初始位线立柱的宽度为凹槽的宽度的1/2-1/3。
本公开实施例可以/至少具有以下优点：
本公开实施例中，通过依次形成目标位线立柱、目标位线保护层及目标间隙，使得目标位线保护层位于目标位线立柱的侧壁部分的内部具有目标间隙，从而减小半导体结构的介电常数，减小位线之间的寄生电容，提高半导体器件的可靠性与稳定性，提高产品的良率。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施 例的附图。
图1为本公开一实施例中一种半导体结构制备方法的流程示意图；
图2a至图2c为本公开一实施例中半导体结构制备方法中步骤S20所得截面结构示意图；
图3为本公开另一实施例中一种半导体结构制备方法的流程示意图；
图4a至图5c为本公开一实施例中半导体结构制备方法中步骤S30所得截面结构示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。在使用本文中描述的“包括”、“具有”、和“包含”的情况下，除非使用了明确的限定用语，例如“仅”、“由……组成”等，否则还可以添加另一部件。除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一个。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。
根据摩尔定律，随着半导体器件结构优化与工艺微缩的发展，尤其是在线宽低于1x的半导体器件制程中，与导电材料互连相关联的电阻-电容(RC)延迟已经成为限制半导体器件速度的重要因素。随着半导体器件集成度的增加，相邻位线之间的距离不断减小，导致所产生的寄生效应增强，位线的寄生电容使得半导体器件的电阻-电容(RC)延迟电应力增大，进而导致导体器件的可靠性与稳定性降低，产品良率下降。
本公开旨在提供一种半导体结构及其制备方法，至少能够降低在半导体制程中由于位线之间距离缩短所产生的寄生电容，提高半导体结构的可靠性、稳定性及良率。
请参考图1及图5c，在一些实施例中，提供了一种半导体结构制备方法，半导体结构制备方法包括：
步骤S10：提供衬底10，其内包括有源区11；
步骤S20：于衬底10的顶部形成目标位线立柱100，目标位线立柱100与其正下方的有源区11电连接；
步骤S30：形成覆盖目标位线立柱100的外表面的目标位线保护层300，目标位线保护层300位于目标位线立柱100的侧壁部分的内部具有目标间隙321。
请继续参考图1及图5c，在步骤S10中，提供衬底10，衬底10内包括有源区11；在步骤S20中，于衬底10的顶部远离有源区11的一侧形成目标位线立柱100，目标位线立柱100与其正下方的有源区11电连接；在步骤S30中，形成覆盖目标位线立柱100的外表面的目标位线保护层300，目标位线保护层300位于目标位线立柱100的侧壁部分的内部具有目标间隙321；通过在衬底10上依次形成目标位线立柱100、目标位线保护层300及目标位线立柱100内部的目标间隙321，减小半导体结构的介电常数，从而减小相邻位线之间的寄生电容，提高半导体器件的可靠性、稳定性及产品良率。
请参考图2a至图2b，在一些实施例中，步骤S10中衬底10可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底10可以为单层结构，也可以为多层 结构。例如，衬底10可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底10可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。本领域的技术人员可以根据衬底10上形成的晶体管类型选择衬底10类型，因此衬底10的类型不应限制本公开的保护范围。可以采用离子注入工艺向衬底10内注入P型离子，以形成第一类型掺杂阱区(未图示)，P型离子可以包括但不限于硼(B)离子、镓(Ga)离子、氟化硼(BF2)离子及铟(In)离子等中任一种或多种。
作为示例，请继续参阅图2a至图2b，衬底10内可以形成有浅沟槽隔离结构(Shallow Trench Isolation，简称STI)，浅沟槽隔离结构可以于衬底10内隔离出若干个间隔排布的有源区11。在衬底10包括P型衬底的实施例中，可以通过注入N型离子以形成有源区11；与之对应的，在硅衬底包括N型衬底的实施例中，可以通过注入P型离子以形成有源区11。相应地，有源区可以为P型有源区，也可以为N型有源区。P型有源区可以形成N型金属氧化物半导体(Negative channel Metal Oxide Semiconductor，简称NMOS)器件，N型有源区可以形成P型金属氧化物半导体(Positive channel Metal Oxide Semiconductor，简称PMOS)器件。N型杂质离子可以包括但不限于磷(P)离子、砷(As)离子及锑(Sb)离子等中任一种或多种。
请参考图2a至图2b，在一些实施例中，相邻的凹槽101之间的衬底10的顶面覆盖有绝缘保护层102；于凹槽101内有源区11表面形成初始位线立柱110。请继续参考图2a至图2b，于凹槽101内有源区11表面形成初始位线立柱110包括：形成填充满凹槽101并覆盖绝缘保护层102的位线接触材料层111；于位线接触材料层111的顶面形成沿衬底10的厚度方向依次叠置的金属阻挡层112、位线材料层113、保护材料层114及位线掩膜版115，金属阻挡层112与位线接触材料层111相邻；基于位线掩膜版115沿厚度方向刻蚀保护材料层114、位线材料层113、金属阻挡层112及位线接触材料层111，剩余的位线接触材料层111、剩余的金属阻挡层112、剩余的位线材料层113及剩余的保护材料层114构成初始位线立柱110，衬底10的厚度方向可以为OY方向。例如，位线接触材料层111的材料可以包括多晶硅；绝缘保护层102及金属阻挡层112的材料可以包括硅氧化物、氧化铝、氧化铪、氮氧化铪、氧化锆、氧化钽、氧化钛、锶钛氧化物或其组合，例如，氮化钽或氮化钛且具有良好的阻挡能力；位线材料层113的材料可以包括钛、钨、钽、钼、钴、铂、钛钨、氮化钨、氮化钛、氮硅化钛或其组合，例如，钌、钨、金或银都属于低电阻金属，能够进一步减小位线材料层113的电阻，提高器件的运行速度。
请参考图2c，在一些实施例中，可以根据凹槽101的宽度D设置初始位线立柱110的宽度d，可以设置初始位线立柱110的宽度d的范围包括1/2D至1/3D，例如可以设置d为1/2D、5/12D或1/3D等，从而进一步降低连接阻抗，提升产品性能。
请参考图2c，在一些实施例中，于衬底10的顶部形成目标位线立柱100包括：于凹槽101内有源区11表面形成初始位线立柱110；沉积初始保护层120，初始保护层120覆盖初始位线立柱110的外表面及衬底10的裸露的顶面；初始保护层120位于初始位线立柱110的外表面的部分及初始位线立柱110构成目标位线立柱100。初始保护层120覆盖目标位线立柱100，能够避免目标位线立柱100中的导电材料被氧化，降低器件的故障频率。例如，可以采用原子层沉积工艺形成初始保护层120，由于原子层沉积工艺在三维复杂表面进行沉积时具有优异的共形性及均匀性，从而能够在初始位线立柱110的外表面及衬底10的裸露的顶面形成均匀的初始保护层120，提高台阶覆盖率及保形覆盖性，进一步避免目标位线立柱100中的导电材料被氧化，延长故障平均时间。
请继续参考图3-图4d，在一些实施例中，衬底10的顶面具有凹槽101，目标位线立柱100位于凹槽101暴露的有源区11表面；形成目标牺牲立柱200包括：于凹槽101相 对两侧的衬底10的顶面均形成目标牺牲立柱200，目标位线立柱100位于凹槽101内能够降低连接阻抗，提高产品性能。
请参考图4a至图4d，在一些实施例中，于凹槽101相对两侧的衬底10的顶面均形成目标牺牲立柱200包括：形成顶面齐平的牺牲层210，牺牲层210覆盖目标牺牲位线立柱的外表面，以及填充满相邻的目标位线立柱100之间的间隙；于牺牲层210的顶面形成初始图形化掩膜版220；请参考图4b，基于初始图形化掩膜版220刻蚀牺牲层210的顶部，至暴露出目标位线立柱100的顶面，剩余的初始图形化掩膜版220及高于目标位线立柱100的牺牲层210构成目标图形化掩膜版230；请参考图4b至图4c，基于目标图形化掩膜版230沿衬底10的厚度方向刻蚀剩余的牺牲层210，衬底10的厚度方向可以为OY方向，至暴露出位于衬底10的顶面的初始保护层120，剩余的牺牲层210构成目标牺牲立柱200，刻蚀牺牲层210的方法包括湿法刻蚀及/或干法刻蚀，例如，刻蚀牺牲层210可以采用等离子刻蚀工艺，等离子体刻蚀是是指利用高频辉光放电反应，将反应气体激活成活性粒子，例如源自或游离基，这些活性粒子扩散到刻蚀的部位与被刻蚀材料进行反应，形成挥发性生成物而被去除，达到刻蚀的目的，刻蚀气体可以包括NF3、CF3、HF、CHF4中的一种或几种，从而提高刻蚀速率。
请参考图4a-图4b，在一些实施例中，于牺牲层210的顶面形成初始图形化掩膜版220包括：于牺牲层210的顶面形成第一掩膜层221；于第一掩膜层221的顶面形成图形化掩膜层222，图形化掩膜层222内具有开口图形，目标位线立柱100在牺牲层210的顶面的正投影，位于开口图形在牺牲层210的顶面的正投影的内部；形成填充满开口图形的第一介质层223，第一介质层223的顶面高于图形化掩膜层222的顶面；第一介质层223、图形化掩膜层222及第一掩膜层221构成初始图形化掩膜版220。
请继续参考图4a，在一些实施例中，第一介质层223的材料包括：氧化硅、氮化硅、氮氧化硅、氮碳化硅或其组合，以满足多种不同应用场景的实际需求。
请继续参考图4a，在一些实施例中，第一掩膜层221的材料包括：氮氧化硅、硬掩膜上旋体、旋涂碳或其组合。例如，旋涂碳(SOC)是一种含高碳的聚合物溶液，具有良好的填充性，可以降低排气的产生，提高热稳定性和平面化性能。
请继续参考图4a，在一些实施例中，可以根据凹槽101的宽度D设置初始位线立柱110的宽度d，可以设置初始位线立柱110的宽度d的范围包括1/2D至1/3D，例如可以设置d为1/2D、5/12D或1/3D等，从而进一步降低连接阻抗，提升产品性能。
请参考图4c至图4d，在一些实施例中，在形成目标牺牲立柱200之后，及形成第一子保护层310之前，去除剩余的初始图形化掩膜版220，从而暴露出目标牺牲立柱200的顶面。初始图形化掩膜版220的材料可以包括光刻胶或硬掩膜等，对于由光刻胶所构成的初始图形化掩膜版220，去除方法可以包括灰化去胶及湿法清洗；对于由二氧化硅等硬掩膜构成的初始图形化掩膜版220，去除方法包括湿法刻蚀及/或干法刻蚀，例如，刻蚀初始图形化掩膜版220可以采用激光刻蚀工艺，激光刻蚀工艺是利用高能量激光光束照射到被刻蚀件表面，使其融化或气化，形成一定深度的凹槽，实现对材料刻蚀的目的，采用激光刻蚀工艺可以提升产品的良率及稳定性，实现不同图形不同角度的一次性成型，且无耗材、无污染，成本低。
请参考图3及图5a至5c，在一些实施例中，半导体结构制备方法的步骤S30：形成覆盖目标位线立柱100的外表面的目标位线保护层300，目标位线保护层300位于目标位线立柱100的侧壁部分的内部具有目标间隙321还包括：
步骤S31：形成目标牺牲立柱200，目标位线立柱100与目标牺牲立柱200交替排布，相邻的目标位线立柱100与目标牺牲立柱200之间具有间隔沟槽12，目标牺牲立柱200的顶面高于目标位线立柱100的顶面；
步骤S32：采用预设原子层沉积工艺形成第一子保护层310，第一子保护层310覆盖 目标牺牲立柱200的外表面、目标位线立柱100的外表面，及间隔沟槽12的底面；
步骤S33：采用预设化学气相沉积工艺于间隔沟槽12内形成第二子保护层320，第二子保护层320的顶面不低于目标子保护层311的顶面，第一子保护层310位于目标位线立柱100的顶面的部分构成目标子保护层311，第二子保护层320内具有目标间隙321；
步骤S34：去除第一子保护层310位于目标牺牲立柱200外表面的部分及目标牺牲立柱200，剩余的第一子保护层310及第二子保护层320构成目标位线保护层300。
作为示例，请继续参考图5a，通过设置目标位线立柱100与目标牺牲立柱200交替排布，且目标牺牲立柱200的顶面高于目标位线立柱100的顶面，以形成高度差，提高后续对间隔沟槽12上方开口封口地效率，从而提高间隙中低介电常数的介质浓度，进一步减小位线之间的寄生电容。
请参考图5a，在一些实施例中，在步骤S32中：采用预设原子层沉积工艺形成第一子保护层310，第一子保护层310覆盖目标牺牲立柱200的外表面、目标位线立柱100的外表面，及间隔沟槽12的底面。原子层沉积是通过将气相前驱体脉冲交替地通入反应器并在沉积基体上化学吸附并反应而形成沉积膜的一种技术，当前驱体达到沉积基体表面时，会在其表面化学吸附并发生表面反应，原子层沉积的表面反应具有自限制性(self-limiting)，通过在原子层沉积中不断重复自限制反应形成所需要的结构，前驱体材料可以包括非金属前驱体材料及/或金属前驱体材料。例如，非金属前驱体包括卤化物(SiCl4或AlCl3等)、氮化物(NH3、(CH3)NH2或BuNH2等)，金属前驱体包括烷基前驱体(Ga(CH3)3或Mg(C2H5)2)、β-二酮前驱体(La(thd)3或Ca(thd)2)、醇盐前驱体(Ta(OC2H5)5或Zr[(OC)(CH3)3]4)或烷基胺及硅胺基前驱体(Ti[N(C2H5CH3)2]4或Pr[N(SiMe3)2]3)等；传统的溶液化学沉积技术以及溅射或蒸镀等物理沉积技术由于缺乏表面控制性或存在溅射阴影区，在三维复杂结构的表面进行沉积的效果较差，然而原子层沉积技术基于表面自限制性、自饱和吸附反应，从而具有表面控制性，所制备的结构具有优异的三维共形性及大面积的均匀性，对于复杂高深宽比的表面沉积制程的适应性更强，同时原子层沉积工艺可以制造出光滑的表面形貌，紧密地贴合填充层，从而减小沉积制程产生的应力，例如，相比于传统的钨沉积技术，原子层沉积低氟钨技术可以降低一个数量级(GPa至hMPa)的应力、99％的氟含量以及30％的电阻率，因此，根据原子层沉积工艺自身的特性，采用原子层沉积工艺形成第一子保护层310，实现对于目标牺牲立柱200的外表面、目标位线立柱100的外表面及间隔沟槽12的底面的均匀覆盖，使得沉积第一子保护层310制程的保形性、均匀性及阶梯覆盖率提升，降低后续形成间隙的制程工艺难度。
请参考图5a及5b，在一些实施例中，在步骤S33中：采用预设化学气相沉积工艺于间隔沟槽12内形成第二子保护层320，第二子保护层320的顶面高于目标子保护层311的顶面，或与目标子保护层311的顶面齐平，第一子保护层310位于目标位线立柱100的顶面的部分构成目标子保护层311，第二子保护层320内具有目标间隙321；化学气相沉积是使气态物质在固体的表面上发生化学反应并在该表面上沉积形成稳定结构的一种技术，由于化学反应速度较快，气态物质在达到固体表面前已然发生化学反应产生固态物质，因此，根据化学气相沉积工艺自身的特性，采用化学气相沉积工艺对具有台阶的表面进行沉积时，台阶底部至顶部的厚度逐渐增加，直至在顶部开口处闭合，因此，在采用化学气相沉积工艺在形成第二子保护层320的同时在第二子保护层320的内部形成目标间隙321的过程中，间隔沟槽12两侧表面所沉积的第二子保护层320的厚度沿OY方向从底部至顶部逐渐增加，在间隔沟槽12内存在未进行沉积的开口部分，至沉积至目标位线立柱100的顶面开口闭合，形成内部具有目标间隙321的第二子保护层320，从而降低半导体结构的介电常数，减小位线之间的寄生电容，由于目标牺牲立柱200的顶面高于目标位线立柱100的顶面，从而提高封口效率与目标间隙321中低介电常数的介质浓度，进一步减小位线之间的寄生电容，提高半导体器件的可靠性、稳定性及良率。
请参考图5c，在一些实施例中，在步骤S34中：去除第一子保护层310位于目标牺牲立柱200外表面的部分及目标牺牲立柱200，剩余的第一子保护层310及第二子保护层320构成目标位线保护层300；可以采用刻蚀工艺去除第一子保护层310位于目标牺牲立柱200外表面的部分及目标牺牲立柱200。刻蚀工艺包括干法刻蚀工艺及/或湿法刻蚀工艺，干法刻蚀工艺包括但不限于反应离子刻蚀(RIE)、感应耦合等离子体刻蚀(ICP)或高浓度等离子体刻蚀(HDP)中的一种或多种。本实施例通过在目标保护层内形成目标间隙321，降低介电常数，从而降低位线之间的寄生电容。
在一些实施例中，可以设置原子层沉积工艺沉积的速率范围包括：每秒0.5埃至每秒2埃，例如可以设置原子层沉积工艺沉积的速率为每秒0.5埃、每秒0.8埃、每秒1.1埃、每秒1.4埃、每秒1.7埃或每秒2埃等。可以设置原子层沉积工艺压力的范围包括：0.1torr至50torr，例如可以设置原子层沉积工艺压力为0.1torr、0.5torr、2.5torr、12.5torr或50torr等。可以设置原子层沉积工艺温度的范围包括：25℃-600℃，例如可以设置原子层沉积工艺温度为25℃、140℃、255℃、370℃、485℃或600℃等。可以设置原子层沉积工艺中氧气的流量范围包括：0.1L至10L，例如可以设置原子层沉积工艺中氧气的流量为0.1L、0.5L、1L、5L或10L等。原子层沉积工艺的前驱体材料可以包括硅烷，例如，硅烷包括：二(异丙氨基)硅烷、双(叔丁基氨基)硅烷、双(二乙氨基)硅烷或其组合。通过在原子层沉积工艺中采取不同的沉积速率、压力、温度、氧气流量及前驱体材料，提升对不同结构及材料进行沉积的适应性，精准可控地降低位线之间的寄生电容，从而进一步提高半导体器件的可靠性与稳定性。
在一些实施例中，可以设置化学气相沉积工艺的温度范围包括600℃至900℃，例如可以设置化学气相沉积工艺的温度为600℃、700℃、800℃或900℃等，从而提升对不同结构及材料进行沉积的适应性，精准可控地降低位线之间的寄生电容，从而进一步提高半导体器件的可靠性与稳定性。
在一些实施例中，间隔沟槽12的宽度包括5nm至50nm，例如可以设置间隔沟槽12的宽度为5nm、20nm、35nm或50nm等，从而适应不同尺寸的半导体器件制程。
请参考图5c，在一些实施例中，目标间隙321包括空气间隙。由于寄生电容的大小与介电常数的大小呈正相关，为了减小位线之间的寄生电容，需要选择介电常数较小的材料作为位线之间的间隙材料，因此可以采用介电常数为1的空气作为间隙，进一步降低位线之间的寄生电容。
应该理解的是，虽然图1、图3的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，虽然图1、图3中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
请参考图5c，在一些实施例中，提供了一种半导体结构，包括衬底10、目标位线立柱100、目标位线保护层300及目标间隙321；衬底10内包括有源区11；目标位线立柱100位于衬底10的顶部且与其正下方的有源区11电连接；目标位线保护层300覆盖目标位线立柱100的外表面；目标位线保护层300位于目标位线立柱100的侧壁部分的内部具有目标间隙321。通过依次形成衬底10、目标位线立柱100、目标位线保护层300及目标间隙321，使得目标位线立柱100的侧壁部分的内部具有目标间隙321，从而减小半导体结构的介电常数，减小位线之间的寄生电容，提高半导体器件的可靠性与稳定性，提高产品的良率。
请参考图5c，在一些实施例中，半导体结构还包括凹槽101，凹槽101位于衬底10 的顶面，目标位线立柱100位于凹槽101暴露的有源区11表面，从而降低连接阻抗，提高产品性能。
请参考图5c，在一些实施例中，目标位线立柱100包括初始位线立柱110及初始位线保护层(图中未示出)；初始位线立柱110位于凹槽101内有源区11表面；初始位线保护层覆盖初始位线立柱110的外表面，能够避免目标位线立柱100中的导电材料被氧化，降低器件的故障频率。
请继续参考图5c，在一些实施例中，半导体结构还包括绝缘保护层102，绝缘保护层102覆盖相邻的凹槽101之间的衬底10的顶面；初始位线立柱110包括位线接触材料层111、金属阻挡层112、位线材料层113及保护材料层114；位线接触材料层111填充满凹槽101并覆盖绝缘保护层102；金属阻挡层112、位线材料层113、保护材料层114及位线掩膜版115沿衬底10的厚度方向依次设置于位线接触材料层111的顶面，金属阻挡层112与位线接触材料层111相邻，衬底10的厚度方向可以为OY方向；例如，位线接触材料层111的材料可以包括多晶硅；绝缘保护层102或金属阻挡层112的材料可以包括硅氧化物、氧化铝、氧化铪、氮氧化铪、氧化锆、氧化钽、氧化钛、锶钛氧化物或其组合，例如，氮化钽或氮化钛且具有良好的阻挡能力；位线材料层113的材料可以包括钛、钨、钽、钼、钴、铂、钛钨、氮化钨、氮化钛、氮硅化钛或其组合，例如，钌、钨、金或银都属于低电阻金属，能够进一步减小位线材料层113的电阻，提高器件的运行速度。
请继续参考图5c，在一些实施例中，可以根据凹槽101的宽度D设置初始位线立柱110的宽度d，可以设置初始位线立柱110的宽度d的范围包括1/2D至1/3D，例如可以设置d为1/2D、5/12D或1/3D。
请继续参考图5c，在一些实施例中，目标间隙321包括空气间隙。由于寄生电容的大小与介电常数的大小呈正相关，为了减小位线之间的寄生电容，需要选择介电常数较小的材料作为位线之间的间隙材料，因此可以采用介电常数为1的空气作为间隙，进一步降低位线之间的寄生电容。
请参考图5a至图5c，在一些实施例中，半导体结构还包括目标位线保护层300，目标位线保护层300覆盖目标位线立柱100的外表面，目标间隙321位于目标位线保护层300位于目标位线立柱100的侧壁部分的内部；在一些实施例中，目标位线保护层300包括第一子保护层310及第二子保护层320；第一子保护层310覆盖目标位线立柱100的外表面，及间隔沟槽12的底面，可以采用预设原子层沉积工艺形成第一子保护层310，原子层沉积是通过将气相前驱体脉冲交替地通入反应器并在沉积基体上化学吸附并反应而形成沉积膜的一种技术，当前驱体达到沉积基体表面时，会在其表面化学吸附并发生表面反应，原子层沉积的表面反应具有自限制性(self-limiting)；传统的溶液化学沉积技术以及溅射或蒸镀等物理沉积技术由于缺乏表面控制性或存在溅射阴影区，在三维复杂结构的表面进行沉积的效果较差，然而原子层沉积技术基于表面自限制性、自饱和吸附反应，从而具有表面控制性，所制备的结构具有优异的三维共形性及大面积的均匀性，对于复杂高深宽比的表面沉积支撑的适应性更强，因此，根据原子层沉积工艺自身的特性，采用原子层沉积工艺形成第一子保护层310，实现对于目标牺牲立柱200的外表面、目标位线立柱100的外表面及间隔沟槽12的底面的均匀覆盖，使得沉积第一子保护层310制程的保形性、均匀性及阶梯覆盖率提升，降低后续形成间隙的制程工艺难度；第二子保护层320顶面不低于目标子保护层311的顶面，第二子保护层320内具有目标间隙321，可以采用预设化学气相沉积工艺于间隔沟槽12内形成第二子保护层320，第二子保护层320内具有目标间隙321，化学气相沉积工艺中，由于化学反应速度较快，气态物质在达到固体表面前已然发生化学反应产生固态物质，因此，根据化学气相沉积工艺自身的特性，在采用化学气相沉积工艺在形成第二子保护层320的同时在第二子保护层320的内部形成目标间隙321的过程中，间隔沟槽12两侧表面所沉积的第二子保护层320的厚度沿OY方向从底 部至顶部逐渐增加，因此在间隔沟槽12内存在未进行沉积的开口部分，直至沉积至目标位线立柱100的顶面开口闭合，形成内部具有目标间隙321的，从而降低半导体结构的介电常数，减小位线之间的寄生电容，由于目标牺牲立柱200的顶面高于目标位线立柱100的顶面，从而提高封口效率与目标间隙321中低介电常数的介质浓度，进一步减小位线之间的寄生电容，提高半导体器件的可靠性与稳定性，提高产品的良率。
请继续参考图5a至图5c，在一些实施例中，第一子保护层310采用原子层沉积工艺形成，可以设置原子层沉积工艺沉积的速率范围包括：每秒0.5埃至每秒2埃，例如可以设置原子层沉积工艺沉积的速率为每秒0.5埃、每秒0.8埃、每秒1.1埃、每秒1.4埃、每秒1.7埃或每秒2埃等；可以设置原子层沉积工艺压力的范围包括：0.1torr至50torr，例如可以设置原子层沉积工艺压力为0.1torr、0.5torr、2.5torr、12.5torr或50torr等；可以设置原子层沉积工艺温度的范围包括：25℃-600℃，例如可以设置原子层沉积工艺温度为25℃、140℃、255℃、370℃、485℃或600℃等；可以设置原子层沉积工艺中氧气的流量范围包括：0.1L至10L，例如可以设置原子层沉积工艺中氧气的流量为0.1L、0.5L、1L、5L或10L等；原子层沉积工艺的前驱体材料可以包括硅烷，例如，硅烷包括：二(异丙氨基)硅烷、双(叔丁基氨基)硅烷、双(二乙氨基)硅烷或其组合。第二子保护层320采用化学气相沉积工艺形成，可以设置化学气相沉积工艺的温度范围包括600℃至900℃，例如可以设置化学气相沉积工艺的温度为600℃、700℃、800℃或900℃等。通过在原子层沉积工艺中采取不同的沉积速率、压力、温度、氧气流量及前驱体材料，并在化学气相沉积工艺中采用不同的温度，提升对不同结构及材料进行沉积的适应性，精准可控地降低位线之间的寄生电容，从而进一步提高半导体器件的可靠性与稳定性。
请注意，上述实施例仅出于说明性目的而不意味对本公开的限制。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对公开专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体结构制备方法，包括：
    提供衬底，其内包括有源区；
    于所述衬底的顶部形成目标位线立柱，所述目标位线立柱与其正下方的有源区电连接；
    形成覆盖所述目标位线立柱的外表面的目标位线保护层，所述目标位线保护层位于所述目标位线立柱的侧壁部分的内部具有目标间隙。
  2. 根据权利要求1所述的半导体结构制备方法，其中，所述形成覆盖所述目标位线立柱的外表面的目标位线保护层，包括：
    形成目标牺牲立柱，所述目标位线立柱与所述目标牺牲立柱交替排布，相邻的所述目标位线立柱与所述目标牺牲立柱之间具有间隔沟槽，所述目标牺牲立柱的顶面高于所述目标位线立柱的顶面；
    采用预设原子层沉积工艺形成第一子保护层，所述第一子保护层覆盖所述目标牺牲立柱的外表面、所述目标位线立柱的外表面，及所述间隔沟槽的底面；
    采用预设化学气相沉积工艺于所述间隔沟槽内形成第二子保护层，所述第二子保护层的顶面不低于目标子保护层的顶面，所述第一子保护层位于所述目标位线立柱的顶面的部分构成所述目标子保护层，所述第二子保护层内具有所述目标间隙；
    去除所述第一子保护层位于所述目标牺牲立柱外表面的部分及所述目标牺牲立柱，剩余的所述第一子保护层及所述第二子保护层构成所述目标位线保护层。
  3. 根据权利要求2所述的半导体结构制备方法，其中，所述衬底的顶面具有凹槽，所述目标位线立柱位于所述凹槽暴露的有源区表面；所述形成目标牺牲立柱，包括：
    于所述凹槽相对两侧的所述衬底的顶面均形成所述目标牺牲立柱。
  4. 根据权利要求3所述的半导体结构制备方法，其中，所述于所述衬底的顶部形成目标位线立柱，包括：
    于所述凹槽内有源区表面形成初始位线立柱；
    沉积初始保护层，所述初始保护层覆盖所述初始位线立柱的外表面及所述衬底的裸露的顶面；所述初始保护层位于所述初始位线立柱的外表面的部分及所述初始位线立柱构成所述目标位线立柱。
  5. 根据权利要求4所述的半导体结构制备方法，其中，所述于所述凹槽相对两侧的衬底的顶面均形成所述目标牺牲立柱，包括：
    形成顶面齐平的牺牲层，所述牺牲层覆盖所述目标位线立柱的外表面，以及填充满相邻的所述目标位线立柱之间的间隙；
    于所述牺牲层的顶面形成初始图形化掩膜版；
    基于所述初始图形化掩膜版刻蚀所述牺牲层的顶部，至暴露出所述目标位线立柱的顶面，剩余的所述初始图形化掩膜版及高于所述目标位线立柱的所述牺牲层构成目标图形化掩膜版；
    基于所述目标图形化掩膜版沿所述衬底的厚度方向刻蚀剩余的所述牺牲层，至暴露出位于所述衬底的顶面的所述初始保护层，剩余的所述牺牲层构成所述目标牺牲立柱。
  6. 根据权利要求5所述的半导体结构制备方法，其中，所述于所述牺牲层的顶面形成初始图形化掩膜版，包括：
    于所述牺牲层的顶面形成第一掩膜层；
    于所述第一掩膜层的顶面形成图形化掩膜层，所述图形化掩膜层内具有开口图形，所述目标位线立柱在所述牺牲层的顶面的正投影，位于所述开口图形在所述牺牲层的顶面的正投影的内部；
    形成填充满所述开口图形的第一介质层，所述第一介质层的顶面高于所述图形化掩膜 层的顶面；所述第一介质层、所述图形化掩膜层及所述第一掩膜层构成所述初始图形化掩膜版。
  7. 根据权利要求5所述的半导体结构制备方法，其中，在形成所述目标牺牲立柱之后，及形成所述第一子保护层之前，还包括：
    去除剩余的所述初始图形化掩膜版。
  8. 根据权利要求6所述的半导体结构制备方法，其中，所述第一介质层的材料包括：氧化硅、氮化硅、氮氧化硅、氮碳化硅或其组合。
  9. 根据权利要求4-8任一项所述的半导体结构制备方法，其中，相邻的所述凹槽之间的衬底的顶面覆盖有绝缘保护层；所述于所述凹槽内有源区表面形成初始位线立柱，包括：
    形成填充满所述凹槽并覆盖所述绝缘保护层的位线接触材料层；
    于所述位线接触材料层的顶面形成沿所述衬底的厚度方向依次叠置的金属阻挡层、位线材料层、保护材料层及位线掩膜版，所述金属阻挡层与所述位线接触材料层相邻；
    基于所述位线掩膜版沿所述厚度方向刻蚀所述保护材料层、所述位线材料层、所述金属阻挡层及所述位线接触材料层，剩余的位线接触材料层、剩余的金属阻挡层、剩余的位线材料层及剩余的保护材料层构成所述初始位线立柱。
  10. 根据权利要求2-8任一项所述的半导体结构制备方法，其中，所述预设原子层沉积工艺包括如下特征中至少一个：
    沉积速率范围包括：0.5埃/秒-2埃/秒；
    压力范围包括：0.1torr-50torr；
    温度范围包括：25℃-600℃；
    氧气流量范围包括：0.1L-10L；
    硅烷包括：二(异丙氨基)硅烷、双(叔丁基氨基)硅烷、双(二乙氨基)硅烷或其组合。
  11. 根据权利要求2-8任一项所述的半导体结构制备方法，其中，所述预设化学气相沉积工艺的温度范围包括：600℃-900℃。
  12. 根据权利要求2-8任一项所述的半导体结构制备方法，其中，所述间隔沟槽的宽度为5nm-50nm。
  13. 根据权利要求1-8任一项所述的半导体结构制备方法，其中，所述目标间隙包括空气间隙。
  14. 根据权利要求4-8任一项所述的半导体结构制备方法，其中，所述初始位线立柱的宽度为所述凹槽的宽度的1/2-1/3。
  15. 根据权利要求6-8任一项所述的半导体结构制备方法，其中，所述第一掩膜层的材料包括：氮氧化硅、硬掩膜上旋体、旋涂碳或其组合。
  16. 一种半导体结构，包括：
    衬底，其内包括有源区；
    目标位线立柱，位于所述衬底的顶部且与其正下方的有源区电连接；
    目标位线保护层，覆盖所述目标位线立柱的外表面；
    其中，所述目标位线保护层位于所述目标位线立柱的侧壁部分的内部具有目标间隙。
  17. 根据权利要求16所述的半导体结构，其中，所述衬底的顶面具有凹槽，所述目标位线立柱位于所述凹槽暴露的有源区表面。
  18. 根据权利要求17所述的半导体结构，其中，所述目标间隙包括空气间隙。
  19. 根据权利要求16-18任一项所述的半导体结构，其中，所述目标位线立柱包括：
    初始位线立柱，位于所述凹槽内有源区表面；
    初始位线保护层，覆盖所述初始位线立柱的外表面。
  20. 根据权利要求19所述的半导体结构，其中，所述初始位线立柱的宽度为所述凹槽的宽度的1/2-1/3。
PCT/CN2023/076162 2022-10-12 2023-02-15 半导体结构及其制备方法 WO2024077826A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277643A (ja) * 2005-03-30 2006-10-12 Tokyo Electric Power Co Inc:The 屋上蓄熱架台計画支援プログラム
CN113035872A (zh) * 2021-03-05 2021-06-25 长鑫存储技术有限公司 半导体结构及其制作方法
CN113675146A (zh) * 2021-08-11 2021-11-19 长鑫存储技术有限公司 半导体结构及其形成方法和存储器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277643A (ja) * 2005-03-30 2006-10-12 Tokyo Electric Power Co Inc:The 屋上蓄熱架台計画支援プログラム
CN113035872A (zh) * 2021-03-05 2021-06-25 长鑫存储技术有限公司 半导体结构及其制作方法
CN113675146A (zh) * 2021-08-11 2021-11-19 长鑫存储技术有限公司 半导体结构及其形成方法和存储器

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