WO2024077713A1 - 电源控制电路及存储器 - Google Patents

电源控制电路及存储器 Download PDF

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Publication number
WO2024077713A1
WO2024077713A1 PCT/CN2022/133021 CN2022133021W WO2024077713A1 WO 2024077713 A1 WO2024077713 A1 WO 2024077713A1 CN 2022133021 W CN2022133021 W CN 2022133021W WO 2024077713 A1 WO2024077713 A1 WO 2024077713A1
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Prior art keywords
control
signal
switch
voltage
gate
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PCT/CN2022/133021
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English (en)
French (fr)
Inventor
刘忠来
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长鑫存储技术有限公司
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Publication of WO2024077713A1 publication Critical patent/WO2024077713A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Definitions

  • the present disclosure relates to memory technology, and more particularly to a power control circuit and a memory.
  • DRAM dynamic random access memory
  • the memory contains multiple circuit modules, and the circuit modules need power signals when working.
  • the power signals here include power supply, ground power, etc.
  • a total power supply is set in some examples, and the power control of each circuit module is achieved by controlling the transmission module between the total power supply and the circuit module. Therefore, it is necessary to consider how to achieve effective power control.
  • Embodiments of the present disclosure provide a power control circuit and a memory.
  • the first aspect of the present disclosure provides a power control circuit, including: a control module, coupled to the control end of the transmission module, for outputting a control signal of a first voltage in response to a mode signal being in a first level state; and, in response to the mode signal being in a second level state, outputting a control signal of a second voltage; the transmission module, coupled between the first power signal and the circuit module, for transmitting the first power signal to the circuit module in response to the control signal of the first voltage; and, in response to the control signal of the second voltage, disconnecting the transmission; wherein the first voltage represents a low level state, and the second voltage is higher than the voltage of the first power signal.
  • the transmission module includes: a first PMOS transistor; the source of the first PMOS transistor receives the first power supply signal, and the drain of the first PMOS transistor is connected to the circuit module; the gate of the first PMOS transistor serves as the control end of the transmission module and is connected to the control module.
  • the control module includes: a first switch, a second switch and a first control unit; the first end of the first switch is connected to the second power signal, and the second end of the first switch is connected to the control end of the transmission module; the voltage of the second power signal is the second voltage; the input end of the first control unit is connected to the mode signal, and the output end of the first control unit is connected to the control end of the first switch; the first control unit is used to control the first switch to turn off when the mode signal switches to the first level state, and to control the first switch to turn on after a first delay when the mode signal switches to the second level state; the first end of the second switch is connected to the control end of the transmission module, the second end of the second switch is grounded, and the control end of the second switch is connected to the mode signal; the second switch is used to turn on when the mode signal switches to the first level state, and to turn off when the mode signal switches to the second level state.
  • control module also includes: a second control unit; the input end of the second control unit is connected to the mode signal, and the output end of the second control unit is connected to the control end of the second switch; the second control unit is used to control the second switch to be turned on after a second delay when the mode signal switches to the first level state, and to control the second switch to be turned off when the mode signal switches to the second level state.
  • the second control unit includes: a first delay unit and an AND gate; the first input end of the AND gate is connected to the output end of the first delay unit, the second input end of the AND gate is connected to the mode signal, and the output end of the AND gate is connected to the control end of the second switch; the input end of the first delay unit is connected to the second input end of the AND gate, and the first delay unit is used to transmit the received signal to the first input end of the AND gate after the second delay.
  • the first control unit includes: a first logic unit and a first level conversion unit; the input end of the first logic unit is connected to the mode signal, and the output end of the first logic unit is connected to the input end of the first level conversion unit; the first logic unit is used to output a signal whose level state is the first level state when the received signal is switched to the first level state, and to output a signal whose level state is the second level state after the first delay when the received signal is switched to the second level state; the output end of the first level conversion unit is connected to the control end of the first switch; the first level conversion unit is used to convert the voltage of the received high level signal into the second voltage.
  • the first logic unit includes: a second delay unit and a first OR gate; the first input end of the first OR gate is connected to the mode signal, the second input end of the first OR gate is connected to the output end of the second delay unit, and the output end of the first OR gate is connected to the input end of the first level conversion unit; the input end of the second delay unit is connected to the first input end of the first OR gate; the delay length of the second delay unit is the first delay.
  • control module also includes: a third switch and a third control unit; the first end of the third switch is connected to the first power supply signal, and the second end of the third switch is connected to the control end of the transmission module; the input end of the third control unit is connected to the first control unit, and the output end of the third control unit is connected to the control end of the third switch; the third control unit is used to control the third switch to turn off when the mode signal switches to the first level state, and to control the third switch to turn on and control the third switch to turn off after the first delay when the mode signal switches to the second level state.
  • the third control unit includes: a NOT gate and a second OR gate; the input end of the NOT gate is connected to the output end of the second delay unit, and the output end of the NOT gate is connected to the first input end of the second OR gate; the second input end of the second OR gate is connected to the input end of the second delay unit, and the output end of the second OR gate is connected to the control end of the third switch.
  • the third control unit further includes: a second level conversion unit; an input end of the second level conversion unit is connected to an output end of the second OR gate, an output end of the second level conversion unit is connected to a control end of the third switch, and a delay of the second level conversion unit is consistent with a delay of the first level conversion unit.
  • the first switch includes a second PMOS transistor and the second switch includes a first NMOS transistor.
  • the third switch comprises a third PMOS transistor.
  • the voltage difference between the second voltage and the voltage of the first power signal is in a voltage range of 0.2 to 0.3 volts.
  • the mode signal being in a first level state represents a working state
  • the mode signal being in a second level state represents an idle state
  • the second aspect of the present disclosure provides a memory, comprising: a circuit module and a power control circuit as described above; the power control circuit is coupled to the circuit module, and is used to provide a first power signal to the circuit module in a working state, and stop providing the first power signal to the circuit module in an idle state.
  • the control module outputs control signals of different voltages in response to different level states of the mode signal
  • the transmission module coupled between the main power supply and the circuit module is turned on or off under the control of the control signals of different voltages to realize the power control of each circuit module, wherein the voltage of the control signal used to control the disconnection of the transmission module is higher than the voltage of the main power supply.
  • FIG1 is an example diagram of a memory architecture according to an embodiment of the present disclosure
  • FIG2 is a structural diagram of a storage unit according to an embodiment of the present disclosure.
  • FIG3 is a structural diagram of an exemplary power supply control circuit
  • FIG4 is a structural diagram of a power control circuit provided by an embodiment
  • FIG5 is a state diagram of a power supply control circuit in a working state
  • FIG6 is a state diagram of a power control circuit in an idle state
  • FIG7 is a structural diagram of a power control circuit provided by an embodiment
  • FIG8 is a timing diagram of an example
  • FIG9 is a structural diagram of a power control circuit provided by an embodiment
  • FIG10 is a structural diagram of a power control circuit provided by an embodiment
  • FIG11 is a timing diagram of an example
  • FIG12 is a structural diagram of a power control circuit provided by an embodiment
  • FIG. 13 is a timing diagram of an example.
  • FIG1 is an example diagram of the architecture of a memory device according to an embodiment of the present disclosure.
  • DRAM taking DRAM as an example, it includes a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a memory array.
  • the memory array is mainly composed of word lines, bit lines, and memory cells.
  • the word lines in the memory array extend in the row direction, and the bit lines in the memory array extend in the column direction.
  • the intersection of the word lines and the bit lines is the memory cell of the memory array.
  • FIG2 is a structural example diagram of a storage unit according to an embodiment of the present disclosure.
  • the storage unit is mainly composed of a transistor M and a capacitor C.
  • the capacitor is used to store data, and the transistor is used to turn off or on according to the state of the word line.
  • a certain storage cell can be activated by controlling the row and column to access the storage cell.
  • the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder, and accordingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa.
  • the write scenario as an example: when data needs to be written to a certain storage cell, such as writing 1.
  • the word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.
  • the memory contains multiple different circuit modules, such as data input/output buffer, row decoder, column decoder, sense amplifier, etc., and each circuit module works together to realize the functions of the memory, such as writing and reading data. Therefore, in order to facilitate power management and save power consumption, a main power supply is set in some examples, and each transmission module is set between the main power supply and each circuit module. By controlling the transmission module to turn on or off, it controls whether to provide a power signal to the circuit module.
  • the power signal here includes but is not limited to the power supply VCC and/or the ground power VSS.
  • FIG3 is a structural example diagram of an example power control circuit.
  • the example is a power control scheme applied to a memory.
  • VCC is a total power supply, but it is not directly connected to all circuit modules to provide power.
  • the total power supply VCC supplies power to different circuit modules through one or more transmission modules.
  • the memory can be controlled to supply power to different circuit modules in different working states. For example, in the figure, VCC generates VCCZ through the transmission module to power the logic circuit.
  • the IDD2P current refers to the total current consumed by the memory in the idle state, when the clock enable signal and the chip select signal are both in an invalid state, the data line remains unchanged, and the command/address line signal does not receive the command and address signals, so it also remains unchanged. In practical applications, it is hoped to reduce the IDD2P current.
  • FIG. 4 is a structural diagram of a power control circuit provided by an embodiment. As shown in FIG. 4 , the power control circuit includes:
  • the control module 11 is coupled to the control end of the transmission module 12, and is used to output a control signal of a first voltage in response to the mode signal being in a first level state; and to output a control signal of a second voltage in response to the mode signal being in a second level state;
  • the transmission module 12 is coupled between the first power signal VCC and the circuit module 13, and is used to transmit the first power signal VCC to the circuit module 13 in response to a control signal of a first voltage; and, in response to a control signal of a second voltage, disconnect the transmission; wherein the first voltage represents a low level state, and the second voltage is higher than the voltage of the first power signal VCC.
  • the chip test circuit provided in this embodiment can be applied to various memories, and as an example, can be applied to, including but not limited to, double data rate synchronous dynamic random access memory (DDR for short).
  • DDR double data rate synchronous dynamic random access memory
  • the mode signal can be understood as a flag signal, which is used to indicate that it is currently in a working state or an idle state.
  • the mode signal is in a first level state to indicate a working state, and the mode signal is in a second level state to indicate an idle state.
  • the mode signal in the working state, that is, the memory is in the ACTIVE mode, the mode signal is in a high level state at this time; on the contrary, in the idle state, or also called the memory is in the IDD2P mode, the mode signal is in a low level state at this time. That is to say, in one example, the first level state is a high level state, and the second level state is a low level state.
  • This embodiment does not limit the generation method of the mode signal.
  • FIG. 5 is an example diagram of the state of the power control circuit in the working state.
  • the mode signal EN when the memory is working normally, the mode signal EN is in a high level state.
  • the circuit module needs to work normally.
  • the control module 11 responds to the high level state of the mode signal EN (the example in the figure is "1") and outputs a control signal.
  • the voltage of the control signal is a first voltage, and the first voltage represents a low level state (the example in the figure is "0"); the transmission module 12 is turned on under the control of the control signal in the low level state, and the first power signal VCC is used as the total power supply.
  • the power supply VCCZ of the circuit module 13 is generated through the transmission module 12 to supply power to the circuit module 13.
  • FIG6 is a state example diagram of the power control circuit in the idle state.
  • the mode signal EN when the memory is idle, the mode signal EN is in a low level state.
  • the circuit module does not need to work. Accordingly, the control module 11 responds to the low level state of the mode signal EN (the example in the figure is "0") and outputs a control signal.
  • the voltage of the control signal at this time is a second voltage
  • the second voltage represents a high level state (the example in the figure is "1" and the second voltage VCCH is higher than the voltage of the first power signal VCC
  • the transmission module 12 is turned off under the control of the control signal in the high level state, and the transmission module 12 between the first power signal VCC and the circuit module 13 is turned off, and no power is supplied to the circuit module 13.
  • the transmission module 12 is turned off by a control signal with a voltage higher than the voltage of the first power signal, and the leakage current passing through the transmission module in the off state can be further reduced while the transmission module is turned off, thereby achieving the effect of reducing the IDD2P current.
  • the second voltage is the voltage after the control signal reaches a stable state.
  • the voltage difference between the second voltage and the voltage of the first power signal VCC is in the voltage range of 0.2 to 0.3 volts.
  • the transmission module is turned on at a low level.
  • the specific structure of the transmission module can be implemented through a variety of circuit structures, and this embodiment does not limit it here.
  • the transmission module 12 includes: a first PMOS transistor; the source of the first PMOS transistor receives the first power signal VCC, and the drain of the first PMOS transistor is connected to the circuit module 13; the gate of the first PMOS transistor serves as the control end of the transmission module 12 and is connected to the control module 11.
  • the transmission module is implemented by a single MOS device, which can further simplify the circuit structure and reduce costs while responding to power control quickly and timely.
  • the transmission module 12 may include: a transmission gate and an inverter.
  • the structure of the transmission gate is not limited.
  • the transmission gate may be formed by symmetrically connecting PMOS and NMOS in parallel, the input end of the inverter is connected to the control signal, and the output end is connected to the control end of the NMOS, that is, the gate.
  • the transmission gate has a lower on-resistance and a higher off-resistance, so it can effectively realize power control.
  • FIG. 7 is a structural example diagram of a power control circuit provided in one embodiment, and an example is given of the architecture of the control module 11.
  • the control module 11 includes: a first switch 111, a second switch 112, and a first control unit 113;
  • a first end of the first switch 111 is connected to the second power signal VCCH, and a second end of the first switch 111 is connected to the control end of the transmission module 12; a voltage of the second power signal VCCH is a second voltage;
  • the input end of the first control unit 113 is connected to the mode signal EN, and the output end of the first control unit 113 is connected to the control end of the first switch 111; the first control unit 113 is used to control the first switch 111 to be turned off when the mode signal EN is switched to the first level state, and to control the first switch 111 to be turned on after a first delay t1 when the mode signal EN is switched to the second level state;
  • the first end of the second switch 112 is connected to the control end 13 of the transmission module, the second end of the second switch 112 is grounded, and the control end of the second switch 112 is connected to the mode signal EN; the second switch 112 is used to turn on when the mode signal EN switches to the first level state, and to turn off when the mode signal EN switches to the second level state.
  • FIG8 is an example timing diagram, in which KsGate represents the signal at the control end of the transmission module, ie, the control signal; K1Gate represents the signal at the control end of the first switch; and K2Gate represents the signal at the control end of the second switch.
  • the mode signal EN When the memory is in working state, the mode signal EN is in high level state. Accordingly, when the mode signal EN is in high level state, the first control unit 113 controls the first switch 111 to be turned off, and the second power signal VCCH is disconnected from the control end of the transmission module 12. At the same time, the second switch 112 is turned on when the mode signal EN is in high level state, so the control end of the transmission module 12 is grounded through the turned-on second switch 112. At this time, the voltage at the control end of the transmission module 12 is the ground voltage, that is, it is in low level state. Accordingly, the transmission module 12 is turned on in response to the low level state of the control end, and the first power signal VCC generates VCCZ through the turned-on transmission module 12 and is provided to the circuit module.
  • the first switch includes a second PMOS transistor
  • the second switch includes a first NMOS transistor.
  • the first switch and the second switch can also be implemented by other structures that can be turned on and off, such as a transmission gate structure, etc., and other possible methods are not limited here.
  • the mode signal EN When the memory is in an idle state, the mode signal EN is in a low level state. Accordingly, when the mode signal EN is switched to a low level state, the first control unit 113 first delays t1 and then controls the first switch 111 to turn on. That is, when the mode signal is just switched from a high level state to a low level state, the first switch 111 will remain in an off state for a period of time until it is turned on under the control of the first control unit 113 after the first delay t1, so that the second power signal VCCH and the control end of the transmission module 12 are electrically connected through the turned-on first switch 111.
  • the second switch 112 when the mode signal is switched from a high level state to a low level state, the second switch 112 is turned off, so that the control end of the transmission module 12 is disconnected from the ground signal, and the voltage at the control end is pulled up to the second voltage by the second power signal VCCH through the turned-on first switch 111, and the second voltage is higher than the voltage of the first power signal VCC. Accordingly, the transmission module 12 is turned off in response to the high level state of the control end, and the first power signal VCC is electrically disconnected from the circuit module 13.
  • the “connection” in this embodiment includes direct connection and indirect connection.
  • the control module is composed of two switches and a first control unit, and can output a control signal representing a low-level state and a control signal with a voltage higher than the voltage of the first power signal in the working state and the idle state, respectively, so as to realize power control while reducing leakage current.
  • an appropriate delay is added to the control strategy. Specifically, when switching from the working state to the idle state, the second switch is first disconnected to disconnect the ground, and the first switch is turned on after the first delay to pull up the voltage at the control end of the control unit, so as to avoid the situation in which the charging effect is insufficient if the first switch is turned on too early and the second switch is still grounded during the voltage pull-up process, thereby avoiding energy waste and saving energy consumption.
  • FIG9 is a structural example diagram of a power control circuit provided by an embodiment.
  • the first control unit 113 includes: a first logic unit 21 and a first level conversion unit 22;
  • the input end of the first logic unit 21 is connected to the mode signal EN, and the output end of the first logic unit 21 is connected to the input end of the first level conversion unit 22; the first logic unit 21 is used for outputting a signal whose level state is the first level state when the received signal is switched to the first level state, and for outputting a signal whose level state is the second level state after a first delay t1 when the received signal is switched to the second level state;
  • the output end of the first level conversion unit 22 is connected to the control end of the first switch 111 ; the first level conversion unit 22 is used to convert the voltage of the received high level signal into a second voltage.
  • the duration of the first delay t1 can be set according to the situation.
  • the first end of the first switch 111 is connected to the second power signal VCCH, and the voltage of the second power signal VCCH is a second voltage, which is higher than the voltage of the usual first power signal VCC. Therefore, in order to further ensure the effective on and off of the first switch 111, a suitable control voltage is adapted for the first switch 111.
  • a first level conversion unit 22 is provided to convert the voltage of the received signal into a voltage, such as a second voltage, that matches the first switch 111 when the received signal is a signal representing a high level state.
  • the first level conversion unit 22 may include a level converter.
  • the first level conversion unit 22 when it is desired to turn on the first switch, the first level conversion unit 22 will receive a signal representing a low level state, and the voltage conversion may not be performed at this time, because the source of the first switch is connected to the second power signal, and when the gate of the first switch receives a signal representing a low level state, a voltage difference can be formed between the gate and the source of the first switch, and the voltage difference reaches the conduction threshold voltage of the PMOS transistor, so the first switch can be turned on in time.
  • the first level conversion unit 22 when it is desired to turn off the first switch, the first level conversion unit 22 will receive a signal representing a high level state (for example, the voltage is the voltage of the first power signal VCC), the source of the first switch is connected to the second power signal, and the voltage of the second power signal is the second voltage, which is higher than the voltage of VCC, and the voltage of the gate of the PMOS transistor is still less than the voltage of the source, resulting in incomplete shutdown. Therefore, in this example, the first level conversion unit 22 is set to convert the voltage of the received signal when receiving a signal representing a high level state, and obtain a signal with a voltage of the second voltage, so as to effectively control the first switch to be turned off.
  • a signal representing a high level state for example, the voltage is the voltage of the first power signal VCC
  • the source of the first switch is connected to the second power signal
  • the voltage of the second power signal is the second voltage, which is higher than the voltage of VCC
  • the voltage of the gate of the PMOS transistor is still
  • the first logic unit 21 is mainly used to control the on and off timing of the first switch. Specifically, when the memory switches from the idle state to the working state, the mode signal EN received by the first logic unit 21 switches from the low level state to the high level state. In one example, the first logic unit 21 is responsible for responding to the change in the above level state and immediately transmitting the changed mode signal EN to the first level conversion unit 22 for voltage conversion, thereby controlling the first switch 111 to turn off, so as to timely pull down the voltage at the control end of the transmission module when switching from the idle state to the working state, and control the transmission module to turn on. On the other hand, when the memory switches from the working state to the idle state, the mode signal EN received by the first logic unit 21 switches from the high level state to the low level state.
  • the first logic unit 21 is responsible for responding to the change in the above-mentioned level state and still maintaining the previous output (signal in the high level state). Accordingly, the first level conversion unit 22 still performs voltage conversion and the first switch 111 is still turned off until the first logic unit 21 transmits the changed mode signal EN (at this time in the low level state) to the first level conversion unit 22 after the first delay t1.
  • the first level conversion unit 22 does not need to perform voltage conversion and outputs a low level signal to the first switch 111 to control the first switch 111 to turn on, thereby achieving a delay in pulling up the voltage at the control end of the transmission module when switching from the working state to the idle state, so as to delay the shutdown of the transmission module and improve the reliability of power supply control.
  • the first logic unit 21 includes: a second delay unit 211 and a first OR gate 212; wherein, the first input end of the first OR gate 212 is connected to the mode signal EN, the second input end of the first OR gate 212 is connected to the output end of the second delay unit 211, and the output end of the first OR gate 212 is connected to the input end of the first level conversion unit 22; the input end of the second delay unit 211 is connected to the first input end of the first OR gate 212; the delay length of the second delay unit 211 is the first delay t1.
  • the mode signal EN flips from a low level state to a high level state, and accordingly, the first input end of the first OR gate 212 and the input end of the second delay unit 211 receive a mode signal in a high level state.
  • the second input end of the first OR gate 212 has not received a signal in a high level state due to the delayed transmission of the second delay unit 211, since the first input end of the first OR gate 212 has received a high level state signal, through an OR logic operation, the first OR gate 212 immediately outputs a high level state signal to the first level conversion unit 22 for voltage conversion, and the converted high level signal is transmitted to the first switch 111, and the first switch 111 is turned off.
  • the mode signal EN flips from the high level state to the low level state. Accordingly, the first input end of the first OR gate 212 and the input end of the second delay unit 211 receive the mode signal in the low level state. The output of the first OR gate 212 depends on the signal received at the second input end.
  • the second input end of the first OR gate 212 has not received the flipped low level signal at this time, that is, the currently received signal is still a high level signal, so the first OR gate 212 still outputs a high level signal, and the first switch 111 remains turned off; until the flipped low level mode signal passes through the delayed transmission of the second delay unit 211 and reaches the second input end of the first OR gate 212, then after the OR logic operation, the current two inputs are both low level signals, so the output of the first OR gate 212 flips to a low level signal, and the first switch is turned on.
  • the first logic unit is formed by a delay unit and an OR gate, which can realize immediate control or delayed control of the first switch according to the switching condition of the mode signal, and can simplify the circuit and save costs.
  • the first control unit includes a first logic unit and a first level conversion unit.
  • the first logic unit is used to control the on and off timing of the first switch.
  • the first level conversion unit is used to convert the voltage of the received high-level signal to adapt the control voltage of the first switch, thereby achieving effective control of the first switch and timely and reliable power supply control.
  • FIG. 10 is a structural example diagram of a power control circuit provided by an embodiment.
  • the control module 11 further includes: a second control unit 114;
  • An input terminal of the second control unit 114 is connected to the mode signal EN, and an output terminal of the second control unit 114 is connected to a control terminal of the second switch 112;
  • the second control unit 114 is used for controlling the second switch 112 to be turned on after a second delay t2 when the mode signal EN switches to the first level state, and controlling the second switch 112 to be turned off when the mode signal EN switches to the second level state.
  • Figure 11 is a timing diagram of an example.
  • the mode signal EN switches from the low level state to the high level state
  • the first control unit 113 immediately controls the first switch 111 to turn off, and the second power signal VCCH is disconnected from the control end of the transmission module 12.
  • the second switch 112 under the control of the second control unit 114, remains turned off until it is turned on after the second delay t2, the control end of the transmission module 12 is grounded through the turned-on second switch 112, the transmission module 12 is turned on in response to the low level state of the control end, the first power signal VCC generates VCCZ through the turned-on transmission module 12 and is provided to the circuit module, and the circuit module starts to work.
  • the mode signal EN switches from the high level state to the low level state.
  • the first control unit 113 first delays t1, and then controls the first switch 111 to turn on.
  • the second power signal VCCH and the control end of the transmission module 12 are electrically connected through the turned-on first switch 111.
  • the mode signal EN switches from the high level state to the low level state
  • the second switch 112 is immediately turned off, so the control end of the transmission module 12 is disconnected from the ground voltage, and the voltage at the control end is pulled up to the second voltage, which is higher than the voltage of the first power signal VCC. Accordingly, the transmission module 12 is turned off in response to the high level state of the control end, and the first power signal VCC is electrically disconnected from the circuit module 13.
  • the second control unit 114 includes: a first delay unit 31 and an AND gate 32; wherein the first input terminal of the AND gate 32 is connected to the output terminal of the first delay unit 31, the second input terminal of the AND gate 22 is connected to the mode signal EN, and the output terminal of the AND gate 32 is connected to the control terminal of the second switch 112; the input terminal of the first delay unit 31 is connected to the second input terminal of the AND gate 32, and the first delay unit 31 is used to transmit the received signal to the first input terminal of the AND gate 32 after the second delay t2.
  • the delay of the first delay unit is the second delay t2, and the duration of the second delay t2 can be set according to the situation.
  • the first delay t1 and the second delay t2 can be the same or different.
  • t2 can be set to a smaller value or no delay can be set to ensure timely power supply.
  • the mode signal EN flips from the low level state to the high level state.
  • the second input end of the AND gate 32 and the input end of the first delay unit 31 receive the mode signal in the high level state.
  • the output of the AND gate 32 depends on the signal received at the first input end.
  • the first input end of the AND gate 32 has not received the flipped high level signal at this time, that is, the currently received signal is still a low level signal, so the AND gate 32 still outputs a low level signal, and the second switch 112 remains turned off; until the flipped high level mode signal passes through the delayed transmission of the first delay unit 31 and reaches the first input end of the AND gate 32, then after the AND logic operation, the current two inputs are both high level signals, so the output of the AND gate 32 flips to a high level signal, and the second switch 112 is turned on.
  • the mode signal EN flips from the high level state to the low level state, and accordingly, the second input end of the AND gate 32 receives the mode signal in the low level state.
  • the first input end of the AND gate 32 has not received the signal in the low level state due to the delayed transmission of the first delay unit 31, the second input end of the AND gate 32 has received the signal in the low level state.
  • the AND gate 32 immediately outputs the signal in the low level state to the second switch 112, and the second switch 112 is turned off.
  • the second control unit is formed by the delay unit and the AND gate, thereby simplifying the circuit structure.
  • the first switch when switching from the idle state to the working state, the first switch is first disconnected to disconnect the control end of the transmission module from the second power supply signal.
  • the second control unit turns on the second switch to ground the control end of the transmission module, so as to avoid the control end of the transmission module from being pulled down too early when the second switch is still connected to the second power supply signal, resulting in an increase in discharge, thereby avoiding energy waste, saving energy consumption, and improving the reliability of power supply control.
  • the transmission module when the memory switches from the working state to the idle state, the transmission module needs to be disconnected to cut off the power supply of the circuit module.
  • the transmission module is a low level conduction device and a high level shutoff device.
  • the transmission module is shut off by increasing the voltage at the control end of the transmission module to a second voltage after reaching a stable state, wherein the second voltage is higher than the voltage of the first power signal.
  • FIG12 is a structural example diagram of a power control circuit provided by an embodiment.
  • the control module 11 further includes: a third switch 115 and a third control unit 116;
  • a first end of the third switch 115 is connected to the first power signal VCC, and a second end of the third switch 115 is connected to the control end of the transmission module 12;
  • the input end of the third control unit 116 is connected to the first control unit 113, and the output end of the third control unit 116 is connected to the control end of the third switch 115; the third control unit 116 is used to control the third switch 115 to be turned off when the mode signal EN switches to the first level state, and to control the third switch 115 to be turned on and to be turned off after a first delay t1 when the mode signal EN switches to the second level state.
  • FIG13 is an example timing diagram, wherein KsGate represents the signal at the control end of the transmission module, K1Gate represents the signal at the control end of the first switch, K2Gate represents the signal at the control end of the second switch, and K3Gate represents the signal at the control end of the third switch.
  • the third switch includes a third PMOS transistor. It should be noted that the third switch can also be implemented by other structures that can be turned on and off, such as a transmission gate structure, etc., and other possible methods are not limited here.
  • the mode signal EN when the memory switches from the idle state to the working state, the mode signal EN is flipped from a low level signal to a high level state, and accordingly, the first control unit 113 controls the first switch 111 to be disconnected, that is, the second power signal VCCH is disconnected from the control end of the transmission module 12; at the same time, when the mode signal EN is flipped from a low level signal to a high level state, the third control unit 116 immediately controls the third switch 115 to be turned off, that is, the first power signal VCC is disconnected from the control end of the transmission module 12; and when the mode signal EN is flipped from a low level signal to a high level state, the second switch 112 still maintains the off state before the mode signal EN is flipped to a high level, until after the second delay t2, the second control unit 114 controls the second switch 112 to be turned on.
  • the voltage at the control end of the transmission module 12 is grounded through the turned-on second switch 112, the transmission module 12 is turned on, and the
  • the mode signal EN is flipped from a high level signal to a low level state. Accordingly, the second control unit 114 immediately controls the second switch 112 to be disconnected. At the same time, the third control unit 116 first controls the third switch 115 to be turned on, so that the first power signal VCC is electrically connected to the control end of the transmission module 12, and the voltage at the control end of the transmission module 12 is pulled up by VCC until the first delay t1 passes.
  • the first switch 111 continues to maintain the previous off state, that is, the second power signal VCCH and the control end of the transmission module 12 are still in a disconnected state, and the control end of the transmission module 12 is only charged by the first power signal VCC until the first delay t1 passes.
  • the third control unit 116 controls the third switch 115 to be turned off, and the first control unit 113 controls the first switch 111 to be turned on, that is, the control end of the transmission module 12 is disconnected from the first power signal VCC and turned on to the second power signal VCC.
  • the control end of the transmission module 12 is continuously charged by the second power signal VCCH until the second voltage reaches a stable state, the transmission module 12 is completely shut down, and the circuit module 13 stops supplying power.
  • the third control unit 116 includes: a NOT gate 41 and a second OR gate 42; wherein,
  • the input end of the NOT gate 41 is connected to the output end of the second delay unit 211 , and the output end of the NOT gate 41 is connected to the first input end of the second OR gate 42 ;
  • a second input terminal of the second OR gate 42 is connected to the input terminal of the second delay unit 211 , and an output terminal of the second OR gate 42 is connected to the control terminal of the third switch 115 .
  • the mode signal EN when the memory is switched from the idle state to the working state, the mode signal EN is flipped from a low level signal to a high level state. Accordingly, the first logic unit 21 outputs a signal with a high level state in response to the received high level signal.
  • the first level conversion unit 22 performs voltage conversion on the high level signal output by the first logic unit 21, and outputs a high level signal with a voltage magnitude of the second voltage, thereby controlling the first switch 111 to be turned off, and the second power supply signal VCCH is disconnected from the control end of the transmission module 12.
  • the second input end of the second OR gate 42 receives a high level mode signal and immediately outputs a high level signal, thereby controlling the third switch 115 to be turned off, that is, the first power supply signal VCC is disconnected from the control end of the transmission module 12.
  • the second switch 112 still maintains the off state before the mode signal EN is flipped to a high level until the second delay t2 passes, and the second control unit 114 controls the second switch 112 to be turned on.
  • the voltage at the control end of the transmission module 12 is grounded through the turned-on second switch 112 , the transmission module 12 is turned on, and the circuit module 13 is powered.
  • the mode signal EN is flipped from a high level signal to a low level state. Accordingly, the second control unit 114 immediately controls the second switch 112 to be disconnected. At the same time, due to the second delay unit 211 in the first logic unit 21, the input end of the NOT gate 41 has not received the mode signal in the low level state, and the NOT gate 41 still outputs a low level signal to the first input end of the second OR gate 42. At this time, the second input end of the second OR gate 42 has received the mode signal in the low level state, so the output of the second OR gate 42 is flipped from a high level state to a low level state, so that the third switch 115 is turned on.
  • the second input end of the first OR gate 212 has not received the flipped low level state signal, and still receives a high level signal, so the first OR gate 212 outputs a high level signal.
  • the first switch 111 continues to maintain the previous off state, and only the first power signal VCC charges the control end of the transmission module 12; until the first delay t1 of the second delay unit passes, the second delay unit 211 outputs a low-level state mode signal, and after the input end of the NOT gate 41 receives the low-level signal, it outputs a high-level signal to the first input end of the second OR gate 42, and the second OR gate 42 outputs a high-level state to control the third switch 15 to be disconnected.
  • the low-level state mode signal output by the second delay unit 211 is also transmitted to the second input end of the first OR gate 212, and the output of the first OR gate 212 is flipped to a low-level signal, the first switch 111 is turned on, and the second power signal VCCH charges the control end of the transmission module 12 until it stabilizes to the second voltage, the transmission module 12 is completely shut down, and the circuit module 13 stops supplying power.
  • the third control unit is formed by a NOT gate and an OR gate, and the third switch can be instantly controlled or delayed controlled according to the switching of the mode signal. Then, under the cooperation of the third switch and the first switch, the voltage at the control end of the transmission module is stepped up, thereby realizing power supply control, saving charging current, and saving power consumption.
  • the third control unit 116 further includes: a second level conversion unit 43; the input end of the second level conversion unit 43 is connected to the output end of the second OR gate 42, the output end of the second level conversion unit 43 is connected to the control end of the third switch 115, and the delay of the second level conversion unit 43 is consistent with the delay of the first level conversion unit 22.
  • the second level conversion unit 43 may include a level converter. In this example, by setting the second level conversion unit, it is possible to match the delay generated by the first level conversion unit, calibrate the time difference of the control signals received by the first switch and the third switch, improve the time accuracy of the cooperation between the first switch and the third switch, and further improve the reliability of power supply control.
  • a third control unit and a third switch are set up, and the third control unit is used to control the on and off timing of the third switch, so that the voltage at the control end of the transmission module is step-up under the cooperation of the third switch and the first switch, so as to save charging current and power consumption while realizing power supply control.
  • the control module outputs control signals of different voltages in response to different level states of the mode signal
  • the transmission module coupled between the main power supply and the circuit module is turned on or off under the control of the control signals of different voltages to realize the power control of each circuit module, wherein the voltage of the control signal used to control the disconnection of the transmission module is higher than the voltage of the main power supply.
  • the second embodiment of the present disclosure provides a memory, which includes: a circuit module and a power control circuit as described above; wherein:
  • the power control circuit is coupled to the circuit module, and is used to provide a first power signal to the circuit module in a working state, and stop providing the first power signal to the circuit module in an idle state.
  • the mode signal when the memory is working normally, the mode signal is in a high level state.
  • the circuit module needs to work normally, and accordingly, the control module of the power control circuit responds to the high level state of the mode signal and outputs a control signal, and the voltage of the control signal at this time is a first voltage, and the first voltage represents a low level state; the transmission module of the power control circuit is turned on under the control of the control signal in the low level state, and the first power signal is used as the total power supply, and the power supply of the circuit module is generated through the transmission module of the power control circuit to supply power to the circuit module.
  • the mode signal When the memory is idle, the mode signal is in a low level state.
  • the circuit module does not need to work, and accordingly, the control module of the power control circuit responds to the low level state of the mode signal and outputs a control signal.
  • the voltage of the control signal at this time is a second voltage, and the second voltage represents a high level state and the second voltage is higher than the voltage of the first power signal; the transmission module of the power control circuit is turned off under the control of the control signal in the high level state, and the transmission module between the first power signal and the circuit module is turned off, and no power is supplied to the circuit module.
  • the transmission module is turned off by a control signal with a voltage higher than the voltage of the first power signal, and the leakage current passing through the transmission module in the off state can be further reduced while the transmission module is turned off, thereby achieving the effect of reducing the IDD2P current.
  • the second voltage is the voltage after the control signal reaches a stable state.
  • the control module of the power control circuit responds to different level states of the mode signal and outputs control signals of different voltages.
  • the transmission module coupled between the main power supply and the circuit module is turned on or off under the control of the control signals of different voltages to realize the power control of each circuit module, wherein the voltage of the control signal used to control the disconnection of the transmission module is higher than the voltage of the main power supply.
  • a second voltage higher than the main power supply voltage is used to control the disconnection of the transmission module.
  • leakage current can be effectively reduced, thereby improving the reliability of power control and further reducing power consumption.

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Abstract

本公开提供一种电源控制电路及存储器，包括：控制模块，耦接于传输模块的控制端，用于响应于模式信号处于第一电平状态，输出第一电压的控制信号；以及，响应于模式信号处于第二电平状态，输出第二电压的控制信号；传输模块，耦接在第一电源信号和电路模块之间，用于响应于第一电压的控制信号，将第一电源信号传输至电路模块；以及，响应于第二电压的控制信号，断开传输；其中，第一电压表征低电平状态，第二电压高于第一电源信号的电压。本方案能够减小漏电流。

Description

电源控制电路及存储器
本公开要求于2022年10月12日提交中国专利局、申请号为202211249968.9、申请名称为“电源控制电路及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器技术，尤其涉及一种电源控制电路及存储器。
背景技术
伴随存储器技术的发展，存储器被广泛应用在多种领域，比如，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的使用非常广泛。
实际应用中，存储器内部包含多个电路模块，电路模块在工作时需要电源信号，这里的电源信号比如，供电电源、接地电源等。为了便于电源管理，降低功耗，在一些示例中设置总电源，通过控制总电源与电路模块之间的传输模块，来实现各电路模块的电源控制。故需考虑如何实现有效的电源控制。
发明内容
本公开的实施例提供一种电源控制电路及存储器。
根据一些实施例，本公开第一方面提供一种电源控制电路，包括：控制模块，耦接于传输模块的控制端，用于响应于模式信号处于第一电平状态，输出第一电压的控制信号；以及，响应于所述模式信号处于第二电平状态，输出第二电压的控制信号；所述传输模块，耦接在第一电源信号和电路模块之间，用于响应于所述第一电压的控制信号，将所述第一电源信号传输至所述电路模块；以及，响应于所述第二电压的控制信号，断开传输；其中，所述第一电压表征低电平状态，所述第二电压高于所述第一电源信号的电压。
在一些实施例中，所述传输模块包括：第一PMOS晶体管；所述第一PMOS晶体管的源极接收所述第一电源信号，所述第一PMOS晶体管的漏极连接至所述电路模块；所述第一PMOS晶体管的栅极作为所述传输模块的控制端，连接至所述控制模块。
在一些实施例中，所述控制模块包括：第一开关、第二开关以及第一控制单元；所述第一开关的第一端连接第二电源信号，所述第一开关的第二端与所述传输模块的控制端连接；所述第二电源信号的电压为所述第二电压；所述第一控制单元的输入端连接所述模式信号，第一控制单元的输出端与所述第一开关的控制端连接；所述第一控制单元用于当所述模式信号切换至所述第一电平状态时，控制所述第一 开关关断，以及当所述模式信号切换至所述第二电平状态时，经过第一延时后控制所述第一开关导通；所述第二开关的第一端连接至所述传输模块的控制端，所述第二开关的第二端接地，所述第二开关的控制端连接所述模式信号；所述第二开关用于当所述模式信号切换至所述第一电平状态时导通，以及当所述模式信号切换至所述第二电平状态时关断。
在一些实施例中，所述控制模块还包括：第二控制单元；所述第二控制单元的输入端连接所述模式信号，所述第二控制单元的输出端与所述第二开关的控制端连接；所述第二控制单元用于当所述模式信号切换至所述第一电平状态时，经过第二延时后控制所述第二开关导通，以及当所述模式信号切换至所述第二电平状态时，控制所述第二开关关断。
在一些实施例中，所述第二控制单元包括：第一延时单元和与门；所述与门的第一输入端与所述第一延时单元的输出端连接，所述与门的第二输入端连接所述模式信号，所述与门的输出端连接至所述第二开关的控制端；所述第一延时单元的输入端与所述与门的第二输入端连接，所述第一延时单元用于将接收的信号经过所述第二延时后传输至所述与门的第一输入端。
在一些实施例中，所述第一控制单元包括：第一逻辑单元和第一电平转换单元；所述第一逻辑单元的输入端连接所述模式信号，所述第一逻辑单元的输出端连接至所述第一电平转换单元的输入端；所述第一逻辑单元用于当接收的信号切换至所述第一电平状态时，输出电平状态为所述第一电平状态的信号，以及当接收的信号切换至所述第二电平状态时，经过所述第一延时后输出电平状态为所述第二电平状态的信号；所述第一电平转换单元的输出端与所述第一开关的控制端连接；所述第一电平转换单元用于将接收到的高电平信号的电压转换为所述第二电压。
在一些实施例中，所述第一逻辑单元包括：第二延时单元和第一或门；所述第一或门的第一输入端连接所述模式信号，所述第一或门的第二输入端与所述第二延时单元的输出端连接，所述第一或门的输出端与所述第一电平转换单元的输入端连接；所述第二延时单元的输入端与所述第一或门的第一输入端连接；所述第二延时单元的延时时长为所述第一延时。
在一些实施例中，所述控制模块还包括：第三开关和第三控制单元；所述第三开关的第一端连接所述第一电源信号，所述第三开关的第二端与所述传输模块的控制端连接；所述第三控制单元的输入端与所述第一控制单元连接，所述第三控制单元的输出端与所述第三开关的控制端连接；所述第三控制单元用于当所述模式信号切换至所述第一电平状态时，控制所述第三开关关断，以及当所述模式信号切换至所述第二电平状态时，控制所述第三开关导通并经过所述第一延时后控制所述第三开关关断。
在一些实施例中，所述第三控制单元包括：非门和第二或门；所述非门的输入端与所述第二延时单元的输出端连接，所述非门的输出端与所述第二或门的第一输入端连接；所述第二或门的第二输入端与所述第二延时单元的输入端连接，所述第二或门的输出端与所述第三开关的控制端连接。
在一些实施例中，所述第三控制单元还包括：第二电平转换单元；所述第二电平转换单元的输入端 与所述第二或门的输出端连接，所述第二电平转换单元的输出端与所述第三开关的控制端连接，所述第二电平转换单元的延迟与所述第一电平转换单元的延迟一致。
在一些实施例中，所述第一开关包括第二PMOS晶体管，所述第二开关包括第一NMOS晶体管。
在一些实施例中，所述第三开关包括第三PMOS晶体管。
在一些实施例中，所述第二电压与所述第一电源信号的电压之间的电压差位于0.2～0.3伏的电压范围。
在一些实施例中，所述模式信号处于第一电平状态表征工作状态，所述模式信号处于第二电平状态表征空闲状态。
根据一些实施例，本公开第二方面提供一种存储器，包括：电路模块以及如前所述的电源控制电路；所述电源控制电路，耦接于所述电路模块，用于在工作状态下向所述电路模块提供第一电源信号，以及在空闲状态下停止向所述电路模块提供所述第一电源信号。
本公开实施例提供的电源控制电路及存储器中，控制模块响应于模式信号的不同电平状态，输出不同电压的控制信号，耦接在总电源和电路模块之间的传输模块在不同电压的控制信号的控制下，导通或者关断，以实现各电路模块的电源控制，其中，用于控制传输模块断开的控制信号的电压高于总电源的电压。本方案中，当无需向电路模块提供电源信号时，采用高于总电源电压的第二电压来控制传输模块断开，相比于采用普通的电源电压的信号来控制传输模块断开，可以有效减小漏电流，从而提高电源控制的可靠性，并且进一步降低功耗。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开实施例的原理。
图1为本公开一实施例示出的存储器的架构示例图；
图2为本公开一实施例示出的存储单元的结构示例图；
图3为一示例的电源控制电路的结构示例图；
图4为一实施例提供的电源控制电路的结构示例图；
图5为工作状态下电源控制电路的状态示例图；
图6为空闲状态下电源控制电路的状态示例图；
图7为一实施例提供的电源控制电路的结构示例图；
图8为一示例的时序图；
图9为一实施例提供的电源控制电路的结构示例图；
图10为一实施例提供的电源控制电路的结构示例图；
图11为一示例的时序图；
图12为一实施例提供的电源控制电路的结构示例图；
图13为一示例的时序图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开中的用语“包括”和“具有”用以表示开放式的包括在内的意思，并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记或区分使用，不是对其对象的先后顺序或数量限制。此外，附图中的不同元件和区域只是示意性示出，因此不限于附图中示出的尺寸或距离。
下面以具体的实施例对技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图1为本公开一实施例示出的存储器的架构示例图，如图1所示，以DRAM作为示例，包括数据输入/输出缓冲、行解码器、列解码器、感测放大器以及存储阵列。存储阵列主要由字线、位线和存储单元组成。存储阵列中的字线沿行方向延伸，存储阵列中的位线沿列方向延伸，字线与位线的交叉处为存储阵列的存储单元。
其中，每个存储单元用于存储一个位(bit)的数据。如图2所示，图2为本公开一实施例示出的存储单元的结构示例图，存储单元主要由晶体管M和电容C组成。其中，电容用于存储数据，晶体管用于根据字线状态，关断或导通。
可以通过控制行和列来激活某个存储单元，以实现对该存储单元的访问。结合读取场景作为示例：需要读取存储单元中的数据时，可以通过行解码器选中该存储单元所在行的字线，相应的，图示中的晶体管M导通，通过对位线信号的感测放大就可以感知到此时电容C上的状态。例如，如果存储单元中存储的数据为1，那么晶体管M导通后就会从存储单元的位线上读到1，反之也是同样的道理。另外，结合写入场景作为示例：需要向某存储单元中写入数据时，比如写入1。可以通过行解码器选中该存储单元所在行的字线，相应的图示中的晶体管M导通，通过将位线的逻辑电平设为1，使得电容C充电，即向存储单元写入1。反之，如果要写入0，那么位线的逻辑电平设为0，使得电容C放电，即向存储单元写入 0。
基于上述示例，可以理解，在存储器内部包含多个不同的电路模块，比如数据输入/输出缓冲、行解码器、列解码器、感测放大器等，各个电路模块配合工作来实现存储器的功能，比如数据的写入和读取。故为了便于电源管理和节省功耗，在一些示例中设置总电源，在总电源与各电路模块之间设置有各传输模块，通过控制传输模块导通或关断，来控制是否向电路模块提供电源信号。这里的电源信号包括但不限于供电电源VCC和/或接地电源VSS。
作为示例，图3为一示例的电源控制电路的结构示例图，如图3所示，示例为应用于存储器的电源控制方案。以供电电源VCC为电源控制电路的总电源为例，VCC是一个总电源，但并非直接连至所有电路模块提供供电。总电源VCC通过一个或多个传输模块来给不同的电路模块供电。通过控制传输模块的导通和关断(比如，通过向传输模块的控制端施加低电平信号或电压为VCC电压的信号)，从而可以控制存储器在不同工作状态时，给不同的电路模块供电。比如图中，VCC通过传输模块产生VCCZ给逻辑电路供电，基于电源控制，当存储器处于空闲状态时，如果示例的电路模块不需要工作，就可以关断传输模块，不向该电路模块提供VCCZ，以节省功耗。实际场景下VCCZ的电压和VCC的电压可以一致，故在以下实施例的一些描述中，对两者的称呼未作明显区分。实际应用中，当存储器处于空闲状态时，存在一些设计参数需要尽量优化，比如，IDD2P电流。具体的，IDD2P电流指当存储器处于空闲状态，时钟使能信号和片选信号都为无效状态，数据线保持不变，命令/地址线信号不接收命令和地址信号，故同样保持不变，此时状态下的存储器消耗的总电流。实际应用中，希望降低IDD2P电流。
本公开实施例的一些方面涉及上述考虑。以下结合本公开的一些实施例对方案进行示例介绍。
实施例一
图4为一实施例提供的电源控制电路的结构示例图，如图4所示，该电源控制电路包括：
控制模块11，耦接于传输模块12的控制端，用于响应于模式信号处于第一电平状态，输出第一电压的控制信号；以及，响应于模式信号处于第二电平状态，输出第二电压的控制信号；
传输模块12，耦接在第一电源信号VCC和电路模块13之间，用于响应于第一电压的控制信号，将第一电源信号VCC传输至电路模块13；以及，响应于第二电压的控制信号，断开传输；其中，第一电压表征低电平状态，第二电压高于第一电源信号VCC的电压。
实际应用中，本实施例提供的芯片测试电路可应用在各种存储器，作为示例，可以应用在包括但不限双倍速率同步动态随机存储器(简称DDR)等。其中，模式信号可以理解为一个标志信号，用于表征当前处于工作状态或者空闲状态。在一个示例中，模式信号处于第一电平状态表征工作状态，模式信号处于第二电平状态表征空闲状态。
举例来说，在工作状态下，即存储器处于ACTIVE模式，模式信号此时为高电平状态；相反的，在空闲状态下，或者也称存储器处于IDD2P模式，模式信号此时为低电平状态。也就是说，在一个示例中， 第一电平状态为高电平状态，第二电平状态为低电平状态。本实施例不对模式信号的生成方式进行限制。
以DDR为例，结合图5和图6进行示例说明：图5为工作状态下电源控制电路的状态示例图，如图所示，当存储器正常工作时，模式信号EN处于高电平状态。电路模块需正常工作，相应的，控制模块11响应于模式信号EN的高电平状态(图中示例为“1”)，输出控制信号，此时的控制信号的电压为第一电压，且第一电压表征低电平状态(图中示例为“0”)；传输模块12在低电平状态的控制信号的控制下导通，第一电源信号VCC作为总电源，经过传输模块12产生电路模块13的电源VCCZ，向该电路模块13供电。
图6为空闲状态下电源控制电路的状态示例图，如图所示，当存储器空闲时，模式信号EN处于低电平状态。电路模块不需工作，相应的，控制模块11响应于模式信号EN的低电平状态(图中示例为“0”)，输出控制信号，此时的控制信号的电压为第二电压，第二电压表征高电平状态(图中示例为“1”)且第二电压VCCH高于第一电源信号VCC的电压；传输模块12在高电平状态的控制信号的控制下关断，第一电源信号VCC与电路模块13之间的传输模块12关断，不向电路模块13供电。需要说明的是，本实施例中，通过电压高于第一电源信号的电压的控制信号关断传输模块12，能够在关断传输模块的同时，进一步减小关断状态下经过传输模块的漏电流，从而达到降低IDD2P电流的效果。其中，第二电压为控制信号达到稳定状态后的电压。在一个示例中，第二电压与第一电源信号VCC的电压之间的电压差位于0.2～0.3伏的电压范围。
本实施例中，传输模块为低电平导通。实际应用中，传输模块的具体结构可以通过多种电路结构实现，本实施例在此不对其进行限制。在一个示例中，传输模块12包括：第一PMOS晶体管；第一PMOS晶体管的源极接收第一电源信号VCC，第一PMOS晶体管的漏极连接至电路模块13；第一PMOS晶体管的栅极作为传输模块12的控制端，连接至控制模块11。本示例中，通过单个MOS器件实现传输模块，能够在快速及时响应电源控制的同时，进一步简化电路结构，降低成本。
在另一个示例中，传输模块12可以包括：传输门和一个反相器。具体的，传输门的结构不限，比如传输门可以由PMOS和NMOS对称并联连接构成，反相器的输入端连接控制信号，输出端连接NMOS的控制端，即栅极。实际应用中，传输门具有较低的导通电阻和较高的截止电阻，因此能够有效实现电源控制。
为了实现提供高于第一电源信号电压的控制信号，在一个示例中，图7为一实施例提供的电源控制电路的结构示例图，关于控制模块11的架构进行示例，如图所示，控制模块11包括：第一开关111、第二开关112以及第一控制单元113；
第一开关111的第一端连接第二电源信号VCCH，第一开关111的第二端与传输模块12的控制端连接；第二电源信号VCCH的电压为第二电压；
第一控制单元113的输入端连接模式信号EN，第一控制单元113的输出端与第一开关111的控制端 连接；第一控制单元113用于当模式信号EN切换至第一电平状态时，控制第一开关111关断，以及当模式信号EN切换至第二电平状态时，经过第一延时t1后控制第一开关111导通；
第二开关112的第一端连接至传输模块的13控制端，第二开关112的第二端接地，第二开关112的控制端连接模式信号EN；第二开关112用于当模式信号EN切换至第一电平状态时导通，以及当模式信号EN切换至第二电平状态时关断。
结合图8进行示例：图8为一示例的时序图，其中，KsGate表征传输模块的控制端处的信号，即控制信号；K1Gate表征第一开关的控制端处的信号；K2Gate表征第二开关的控制端处的信号。
当存储器处于工作状态时，模式信号EN为高电平状态，相应的，第一控制单元113在模式信号EN为高电平状态时，控制第一开关111关断，第二电源信号VCCH和传输模块12的控制端之间断开，同时第二开关112在模式信号EN为高电平状态时导通，故传输模块12的控制端通过导通的第二开关112接地，此时传输模块12的控制端处的电压为接地电压，即为低电平状态。相应的，传输模块12响应于控制端的低电平状态导通，第一电源信号VCC经过导通的传输模块12产生VCCZ提供给电路模块。
在一个示例中，第一开关包括第二PMOS晶体管，第二开关包括第一NMOS晶体管。需要说明的是，第一开关和第二开关也可以通过其它能够实现导通和关断的结构实现，比如传输门结构等，在此不对其它可能的方式进行限制。
当存储器处于空闲状态时，模式信号EN为低电平状态，相应的，第一控制单元113在模式信号EN切换为低电平状态时，先经过第一延时t1，之后再控制第一开关111导通。也就是说，在模式信号刚由高电平状态切换至低电平状态时，第一开关111仍会保持一段时间处于关断状态，直至经过第一延时t1后，在第一控制单元113的控制下导通，从而第二电源信号VCCH和传输模块12的控制端之间通过导通的第一开关111电连接。并且，在模式信号由高电平状态切换至低电平状态时，第二开关112关断，故传输模块12的控制端与接地信号之间断开，控制端处的电压通过导通的第一开关111，由第二电源信号VCCH上拉至第二电压，第二电压高于第一电源信号VCC的电压。相应的，传输模块12响应于控制端的高电平状态关断，第一电源信号VCC与电路模块13之间断开电连接。需要说明的是，本实施例中的“连接”包括直接连接和间接连接。
本示例中，控制模块由两个开关和第一控制单元构成，能够在工作状态和空闲状态下分别输出表征低电平状态的控制信号和电压高于第一电源信号的电压的控制信号，从而实现电源控制的同时，降低漏电流。并且本实施例中，在控制策略中加入适当延迟，具体的，当由工作状态切换至空闲状态时，先断开第二开关以断开接地，待经过第一延迟后方导通第一开关，以上拉控制单元的控制端处电压，避免电压上拉过程中，如果第一开关导通过早第二开关尚正处于接地，导致充电效果不足的情况，从而避免电能浪费，节省能耗。
其中，第一控制单元的实现结构不限。在一些示例中，图9为一实施例提供的电源控制电路的结构 示例图，如图9所示，第一控制单元113包括：第一逻辑单元21和第一电平转换单元22；其中，
第一逻辑单元21的输入端连接模式信号EN，第一逻辑单元21的输出端连接至第一电平转换单元22的输入端；第一逻辑单元21用于当接收的信号切换至第一电平状态时，输出电平状态为第一电平状态的信号，以及当接收的信号切换至第二电平状态时，经过第一延时t1后输出电平状态为第二电平状态的信号；
第一电平转换单元22的输出端与第一开关111的控制端连接；第一电平转换单元22用于将接收到的高电平信号的电压转换为第二电压。
其中，第一延时t1的时长可以根据情况设定。结合前述内容，第一开关111的第一端连接至第二电源信号VCCH，第二电源信号VCCH的电压为第二电压，高于通常的第一电源信号VCC的电压，故为了进一步保证第一开关111的有效导通和关断，为第一开关111适配合适的控制电压。
具体的，本示例中设置第一电平转换单元22，用于当接收到的信号为表征高电平状态的信号时，将该信号的电压转换为适配第一开关111的电压，比如，第二电压。作为示例，第一电平转换单元22可以包括电平转换器。
以第一开关为PMOS晶体管进行举例，当希望导通第一开关时，第一电平转换单元22将接收到表征低电平状态的信号，此时可以不进行电压大小的转换，这是因为，第一开关的源极连至第二电源信号，第一开关的栅极接收到表征低电平状态的信号时，故在第一开关的栅极和源极之间能够形成压差且压差大小达到PMOS晶体管的导通阈值电压，故第一开关可及时导通。相反的，当希望关断第一开关时，第一电平转换单元22将接收到表征高电平状态的信号(比如，电压为第一电源信号VCC的电压)，第一开关的源极连至第二电源信号，第二电源信号的电压大小为第二电压，高于VCC的电压，PMOS晶体管栅极的电压仍小于源极的电压，导致关断不完全。故本示例中，设置第一电平转换单元22，用于当接收到表征高电平状态的信号时，则将接收的的信号的电压进行转换，得到电压大小为第二电压的信号，以有效控制第一开关关断。
其中，第一逻辑单元21主要用于控制第一开关的导通和关断时机。具体的，当存储器由空闲状态切换至工作状态时，第一逻辑单元21接收到的模式信号EN从低电平状态切换为高电平状态，在一个示例中，第一逻辑单元21负责响应于上述电平状态的变化，立即将改变后的模式信号EN传输至第一电平转换单元22进行电压转换，从而控制第一开关111关断，以从空闲状态切换至工作状态时，及时下拉传输模块的控制端处的电压，控制传输模块导通。另一方面，当存储器由工作状态切换至空闲状态时，第一逻辑单元21接收到的模式信号EN从高电平状态切换为低电平状态，在一个示例中，第一逻辑单元21负责响应于上述电平状态的变化，仍维持之前的输出(高电平状态的信号)，相应的，第一电平转换单元22仍进行电压转换，第一开关111仍关断，直至经过第一延时t1后第一逻辑单元21将改变后的模式信号EN(此时为低电平状态)传输至第一电平转换单元22，第一电平转换单元22无需进行电压转换， 将低电平信号输出给第一开关111，以控制第一开关111导通，从而实现从工作状态切换至空闲状态时，延时上拉传输模块的控制端处的电压，以延时关断传输模块，提高电源控制的可靠性。
作为示例，如图9所示，第一逻辑单元21包括：第二延时单元211和第一或门212；其中，第一或门212的第一输入端连接模式信号EN，第一或门212的第二输入端与第二延时单元211的输出端连接，第一或门212的输出端与第一电平转换单元22的输入端连接；第二延时单元211的输入端与第一或门212的第一输入端连接；第二延时单元211的延时时长为第一延时t1。
具体的，当存储器由空闲状态切换至工作状态时，模式信号EN由低电平状态翻转为高电平状态，相应的，第一或门212的第一输入端和第二延时单元211的输入端接收到高电平状态的模式信号，尽管因为第二延时单元211的延时传输，第一或门212的第二输入端尚未接收到高电平状态的信号，但由于第一或门212的第一输入端已接收到高电平状态信号，通过或逻辑运算，第一或门212即刻输出高电平状态的信号至第一电平转换单元22进行电压转换，转换后的高电平信号传输至第一开关111，第一开关111关断。另一种情形，当存储器由工作状态切换至空闲状态时，模式信号EN由高电平状态翻转为低电平状态，相应的，第一或门212的第一输入端和第二延时单元211的输入端接收到低电平状态的模式信号，第一或门212的输出取决于第二输入端接收到的信号，因为第二延时单元211的延时传输，此时第一或门212的第二输入端尚未接收到翻转后的低电平状态的信号，即当前接收到的仍为高电平信号，故第一或门212仍输出高电平状态的信号，第一开关111保持关断；直至翻转为低电平的模式信号经过第二延时单元211的延时传输，到达第一或门212的第二输入端，则经过或逻辑运算，当前两个输入均为低电平信号，故第一或门212的输出翻转为低电平信号，第一开关导通。
上述示例的方式中，通过延时单元和或门构成第一逻辑单元，能够根据模式信号的切换情况，实现对第一开关的即刻控制或者延时控制，并且能够简化电路，节约成本。
本示例中，第一控制单元包括第一逻辑单元和第一电平转换单元，第一逻辑单元用于控制第一开关的导通和关断时机，第一电平转换单元用于对接收到的高电平信号进行电压转换，以适配第一开关的控制电压，从而实现对第一开关进行有效控制，实现及时可靠的电源控制。
此外，考虑到整个电路的延迟匹配，在一个示例中，图10为一实施例提供的电源控制电路的结构示例图，如图10所示，控制模块11还包括：第二控制单元114；
第二控制单元114的输入端连接模式信号EN，第二控制单元114的输出端与第二开关112的控制端连接；
第二控制单元114用于当模式信号EN切换至第一电平状态时，经过第二延时t2后控制第二开关112导通，以及当模式信号EN切换至第二电平状态时，控制第二开关112关断。
结合图11进行示例：图11为一示例的时序图。当存储器由空闲状态切换至工作状态时，模式信号EN由低电平状态切换为高电平状态，第一控制单元113马上控制第一开关111关断，第二电源信号VCCH 和传输模块12的控制端之间断开，同时模式信号EN由低电平状态切换为高电平状态时，第二开关112在第二控制单元114的控制下，先保持关断，直至经过第二延时t2后导通，传输模块12的控制端通过导通的第二开关112接地，传输模块12响应于控制端的低电平状态导通，第一电源信号VCC经过导通的传输模块12产生VCCZ提供给电路模块，电路模块开始工作。当存储器由工作状态切换至空闲状态时，模式信号EN由高电平状态切换为低电平状态，第一控制单元113在模式信号EN切换为低电平状态时，先经过第一延时t1，之后再控制第一开关111导通，第二电源信号VCCH和传输模块12的控制端之间通过导通的第一开关111电连接。在模式信号EN由高电平状态切换至低电平状态时，第二开关112即刻被关断，故传输模块12的控制端与接地电压之间断开，控制端处的电压上拉至第二电压，第二电压高于第一电源信号VCC的电压。相应的，传输模块12响应于控制端的高电平状态关断，第一电源信号VCC与电路模块13之间断开电连接。
在一些示例中，如图10所示，第二控制单元114包括：第一延时单元31和与门32；其中，与门32的第一输入端与第一延时单元31的输出端连接，与门22的第二输入端连接模式信号EN，与门32的输出端连接至第二开关112的控制端；第一延时单元31的输入端与与门32的第二输入端连接，第一延时单元31用于将接收的信号经过第二延时t2后传输至与门32的第一输入端。
其中，第一延时单元的延时为第二延时t2，第二延时t2的时长可以根据情况设定，比如，第一延时t1和第二延时t2的时长可以相同也可以不同。实际应用中，可以将t2设置为较小的值或者不设置延时，以保证及时供电。具体的，当存储器由空闲状态切换至工作状态时，模式信号EN由低电平状态翻转为高电平状态，相应的，与门32的第二输入端和第一延时单元31的输入端接收到高电平状态的模式信号，与门32的输出取决于第一输入端接收到的信号，因为第一延时单元31的延时传输，此时与门32的第一输入端尚未接收到翻转后的高电平状态的信号，即当前接收到的仍为低电平信号，故与门32仍输出低电平状态的信号，第二开关112保持关断；直至翻转为高电平的模式信号经过第一延时单元31的延时传输，到达与门32的第一输入端，则经过与逻辑运算，当前两个输入均为高电平信号，故与门32的输出翻转为高电平信号，第二开关112导通。
另一种情形，当存储器由工作状态切换至空闲状态时，模式信号EN由高电平状态翻转为低电平状态，相应的，与门32的第二输入端接收到低电平状态的模式信号，尽管因为第一延时单元31的延时传输，与门32的第一输入端尚未接收到低电平状态的信号，但由于与门32的第二输入端已接收到低电平状态信号，通过与逻辑运算，与门32即刻输出低电平状态的信号至第二开关112，第二开关112关断。本示例中，通过延时单元和与门构成第二控制单元，从而简化电路结构。
上述示例中，当由空闲状态切换至工作状态时，先断开第一开关以使传输模块的控制端与第二电源信号之间先断开，待经过第二延迟后第二控制单元方导通第二开关，以将传输模块的控制端接地，避免传输模块的控制端电压下拉过程中，如果第二开关过早导通第一开关尚仍接至第二电源信号，导致放电 量加大，从而避免电能浪费，节省能耗，提高电源控制的可靠性。
结合前述内容，当存储器由工作状态切换至空闲状态时，需断开传输模块以切断电路模块的供电。在一个示例中，传输模块为低电平导通，高电平关断器件。本实施例中，通过将传输模块的控制端处的电压提升至稳定状态后达到第二电压来实现传输模块的关断，其中，第二电压高于第一电源信号的电压。
实际应用中，为了快速将传输模块的控制端处的电压提升至第二电压需要较大的充电电流，故出于节省功耗的考虑，在一个示例中，图12为一实施例提供的电源控制电路的结构示例图，如图12所示，控制模块11还包括：第三开关115和第三控制单元116；
第三开关115的第一端连接第一电源信号VCC，第三开关115的第二端与传输模块12的控制端连接；
第三控制单元116的输入端与第一控制单元113连接，第三控制单元116的输出端与第三开关115的控制端连接；第三控制单元116用于当模式信号EN切换至第一电平状态时，控制第三开关115关断，以及当模式信号EN切换至第二电平状态时，控制第三开关115导通并经过第一延时t1后控制第三开关115关断。
结合图13所示的时序图，对电源控制电路的工作过程进行示例：图13为一示例的时序图，其中，KsGate表征传输模块的控制端处的信号，K1Gate表征第一开关的控制端处的信号，K2Gate表征第二开关的控制端处的信号，K3Gate表征第三开关的控制端处的信号。在一个示例中，第三开关包括第三PMOS晶体管。需要说明的是，第三开关也可以通过其它能够实现导通和关断的结构实现，比如传输门结构等，在此不对其它可能的方式进行限制。
结合图12和图13所示，当存储器由空闲状态切换至工作状态时，模式信号EN由低电平信号翻转为高电平状态，相应的，第一控制单元113控制第一开关111断开，即第二电源信号VCCH和传输模块12的控制端之间断开；同时，在模式信号EN由低电平信号翻转为高电平状态时，第三控制单元116即刻控制第三开关115关断，即第一电源信号VCC和传输模块12的控制端之间断开；并且，在模式信号EN由低电平信号翻转为高电平状态时，第二开关112仍维持模式信号EN翻转为高电平之前的关断状态，直至经过第二延时t2，第二控制单元114控制第二开关112导通。传输模块12的控制端处电压通过导通的第二开关112接地，传输模块12导通，电路模块13被供电。
当存储器由工作状态切换至空闲状态时，模式信号EN由高电平信号翻转为低电平状态，相应的，第二控制单元114即刻控制第二开关112断开，同时，第三控制单元116先控制第三开关115导通，以使第一电源信号VCC和传输模块12的控制端之间电连接，传输模块12的控制端处电压被VCC上拉提升，直至经过第一延时t1；在此期间，第一开关111继续保持之前的关断状态，即第二电源信号VCCH和传输模块12的控制端之间仍处于断开状态，仅由第一电源信号VCC向传输模块12的控制端充电，直至经过第一延时t1；经过第一延时t1后，第三控制单元116控制第三开关115关断，同时第一控制单元113控制第一开关111导通，即传输模块12的控制端断开与第一电源信号VCC的连接，导通与第二电源信 号VCCH的连接，由第二电源信号VCCH继续向传输模块12的控制端充电，直至达到第二电压达到稳定状态，传输模块12彻底关断，电路模块13停止供电。
作为示例，如图12所示，第三控制单元116包括：非门41和第二或门42；其中，
非门41的输入端与第二延时单元211的输出端连接，非门41的输出端与第二或门42的第一输入端连接；
第二或门42的第二输入端与第二延时单元211的输入端连接，第二或门42的输出端与第三开关115的控制端连接。
需要说明的是，前述的各模块和单元，比如各控制单元和开关等的具体实现结构还可以为其它可能的结构，图中所示的电路结构仅为一种示例，本实施例并未排除其它可能的实现方式。
具体的，结合图12所示的结构，当存储器由空闲状态切换至工作状态时，模式信号EN由低电平信号翻转为高电平状态，相应的，第一逻辑单元21响应于接收到的高电平信号，输出电平状态为高电平状态的信号，第一电平转换单元22对第一逻辑单元21输出的高电平信号进行电压转换，输出电压大小为第二电压的高电平信号，从而控制第一开关111断开，第二电源信号VCCH和传输模块12的控制端之间断开；同时，在模式信号EN由低电平信号翻转为高电平状态时，第二或门42的第二输入端接收到高电平的模式信号，即刻输出高电平信号，从而控制第三开关115关断，即第一电源信号VCC和传输模块12的控制端之间断开；并且，在模式信号EN由低电平信号翻转为高电平状态时，第二开关112仍维持模式信号EN翻转为高电平之前的关断状态，直至经过第二延时t2，第二控制单元114控制第二开关112导通。传输模块12的控制端处电压通过导通的第二开关112接地，传输模块12导通，电路模块13被供电。
当存储器由工作状态切换至空闲状态时，模式信号EN由高电平信号翻转为低电平状态，相应的，第二控制单元114即刻控制第二开关112断开，同时，由于第一逻辑单元21中的第二延时单元211，非门41的输入端尚未接收到低电平状态的模式信号，非门41仍输出低电平信号至第二或门42的第一输入端，此时第二或门42的第二输入端已接收到低电平状态的模式信号，故第二或门42的输出由高电平状态翻转至低电平状态，使第三开关115导通，此时同样由于第二延时单元211，第一或门212的第二输入端尚未接收到翻转后的低电平状态的信号，仍接收到高电平信号，故第一或门212输出高电平信号，第一开关111继续保持之前的关断状态，仅由第一电源信号VCC向传输模块12的控制端充电；直至经过第二延时单元的第一延时t1，第二延时单元211输出低电平状态的模式信号，非门41的输入端接收到低电平信号后，输出高电平信号至第二或门42的第一输入端，第二或门42输出高电平状态，控制第三开关15断开，同时，第二延时单元211输出的低电平状态的模式信号也传输至第一或门212的第二输入端，第一或门212的输出翻转为低电平信号，第一开关111导通，转由第二电源信号VCCH向传输模块12的控制端充电，直至稳定至第二电压，传输模块12彻底关断，电路模块13停止供电。
上述示例的方式中，通过非门和或门构成第三控制单元，能够根据模式信号的切换情况，对第三开 关即刻控制或者延时控制，进而在第三开关和第一开关的配合作用下，实现对传输模块的控制端处的电压进行阶梯提升，从而实现电源控制，并且节省充电电流，节省功耗。
在一个示例中，为了匹配信号延迟，如图12所示，第三控制单元116还包括：第二电平转换单元43；第二电平转换单元43的输入端与第二或门42的输出端连接，第二电平转换单元43的输出端与第三开关115的控制端连接，第二电平转换单元43的延迟与第一电平转换单元22的延迟一致。可选的，第二电平转换单元43可以包括电平转换器。本示例中，通过设置第二电平转换单元，能够实现对第一电平转换单元产生的延迟进行匹配，校准第一开关和第三开关接收到的控制信号的时差，提高第一开关和第三开关配合作用的时间精度，进一步提升电源控制的可靠性。
本示例中，通过设置第三控制单元和第三开关，第三控制单元用于控制第三开关的导通和关断时机，从而实现第三开关和第一开关的配合作用下，对传输模块的控制端处的电压进行阶梯提升，以在实现电源控制的同时，节省充电电流，节省功耗。
本实施例提供的电源控制电路中，控制模块响应于模式信号的不同电平状态，输出不同电压的控制信号，耦接在总电源和电路模块之间的传输模块在不同电压的控制信号的控制下，导通或者关断，以实现各电路模块的电源控制，其中，用于控制传输模块断开的控制信号的电压高于总电源的电压。本方案中，当无需向电路模块提供电源信号时，采用高于总电源电压的第二电压来控制传输模块断开，相比于采用普通的电源电压的信号来控制传输模块断开，可以有效减小漏电流，从而提高电源控制的可靠性，并且进一步降低功耗。
实施例二
本公开实施例二提供一种存储器，该存储器包括：电路模块以及如前的电源控制电路；其中，
所述电源控制电路，耦接于所述电路模块，用于在工作状态下向所述电路模块提供第一电源信号，以及在空闲状态下停止向所述电路模块提供所述第一电源信号。
作为示例，当存储器正常工作时，模式信号处于高电平状态。电路模块需正常工作，相应的，电源控制电路的控制模块响应于模式信号的高电平状态，输出控制信号，此时的控制信号的电压为第一电压，且第一电压表征低电平状态；电源控制电路的传输模块在低电平状态的控制信号的控制下导通，第一电源信号作为总电源，经过电源控制电路的传输模块产生电路模块的电源，向该电路模块供电。
当存储器空闲时，模式信号处于低电平状态。电路模块不需工作，相应的，电源控制电路的控制模块响应于模式信号的低电平状态，输出控制信号，此时的控制信号的电压为第二电压，第二电压表征高电平状态且第二电压高于第一电源信号的电压；电源控制电路的传输模块在高电平状态的控制信号的控制下关断，第一电源信号与电路模块之间的传输模块关断，不向电路模块供电。需要说明的是，本实施例中，通过电压高于第一电源信号的电压的控制信号关断传输模块，能够在关断传输模块的同时，进一 步减小关断状态下经过传输模块的漏电流，从而达到降低IDD2P电流的效果。其中，第二电压为控制信号达到稳定状态后的电压。
本实施例提供的存储器中，电源控制电路的控制模块响应于模式信号的不同电平状态，输出不同电压的控制信号，耦接在总电源和电路模块之间的传输模块在不同电压的控制信号的控制下，导通或者关断，以实现各电路模块的电源控制，其中，用于控制传输模块断开的控制信号的电压高于总电源的电压。本方案中，当无需向电路模块提供电源信号时，采用高于总电源电压的第二电压来控制传输模块断开，相比于采用普通的电源电压的信号来控制传输模块断开，可以有效减小漏电流，从而提高电源控制的可靠性，并且进一步降低功耗。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (15)

  1. 一种电源控制电路，包括：
    控制模块，耦接于传输模块的控制端，用于响应于模式信号处于第一电平状态，输出第一电压的控制信号；以及，响应于所述模式信号处于第二电平状态，输出第二电压的控制信号；
    所述传输模块，耦接在第一电源信号和电路模块之间，用于响应于所述第一电压的控制信号，将所述第一电源信号传输至所述电路模块；以及，响应于所述第二电压的控制信号，断开传输；其中，所述第一电压表征低电平状态，所述第二电压高于所述第一电源信号的电压。
  2. 根据权利要求1所述的电源控制电路，其中，所述传输模块包括：第一PMOS晶体管；
    所述第一PMOS晶体管的源极接收所述第一电源信号，所述第一PMOS晶体管的漏极连接至所述电路模块；所述第一PMOS晶体管的栅极作为所述传输模块的控制端，连接至所述控制模块。
  3. 根据权利要求2所述的电源控制电路，其中，所述控制模块包括：第一开关、第二开关以及第一控制单元；
    所述第一开关的第一端连接第二电源信号，所述第一开关的第二端与所述传输模块的控制端连接；所述第二电源信号的电压为所述第二电压；
    所述第一控制单元的输入端连接所述模式信号，第一控制单元的输出端与所述第一开关的控制端连接；所述第一控制单元用于当所述模式信号切换至所述第一电平状态时，控制所述第一开关关断，以及当所述模式信号切换至所述第二电平状态时，经过第一延时后控制所述第一开关导通；
    所述第二开关的第一端连接至所述传输模块的控制端，所述第二开关的第二端接地，所述第二开关的控制端连接所述模式信号；所述第二开关用于当所述模式信号切换至所述第一电平状态时导通，以及当所述模式信号切换至所述第二电平状态时关断。
  4. 根据权利要求3所述的电源控制电路，其中，所述控制模块还包括：第二控制单元；
    所述第二控制单元的输入端连接所述模式信号，所述第二控制单元的输出端与所述第二开关的控制端连接；
    所述第二控制单元用于当所述模式信号切换至所述第一电平状态时，经过第二延时后控制所述第二开关导通，以及当所述模式信号切换至所述第二电平状态时，控制所述第二开关关断。
  5. 根据权利要求4所述的电源控制电路，其中，所述第二控制单元包括：第一延时单元和与门；
    所述与门的第一输入端与所述第一延时单元的输出端连接，所述与门的第二输入端连接所述模式信号，所述与门的输出端连接至所述第二开关的控制端；
    所述第一延时单元的输入端与所述与门的第二输入端连接，所述第一延时单元用于将接收的信号经过所述第二延时后传输至所述与门的第一输入端。
  6. 根据权利要求3所述的电源控制电路，其中，所述第一控制单元包括：第一逻辑单元和第一电平转换单元；
    所述第一逻辑单元的输入端连接所述模式信号，所述第一逻辑单元的输出端连接至所述第一电平转换单元的输入端；所述第一逻辑单元用于当接收的信号切换至所述第一电平状态时，输出电平状态为所述第一电平状态的信号，以及当接收的信号切换至所述第二电平状态时，经过所述第一延时后输出电平状态为所述第二电平状态的信号；
    所述第一电平转换单元的输出端与所述第一开关的控制端连接；所述第一电平转换单元用于将接收到的高电平信号的电压转换为所述第二电压。
  7. 根据权利要求6所述的电源控制电路，其中，所述第一逻辑单元包括：第二延时单元和第一或门；
    所述第一或门的第一输入端连接所述模式信号，所述第一或门的第二输入端与所述第二延时单元的输出端连接，所述第一或门的输出端与所述第一电平转换单元的输入端连接；
    所述第二延时单元的输入端与所述第一或门的第一输入端连接；所述第二延时单元的延时时长为所述第一延时。
  8. 根据权利要求7所述的电源控制电路，其中，所述控制模块还包括：第三开关和第三控制单元；
    所述第三开关的第一端连接所述第一电源信号，所述第三开关的第二端与所述传输模块的控制端连接；
    所述第三控制单元的输入端与所述第一控制单元连接，所述第三控制单元的输出端与所述第三开关的控制端连接；所述第三控制单元用于当所述模式信号切换至所述第一电平状态时，控制所述第三开关关断，以及当所述模式信号切换至所述第二电平状态时，控制所述第三开关导通并经过所述第一延时后控制所述第三开关关断。
  9. 根据权利要求8所述的电源控制电路，其中，所述第三控制单元包括：非门和第二或门；
    所述非门的输入端与所述第二延时单元的输出端连接，所述非门的输出端与所述第二或门的第一输入端连接；
    所述第二或门的第二输入端与所述第二延时单元的输入端连接，所述第二或门的输出端与所述第三开关的控制端连接。
  10. 根据权利要求9所述的电源控制电路，其中，所述第三控制单元还包括：第二电平转换单元；
    所述第二电平转换单元的输入端与所述第二或门的输出端连接，所述第二电平转换单元的输出端与所述第三开关的控制端连接，所述第二电平转换单元的延迟与所述第一电平转换单元的延迟一致。
  11. 根据权利要求3-10任一项所述的电源控制电路，其中，所述第一开关包括第二PMOS晶体管，所述第二开关包括第一NMOS晶体管。
  12. 根据权利要求8-10任一项所述的电源控制电路，其中，所述第三开关包括第三PMOS晶体管。
  13. 根据权利要求1-10任一项所述的电源控制电路，其中，所述第二电压与所述第一电源信号的电压之间的电压差位于0.2～0.3伏的电压范围。
  14. 根据权利要求1-10任一项所述的电源控制电路，其中，所述模式信号处于第一电平状态表征工作状态，所述模式信号处于第二电平状态表征空闲状态。
  15. 一种存储器，包括：电路模块以及如权利要求1-14任一项所述的电源控制电路；
    所述电源控制电路，耦接于所述电路模块，用于在工作状态下向所述电路模块提供第一电源信号，以及在空闲状态下停止向所述电路模块提供所述第一电源信号。
PCT/CN2022/133021 2022-10-12 2022-11-18 电源控制电路及存储器 WO2024077713A1 (zh)

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