WO2024074969A1 - 記憶装置 - Google Patents

記憶装置 Download PDF

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Publication number
WO2024074969A1
WO2024074969A1 PCT/IB2023/059840 IB2023059840W WO2024074969A1 WO 2024074969 A1 WO2024074969 A1 WO 2024074969A1 IB 2023059840 W IB2023059840 W IB 2023059840W WO 2024074969 A1 WO2024074969 A1 WO 2024074969A1
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Prior art keywords
conductor
transistor
oxide
insulator
opening
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PCT/IB2023/059840
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English (en)
French (fr)
Japanese (ja)
Inventor
齋藤利彦
松嵜隆徳
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2024555466A priority Critical patent/JPWO2024074969A1/ja
Priority to US19/112,491 priority patent/US20260101500A1/en
Publication of WO2024074969A1 publication Critical patent/WO2024074969A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]

Definitions

  • One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one aspect of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer and a module.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices.
  • Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
  • one aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on printed wiring boards and used as one of the components of various electronic devices.
  • IC chips Semiconductor circuits
  • technology that uses semiconductor thin films to construct transistors has attracted attention.
  • These transistors have been put to practical use as electronic devices such as image display devices (also simply referred to as display devices), and it is expected that they will also be applied to the semiconductor circuits mentioned above.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials. Transistors using oxide semiconductors are known to have extremely low leakage current when in a non-conducting state.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors that use oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain memory contents for a long period of time by utilizing the property of low leakage current of transistors that use oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulator.
  • a DRAM cell that uses silicon semiconductors has one transistor and one capacitance element, and in order to increase the degree of integration in the two-dimensional direction (plane direction), a trench capacitor is used as the capacitance element.
  • Trench capacitors are cylindrical and can be formed with a wide electrode area, which increases the capacitance per unit area.
  • one object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Another object is to provide a memory device having a thin memory cell array. Another object is to provide a memory device having good electrical characteristics. Another object is to provide a memory device with good reliability. Another object is to provide a memory device with low power consumption. Another object is to provide a new memory device. Another object is to provide a new semiconductor device or the like.
  • the second opening has an area that overlaps with the first opening.
  • the diameter of the second opening is the same as the width of the other of the source electrode or drain electrode of the transistor.
  • the channel length of the transistor is smaller than the channel width of the transistor.
  • the dielectric is preferably a laminate of a first zirconium oxide, an aluminum oxide, and a second zirconium oxide.
  • the channel formation region of the transistor preferably has an oxide semiconductor, and the oxide semiconductor preferably has one or more selected from the group consisting of In, Ga, and Zn.
  • One embodiment of the present invention can provide a memory device that can be miniaturized or highly integrated. Or, a memory device having a thin memory cell array can be provided. Or, a memory device having good electrical characteristics can be provided. Or, a memory device with good reliability can be provided. Or, a memory device with low power consumption can be provided. Or, a new memory device can be provided. Or, a new semiconductor device or the like can be provided.
  • FIG. 1A is a plan view illustrating a memory device
  • Fig. 1B and Fig. 1C are cross-sectional views illustrating the memory device
  • 2A and 2B are plan views illustrating a storage device.
  • FIG. 3 is a circuit diagram for explaining the configuration of the storage device.
  • 4A to 4D are diagrams illustrating a storage device.
  • 5A and 5C are diagrams for explaining a model of a capacitance element
  • FIG 5B is a diagram for explaining a model of a transistor.
  • FIG. 6 is a diagram illustrating the relationship between the density of memory cells and the thickness of a dielectric film.
  • FIG. 7 is a diagram for explaining the relationship between memory cell density and bit line load.
  • FIG. 1A is a plan view illustrating a memory device
  • Fig. 1B and Fig. 1C are cross-sectional views illustrating the memory device.
  • 2A and 2B are plan views illustrating a storage device.
  • FIG. 3 is a circuit diagram for
  • FIG 8 is a diagram illustrating the relationship between the density of memory cells and the thickness of a dielectric film.
  • 9A and 9B are diagrams illustrating a transistor.
  • 10A and 10B are cross-sectional views showing an example of a memory device.
  • 11A and 11B are cross-sectional views showing an example of a memory device.
  • 12A is a plan view illustrating an example of a storage device, and
  • FIG 12B is a cross-sectional view illustrating an example of the storage device.
  • 13A is a plan view illustrating an example of a storage device, and
  • FIG. 13B is a cross-sectional view illustrating an example of the storage device.
  • FIG. 14A is a plan view illustrating an example of a storage device
  • FIG 14B is a cross-sectional view illustrating an example of the storage device.
  • 15A to 15C are plan layouts for explaining an example of a storage device.
  • 16A to 16C are plan layouts illustrating an example of a storage device.
  • FIG. 17 is a block diagram illustrating an example of the configuration of a storage device.
  • Fig. 18A is a schematic diagram illustrating a configuration example of a memory device, and Fig. 18B is a circuit diagram illustrating the configuration example of a memory device.
  • 19A and 19B are schematic diagrams illustrating an example of the configuration of a storage device.
  • FIG. 20 is a circuit diagram illustrating an example of the configuration of a storage device.
  • 21A and 21B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
  • 22A and 22B are diagrams illustrating an example of an electronic component.
  • 23A to 23E are schematic diagrams of a memory device according to one embodiment of the present invention.
  • 24A to 24H are diagrams illustrating electronic devices according to one embodiment of the present invention.
  • FIG. 25 is a diagram showing an example of space equipment.
  • an oxynitride is a material whose composition contains more oxygen than nitrogen.
  • examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.
  • a nitride oxide is a material whose composition contains more nitrogen than oxygen. Examples of nitride oxides include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.
  • the term “insulator” can be replaced with “insulating film” or “insulating layer.”
  • the term “conductor” can be replaced with “conductive film” or “conductive layer.”
  • the term “semiconductor” can be replaced with “semiconductor film” or “semiconductor layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • the memory device according to one embodiment of the present invention includes one transistor and one capacitor.
  • vertical transistors are used that occupy a small area and have a channel formation region on the side of an insulating layer in an opening provided in the insulating layer.
  • Vertical transistors have a short channel length and a long channel width, which allows for a high on-current.
  • trench capacitors are used for the capacitive elements.
  • the capacitance element can be formed directly under the vertical transistor, and one of the source or drain electrodes of the vertical transistor is shared with one of the electrodes of the capacitance element. Therefore, the overlapping area of the vertical transistor and the capacitance element is large, making it possible to form a highly integrated memory device.
  • the overlapping area between the transistor and the capacitance element cannot be easily increased due to the structure, but in one embodiment of the present invention, the occupied areas of the vertical transistor and the capacitance element can be made approximately equal. Therefore, the area ratio of the transistor and the capacitance element to the cell area can be increased.
  • a capacitance element trench capacitor
  • the larger the diameter is for the same capacitance the lower the height can be, and a thinner memory cell array can be formed.
  • one embodiment of the present invention can be said to be a configuration that makes it easy to increase the degree of integration even when the memory device has a three-dimensional structure.
  • low profile means reducing the height of the structure.
  • FIGS. 1A to 1C are plan and cross-sectional views of a memory device having a transistor 200 and a capacitor 100.
  • FIG. 1A is a plan view of the memory device.
  • FIGS. 1B and 1C are cross-sectional views of the memory device.
  • FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. Note that some elements are omitted from the plan view of FIG. 1A for clarity.
  • arrows indicating the X-direction, Y-direction, and Z-direction may be attached.
  • the "X-direction” is the direction along the X-axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated.
  • the X-direction, Y-direction, and Z-direction are directions that intersect with each other. More specifically, the X-direction, Y-direction, and Z-direction are directions that are perpendicular to each other.
  • one of the X-direction, Y-direction, and Z-direction may be called the "first direction” or “first direction”.
  • the other may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • the memory device shown in Figures 1A to 1C has an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 on the conductor 110, an insulator 180 on the conductor 110, an insulator 280, and an insulator 283 on the memory cell 150.
  • the insulator 140, the insulator 180, the insulator 280, and the insulator 283 function as interlayer films.
  • the conductor 110 functions as wiring.
  • the memory cell 150 has a capacitance element 100 on a conductor 110 and a transistor 200 on the capacitance element 100.
  • the capacitance element 100 has a conductor 115 provided on and in contact with the conductor 110, an insulator 130 provided in contact with the conductor 115, and a conductor 120 provided in contact with the insulator 130.
  • the conductor 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductor 115 functions as the other of the pair of electrodes (sometimes called a lower electrode)
  • the insulator 130 functions as a dielectric.
  • the capacitance element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • the insulator 180 has an opening 190 that reaches the conductor 110. At least a portion of the conductor 115 is disposed in the opening 190. The conductor 115 has a region in contact with the upper surface of the conductor 110 in the opening 190 and a region disposed along the side surface of the insulator 180 in the opening 190. The insulator 130 is disposed so that at least a portion of it covers the opening 190. The conductor 120 is disposed so that at least a portion of it is located within the opening 190. It is preferable that the conductor 120 is disposed so that it fills the opening 190 as shown in FIG. 1B and 1C.
  • Figure 2A is a plan view selectively showing conductor 110, conductor 115, conductor 120, and opening 190. Note that opening 190 provided in insulator 180 is indicated by a dashed line. As shown in Figure 2A, conductor 115 is arranged to cover opening 190 in the area where it overlaps with conductor 110.
  • the capacitance element 100 is configured such that an upper electrode and a lower electrode face each other with a dielectric between them on the side of the opening 190, which allows the capacitance per unit area to be increased. Therefore, the deeper the opening 190, the greater the capacitance of the capacitance element 100. Increasing the capacitance per unit area of the capacitance element 100 in this way can stabilize the read operation of the memory device. It also allows for miniaturization or high integration of memory devices to be promoted.
  • the opening 190 has a cylindrical shape with a circular upper surface. This configuration allows for miniaturization or high integration of the memory device. It is preferable that the side of the opening 190 is perpendicular to the upper surface of the conductor 110.
  • a conductor 115 and an insulator 130 are laminated along the side of the opening 190 and the top surface of the conductor 110.
  • a conductor 120 is provided on the insulator 130 so as to fill the opening 190.
  • a capacitance element 100 having such a configuration can also be called a trench capacitance or a trench capacitor.
  • the insulator 280 is disposed on the capacitance element 100. That is, the insulator 280 is disposed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is disposed below the insulator 280.
  • the transistor 200 has a conductor 120, a conductor 240 on the insulator 280, an oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250.
  • the oxide semiconductor 230 functions as a semiconductor layer
  • the conductor 260 functions as a gate electrode
  • the insulator 250 functions as a gate insulator
  • the conductor 120 functions as one of the source electrode and the drain electrode
  • the conductor 240 functions as the other of the source electrode and the drain electrode.
  • the insulator 280 and the conductor 240 have an opening 290 that reaches the conductor 120. At least a portion of the oxide semiconductor 230 is disposed in the opening 290.
  • the oxide semiconductor 230 has a region that contacts the upper surface of the conductor 120 in the opening 290, a region that contacts the side surface of the conductor 240 in the opening 290, and a region that contacts at least a portion of the upper surface of the conductor 240 outside the opening 290.
  • the insulator 250 is disposed so that at least a portion of it is located in the opening 290.
  • the conductor 260 is disposed so that at least a portion of it is located in the opening 290. It is preferable that the conductor 260 is disposed so that it fills the opening 290, as shown in FIG. 1B and 1C.
  • Figure 2B is a plan view showing an excerpt of the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290. Note that the opening 290 provided in the insulator 280 is shown by a dashed line. As shown in Figure 2B, the conductor 240 has an opening 290 in the region where it overlaps with the conductor 120.
  • the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the top surface of the conductor 240. In this way, the oxide semiconductor 230 contacts not only the side surface but also the top surface of the conductor 240, so that the area of contact between the oxide semiconductor 230 and the conductor 240 can be increased.
  • the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, the opening 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which part of the structure of the capacitor 100 is provided.
  • the conductor 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100, so that the transistor 200 and the capacitor 100 share part of their structures.
  • the transistor 200 and the capacitor element 100 can be provided without significantly increasing the area occupied in a plan view. This reduces the area occupied by the memory cells 150, so that the memory cells 150 can be arranged at a high density and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.
  • one of the source electrode or drain electrode of the transistor 200 and one of the electrodes of the capacitor 100 are shared, that is, the transistor 200 and the capacitor 100 are directly connected without any wiring. Therefore, the electrical resistance between them can be minimized, and the current loss during charging or discharging can be reduced.
  • FIG. 3 A circuit diagram of the memory device shown in this embodiment is shown in FIG. 3.
  • the configuration shown in FIG. 1A to FIG. 1C functions as a memory cell of the memory device.
  • the memory cell has a transistor Tr and a capacitor C.
  • the transistor Tr corresponds to the transistor 200
  • the capacitor C corresponds to the capacitor 100.
  • One of the source and drain of the transistor Tr is connected to one of a pair of electrodes of the capacitance element C.
  • the other of the source and drain of the transistor Tr is connected to the wiring BL.
  • the gate of the transistor Tr is connected to the wiring WL.
  • the other of the pair of electrodes of the capacitance element C is connected to the wiring PL.
  • the wiring BL corresponds to the conductor 240
  • the wiring WL corresponds to the conductor 260
  • the wiring PL corresponds to the conductor 110.
  • the conductor 260 is provided extending in the Y direction
  • the conductor 240 is provided extending in the X direction.
  • the wiring BL and the wiring WL are provided so as to intersect with each other.
  • the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited to this.
  • the wiring PL may be provided parallel to the wiring WL (conductor 260) or parallel to the wiring BL (conductor 240).
  • the transistor 200 and the capacitor 100 can be provided so that the overlapping area is large. Therefore, the cell size can be easily reduced, and the area ratio of the capacitor to the cell area can be increased.
  • the diameter of the capacitance element 100 can be increased, and therefore the area of the electrode provided on the side of the opening 190 can be increased. Therefore, a thin memory cell array having a low-profile capacitance element 100 can be formed.
  • the transistor 200 and the capacitor 100 are arranged so that the overlapping area is large, the area of the top surface of the conductor 120, which is the upper electrode of the capacitor 100 and one of the source or drain electrodes of the transistor 200, can be made small.
  • the parasitic capacitance formed between the conductor 120 and the conductor 240 can be made extremely small.
  • the conductor 240 functions as a bit line (corresponding to the wiring BL in FIG. 3), so the bit line load is reduced.
  • the capacitance of the capacitance element 100 can be reduced, making it easier to further reduce the height of the capacitance element 100.
  • FIGS. 4A to 4D show an example of a memory cell composed of a planar type transistor and a capacitance element.
  • Figure 4A is a top view showing an outline of the arrangement of a transistor 200p and a capacitance element 100 provided below the transistor 200p in a cell when a planar transistor is used.
  • Figure 4B is a cross-sectional view corresponding to the dashed line B1-B2 shown in Figure 4A.
  • an element CE such as a wiring and a plug that connects the source electrode or drain electrode of the transistor 200p to one electrode (upper electrode) of the capacitance element 100 is provided.
  • the transistor and capacitance element 100 need to be placed taking into account the element CE, which hinders cell miniaturization.
  • a process is required to form the element CE.
  • Figure 4C is a top view showing an outline of the arrangement of transistor 200p and capacitive element 100 provided above transistor 200p in a memory cell when a planar transistor is used.
  • Figure 4D is a cross-sectional view corresponding to dashed line B1-B2 shown in Figure 4C.
  • the capacitance required for the capacitance element 100 can be determined based on the load connected to the bit line. A number of memory cells are connected to the bit line, and parasitic capacitance is added. To increase the degree of integration, it is desirable for the capacitance element 100 to have a small capacitance, but the potential of the bit line must be changed so that the sense amplifier is activated when reading data. Therefore, the capacitance element 100 is required to have a capacitance that is a certain ratio or more to the bit line load.
  • Fig. 5A is a diagram for explaining a model for calculating the capacitance of the capacitance element 100, which is a trench capacitor.
  • the configuration of the capacitance element 100 shown in Fig. 5 is basically the same as the configuration shown in Fig. 1B, Fig. 1C, etc., but is premised on a top surface layout of 4F 2 (F is the minimum processing dimension) as shown in Fig. 5B and Fig. 5C.
  • Fig. 5B is a top view showing some elements of the transistor 200
  • Fig. 5C is a top view showing some elements of the capacitance element 100.
  • the width of the bit line (conductor 240), the width of the word line (conductor 260), and the diameter of the opening 290 are each F, and the cell size is 4F2 (2F ⁇ 2F).
  • the diameter of the opening 190 is F, and the top surface shape of the conductor 115 and the conductor 120 is F ⁇ F.
  • the density can be calculated from the reciprocal of 4F2 .
  • the radius of conductor 120 one electrode of capacitance element 100 provided within opening 190 is a
  • the film thickness of insulator 130 dielectric
  • the film thickness of conductor 115 is c
  • the area of the lower surface (bottom surface) of conductor 120 is Sb
  • the area of conductor 120 that does not overlap opening 190 is St (see FIG.
  • the depth (height) of the opening 190 is defined as L
  • the length of the conductor 120 at the opening 190 may also be defined as L.
  • the film thickness c of the conductor 115 and the film thickness b of the insulator 130 provided at the opening 190 are extremely small values compared to the depth of the opening 190 and can be ignored.
  • the film thickness of the insulator 180 in which the opening 190 is provided may also be defined as L.
  • the depth (height) L of the opening 190 may also be referred to as the L length in the following description.
  • F/4L 0.0125.
  • F/4L 0.0055.
  • F(1- ⁇ /4)/ ⁇ L 0.0034.
  • F(1- ⁇ /4)/ ⁇ L 0.0015.
  • the diameter of the bottom of the opening 190 tends to be smaller than the diameter of the top due to process influences.
  • the area Sb of the bottom surface of the conductor 120 tends to be small, and the actual capacitance C1 is smaller than the value calculated according to the model.
  • capacitance C1 is an extremely small value compared to capacitance C2 and is difficult to calculate accurately, it is preferable to ignore capacitance C1.
  • capacitance C1 it is preferable to consider capacitance C1 to be 0.
  • Cs C2
  • the density is preferably 100 pieces/ ⁇ m2 or more, more preferably 200 pieces/ ⁇ m2 or more, and even more preferably 300 pieces/ ⁇ m2 or more.
  • the diameter of the opening 190 is larger than 20 nm. That is, when the diameter of the opening 190 is 20 nm, the density is 625 pieces/ ⁇ m2 , so the density is preferably about 600 pieces/ ⁇ m2 or less, and more preferably 500 pieces/ ⁇ m2 or less.
  • the L length is preferably 1000 nm or less, more preferably 600 nm or less, and even more preferably 400 nm or less.
  • the L length is preferably 1000 nm or less, more preferably 600 nm or less, and even more preferably 400 nm or less.
  • the L length is preferably 1000 nm or less, more preferably 600 nm or less, and even more preferably 400 nm or less.
  • the L length there is no particular lower limit for the L length, and it is sufficient if the length is such that the required capacitance can be obtained.
  • the configuration of the memory cell according to one embodiment of the present invention in which the capacitor 100 is provided directly under the transistor 200, greatly contributes to forming the capacitor 100 with a low height.
  • FIG. 6 is a graph illustrating the film thickness of the insulator 130 (dielectric) calculated from formula 3 when the L length is set to 1000 nm to 400 nm.
  • the relative dielectric constant ⁇ r of the insulator 130 is set to 25.
  • the value of Cs is calculated from formula 1 with the number of cells N set to 16, the load Csa of the sense amplifier set to 1E-15F, and the ratio P of the bit line load Cbl per cell to the capacitance Cs of the capacitive element set to 2.
  • bit line load Cbl was calculated using the software CLEVER manufactured by Silvaco.
  • Figure 7 is a graph showing the bit line load per cell versus the diameter of the opening 190 calculated using CLEVER.
  • the memory cell model used to calculate the bit line load used the configurations described in Figures 1A to 1C and Figures 5A to 5C, and the physical properties of each element were the general physical properties of the materials that can be used for each element described later.
  • Any material can be used for the insulator 130, but by using a material with a relatively high dielectric constant, the film thickness can be increased, thereby reducing leakage current and forming a capacitance element with good characteristics.
  • Figures 6 and 8 show the range of possible film thicknesses of the insulator 130 when several parameters are fixed, but the thickness can also be calculated using Equation 3 when these parameters take different values.
  • the film thickness of the insulator 130 calculated from formula 3 is the film thickness for providing the capacitance element 100 with the minimum required capacitance.
  • the film thickness B of the insulator 130 in the actual capacitance element 100 is preferably greater than 0.85b and less than b (0.85b ⁇ B ⁇ b), more preferably greater than 0.90b and less than b (0.90b ⁇ B ⁇ b), and even more preferably greater than 0.95b and less than b (0.95b ⁇ B ⁇ b).
  • the value required for the capacitance Cs can be reduced. From formula 1, the value required for the capacitance Cs can be reduced by reducing one or more of the values of the bit line load Cbl per cell, the number of cells N, and the sense amplifier load Csa. As described above, the bit line load Cbl can be reduced by the configuration of the memory cell of one embodiment of the present invention (the transistor 200 and the capacitor 100 are arranged so that the overlapping area is large).
  • the memory cell configuration of one aspect of the present invention can be said to be suitable for making the capacitive element low-profile.
  • one aspect of the present invention makes it possible to form a high-density, thin memory cell array.
  • Capacitive element 100 Next, the structure of the capacitor 100 according to one embodiment of the present invention will be described in detail.
  • the capacitor element 100 has a conductor 115, an insulator 130, and a conductor 120.
  • a conductor 110 is provided below the conductor 115.
  • the conductor 115 has a region in contact with the conductor 110 (see Figures 1A to 1C).
  • the conductor 110 is provided on the insulator 140.
  • the conductor 110 functions as the wiring PL (see FIG. 3) and can be provided in a planar shape, for example.
  • the conductors described in the [Conductor] section below can be used as the conductor 110 in a single layer or multilayer.
  • a conductive material with high conductivity such as tungsten, can be used as the conductor 110. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved, allowing it to function sufficiently as the wiring PL.
  • the conductor 115 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, and is used in a single layer or a laminated layer.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen may be used in a single layer or a laminated layer.
  • titanium nitride or indium tin oxide with added silicon may be used.
  • tungsten Alternatively, for example, a structure in which titanium nitride is laminated on tungsten may be used.
  • a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used.
  • the insulator 130 is provided on the conductor 115.
  • the insulator 130 is provided so as to contact the top and side surfaces of the conductor 115.
  • the insulator 130 is structured to cover the side end portion of the conductor 110. This can prevent the conductor 115 and the conductor 120 from shorting out.
  • the side end of the insulator 130 may be aligned with the side end of the conductor 115.
  • the insulator 130 and the conductor 115 can be formed using the same mask, simplifying the manufacturing process of the memory device.
  • the insulator 130 it is preferable to use a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below.
  • high-k material a material with a high relative dielectric constant
  • the insulator 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitance element 100 can be sufficiently ensured.
  • the insulator 130 is preferably made of a laminate of insulating layers made of a high-k material, and preferably has a laminate structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high-k material.
  • the insulator 130 can be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide.
  • an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.
  • an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • the conductor 120 is provided in contact with a portion of the upper surface of the insulator 130. As shown in FIG. 2A, the side end of the conductor 120 is preferably located inside the side end of the conductor 115 in both the X and Y directions. In a structure in which the insulator 130 covers the side end of the conductor 115, the side end of the conductor 120 may be located outside the side end of the conductor 115.
  • the conductor 120 may be a single layer or a laminate of the conductors described in the section [Conductor] described later. It is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 120.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 120.
  • titanium nitride or tantalum nitride may be used.
  • a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, the titanium nitride is in contact with the insulator 130, and the tantalum nitride is in contact with the oxide semiconductor 230.
  • the conductor 120 can be prevented from being excessively oxidized by the oxide semiconductor 230.
  • the conductor 120 can be prevented from being excessively oxidized by the insulator 130.
  • the conductor 120 may be a structure in which tungsten is laminated on titanium nitride, for example.
  • the conductor 120 since the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described later. By using a conductive material containing oxygen as the conductor 120, the conductor 120 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is preferable because it can maintain its conductivity.
  • indium tin oxide also referred to as ITO
  • indium tin oxide with added silicon also referred to as ITSO
  • indium zinc oxide also referred to as IZO (registered trademark)
  • ITO indium tin oxide
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • the insulator 180 functions as an interlayer film, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.
  • a single layer or a multilayer of insulators containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. In this case, the insulator 180b contains at least silicon and oxygen.
  • the insulator 180 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 180 may have a laminated structure.
  • the transistor 200 can have a configuration including a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230 provided in contact with the upper surface of the conductor 120 exposed in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and at least a portion of the upper surface of the conductor 240, an insulator 250 provided in contact with the upper surface of the oxide semiconductor 230, and a conductor 260 provided in contact with the upper surface of the insulator 250.
  • the bottom of the opening 290 is the top surface of the conductor 120
  • the sides of the opening 290 are the sides of the insulator 280 and the sides of the conductor 240.
  • the opening 290 has a cylindrical shape with a circular upper surface. This configuration allows for miniaturization or high integration of the memory device. It is preferable that the side of the opening 290 is perpendicular to the upper surface of the conductor 110.
  • the opening 290 is circular in plan view, but the present invention is not limited to this.
  • the opening 290 may be approximately circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in plan view.
  • the maximum width of the opening 290 may be calculated appropriately according to the shape of the top of the opening 290. For example, if the opening is rectangular in plan view, the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.
  • the top surface shape of the opening 290 and the top surface shape of the opening 190 in which the capacitor 100 is formed are the same or similar.
  • the portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are to be placed in the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor 230 is provided to cover the bottom and side surfaces of the opening 290
  • the insulator 250 is provided to cover the oxide semiconductor 230
  • the conductor 260 is provided to fill the recess in the insulator 250 that reflects the shape of the opening 290.
  • FIG. 9A shows an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 1B.
  • FIG. 9B shows a cross-sectional view in the XY plane including the conductor 240.
  • the oxide semiconductor 230 has a region 230i and regions 230na and 230nb arranged to sandwich the region 230i.
  • Region 230na is a region of oxide semiconductor 230 in contact with conductor 120. At least a portion of region 230na functions as one of the source region and drain region of transistor 200.
  • Region 230nb is a region of oxide semiconductor 230 in contact with conductor 240. At least a portion of region 230nb functions as the other of the source region and drain region of transistor 200.
  • conductor 240 contacts the entire outer periphery of oxide semiconductor 230.
  • the other of the source region and drain region of transistor 200 can be formed on the entire outer periphery of a portion of oxide semiconductor 230 that is formed in the same layer as conductor 240.
  • Region 230i is a region between regions 230na and 230nb of the oxide semiconductor 230. At least a part of region 230i functions as a channel formation region of the transistor 200. In other words, the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or in the vicinity of the region.
  • the channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120.
  • the channel length L of the transistor 200 is indicated by a dashed double-headed arrow.
  • the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 contact each other and the end of the region where the oxide semiconductor 230 and the conductor 240 contact each other in a cross-sectional view. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200, and improves the frequency characteristics. Therefore, the read speed and write speed of the memory cell 150 can be improved, and a memory device with high operating speed can be provided.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the area occupied by the transistor 200 to be reduced compared to conventional transistors in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, thereby increasing the memory capacity per unit area.
  • a transistor having a channel formation region along the side of the insulator 280 in the opening 290 is also called a vertical transistor.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically in the XY plane including the channel formation region of the oxide semiconductor 230. Therefore, the side of the conductor 260 arranged at the center faces the side of the oxide semiconductor 230 through the insulator 250. That is, in a plan view, the entire circumference of the oxide semiconductor 230 becomes the channel formation region.
  • the channel width of the transistor 200 is determined by the outer periphery length of the oxide semiconductor 230. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (maximum diameter when the opening 290 is circular in a plan view). In FIGS.
  • the maximum width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200 is indicated by a double-dot chain line of a one-dot chain line.
  • the maximum width D of the opening 290 is set by the exposure limit of photolithography.
  • the maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200.
  • the channel length L of the transistor 200 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. This makes the distance between the conductor 260 and the oxide semiconductor 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.
  • the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions.
  • impurities such as hydrogen, nitrogen, and metal elements
  • VOH defects in which hydrogen enters the oxygen vacancies and generate electrons that serve as carriers
  • VOH is also reduced in the channel formation region.
  • the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, it can be said that the channel formation region of the transistor is i-type (intrinsic) or substantially i-type.
  • the source and drain regions of a transistor that uses an oxide semiconductor for its semiconductor layer have more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, and thus have an increased carrier concentration and low resistance.
  • the source and drain regions of the transistor are n-type regions that have a higher carrier concentration and lower resistance than the channel formation region.
  • the opening 290 is provided so that the side of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this.
  • the side of the opening 290 may be tapered.
  • the storage device shown in Figures 10A and 10B has a configuration in which the side of the opening 290 is tapered. Note that Figure 1A can be referred to for a plan view of the storage device shown in Figures 10A and 10B.
  • the angle (angle ⁇ 1 shown in FIG. 10A ) between the side of the insulator 280 at the opening 290 and the top surface of the conductor 120 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed.
  • the structure has a region in which the angle between the inclined side and the substrate surface (hereinafter, sometimes referred to as the taper angle) is less than 90 degrees.
  • the side of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • the shape of the opening 290 shown in Figures 10A and 10B is a truncated cone.
  • the opening 290 is circular in plan view and trapezoidal in cross section.
  • the area of the upper base surface of the truncated cone e.g., the opening provided in the conductor 240
  • the area of the lower base surface of the truncated cone is larger than the area of the lower base surface of the truncated cone (the upper surface of the conductor 120 exposed at the opening 290).
  • the maximum diameter of the opening 290 may be calculated based on the upper base surface of the truncated cone.
  • the channel length can be set by the film thickness of the insulator 280 and the angle ⁇ 1 between the side of the insulator 280 at the opening 290 and the top surface of the conductor 110.
  • the outer periphery of the oxide semiconductor 230 may be determined, for example, in a region facing the conductor 240 or at a position half the film thickness of the insulator 280. If necessary, the periphery at any position of the opening 290 may be the channel width of the transistor 200. For example, the periphery at the bottom of the opening 290 may be the channel width, or the periphery at the top of the opening 290 may be the channel width.
  • the side surface of the conductor 240 in the opening 290 coincides with the side surface of the insulator 280 in the opening 290, but this is not a limitation of one embodiment of the present invention.
  • the side surface of the conductor 240 in the opening 290 may be discontinuous with the side surface of the insulator 280 in the opening 290.
  • the inclination of the side surface of the conductor 240 in the opening 290 may differ from the inclination of the side surface of the insulator 280 in the opening 290.
  • the angle between the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 280 is preferably smaller than the angle ⁇ 1.
  • the band gap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more.
  • the frequency of the refresh operation can be about once per 10 sec, which is 10 times or more or 100 times or more. Note that in the memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to once per 1 sec to 100 sec, preferably once per 5 sec to 50 sec.
  • oxide semiconductor 230 can be a single layer or a stack of metal oxides described in the [Metal Oxide] section below.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic ratio. It is also preferable to use gallium as the element M.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • energy dispersive X-ray spectrometry EDX
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the oxide semiconductor 230 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, single crystal oxide semiconductor, and the like. It is preferable to use CAAC-OS or nc-OS as the oxide semiconductor 230, and it is particularly preferable to use CAAC-OS.
  • the CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed.
  • the oxide semiconductor 230 preferably has layered crystals that are approximately parallel to the side surface of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 230 are formed approximately parallel to the channel length direction of the transistor 200, thereby increasing the on-state current of the transistor.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies).
  • a temperature e.g. 400° C. or higher and 600° C. or lower
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the oxide semiconductor 230 by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 230 may have a laminated structure of multiple oxide layers with different chemical compositions.
  • the oxide semiconductor 230 may have a structure in which multiple types selected from the above metal oxides are appropriately laminated.
  • the oxide semiconductor 230 may have a layered structure of an oxide semiconductor 230a and an oxide semiconductor 230b on the oxide semiconductor 230a.
  • the conductivity of the material used for oxide semiconductor 230a is preferably different from the conductivity of the material used for oxide semiconductor 230b.
  • the oxide semiconductor 230a can be made of a material having a higher conductivity than the oxide semiconductor 230b.
  • a material having a high conductivity for the oxide semiconductor 230a in contact with the conductor 120 and the conductor 240 that function as a source electrode or a drain electrode the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with a large on-current can be obtained.
  • the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as a normally-off transistor.
  • the oxide semiconductor 230 As described above, by forming the oxide semiconductor 230 into a stacked structure and using a material having a higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, a memory device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide semiconductor 230a is preferably higher than that of the oxide semiconductor 230b. Increasing the carrier concentration of the oxide semiconductor 230a increases the conductivity, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, resulting in a transistor with a large on-current. Reducing the carrier concentration of the oxide semiconductor 230b decreases the conductivity, resulting in a normally-off transistor.
  • the oxide semiconductor 230a is made of a material having a higher conductivity than the oxide semiconductor 230b; however, one embodiment of the present invention is not limited to this.
  • the oxide semiconductor 230a may be made of a material having a lower conductivity than the oxide semiconductor 230b.
  • a configuration can be adopted in which the carrier concentration of the oxide semiconductor 230a is lower than the carrier concentration of the oxide semiconductor 230b.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used in the oxide semiconductor 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b. This can reduce the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240, and can provide a transistor with a large on-state current.
  • the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • band gap of the first metal oxide is smaller than the band gap of the second metal oxide, but one embodiment of the present invention is not limited to this.
  • a configuration in which the band gap of the first metal oxide is larger than the band gap of the second metal oxide can be used.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b.
  • the composition of the first metal oxide is preferably different from that of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxides
  • the first metal oxide may not contain the element M.
  • the first metal oxide used in the oxide semiconductor 230a may be an In-Zn oxide
  • the second metal oxide used in the oxide semiconductor 230b may be an In-M-Zn oxide.
  • the first metal oxide may be an In-Zn oxide
  • the second metal oxide may be an In-Ga-Zn oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the contents of elements other than element M may be different.
  • the thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer (here, oxide semiconductor 230a and oxide semiconductor 230b) constituting oxide semiconductor 230 may be determined so that the thickness of oxide semiconductor 230 falls within the above-mentioned range.
  • the thickness of oxide semiconductor 230a can be determined so that the contact resistance between oxide semiconductor 230a and conductor 120 and the contact resistance between oxide semiconductor 230a and conductor 240 fall within the required range.
  • the thickness of oxide semiconductor 230b can be determined so that the threshold voltage of the transistor falls within the required range. Note that the thickness of oxide semiconductor 230a may be the same as or different from the thickness of oxide semiconductor 230b.
  • 11A and 11B show a configuration in which the oxide semiconductor 230 has a two-layer stacked structure of the oxide semiconductor 230a and the oxide semiconductor 230b, but the present invention is not limited to this.
  • the oxide semiconductor 230 may have a stacked structure of three or more layers.
  • the insulators described in the section [Insulators] below can be used in a single layer or a multilayer.
  • silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferred because they are stable against heat.
  • the insulator 250 may be a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below.
  • high-k material such as hafnium oxide or aluminum oxide may be used.
  • the thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that the insulator 250 has a region with the above-mentioned thickness in at least a portion.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • a portion of the insulator 250 is located outside the opening 290, i.e., above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 covers the side end of the oxide semiconductor 230. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out. It is also preferable that the insulator 250 covers the side end of the conductor 240. This can prevent the conductor 260 and the conductor 240 from shorting out.
  • the insulator 250 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure.
  • the insulator 250 may have a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.
  • the insulator 250b is preferably made of a material with a low dielectric constant, as described in the [Insulator] section below. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250b contains at least oxygen and silicon. This configuration can reduce the parasitic capacitance between the conductor 260 and the conductor 240. It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.
  • the insulator 250a is preferably an insulator having a barrier property against oxygen, as described in the [Insulator] section below.
  • the insulator 250a has a region in contact with the oxide semiconductor 230.
  • the insulator 250a has a barrier property against oxygen, it is possible to suppress oxygen from being released from the oxide semiconductor 230 during heat treatment or the like. This can suppress the formation of oxygen vacancies in the oxide semiconductor 230. This can improve the electrical characteristics and reliability of the transistor 200.
  • aluminum oxide is preferably used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.
  • the insulator 250c is preferably an insulator having a barrier property against hydrogen as described in the [Insulator] section below. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has high hydrogen barrier properties and is therefore suitable as the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.
  • the insulator 250c may further have a barrier property against oxygen.
  • the insulator 250c is provided between the insulator 250b and the conductor 260. This prevents the oxygen contained in the insulator 250b from diffusing into the conductor 260, suppressing oxidation of the conductor 260. In addition, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.
  • an insulator may be provided between the insulator 250b and the insulator 250c.
  • the insulator it is preferable to use an insulator having a function of capturing or fixing hydrogen, which will be described later in the section [Insulator].
  • the insulator hydrogen contained in the oxide semiconductor 230 can be captured or fixed more effectively.
  • the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • hafnium oxide may be used as the insulator.
  • the insulator contains at least oxygen and hafnium.
  • the insulator may have an amorphous structure.
  • the thicknesses of the insulators 250a to 250c are preferably thin and within the aforementioned range.
  • the thicknesses of the insulators 250a, 250b, the insulator having the function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • 11A and 11B show a configuration in which the insulator 250 has a three-layer stacked structure of insulators 250a to 250c, but one embodiment of the present invention is not limited to this.
  • the insulator 250 may have a two-layer or four or more-layer stacked structure. In this case, each layer included in the insulator 250 may be appropriately selected from the insulators 250a to 250c and an insulator that has a function of capturing or fixing hydrogen.
  • the conductor 260 may be a single layer or a multilayer of the conductors described in the section [Conductor] below.
  • the conductor 260 may be a highly conductive material such as tungsten.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260.
  • conductive materials include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductor 260.
  • the conductor 260 may have a laminated structure.
  • the conductor 260 may have a laminated structure of a conductor 260a and a conductor 260b on the conductor 260a.
  • titanium nitride may be used as the conductor 260a
  • tungsten may be used as the conductor 260b.
  • 11A and 11B show that the conductor 260 has a two-layer laminate structure of conductor 260a and conductor 260b, but the present invention is not limited to this.
  • the conductor 260 may have a laminate structure of three or more layers.
  • the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a part of the recess may be located in the opening 290.
  • the recess may be filled with an inorganic insulating material or the like.
  • a part of the conductor 260 is located outside the opening 290, that is, on the conductor 240 and the insulator 280.
  • the side end of the conductor 260 is located inside the side end of the oxide semiconductor 230. This makes it possible to prevent the conductor 260 and the oxide semiconductor 230 from being short-circuited.
  • the side end of the conductor 260 may coincide with the side end of the oxide semiconductor 230, or may be located outside the side end of the oxide semiconductor 230.
  • the conductor 120 may be provided as described in the [Capacitive element 100] section.
  • FIGS. 1B and 1C show a configuration in which the upper surface of the conductor 120 is flat
  • the present invention is not limited to this.
  • a configuration in which a recess overlapping the opening 290 is formed on the upper surface of the conductor 120 may be used.
  • the conductor 240 may be a single layer or a multilayer of the conductors described in the section [Conductor] below.
  • the conductor 240 may be a highly conductive material such as tungsten.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen, for the conductor 240.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen, for the conductor 240.
  • titanium nitride or tantalum nitride can be used. With this configuration, excessive oxidation of the conductor 240 by the oxide semiconductor 230 can be suppressed.
  • a structure in which tungsten is laminated on titanium nitride may be used. By laminating tungsten in this manner, the conductivity of the conductor 240 can be improved, allowing it to function adequately as the wiring BL.
  • the conductor 240 when the conductor 240 is configured by stacking a first conductor and a second conductor, for example, the first conductor may be formed using a conductive material with high conductivity, and the second conductor may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the second conductor of the conductor 240 that contacts the insulator 250, it is possible to suppress the diffusion of oxygen in the insulator 250 to the first conductor of the conductor 240.
  • the oxide semiconductor 230 and the conductor 120 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of the region 230na of the oxide semiconductor 230 is reduced.
  • the contact resistance between the oxide semiconductor 230 and the conductor 120 is reduced.
  • the resistance of the region 230nb of the oxide semiconductor 230 is reduced. Therefore, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the insulators 140 and 280 function as interlayer films, it is preferable that they have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. As the insulators 140 and 280, insulators containing materials with a low dielectric constant, as described in the [Insulators] section below, can be used in a single layer or stack. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentrations of impurities such as water and hydrogen in the insulator 140 and the insulator 280 are reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230.
  • the insulator 280 disposed in the vicinity of the channel formation region is preferably an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen).
  • excess oxygen By performing heat treatment on the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and VOH .
  • the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.
  • the insulator 280 may be an insulator having a function of capturing or fixing hydrogen, as described in the [Insulator] section below. With such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 230 can be reduced. Magnesium oxide, aluminum oxide, or the like can be used as the insulator 280.
  • the insulator 280 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 280 may have a laminated structure.
  • the insulator 283 is preferably an insulator having barrier properties against hydrogen, as described in the [Insulator] section below. This can prevent hydrogen from diffusing from outside the transistor to the oxide semiconductor 230 through the insulator 250.
  • a silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulator 283.
  • the insulator 283 an insulator having a function of capturing hydrogen or fixing hydrogen, as described in the section [Insulator] below. With such a structure, it is possible to suppress diffusion of hydrogen from above the insulator 283 to the oxide semiconductor 230, and further to capture or fix hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration in the oxide semiconductor 230.
  • the insulator 283, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used.
  • the insulator 283 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the substrate on which the transistor 200 and the capacitor element 100 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • Examples of the semiconductor substrate include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
  • Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • Examples of the conductive substrate include a substrate having a metal nitride and a substrate having a metal oxide.
  • Examples of the conductive substrate include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities and oxygen.
  • an insulator that has a function of suppressing the permeation of impurities and oxygen for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • Insulators in contact with a semiconductor such as a gate insulator, or insulators provided near a semiconductor layer are preferably insulators having a region containing excess oxygen.
  • insulators having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced.
  • Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.
  • Insulators that have a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to have a barrier property against either or both of oxygen and hydrogen.
  • Insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these metal oxides have an amorphous structure, but crystalline regions may be formed in some parts.
  • a barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • the barrier property against oxygen refers to a property that at least one of an oxygen atom, an oxygen molecule, etc. is difficult to diffuse.
  • the conductor it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a nitride of the alloy or an oxide of the alloy may be used as the alloy containing the above-mentioned metal elements as a component.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide, and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor that functions as a gate electrode may also be used.
  • a conductive material containing the above-mentioned metal element and nitrogen may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.
  • Factors that cause lattice defects include a deviation in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.
  • the metal oxide used in the semiconductor layer of a transistor When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.
  • V O H oxygen vacancies
  • the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.
  • the types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.
  • Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures.
  • A-like structures have a structure between the nc structures and the amorphous structures. The classification of crystal structures will be described later.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a metal oxide with high crystallinity for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using such a metal oxide for the transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.
  • a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor.
  • the crystal has a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked.
  • metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS.
  • the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.
  • the above three-layered crystal structure has the following structure.
  • the first layer has an atomic coordination structure of an oxygen octahedron with the metal of the first layer at the center.
  • the second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the second layer at the center.
  • the third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the third layer at the center.
  • the crystal structure of the above crystals includes, for example, a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first layer to the third layer is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen.
  • the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.
  • the above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide of one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element” described in this specification, etc. may include metalloid elements.
  • indium zinc oxide In-Zn oxide
  • indium tin oxide In-Sn oxide
  • indium titanium oxide In-Ti oxide
  • indium gallium oxide In-Ga oxide
  • indium gallium aluminum oxide In-Ga-Al oxide
  • indium gallium tin oxide In-Ga-Sn oxide
  • gallium zinc oxide Ga-Zn oxide, also referred to as GZO
  • aluminum zinc oxide Al-Zn oxide, also referred to as AZO
  • IAZO indium Indium aluminum zinc oxide
  • indium tin zinc oxide In-Sn-Zn oxide
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also written as IGZTO
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may have one or more metal elements with a large periodic number instead of indium.
  • the metal oxide may have one or more metal elements with a large periodic number in addition to indium.
  • Examples of metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • the metal oxide film formation method of the present invention it is preferable to deposit atoms one layer at a time.
  • the ALD method is used, so that it is easy to form a metal oxide having the above-mentioned layered crystal structure.
  • ALD plasma Enhanced ALD
  • the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • the PEALD method may be preferable because it can form films at lower temperatures by using plasma.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.
  • the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles released from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed.
  • a method of forming a first metal oxide film using a sputtering method and forming a second metal oxide film on the first metal oxide using an ALD method can be mentioned.
  • the second metal oxide may grow as a crystal with the crystal part as a nucleus.
  • the ALD method can control the composition of the resulting film by the amount of raw material gas introduced.
  • the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like.
  • the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of memory devices can be increased in some cases.
  • a transistor with high field-effect mobility can be realized.
  • a highly reliable transistor can be realized.
  • a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.
  • an oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less, and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor film, it is only necessary to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film may have a low density of trap states because of its low density of defect states.
  • the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source and drain regions are n + type regions.
  • the OS transistor can have good electrical characteristics even when the memory device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be preferably used as a transistor having a shorter channel length than that of a Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 230 can be rephrased as a semiconductor layer including a channel formation region of a transistor.
  • a semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides.
  • a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer.
  • a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used for the semiconductor material.
  • layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of elemental semiconductors that can be used in the semiconductor material include silicon and germanium.
  • Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.
  • Layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • a new transistor, a new semiconductor device, and a new memory device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a memory device with good frequency characteristics can be provided.
  • a memory device with high operating speed can be provided.
  • a memory device with good reliability can be provided.
  • a memory device with low power consumption can be provided.
  • a memory device having a transistor with a large on-state current can be provided.
  • a memory device with little variation in transistor characteristics can be provided.
  • a memory device with good electrical characteristics can be provided.
  • the memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the use of the transistor 200 in a storage device allows stored contents to be retained for a long period of time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. Furthermore, since the frequency characteristics of the transistor 200 are high, reading and writing to the storage device can be performed at high speed.
  • FIG. 12A is a plan view of the memory device.
  • Figure 12B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 12A. Note that some elements have been omitted from the plan view of Figure 12A to clarify the drawing.
  • each of the memory cells 150a and 150b shown in FIGS. 12A and 12B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitance element 100a and a transistor 200a
  • the memory cell 150b has a capacitance element 100b and a transistor 200b. Therefore, in the memory device shown in FIGS. 12A and 12B, structures having the same functions as the structures constituting the memory device shown in FIGS. 1A to 1C are denoted by the same reference numerals. Note that in this section as well, the materials constituting the memory device can be the materials described in detail in ⁇ Configuration example of memory device>.
  • the conductor 260 functioning as the wiring WL is provided in each of the memory cells 150a and 150b.
  • the conductor 240 functioning as part of the wiring BL is provided in common to the memory cells 150a and 150b. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.
  • the memory device shown in Figures 12A and 12B has conductors 245 and 246 that are electrically connected to memory cells 150a and 150b and function as plugs (which can also be called connection electrodes).
  • Conductor 245 is disposed in openings formed in insulators 180, 280, and 140, and contacts the lower surface of conductor 240.
  • Conductor 246 is disposed in openings formed in insulators 287, 283, and 250, and contacts the upper surface of conductor 240.
  • conductors 245 and 246 can be made of a conductive material that is applicable to conductor 240.
  • the insulator 287 preferably has a low dielectric constant because it functions as an interlayer film. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant, as described above in the [Insulator] section, can be used in a single layer or a multilayer configuration.
  • the concentration of impurities such as water and hydrogen in the insulator 287 be reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • the conductors 245 and 246 function as plugs or wirings for electrically connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitance elements, inductors, resistance elements, and diodes to the memory cells 150a and 150b.
  • the conductor 245 can be electrically connected to a sense amplifier (not shown) provided below the memory device shown in Figures 12A and 12B, and the conductor 246 can be electrically connected to a similar memory device (not shown) provided above the memory device shown in Figures 12A and 12B.
  • the conductors 245 and 246 function as part of the wiring BL. In this way, by providing a memory device or the like above or below the memory device shown in Figures 12A and 12B, the memory capacity per unit area can be increased.
  • memory cell 150a and memory cell 150b are configured to be line-symmetrical with respect to the perpendicular bisector of dashed dotted line A1-A2. Therefore, transistor 200a and transistor 200b are also arranged in line-symmetrical positions with conductor 245 and conductor 246 in between.
  • conductor 240 functions as the other of the source electrode and drain electrode of transistor 200a and as the other of the source electrode and drain electrode of transistor 200b.
  • transistor 200a and transistor 200b share conductor 245 and conductor 246 that function as plugs. In this way, by configuring the connection between two transistors and a plug as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • the conductor 110 functioning as the wiring PL may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b. However, as shown in FIG. 12B, the conductor 110 is provided at a distance from the conductor 245 to prevent the conductor 110 and the conductor 245 from shorting out.
  • a memory cell array can be formed by arranging the memory cells 150 in a three-dimensional matrix.
  • FIGS. 13A and 13B show an example of a memory device in which 4 ⁇ 2 ⁇ 4 memory cells 150 are arranged in the X, Y, and Z directions.
  • FIG. 13A is a plan view of the memory device.
  • FIG. 13B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 13A. Note that some elements have been omitted from the plan view of FIG. 13A to clarify the drawing.
  • each of the memory cells 150a to 150d shown in FIG. 13A and FIG. 13B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitor 100a and a transistor 200a
  • the memory cell 150b has a capacitor 100b and a transistor 200b
  • the memory cell 150c has a capacitor 100c and a transistor 200c
  • the memory cell 150d has a capacitor 100d and a transistor 200d. Therefore, in the memory device shown in FIG. 13A and FIG. 13B, the same reference numerals are attached to structures having the same functions as the structures constituting the memory device shown in FIG. 1. Note that in this section as well, the materials described in detail in ⁇ Configuration example of memory device> can be used as the constituent materials of the memory device.
  • a memory device consisting of memory cells 150a to 150d is referred to as a memory unit.
  • the memory device shown in FIG. 13A and FIG. 13B has memory units 160[1,1] to 160[2,4].
  • memory units 160[1,1] to 160[2,4] may be collectively referred to as memory unit 160.
  • Memory unit 160[1,2] is provided on memory unit 160[1,1]
  • memory unit 160[1,3] is provided on memory unit 160[1,2]
  • memory unit 160[1,4] is provided on memory unit 160[1,3].
  • Memory unit 160[2,1] is provided adjacent to memory unit 160[1,1] in the Y direction.
  • Memory unit 160[2,2] is provided above memory unit 160[2,1]
  • memory unit 160[2,3] is provided above memory unit 160[2,2]
  • memory unit 160[2,4] is provided above memory unit 160[2,3].
  • memory unit 160 has memory cell 150c arranged outside memory cell 150a, and memory cell 150d arranged outside memory cell 150b, with conductor 245 at the center.
  • this is a memory device in which memory cell 150c is provided adjacent to memory cell 150a, and memory cell 150d is provided adjacent to memory cell 150b, in the memory device shown in FIG. 12A and FIG. 12B.
  • the conductor 260 functioning as the wiring WL is shared between memory cells 150 adjacent in the Y direction. Furthermore, the conductor 240 functioning as part of the wiring BL is shared within the same memory unit. In other words, the conductor 240 is in contact with each of the oxide semiconductors 230 of the memory cells 150a to 150d.
  • a conductor 245 is provided between the conductors 240 of memory units adjacent in the Z direction.
  • the conductor 245 is provided in contact with the upper surface of the conductor 240 of memory unit 160[1,1] and the lower surface of the conductor 240 of memory unit 160[1,2].
  • the wiring BL is formed by the conductors 240 and 245 provided in each memory unit 160.
  • the conductor 245 is electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIGS. 13A and 13B.
  • the memory cell of one embodiment of the present invention has a low-profile capacitor element and the memory unit can be formed thin, so that it can be said that the structure makes it easy to increase the degree of integration three-dimensionally.
  • the memory cells 150a and 150c and the memory cells 150b and 150d are configured to be linearly symmetrical with respect to the perpendicular bisector of the dashed dotted line A1-A2. Therefore, the transistors 200a and 200c and the transistors 200b and 200d are also arranged in linearly symmetrical positions with the conductor 245 in between.
  • the conductor 240 functions as the other of the source electrode and drain electrode of each of the transistors 200a to 200d.
  • the transistors 200a to 200d share the conductor 245 that functions as a plug. In this way, by configuring the connections between the four transistors and the plug as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • the cells can be integrated and arranged without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be configured. Note that, although Figures 13A and 13B show an example of a configuration in which four layers each having two memory units are stacked, the present invention is not limited to this.
  • the memory device may have one layer having at least one memory cell 150, or two or more layers may be stacked.
  • Figures 13A and 13B show a configuration in which the conductor 245 functioning as a plug is arranged between the memory cells 150.
  • the configuration shows the conductor 245 functioning as a plug being arranged inside the memory unit 160.
  • the conductor 245 may be arranged outside the memory unit.
  • FIGS. 14A and 14B show an example of a memory device in which 3 ⁇ 3 ⁇ 4 memory cells 150 are arranged in the X, Y, and Z directions.
  • FIG. 14A is a plan view of the memory device.
  • FIG. 14B is a cross-sectional view of the area indicated by the dashed dotted line A1-A2 in FIG. 14A. Note that some elements have been omitted from the plan view of FIG. 14A to clarify the drawing.
  • the memory device illustrated in FIG. 14A and FIG. 14B has a structure in which m layers including memory cells 150 are stacked (m is an integer of 2 or more).
  • the layer provided in the first layer (bottom) is layer 170[1]
  • the layer provided in the second layer is layer 170[2]
  • the layer provided in the (m-1)th layer is layer 170[m-1]
  • the layer provided in the mth layer (top) is layer 170[m], as illustrated in FIG. 14B.
  • the memory device of one embodiment of the present invention may have a structure in which multiple layers including memory cells 150 are stacked.
  • the conductor 245 may be provided outside the memory unit.
  • the conductor 245 may also be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245.
  • the conductor 245 provided in the layer 170[1] is electrically connected to a wiring provided in the layer 170[2].
  • the wiring provided in the layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[2]. In other words, the wiring can be formed in the same process as the conductor 110.
  • the conductor 245 may be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245, but the present invention is not limited to this.
  • the conductor 245 may be electrically connected to a wiring provided in the layer including the conductor 245.
  • the conductor 245 provided in the layer 170[1] may be electrically connected to a wiring provided in the layer 170[1].
  • the wiring provided in the layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 15A the planar layout of the memory device shown in FIG. 14A is shown in FIG. 15A.
  • the planar layout in FIG. 15A shows an area including 4 ⁇ 4 memory cells 150.
  • conductor 260 functioning as wiring WL
  • conductor 240 functioning as wiring BL
  • opening 290 Note that memory cell 150 is provided in an area where conductor 260, conductor 240, and opening 290 overlap.
  • opening 290 is provided in an area of conductor 240 where conductor 240 and conductor 260 intersect.
  • FIG. 15A shows a configuration in which memory cells 150 are arranged in a matrix. Also, a configuration in which openings 290 are arranged in a matrix is shown. Also, a configuration in which conductor 260 is provided extending in the Y direction, and conductor 240 is provided extending in the X direction is shown. In other words, a configuration in which conductor 260 and conductor 240 are perpendicular to each other is shown. Also, a configuration in which conductor 260 has a uniform width in a direction perpendicular to the direction in which conductor 260 extends (X direction), and conductor 240 has a uniform width in a direction perpendicular to the direction in which conductor 240 extends (Y direction) is shown. However, the present invention is not limited to this.
  • Figure 15B is another example of a planar layout of a memory device.
  • the planar layout of Figure 15B illustrates conductor 260, conductor 240, conductor 245, and opening 290, similar to Figure 15A.
  • the memory device shown in Figure 15B differs from the memory device shown in Figure 15A mainly in the arrangement of memory cells 150 (opening 290), the shape of conductor 240, and the direction in which conductor 260 extends.
  • the memory cells 150 may be arranged in a zigzag pattern in the Y direction.
  • the memory cell adjacent to the first memory cell in the X direction is the second memory cell
  • the memory cell adjacent to the first and second memory cells in the Y direction is the third memory cell.
  • the center of the third memory cell may be located on a straight line that passes through the middle of the first and second memory cells and is parallel to the Y direction.
  • the third memory cell can be said to be located at a position that is halfway in the X direction from the first and second memory cells.
  • the conductor 240 has a first region and a second region.
  • the first region is the opening 290 and the region in the vicinity thereof, and the width in the Y direction of the first region is the first width.
  • the first region can be said to have a shape with rounded corners of a rectangle.
  • the second region is the region between adjacent openings 290 in one conductor 240, and the width in the Y direction of the second region is the second width. In this case, it is preferable that the second width is smaller than the first width.
  • the extension direction of the conductor 260 is inclined with respect to the Y direction.
  • the extension direction of the conductor 260 may not be perpendicular to the extension direction of the conductor 240. In other words, it is preferable that the conductor 260 intersects with the conductor 240.
  • Figure 15C is another example of a planar layout of a memory device.
  • the planar layout of Figure 15C illustrates conductor 260, conductor 240, conductor 245, and opening 290, similar to Figure 15B.
  • the memory device shown in Figure 15C differs from the memory device shown in Figure 15B mainly in the shape of the first region of conductor 240.
  • the first region of the conductor 240 shown in FIG. 15B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X or Y direction.
  • the first region of the conductor 240 shown in FIG. 15C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X or Y direction.
  • Figures 15B and 15C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in a plan view, but the present invention is not limited to this.
  • FIG. 16A is another example of a planar layout of a memory device.
  • the planar layout of FIG. 16A illustrates conductor 260, conductor 240, conductor 245, and opening 290, similar to FIG. 15B.
  • the memory device illustrated in FIG. 16A differs from the memory device illustrated in FIG. 15B or FIG. 15C mainly in the shape of the first region of conductor 240.
  • the first region of the conductor 240 shown in FIG. 16B is circular in plan view.
  • the memory cells 150 openings 290
  • the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device.
  • the first region of the conductor 240 in plan view is not limited to the shape described above.
  • the first region of the conductor 240 in plan view may be an approximately circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners.
  • FIG. 16A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, but the present invention is not limited to this.
  • Figure 16B is another example of a planar layout of a memory device.
  • the planar layout of Figure 16B illustrates conductor 260, conductor 240, conductor 245, and opening 290, similar to Figure 16A.
  • the memory device shown in Figure 16B differs from the memory device shown in Figure 16A mainly in the shape of conductor 260.
  • the conductor 260 shown in FIG. 16B has a first region and a second region, similar to the conductor 240.
  • the first region is the opening 290 and the region in its vicinity, and is circular in plan view.
  • the second region is the region between adjacent openings 290 in one conductor 260.
  • the first region of the conductor 260 overlaps with the first region of the conductor 240.
  • Figure 16C is another example of a planar layout of a memory device.
  • the planar layout of Figure 16C illustrates conductor 260, conductor 240, conductor 245, and opening 290, similar to Figure 16A.
  • the memory device shown in Figure 16C differs from the memory device shown in Figure 16A mainly in the shape and extension direction of conductor 260.
  • the conductor 260 shown in FIG. 16C has a triangular wave shape in plan view and extends in the Y direction. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. This allows the memory device to be miniaturized and highly integrated. Note that the conductor 260 in plan view is not limited to the above, and may be meander-shaped, for example.
  • a memory device having a 3D memory cell array will be described in detail in a later embodiment.
  • FIG. 17 is a block diagram illustrating a configuration example of a memory device 300 according to one embodiment of the present invention.
  • the memory device 300 illustrated in Fig. 17 includes a driver circuit 21 and a memory cell array 20.
  • the memory cell array 20 includes a functional layer 50 including a plurality of memory cells 10 and a plurality of functional circuits 51.
  • FIG. 17 shows an example in which the memory cell array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • a functional circuit 51 is provided for each wiring BL that functions as a bit line.
  • FIG. 17 shows an example in which a plurality of functional circuits 51 are provided corresponding to n wirings BL.
  • the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1] and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n].
  • an arbitrary row may be indicated as row i.
  • An arbitrary column may be indicated as column j.
  • i is an integer between 1 and m
  • j is an integer between 1 and n.
  • the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j].
  • i+ ⁇ ⁇ is a positive or negative integer
  • the memory cell array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction.
  • the first wiring WL (first row) is indicated as wiring WL[1]
  • the mth wiring WL (mth row) is indicated as wiring WL[m].
  • the first wiring PL (first row) is indicated as wiring PL[1]
  • the mth wiring PL (mth row) is indicated as wiring PL[m].
  • the first wiring BL (first column) is indicated as wiring BL[1]
  • the nth wiring BL (nth column) is indicated as wiring BL[n].
  • the memory cells 10 in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row.
  • the memory cells 10 in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • the memory cell array 20 can be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory).
  • DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and refers to a memory in which the access transistor is a transistor having an oxide semiconductor in the channel formation region (hereinafter also referred to as an "OS transistor").
  • OS transistor oxide semiconductor in the channel formation region
  • the access transistor In the off state, the current flowing between the source and drain of an OS transistor, that is, the leakage current, is extremely small.
  • DOSRAM can hold a charge corresponding to the data held in the capacitance element (capacitor) for a long time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM consisting of a transistor having silicon in the channel formation region (hereinafter also referred to as an "Si transistor”). As a result, it is possible to achieve low power consumption.
  • the memory cells 10 can be stacked by stacking OS transistors as described in embodiment 1 and the like.
  • the memory cell array 20 shown in FIG. 17 multiple memory cell arrays 20[1] to 20[m] can be stacked.
  • the memory cell arrays 20[1] to 20[m] of the memory cell array 20 can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, thereby improving the memory density of the memory cells 10.
  • the memory cell array 20 can be manufactured by repeatedly using the same manufacturing process in the vertical direction.
  • the memory device 300 can reduce the manufacturing cost of the memory cell array 20.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling the on/off (conductive or non-conductive) of an access transistor that functions as a switch.
  • the wiring PL functions as a constant potential line connected to a capacitance element.
  • the memory cells 10 in each of the memory cell arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL.
  • the wiring BL can be arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided.
  • the length of the wiring between the memory cell array 20 and the functional circuit 51 can be shortened. Therefore, the signal propagation distance between the two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay.
  • the functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via the wiring GBL (not shown) described later.
  • This configuration makes it possible to amplify a slight potential difference in the wiring BL when reading data.
  • the wiring GBL can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, just like the wiring BL.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the memory cell 10 in each layer of the memory cell array 20 to the functional circuit 51 in the vertical direction.
  • the memory cell array 20 can be stacked on the drive circuit 21. By stacking the drive circuit 21 and the memory cell array 20, the signal propagation distance between the drive circuit 21 and the memory cell array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory cell array 20, thereby reducing power consumption and signal delay. In addition, the memory device 300 can be made smaller.
  • the functional circuit 51 is made of OS transistors, similar to the transistors in the memory cells 10 of the DOSRAM, and can be freely arranged on circuits using Si transistors, similar to the memory cell arrays 20[1] to 20[m], making integration easy. By configuring the functional circuit 51 to amplify signals, the circuits in the subsequent stages, such as the sense amplifier 46, can be made smaller, and the memory device 300 can be made smaller.
  • the drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to the memory cells 10.
  • the peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51.
  • the peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
  • the row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of retaining the read data, etc.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is data (Din) to be written to the memory cell 10.
  • the data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the memory device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.
  • the memory cell array 20 having memory cell arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory cell arrays 20 on a driving circuit 21. By stacking multiple layers of memory cell arrays 20, the memory density of the memory cells 10 can be increased.
  • the memory cell array 20 provided in the first layer is shown as memory cell array 20[1]
  • the memory cell array 20 provided in the second layer is shown as memory cell array 20[2]
  • the memory cell array 20 provided in the fifth layer is shown as memory cell array 20[5].
  • the wiring WL and wiring PL extending in the X direction, and the wiring BL extending in the Z direction are illustrated. Note that, in order to make the drawing easier to see, the wiring WL and wiring PL of each memory cell array 20 are partially omitted.
  • FIG. 18A shows a configuration in which the wiring PL is extended in the X direction, the present invention is not limited to this.
  • the wiring PL may be extended in the Y direction, or the wiring PL may be extended in the X direction and the Y direction, for example, the wiring PL may be provided in a planar shape.
  • Figure 18B is a schematic diagram illustrating a configuration example of a functional circuit 51 connected to the wiring BL illustrated in Figure 18A, and memory cells 10 in memory cell arrays 20[1] to 20[5] connected to the wiring BL.
  • Figure 18B also illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string.” Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.
  • Figure 18B illustrates an example of the circuit configuration of a memory cell 10 connected to wiring BL.
  • the memory cell 10 has a transistor 11 and a capacitor 12.
  • the transistor 11, the capacitor 12, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], for example, as wiring BL and wiring WL.
  • one of the source and drain of transistor 11 is connected to wiring BL.
  • the other of the source and drain of transistor 11 is connected to one electrode of capacitance element 12.
  • the other electrode of capacitance element 12 is connected to wiring PL.
  • the gate of transistor 11 is connected to wiring WL.
  • two memory cells 10 connected to a common wiring BL in the same layer can have the structure shown in FIG. 12 according to the first embodiment.
  • FIG. 18B and other figures a configuration is shown in which two memory cells 10 are connected to a common wiring BL in the same layer, but the present invention is not limited to this.
  • a configuration in which four memory cells 10 are connected to a common wiring BL in the same layer may be used, or a configuration in which eight memory cells 10 are connected to a common wiring BL in the same layer may be used.
  • the structure shown in FIG. 13 relating to embodiment 1 may be used.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitance element 12.
  • FIG. 19A shows a schematic diagram of a memory device 300 in which the functional layer 50 and the memory cell arrays 20[1] to 20[m] are repeated as a unit 70. Note that although FIG. 19A shows one wiring GBL, the wiring GBL may be provided as appropriate according to the number of functional circuits 51 provided in the functional layer 50.
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.
  • the repeating unit 70 including the functional circuit 51 and the memory cell arrays 20[1] to 20[m] may be further stacked.
  • the memory device 300A of one embodiment of the present invention can include repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 19B.
  • the wiring GBL is connected to the functional layer 50 included in the repeating unit 70.
  • the wiring GBL may be provided as appropriate depending on the number of functional circuits 51.
  • OS transistors are stacked and wiring that functions as a bit line is arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided.
  • the wiring that functions as a bit line extending from the memory cell array 20 in a vertical direction to the substrate surface By arranging the wiring that functions as a bit line extending from the memory cell array 20 in a vertical direction to the substrate surface, the length of the wiring between the memory cell array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced.
  • a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting the data potential held in the memory cell 10 is provided in the layer in which the memory cell array 20 is provided.
  • a slight potential difference in the wiring BL that functions as a bit line when reading data can be amplified to drive the sense amplifier 46 of the driver circuit 21. Since circuits such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, it is possible to operate the memory device even if the capacitance of the capacitive element 12 in the memory cell 10 is reduced.
  • Example of configuration of memory cell array 20 and functional circuit 51 20 a configuration example of the functional circuit 51 described in FIG. 17 to FIG. 19 and a configuration example of the sense amplifier 46 included in the memory cell array 20 and the driver circuit 21 will be described.
  • the driver circuit 21 connected to wirings GBL (GBL_A, GBL_B) connected to functional circuits 51 (51_A, 51_B) connected to memory cells 10 (10_A, 10_B) connected to different wirings BL (BL_A, BL_B) is illustrated.
  • a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are illustrated.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as functional circuits 51_A and 51_B.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 20 are OS transistors, similar to transistor 11 included in memory cell 10.
  • the functional layer 50 including the functional circuit 51 can be stacked in the same manner as memory cell arrays 20[1] to 20[m].
  • Wirings BL_A and BL_B are connected to the gates of transistors 52_a and 52_b.
  • Wirings GBL_A and GBL_B are connected to one of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b.
  • Wirings GBL_A and GBL_B are provided in the vertical direction like wirings BL_A and BL_B, and are connected to transistors in driver circuit 21.
  • Control signals WE, RE, and MUX are provided to the gates of transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, as shown in FIG. 20.
  • the transistors 81_1 through 81_6 and 82_1 through 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in FIG. 20 are composed of Si transistors.
  • the switches 83_A through 83_D constituting the switch circuit 72_A and switch circuit 72_B can also be composed of Si transistors.
  • One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.
  • the precharge circuit 71_A has n-channel transistors 81_1 to 81_3.
  • the precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL1.
  • the precharge circuit 71_B has n-channel transistors 81_4 to 81_6.
  • the precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL2.
  • the sense amplifier 46 has a p-channel transistor 82_1, a p-channel transistor 82_2, an n-channel transistor 82_3, and an n-channel transistor 82_4 connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring having a function of providing VDD or VSS.
  • the transistors 82_1 to 82_4 are transistors that form an inverter loop.
  • the potentials of the precharged wirings BL_A and BL_B change by selecting the memory cell 10_A and the memory cell 10_B, and the potentials of the wirings GBL_A and GBL_B are set to the high power supply potential VDD or the low power supply potential VSS according to the change.
  • the potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D, and the write/read circuit 73.
  • the wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs.
  • the write/read circuit 73 controls the writing of data signals according to the signal EN_data.
  • the switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and wiring GBL_B.
  • the switch circuit 72_A is switched on or off under the control of the switching signal CSEL1.
  • the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level.
  • the switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46.
  • the switch circuit 72_B is switched on or off under the control of the switching signal CSEL2.
  • the switches 83_C and 83_D may be similar to the switches 83_A and 83_B.
  • the memory device 300 can be configured to connect the memory cell 10, the functional circuit 51, and the sense amplifier 46 via wiring BL and wiring GBL arranged in the vertical direction, which is the shortest distance.
  • the number of functional layers 50 having transistors that constitute the functional circuit 51 increases, the load on the wiring BL is reduced, which shortens the write time and makes it easier to read data.
  • each transistor in the functional circuits 51_A and 51_B is controlled in response to control signals WE, RE, and a selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL in response to the control signal and the selection signal.
  • the functional circuits 51_A and 51_B can function as sense amplifiers composed of OS transistors. With this configuration, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 46 using Si transistors.
  • FIG. 3 an example of a chip 1200 on which a memory device of the present invention is implemented is shown with reference to Figures 21A and 21B.
  • a plurality of circuits (systems) are implemented on the chip 1200.
  • a technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).
  • SoC system on chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.
  • Bumps (not shown) are provided on the chip 1200, which are connected to the first surface of the package substrate 1201, as shown in FIG. 21B.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222.
  • a storage device such as a DRAM 1221 or a flash memory 1222.
  • the DOSRAM described in the previous embodiment may be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory may be the DOSRAM described above.
  • the GPU 1212 is suitable for parallel calculation of multiple data, and may be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.
  • the wiring between the CPU 1211 and GPU 1212 can be shortened, and data can be transferred from the CPU 1211 to the GPU 1212, data can be transferred between the memories of the CPU 1211 and GPU 1212, and the results of calculations performed by the GPU 1212 can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit.
  • the analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. Controllers include a mouse, a keyboard, and a game controller. Examples of such interfaces that can be used include a Universal Serial Bus (USB) and a High-Definition Multimedia Interface (HDMI (registered trademark)).
  • USB Universal Serial Bus
  • HDMI High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • circuits can be formed in chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.
  • the package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are provided can be referred to as a GPU module 1204.
  • the GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles.
  • the product-sum calculation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural networks
  • CNN convolutional neural networks
  • RNN recurrent neural networks
  • DBM deep Boltzmann machines
  • DBN deep belief networks
  • Embodiment 4 This embodiment describes an example of an electronic component and an electronic device in which the memory device described in the above embodiment is built in.
  • the electronic components and electronic devices can have low power consumption and high speed.
  • FIG. 22A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 22A has a memory device 720 in a mold 711.
  • FIG. 22A omits a portion of the electronic component 700 to show its interior.
  • the electronic component 700 has lands 712 on the outside of the mold 711.
  • the lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 720 by wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the memory device 720 has a drive circuit layer 721 and a memory circuit layer 722.
  • FIG 22B shows a perspective view of electronic component 730.
  • Electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 are provided on interposer 731.
  • a semiconductor device 735 and multiple memory devices 720 are provided on interposer 731.
  • the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.
  • the package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like.
  • the interposer 731 may be a silicon interposer, a resin interposer, or the like.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, wiring on silicon interposers can be formed using semiconductor processes, making it easy to form fine wiring that is difficult to achieve with resin interposers.
  • SiP, MCM, etc. that use silicon interposers
  • deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is less likely to occur.
  • the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 22B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.
  • Embodiment 5 an application example of a storage device using the storage device described in the previous embodiment will be described.
  • the storage device described in the previous embodiment can be applied to various electronic devices (e.g., information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.).
  • the storage device described in the above embodiment as a storage device for the electronic device, the electronic device can be made to consume less power and operate at a higher speed.
  • the computer here includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • FIGS. 23A to 23E are schematic diagrams showing some configuration examples of a removable storage device.
  • the storage device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.
  • FIG 23A is a schematic diagram of a USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the board 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the board 1104.
  • the memory device shown in the previous embodiment can be incorporated in the memory chip 1105, etc.
  • FIG 23B is a schematic diagram of the external appearance of an SD card
  • Figure 23C is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a board 1113.
  • the board 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the board 1113.
  • the capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the board 1113 as well.
  • a wireless chip with a wireless communication function may also be provided on the board 1113. This makes it possible to read and write data from and to the memory chip 1114 through wireless communication between the host device and the SD card 1110.
  • the memory device shown in the previous embodiment can be incorporated into the memory chip 1114, etc.
  • FIG 23D is a schematic diagram of the appearance of an SSD
  • Figure 23E is a schematic diagram of the internal structure of the SSD.
  • SSD 1150 has a housing 1151, a connector 1152, and a board 1153.
  • Board 1153 is housed in housing 1151.
  • memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153.
  • Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip.
  • the memory device shown in the previous embodiment can be incorporated into memory chip 1154, etc.
  • a memory device can be used in a processor such as a CPU or a GPU, or a chip.
  • a processor such as a CPU or a GPU, or a chip in an electronic device
  • the electronic device can have low power consumption and high speed.
  • Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip using the memory device are shown in FIG. 24A to FIG. 24H .
  • the GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, and audio playback devices.
  • game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, and audio playback devices.
  • by providing the GPU or chip according to one embodiment of the present invention in an electronic device it is possible to mount artificial intelligence on the electronic device.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention may have a sensor (including a function to sense, detect or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared light).
  • a sensor including a function to sense, detect or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared light).
  • the electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, and the like. Examples of electronic devices are shown in Figures 24A to 24H.
  • [Information terminal] 24A illustrates a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5100 includes a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.
  • the information terminal 5100 can achieve low power consumption and high speed.
  • FIG. 24B shows a notebook type information terminal 5200.
  • the notebook type information terminal 5200 has an information terminal main body 5201, a display unit 5202, and a keyboard 5203.
  • the notebook information terminal 5200 can achieve low power consumption and high speed by applying a chip of one embodiment of the present invention.
  • a smartphone and a notebook type information terminal are shown as examples of electronic devices in Figs. 24A and 24B, respectively, but information terminals other than smartphones and notebook type information terminals can also be applied.
  • Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.
  • [game machine] 24C illustrates a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be detached from the housing 5301.
  • an image displayed on the display portion 5304 can be output to another video device (not shown).
  • the housing 5302 and the housing 5303 can each function as an operation portion. This allows a plurality of players to play a game at the same time.
  • the chips described in the above embodiments can be incorporated in the chips provided on the substrates of the housings 5301, 5302, and 5303.
  • FIG. 24D also shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.
  • a game machine with low power consumption By applying a GPU or chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400, a game machine with low power consumption can be realized.
  • low power consumption can reduce heat generation from the circuit, so that the effect of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • 24C and 24D show a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these.
  • game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.
  • the GPU or chip of one aspect of the present invention can be applied to a large computer.
  • Figure 24E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • Figure 24F is a diagram showing a rack-mounted calculator 5502 that the supercomputer 5500 has.
  • the supercomputer 5500 has a rack 5501 and multiple rack-mounted computers 5502.
  • the multiple computers 5502 are stored in the rack 5501.
  • the computer 5502 is also provided with multiple boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.
  • the supercomputer 5500 is a large computer used mainly for scientific and technological calculations. In scientific and technological calculations, huge amounts of calculations need to be processed at high speed, so power consumption is high and chips generate a lot of heat. For example, in a data center that has multiple supercomputers 5500, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yota) bytes or 10 30 (quetta) bytes.
  • a supercomputer with low power consumption can be realized.
  • low power consumption can reduce heat generation from the circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and make a significant contribution to measures against global warming.
  • a supercomputer is illustrated as an example of a large computer, but large computers to which the GPU or chip of one embodiment of the present invention is applied are not limited to this.
  • Examples of large computers to which the GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).
  • the GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.
  • Figure 24G is a diagram showing the area around the windshield inside an automobile, which is an example of a moving body.
  • Figure 24G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.
  • the display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, air conditioning settings, and the like.
  • the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, making it possible to improve the design.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 can display an image from an imaging device (not shown) installed in the vehicle to complement the field of view (blind spot) blocked by the pillar. In other words, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be increased. Furthermore, by displaying an image that complements the invisible parts, safety can be confirmed more naturally and without any sense of discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, and therefore, for example, the chip can be used in an automatic driving system for automobiles.
  • the chip can also be used in a system that provides road guidance, hazard prediction, and the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.
  • moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide them with a system that utilizes artificial intelligence.
  • [electric appliances] 24H shows an example of an electric appliance, an electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • an electric refrigerator-freezer 5800 with artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on the ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of those ingredients, and a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800.
  • An electric refrigerator-freezer has been described as an example of an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, and audiovisual equipment.
  • a storage device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • FIG. 25 a specific example of application of the storage device of one embodiment of the present invention to space equipment will be described with reference to FIG. 25 .
  • Figure 25 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown as an example of outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 also has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • a storage device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the electrical characteristics of an OS transistor change less when exposed to radiation than those of a Si transistor. In other words, the OS transistor is highly reliable even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited thereto.
  • a storage device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

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Publication number Priority date Publication date Assignee Title
CN119947089A (zh) * 2024-12-30 2025-05-06 北京超弦存储器研究院 一种存储单元、存储器和电子设备
WO2025243161A1 (ja) * 2024-05-23 2025-11-27 株式会社半導体エネルギー研究所 半導体装置

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Publication number Priority date Publication date Assignee Title
JP2005303109A (ja) * 2004-04-14 2005-10-27 Takehide Shirato 半導体記憶装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2018041958A (ja) * 2016-08-31 2018-03-15 株式会社半導体エネルギー研究所 半導体装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303109A (ja) * 2004-04-14 2005-10-27 Takehide Shirato 半導体記憶装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2018041958A (ja) * 2016-08-31 2018-03-15 株式会社半導体エネルギー研究所 半導体装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025243161A1 (ja) * 2024-05-23 2025-11-27 株式会社半導体エネルギー研究所 半導体装置
CN119947089A (zh) * 2024-12-30 2025-05-06 北京超弦存储器研究院 一种存储单元、存储器和电子设备

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