JP2018041958A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2018041958A JP2018041958A JP2017164943A JP2017164943A JP2018041958A JP 2018041958 A JP2018041958 A JP 2018041958A JP 2017164943 A JP2017164943 A JP 2017164943A JP 2017164943 A JP2017164943 A JP 2017164943A JP 2018041958 A JP2018041958 A JP 2018041958A
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- Prior art keywords
- oxide
- transistor
- insulator
- film
- conductor
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 129
- 239000001301 oxygen Substances 0.000 claims abstract description 129
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- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
【解決手段】第1のトランジスタと第2のトランジスタと、第1のトランジスタの少なくとも一部を覆う第1の金属酸化物と、第1のトランジスタおよび第2のトランジスタ上の絶縁膜と、絶縁膜上の第2の金属酸化物を有する半導体装置であって、第1のトランジスタは、第1のゲート電極、第1のゲート絶縁膜、第1の酸化物、第1のソース電極およびドレイン電極、第2のゲート絶縁膜および第2のゲート電極を有し、第2のトランジスタは、第3のゲート電極、第3のゲート絶縁膜、第2の酸化物、第2のソース電極およびドレイン電極、第4のゲート絶縁膜および第4のゲート電極を有し、第1のゲート絶縁膜および第2のゲート絶縁膜は、第1の金属酸化物と接し、第3のゲート絶縁膜および第4のゲート絶縁膜は、絶縁膜と接し、絶縁膜が過剰酸素を有する半導体装置。
【選択図】図1
Description
本発明の一態様によれば、大きさの異なるトランジスタを有する回路のトランジスタ100と、トランジスタが高密度で配される回路のトランジスタ200と、を異なる構造に作り分けることで、それぞれの回路が有するトランジスタの電気特性のバラツキを抑制し、高性能な半導体装置とすることができる。本実施の形態では、大きさの異なるトランジスタを有する回路のトランジスタ100と、トランジスタが高密度で配される回路のトランジスタ200と、を同一基板上に設ける実施形態の一例を説明する。
以下では、本発明の一態様に係るトランジスタ100及びトランジスタ200の構造について説明する。
図3(A)は、トランジスタ100Aの上面図である。また、図3(B)は、図3(A)にA1−A2の一点鎖線で示す部位の断面図である。また、図3(C)は、図3(A)にA3−A4の一点鎖線で示す部位の断面図である。図3(B)において、A1−A2はトランジスタ100Aのチャネル長方向の断面図であり、図3(C)において、A3−A4はトランジスタ100Aのチャネル幅方向の断面図である。図3(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
基板400としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体404a、導電体404b、導電体404c、導電体310a、導電体310b、導電体416a1および導電体416a2としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物406a、酸化物406bおよび酸化物406cとしては、金属酸化物を用いることが好ましい。ただし、酸化物406a、酸化物406bおよび酸化物406cの代わりに、シリコン(歪シリコン含む)、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ガリウムヒ素、アルミニウムガリウムヒ素、インジウムリン、窒化ガリウムまたは有機半導体などを用いても構わない場合がある。
酸化物は、単結晶酸化物と、それ以外の非単結晶酸化物と、に分けられる。非単結晶酸化物としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物などがある。
次に、図20(A)、図20(B)、および図20(C)を用いて、本発明に係る酸化物が有するインジウム、元素Mおよび亜鉛の原子数比の好ましい範囲について説明する。なお、図20(A)、図20(B)、および図20(C)には、酸素の原子数比については記載しない。また、酸化物が有するインジウム、元素M、および亜鉛の原子数比のそれぞれの項を[In]、[M]、および[Zn]とする。
続いて、上記酸化物をトランジスタに用いる場合について説明する。
ここで、酸化物中における各不純物の影響について説明する。
続いて、該酸化物を2層構造、または3層構造とした場合について述べる。酸化物S1、酸化物S2、および酸化物S3の積層構造、および積層構造に接する絶縁体のバンド図と、酸化物S2および酸化物S3の積層構造、および積層構造に接する絶縁体のバンド図と、酸化物S1および酸化物S2の積層構造、および積層構造に接する絶縁体のバンド図と、について、図21を用いて説明する。
<トランジスタの作製方法1>
以下では、本発明に係るトランジスタ100およびトランジスタ200の作製方法を図1、図2および図5乃至図14を用いて説明する。なお、図5乃至図12はトランジスタ100およびトランジスタ200共通の作製方法を示し、図13はトランジスタ100の作製方法を示し、図14はトランジスタ200の作製方法を示す。また、図1、図2および図5乃至図14において、各図の(A)は、上面図である。各図の(B)は各図の(A)にA1−A2の一点鎖線で示す部位の断面図である。また、各図の(C)は、各図の(A)にA3−A4の一点鎖線で示す部位の断面図である。各図の(B)において、A1−A2はトランジスタのチャネル長方向の断面図であり、各図の(C)において、A3−A4はトランジスタのチャネル幅方向の断面図である。
以下では、本発明に係るトランジスタ100Aおよびトランジスタ200Aの作製方法を図3、図4、図5乃至図11、図15および図16を用いて説明する。なお、図5乃至図11はトランジスタ100Aおよびトランジスタ200A共通の作製方法を示し、図15はトランジスタ100Aの作製方法を示し、図16はトランジスタ200Aの作製方法を示す。また、図3、図4、図5乃至図11、図15および図16において、各図の(A)は、上面図である。各図の(B)は各図の(A)にA1−A2の一点鎖線で示す部位の断面図である。また、各図の(C)は、各図の(A)にA3−A4の一点鎖線で示す部位の断面図である。各図の(B)において、A1−A2はトランジスタのチャネル長方向の断面図であり、各図の(C)において、A3−A4はトランジスタのチャネル幅方向の断面図である。
<半導体装置の構成>
本実施の形態では、本明細書等に開示したトランジスタを用いた半導体装置の一例について説明する。
図18は半導体装置1000の断面図である。半導体装置1000はトランジスタ100、トランジスタ200、トランジスタ600、容量素子700を有する。トランジスタ200、トランジスタ600および容量素子700は、図17に示す、トランジスタ200a、トランジスタ600aおよびに容量素子700aにそれぞれ相当する。トランジスタ200は、メモリセルが有するトランジスタである。また、トランジスタ100は、メモリセルを制御する回路が有するトランジスタの一例である。トランジスタ100は、トランジスタ200とは大きさが異なるトランジスタであり、トランジスタ200よりも大きなトランジスタである。
<電子機器>
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図19に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
I2 絶縁体
S1 酸化物
S2 酸化物
S3 酸化物
100 トランジスタ
100A トランジスタ
200 トランジスタ
200a トランジスタ
200A トランジスタ
200b トランジスタ
283 チャネル形成領域
284 低濃度p型不純物領域
285 高濃度p型不純物領域
286 絶縁体
287 導電体
288 側壁
301 絶縁体
302 絶縁体
303 絶縁体
310 導電体
310a 導電体
310b 導電体
400 基板
401a 酸化物
401b 酸化物
402 絶縁体
404 導電体
404a 導電体
404b 導電体
404c 導電体
406a 酸化物
406a1 酸化物
406b 酸化物
406b1 酸化物
406c 酸化物
406c1 酸化物
408a 酸化物
408b 酸化物
410 絶縁体
411 導電体
411a 導電体
411a1 導電体
411a2 導電体
412 絶縁体
412a 絶縁体
416 導電体
416a 導電体
416a1 導電体
416a2 導電体
417 バリア膜
417a バリア膜
417a1 バリア膜
417a2 バリア膜
418 酸化物
420 酸化物
421 レジスト
422 酸化物
501 基板
504 絶縁体
505 絶縁体
514 素子分離領域
521 導電体
522 導電体
525 導電体
526 導電体
527 導電体
528 導電体
529 導電体
534 絶縁体
537 絶縁体
538 絶縁体
539 絶縁体
600 トランジスタ
600a トランジスタ
600b トランジスタ
700 容量素子
700a 容量素子
700b 容量素子
1000 半導体装置
2900 携帯型ゲーム機
2901 筐体
2902 筐体
2903 表示部
2904 表示部
2905 マイクロホン
2906 スピーカ
2907 操作スイッチ
2908 スタイラス
2910 情報端末
2911 筐体
2912 表示部
2913 カメラ
2914 スピーカ部
2915 操作スイッチ
2916 外部接続部
2917 マイク
2920 ノート型パーソナルコンピュータ
2921 筐体
2922 表示部
2923 キーボード
2924 ポインティングデバイス
2940 ビデオカメラ
2941 筐体
2942 筐体
2943 表示部
2944 操作スイッチ
2945 レンズ
2946 接続部
2950 情報端末
2951 筐体
2952 表示部
2960 情報端末
2961 筐体
2962 表示部
2963 バンド
2964 バックル
2965 操作スイッチ
2966 入出力端子
2967 アイコン
2980 自動車
2981 車体
2982 車輪
2983 ダッシュボード
2984 ライト
Claims (11)
- 第1のトランジスタと第2のトランジスタと、前記第1のトランジスタの少なくとも一部を覆う第1の金属酸化物と、
前記第1のトランジスタおよび前記第2のトランジスタ上の絶縁膜と、
前記絶縁膜上の第2の金属酸化物を有する半導体装置であって、
前記第1のトランジスタは、第1のゲート電極と、前記第1のゲート電極上の第1のゲート絶縁膜と、前記第1のゲート絶縁膜上の第1の酸化物と、前記第1の酸化物と電気的に接続される第1のソース電極およびドレイン電極と、前記第1の酸化物上の第2のゲート絶縁膜と、前記第2のゲート絶縁膜上の第2のゲート電極とを有し、
前記第2のトランジスタは、第3のゲート電極と、前記第3のゲート電極上の第3のゲート絶縁膜と、前記第3のゲート絶縁膜上の第2の酸化物と、前記第2の酸化物と電気的に接続される第2のソース電極およびドレイン電極と、前記第2の酸化物上の第4のゲート絶縁膜と、前記第4のゲート絶縁膜上の第4のゲート電極とを有し、
前記第1のゲート絶縁膜および前記第2のゲート絶縁膜は、前記第1の金属酸化物と接し、
前記第3のゲート絶縁膜および前記第4のゲート絶縁膜は、前記絶縁膜と接し、
前記絶縁膜が過剰酸素を有することを特徴とする半導体装置。 - 第1のトランジスタと第2のトランジスタと、前記第1のトランジスタおよび前記第2のトランジスタの少なくとも一部を覆う第1の金属酸化物と、
前記第1のトランジスタおよび前記第2のトランジスタ上の絶縁膜と、
前記絶縁膜上の第2の金属酸化物を有する半導体装置であって、
前記第1のトランジスタは、第1のゲート電極と、前記第1のゲート電極上の第1のゲート絶縁膜と、前記第1のゲート絶縁膜上の第1の酸化物と、前記第1の酸化物と電気的に接続される第1のソース電極およびドレイン電極と、前記第1の酸化物上の第2のゲート絶縁膜と、前記第2のゲート絶縁膜上の第2のゲート電極とを有し、
前記第2のトランジスタは、第3のゲート電極と、前記第3のゲート電極上の第3のゲート絶縁膜と、前記第3のゲート絶縁膜上の第2の酸化物と、前記第2の酸化物と電気的に接続される第2のソース電極およびドレイン電極と、前記第2の酸化物上の第4のゲート絶縁膜と、前記第4のゲート絶縁膜上の第4のゲート電極とを有し、
前記第1のゲート絶縁膜は、前記絶縁膜と接し、
前記第2のゲート絶縁膜は、前記第1の金属酸化物および前記絶縁膜と接し、
前記第3のゲート絶縁膜および前記第4のゲート絶縁膜は、前記絶縁膜と接し、
前記絶縁膜が過剰酸素を有することを特徴とする半導体装置。 - 前記第1の金属酸化物が酸素の透過を抑制する機能を有することを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記第1の金属酸化物および前記第2の金属酸化物は、アルミニウムおよび酸素を含むことを特徴とする請求項1乃至請求項3のいずれか一に記載の半導体装置。
- 第1の回路と第2の回路を有する半導体装置であって、
前記第1の回路は、前記第1のトランジスタを複数有し、
前記第2の回路は、前記第2のトランジスタを複数有することを特徴とする請求項1乃至請求項4のいずれか一に記載の半導体装置。 - 前記第1の回路が有する前記第1のトランジスタのチャネル幅は、前記第1のトランジスタの前記チャネル長の2倍以上1000倍以下であることを特徴とする請求項5に記載の半導体装置。
- 前記第1の回路が有する前記第1のトランジスタのチャネル長は、前記第1のトランジスタの前記チャネル幅の2倍以上1000倍以下であることを特徴とする請求項5または請求項6に記載の半導体装置。
- 前記第2の回路が有する前記第2のトランジスタの密度は、0.01個/μm2以上2500個/μm2以下であることを特徴とする請求項5乃至請求項7のいずれか一に記載の半導体装置。
- 前記第1の回路が有する前記第1のトランジスタの密度は、前記第2の回路が有する前記第2のトランジスタの密度より小さいことを特徴とする請求項5乃至請求項8のいずれか一に記載の半導体装置。
- 前記第1の回路が有する前記第1のトランジスタのチャネル幅は、前記第2の回路が有する前記第2のトランジスタのチャネル幅より大きいことを特徴とする請求項5乃至請求項9のいずれか一に記載の半導体装置。
- 前記第1の回路が有する前記第1のトランジスタのチャネル長は、前記第2の回路が有する前記第2のトランジスタのチャネル長より大きいことを特徴とする請求項5乃至請求項10のいずれか一に記載の半導体装置。
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