WO2024073904A1 - 计数控制电路、计数控制方法以及半导体存储器 - Google Patents

计数控制电路、计数控制方法以及半导体存储器 Download PDF

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Publication number
WO2024073904A1
WO2024073904A1 PCT/CN2022/126387 CN2022126387W WO2024073904A1 WO 2024073904 A1 WO2024073904 A1 WO 2024073904A1 CN 2022126387 W CN2022126387 W CN 2022126387W WO 2024073904 A1 WO2024073904 A1 WO 2024073904A1
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Prior art keywords
counting
signal
module
clock
clock signal
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PCT/CN2022/126387
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English (en)
French (fr)
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黄泽群
孙凯
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长鑫存储技术有限公司
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Priority to US18/452,518 priority Critical patent/US20240119987A1/en
Publication of WO2024073904A1 publication Critical patent/WO2024073904A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Definitions

  • the present disclosure is based on the Chinese patent application with application number 202211230198.3, application date October 8, 2022, and invention name “Counting control circuit, counting control method and semiconductor memory”, and claims the priority of the Chinese patent application.
  • the entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference.
  • the present disclosure relates to the technical field of integrated circuits, and in particular to a counting control circuit, a counting control method and a semiconductor memory.
  • DDR double data rate
  • DRAM dynamic random access memory
  • ECS Error Check and Scrub
  • Embodiments of the present disclosure provide a counting control circuit, a counting control method, and a semiconductor memory.
  • an embodiment of the present disclosure provides a counting control circuit, the counting control circuit comprising a logic control module and a counting statistics module, and the output end of the logic control module is connected to the clock end of the counting statistics module, wherein:
  • a logic control module configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under the control of the first identification signal;
  • the counting and statistics module is configured to receive a counting clock signal, count according to the counting clock signal, and generate a first identification signal, wherein the first identification signal is used to indicate the generation of a command signal for executing a first operation; wherein, when the count value meets a preset condition, the first identification signal is in a valid state.
  • the logic control module is configured to generate a counting clock signal based on the first clock signal when the first identification signal is in an invalid state, so that the counting statistics module counts the counting clock signal; or, when the first identification signal is in a valid state, shield the first clock signal to prevent the generation of the counting clock signal, so that the counting statistics module stops counting.
  • the logic control module includes a first driver module and a first logic module, wherein:
  • a first driving module is configured to drive the first clock signal to obtain a first intermediate signal
  • the first logic module is configured to perform a logic operation on the first intermediate signal and the first identification signal to obtain a counting clock signal.
  • the first driving module includes an even number of cascaded first NOT gates.
  • the first logic module includes a first delayed inversion module, a first NAND gate, and a second NOT gate, wherein:
  • a first delay and inversion module is configured to delay and invert the first identification signal to obtain a second intermediate signal
  • a first NAND gate used for performing a NAND logic operation on the first intermediate signal and the second intermediate signal to obtain a third intermediate signal
  • the second NOT gate is used to perform a NOT logic operation on the third intermediate signal to obtain a counting clock signal.
  • the first delayed inversion module includes an odd number of cascaded third NOT gates.
  • the counting and statistics module is further configured to receive a counting reset signal, clear the count according to the counting reset signal, and put the first identification signal in an invalid state.
  • the counting control circuit also includes a reset logic module; wherein the reset logic module is configured to receive a first command signal and an external reset signal, perform logic operations on the first command signal and the external reset signal, and generate a counting reset signal, and the counting reset signal is used to send to the counting statistics module; wherein, when the first identification signal is in a valid state, it is used to indicate the generation of the first command signal.
  • the reset logic module includes a first OR gate; wherein, the first input terminal of the first OR gate is used to receive an external reset signal, the second input terminal of the first OR gate is used to receive a first command signal, and the output terminal of the first OR gate is used to output a counting reset signal.
  • the counting and statistics module includes a counting module and a decoding module, and the output end of the counting module is connected to the input end of the decoding module, wherein:
  • a counting module is configured to receive a counting clock signal, count according to the counting clock signal, and generate a counting signal, wherein the counting signal is used to represent a counting value;
  • the decoding module is configured to receive the counting signal, decode the counting signal, and generate a first identification signal; wherein, when the counting value meets a preset condition, the first identification signal is in a valid state.
  • the counting module includes a synchronous binary counter, which includes a plurality of counting submodules cascaded in sequence, and each counting submodule includes a trigger, and a clock end of each trigger is connected to a counting clock signal, wherein:
  • a plurality of counting submodules are configured to receive a counting clock signal, perform clock sampling processing through triggers contained in each module, and output a counting signal;
  • the counting signal includes a plurality of bits, and there is a corresponding relationship between the plurality of counting submodules and the plurality of bits included in the counting signal.
  • the first counting submodule includes a first trigger, an input end of the first trigger is connected to the second output end of the first trigger, a clock end of the first trigger is used to receive a counting clock signal, and a first output end of the first trigger is used to output a first counting signal, and the first counting signal is the 0th bit in the counting signal;
  • the second counting submodule includes a second trigger and a second XOR gate, the first input end of the second XOR gate is connected to the first output end of the first trigger, the second input end of the second XOR gate is connected to the first output end of the second trigger, the output end of the second XOR gate is connected to the input end of the second trigger, the clock end of the second trigger is used to receive the counting clock signal, and the first output end of the second trigger is used to output a second counting signal, and the second counting signal is the first bit in the counting signal;
  • the i-th counting submodule includes an i-th trigger, an i-th NAND gate, an i-th NOT gate and an i-th XOR gate, wherein the first input end of the i-th NAND gate is connected to the first output end of the i-1-th trigger, the second input end of the i-th NAND gate is connected to the first input end of the i-1-th XOR gate, the output end of the i-th NAND gate is connected to the input end of the i-th NAND gate, the output end of the i-th NOT gate is connected to the first input end of the i-th XOR gate, the second input end of the i-th XOR gate is connected to the first output end of the i-th trigger, the output end of the i-th XOR gate is connected to the input end of the i-th trigger, the clock end of the i-th trigger is used to receive a counting clock signal, and the first output end of the i-th trigger is used
  • the counting control circuit further includes a command control module, wherein:
  • the command control module is configured to receive a first identification signal and a refresh command signal, and to generate a first command signal according to the refresh command signal when the first identification signal is in a valid state; or to generate a second command signal according to the refresh command signal when the first identification signal is in an invalid state.
  • the first command signal is an error check and clear (ECS) command signal for performing an ECS operation
  • the second command signal is an internal refresh signal for performing a refresh operation
  • the refresh command signal includes at least one of the following: a refresh signal and a self-refresh signal.
  • the counting control circuit further comprises a clock generating circuit, wherein:
  • the clock generating circuit is used to generate a first clock signal.
  • the clock generation circuit includes an oscillation module and a frequency division module, wherein:
  • An oscillation module configured to output a second clock signal of a preset frequency
  • a frequency division module configured to perform n-frequency division processing on the second clock signal to obtain a first clock signal
  • the frequency of the first clock signal is one nth of the preset frequency, where n is an integer greater than zero.
  • an embodiment of the present disclosure provides a counting control method, the method comprising:
  • Counting is performed according to the counting clock signal to generate a first identification signal, wherein the first identification signal is used to indicate the generation of a command signal for executing a first operation; wherein, when the count value meets a preset condition, the first identification signal is put into a valid state.
  • an embodiment of the present disclosure provides a semiconductor memory, which includes the counting control circuit as described in the first aspect.
  • the semiconductor memory includes dynamic random access memory DRAM.
  • the embodiments of the present disclosure provide a counting control circuit, a counting control method and a semiconductor memory, wherein the counting control circuit includes a logic control module and a counting statistics module, and the output end of the logic control module is connected to the clock end of the counting statistics module, wherein the logic control module is configured to receive a first clock signal and a first identification signal, and under the control of the first identification signal, generate a counting clock signal according to the first clock signal; the counting statistics module is configured to receive the counting clock signal, count according to the counting clock signal, and generate a first identification signal, wherein the first identification signal is used to indicate the generation of a command signal for executing a first operation; wherein when the count value meets a preset condition, the first identification signal is put into a valid state.
  • the counting control circuit includes a logic control module and a counting statistics module, and the output end of the logic control module is connected to the clock end of the counting statistics module, wherein the logic control module is configured to receive a first clock signal and a first identification signal, and under the
  • the logic control module can obtain a counting clock signal for counting by performing a logical operation in combination with the first identification signal.
  • the first identification signal can be generated based on the counting clock signal to generate a command signal for executing the first operation.
  • the command generation for executing the ECS operation is not restricted by the refresh command, which solves the technical problem in the related art that the ECS command signal can only be generated by counting with the help of REF_AB, and can ensure that the complete ECS operation is completed in 24 hours.
  • FIG1 is a schematic diagram of a signal timing of an ECS mode
  • FIG. 2 is a schematic diagram of a framework for generating an ECS command
  • FIG3 is a schematic diagram of a structure of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG4 is a second schematic diagram of a structure of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG5 is a third schematic diagram of the structure of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG6 is a fourth schematic diagram of the structure of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the structure of an asynchronous binary counter provided by an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the structure of a synchronous binary counter provided by an embodiment of the present disclosure.
  • FIG9 is a fifth structural diagram of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG10 is a sixth schematic diagram of the structure of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG11 is a seventh schematic diagram of a counting control circuit according to an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of a structure of a counting control circuit according to an embodiment of the present disclosure.
  • FIG13 is a ninth structural diagram of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG14 is a schematic diagram of a structure of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG15 is a schematic diagram of a structure of a counting control circuit provided by an embodiment of the present disclosure.
  • FIG16 is a schematic diagram of a signal timing sequence of a counting control circuit provided by an embodiment of the present disclosure.
  • FIG17 is a schematic diagram 12 of a counting control circuit provided in an embodiment of the present disclosure.
  • FIG18 is a signal timing diagram of another counting control circuit provided by an embodiment of the present disclosure.
  • FIG19 is a flow chart of a counting control method provided in an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that “first ⁇ second ⁇ third” can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDR5 5th generation DDR standard (DDR5 Specification, DDR5SPEC);
  • Multi-Purpose Command (MPC)
  • ECS Error Check and Scrub
  • the ECS mode can be divided into automatic ECS operation mode and manual ECS operation mode.
  • the MPC command sent by the memory controller (Controller) is used to generate the ECS command signal;
  • the ECS command signal can be generated by refresh or self-refresh.
  • a specific MPC command can generate an ECS operation, there is no MPC command in the automatic ECS operation mode, so it is necessary to use refresh and self-refresh to generate the ECS command for the automatic ECS operation.
  • the embodiment of the present disclosure needs to perform a complete ECS operation on the DRAM at least once within 24 hours, so it is necessary to plan the time of the ECS operation.
  • the DRAM In order to achieve complete error checking and clearing of the DRAM, it is necessary to perform error checking on all rows (Row), columns (Column, Col), storage blocks (Bank, BA), and storage groups (Bank Group, BG) in the DRAM, so multiple ECS operations need to be performed within 24 hours, and the average interval time is tECSint, which is about 644 microseconds (microsecond, us) taking 16 Gigabyte (Gb) memory as an example. Among them, the interval time is the minimum time to complete the entire 16Gb memory ECS operation within 24 hours, and the specific calculation method is 24 hours ⁇ 60 minutes/hour ⁇ 60 seconds/minute/2 ⁇ (3+2+16+6).
  • FIG. 1 shows a signal timing diagram of an ECS mode (ECS Mode).
  • ECS Mode ECS Mode
  • CK_t and CK_c represent a pair of complementary clock signals
  • CA[13:0] represents the command address signal
  • CMD represents the command signal
  • CS0 represents the low-level effective chip select signal
  • valid represents the valid command address
  • DES represents the invalid command.
  • the command signal at this time is the MPC command
  • the corresponding command address is OP00001100.
  • ECS Mode Entry ECS Mode Entry
  • a delay time such as tMPC Delay
  • the order of the self-generated command signals in the DRAM is the activation signal (Active, ACT), the read signal (Read, RD), the write signal (Write, WR) and the precharge signal (Precharge, PRE)
  • tRCD represents the interval time between ACT and RD
  • WL represents the interval time between RD and WR
  • tWR represents the interval time between WR and PRE.
  • DDR5SPEC stipulates that the minimum time for each execution of an ECS operation is tECSc.
  • an ECS operation needs to perform internal read and write error detection modification on a Col corresponding to a Row in a Bank in a BG, so it is necessary to self-generate an internal command ACT-RD-WR-PRE, and the timing tRCD, WL, and tWR are met between each adjacent command, so that the internal operation of executing an ECS command can be completed within tECSc.
  • Table 1 shows the time specification of the average ECS interval under 16Gb memory.
  • the average interval time of the refresh command is tREFI.
  • FIG2 shows a schematic diagram of a framework for generating an ECS command.
  • the framework may include a counting and statistics module 201 and a command control module 202.
  • a counting and statistics module 201 by counting the number of refresh commands REF_AB, a counting signal CNT ⁇ N:0> is output; when the count reaches a preset value (such as 165), an ECS identification signal ECS_Flag may be generated; finally, when the ECS_Flag signal is in a valid state, the command control module 202 will steal the next refresh command REF_AB to generate an ECS command signal ECS_CMD.
  • a preset value such as 165
  • the refresh command REF_AB can be used as the clock of the first stage of the counting module, and can also be used as the input of the command control module.
  • the decoding module when the count reaches the preset value, the decoding module generates the ECS_Flag signal through decoding, and then steals the next refresh command through the command control module to use as the ECS command. At the same time, the corresponding stolen refresh command will disappear, and other refresh commands will not be affected.
  • the counting module will reset after the ECS command is generated and start counting again.
  • a refresh command REF_AB is used as the clock signal of the counting module. If the controller uses other methods such as REFsb to refresh, the count will not increase, and the ECS command indicating the execution of the ECS operation will be delayed, so that the entire ECS operation may not be completed within 24 hours. In addition, when the ECS_Flag signal is generated, the current counting module may still continue to count REF_AB until it receives the count reset signal ECS_RST, which will cause the ECS_RST and the counting module to conflict in time, and also generate additional power consumption.
  • the embodiment of the present disclosure provides a counting control circuit, which includes a logic control module and a counting statistics module.
  • the logic control module can obtain a counting clock signal for counting by performing a logic operation in combination with the first identification signal, and can generate a first identification signal according to the counting clock signal, thereby generating a command signal for performing the first operation.
  • the command generation for performing the ECS operation is not restricted by the refresh command, which solves the technical problem in the related art that the ECS command signal can only be generated by counting with the help of REF_AB, and can ensure that the complete ECS operation is completed in 24 hours; in addition, there is a logical relationship between the counting clock signal and the first identification signal, and the counting statistics module can be controlled to stop counting according to the state of the first identification signal, thereby achieving the purpose of reducing power consumption and ultimately improving the performance of the memory.
  • FIG3 shows a schematic diagram of the composition structure of a counting control circuit 30 provided in an embodiment of the present disclosure.
  • the counting control circuit 30 may include a logic control module 301 and a counting statistics module 302, and the output end of the logic control module 301 is connected to the clock end of the counting statistics module 302, wherein:
  • the logic control module 301 is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under the control of the first identification signal;
  • the counting and statistics module 302 is configured to receive a counting clock signal, count according to the counting clock signal, and generate a first identification signal, wherein the first identification signal is used to indicate the generation of a command signal for executing a first operation; wherein, when the count value meets a preset condition, the first identification signal is in a valid state.
  • the counting control circuit 30 can be applied to related circuits for performing ECS operations, and specifically can be a counting circuit applicable to all automatic ECS operations, but is not limited to this, and can also be applied to other counting circuits that generate command signals.
  • the interval time for generating the command signal is planned through the counting and statistics module 302 to ensure that all error checks and clearing of the memory can be completed within 24 hours.
  • the counting and statistics module 302 counts the received counting clock signal, and when the count value meets the preset condition, the first identification signal is in a valid state, so as to generate a command signal for performing the first operation; in this way, when the first operation is an ECS operation, according to the command signal generated by the counting control circuit 30, it can ensure that all error checks and clearing are completed within 24 hours.
  • the counting clock signal is generated by logical operation of the first clock signal and the first identification signal, and the first clock signal here can be a clock signal with a fixed frequency
  • the counting at this time does not need to consider the limitation of the refresh command, which solves the problem in the related art (when using the REF_AB command for counting to generate the ECS command signal) that the controller sends other refresh commands other than REF_AB, resulting in the inability to complete the complete ECS operation within 24 hours;
  • the counting statistics module 302 is controlled to stop counting according to the state of the first identification signal, thereby achieving the purpose of reducing power consumption and ultimately improving the performance of the memory.
  • the logic control module 301 is configured to generate a counting clock signal based on the first clock signal when the first identification signal is in an invalid state, so that the counting statistics module 302 counts the counting clock signal; or, when the first identification signal is in a valid state, shield the first clock signal to prevent the generation of the counting clock signal, so that the counting statistics module 302 stops counting.
  • the counting clock signal there is a logical relationship between the counting clock signal and the first identification signal. If the first identification signal is in an invalid state, the counting clock signal will be generated according to the first clock signal, so as to control the counting statistics module 302 to count according to the counting clock signal; otherwise, if the first identification signal is in a valid state, the counting clock signal will be prevented from being generated, so that the counting statistics module 302 stops working, thereby achieving the purpose of reducing power consumption.
  • the logic control module 301 may include a first driving module 3011 and a first logic module 3012, wherein:
  • a first driving module 3011 is configured to drive the first clock signal to obtain a first intermediate signal
  • the first logic module 3012 is configured to perform a logic operation on the first intermediate signal and the first identification signal to obtain a counting clock signal.
  • the first clock signal may be represented by ECS_CLK
  • the first identification signal may be represented by ECS_Flag
  • the counting clock signal may be represented by CNT_CLK.
  • the first driving module 3011 may include an even number of cascaded first NOT gates to enhance the driving capability of the first clock signal; however, due to the delay of the first NOT gate itself, it will also have a certain delay effect on the first clock signal.
  • the number of first NOT gates included in the first driving module 3011 may be 2, 4, 6, 8, etc., which is not specifically limited here.
  • the first driving module 3011 may include two first NOT gates ( U1 and U2 ).
  • the input end of U1 (as the input end of the first driving module 3011) is used to receive the first clock signal
  • the output end of U1 is connected to the input end of U2
  • the output end of U2 (as the output end of the first driving module 3011) is used to output the first intermediate signal.
  • the first driving module 3011 may be composed of two NOT gates, or may be composed of one or more buffers, etc.
  • the first driving module 3011 is concerned, as long as it can drive the first clock signal, its internal structure is not specifically limited.
  • the first logic module 3012 may include a first delay inversion module U3, a first NAND gate U4, and a second NOT gate U5, wherein:
  • a first delay and inversion module U3 is configured to delay and invert the first identification signal to obtain a second intermediate signal
  • a first NAND gate U4 used for performing a NAND logic operation on the first intermediate signal and the second intermediate signal to obtain a third intermediate signal
  • the second NOT gate U5 is used to perform a NOT logic operation on the third intermediate signal to obtain a counting clock signal.
  • the input end of the first delayed inversion module U3 is used to receive the first identification signal, and the output end of the first delayed inversion module U3 is connected to the first input end of the first NAND gate U4;
  • the input end of the first driving module 3011 is used to receive the first clock signal, the output end of the first driving module 3011 is connected to the second input end of the first NAND gate U4, the output end of the first NAND gate U4 is connected to the input end of the second NAND gate U5, and the output end of the second NAND gate U5 is used to output a counting clock signal.
  • the first delay inversion module U3 may include an odd number of cascaded third NOT gates, which are used to delay and invert the first identification signal.
  • the number of third NOT gates included in the first delay inversion module U3 may be 1, 3, 5, 7, etc., and no limitation is made here.
  • the first delay inversion module U3 includes only one third NOT gate, and at this time, the first identification signal can be delayed and inverted by the third NOT gate.
  • the first logic module 3012 can realize the function of generating a counting clock signal according to the first identification signal.
  • the first logic module 3012 can be a combination of two NOT gates and a NAND gate logic device, or a combination of a NOT gate and an AND gate logic device, etc.
  • the first logic module 3012 as long as it can realize the same function of the first logic module 3012, its internal structure is not specifically limited.
  • the counting statistics module 302 can not only count the counting clock signal, but also reset the count to re-count. Therefore, in some embodiments, the counting statistics module 302 is further configured to receive a counting reset signal, reset the count according to the counting reset signal, and make the first identification signal in an invalid state.
  • the counting statistics module 302 needs to be reset, that is, the counting statistics module 302 needs to receive the counting reset signal first.
  • the time interval between the moment when the counting reset signal is generated and the moment when the counting clock signal is generated can be adjusted by the first delayed inversion module U3. According to this time interval, it can be ensured that after the counting statistics module 302 is reset, re-counting can be started according to the counting clock signal.
  • the invalid state of the first identification signal it can be that after the counting statistics module 302 receives the counting reset signal, the counting is cleared according to the counting reset signal, and the first identification signal is reset to the invalid state according to the cleared counting value.
  • the invalid state of the first identification signal it can also be that after the first command signal for instructing to execute the ECS operation is generated according to the first identification signal, the first identification signal is also placed in the invalid state.
  • the first identification signal can be in a valid state or in an invalid state.
  • the counting and statistics module 302 generates a first identification signal in a valid state after each interval (i.e., the count value reaches a preset condition) to indicate the generation of a first command signal for performing an ECS operation, and after the first command signal is generated, the first identification signal is in an invalid state; and when the first identification signal is in an invalid state, a counting clock signal can be generated by the logic control module 301, and the counting and statistics module 302 can perform counting according to the counting clock signal.
  • the counting statistics module 302 may include a counting module 3021 and a decoding module 3022, and the output end of the counting module 3021 is connected to the input end of the decoding module 3022, wherein:
  • the counting module 3021 is configured to receive a counting clock signal, count according to the counting clock signal, and generate a counting signal, where the counting signal is used to represent a counting value;
  • the decoding module 3022 is configured to receive the counting signal, decode the counting signal, and generate a first identification signal; wherein, when the counting value meets a preset condition, the first identification signal is in a valid state.
  • the counting signal can be represented by N+1 bits of binary data Code ⁇ N:0>.
  • the counting signal is not just one signal, it represents a group of signals.
  • the counting signal may include N+1 bits, each bit corresponds to a signal, specifically: Code ⁇ 0>, Code ⁇ 1>, Code ⁇ 2>, ..., Code ⁇ N>; wherein the value of N is associated with the counting value of the preset condition.
  • the counting value of the preset condition is 146, and the corresponding binary number is 10001010, then at least 8 bits of binary counting signal are required to count the counting clock signal; assuming that the counting value of the preset condition is 60, and the corresponding binary number is 111100, then at least 6 bits of binary counting signal are required to count the counting clock signal.
  • the counting module 3021 can be composed of a number of triggers cascaded in sequence, and the number of triggers is equal to the number of bits of the counting signal (N+1).
  • the counting signal is an 8-bit binary signal
  • the number of triggers in the counting module 3021 is 8.
  • the time interval of the ECS operation is 644us
  • the cycle of the counting clock signal is 4.4us
  • a counting signal Code ⁇ 7:0> for characterizing the count value can be obtained; then, by decoding the counting signal Code ⁇ 7:0>, a decoding output result (i.e., a first identification signal) can be obtained.
  • a decoding output result i.e., a first identification signal
  • the counting signal may include several bits, and there is a corresponding relationship between the number of bits and the number of triggers; these several bits can be used to represent the count value, and the number of triggers can determine the upper limit of the count value.
  • the counting signal may include 8 bits, such as Code ⁇ 7:0>; at this time, the count value range corresponding to the counting signal Code ⁇ 7:0> is 00000000 ⁇ 111111111.
  • the counting module 3021 may include an asynchronous binary counter, wherein:
  • the asynchronous binary counter includes a plurality of triggers cascaded in sequence, wherein the input terminal (D) of each stage of the trigger is connected to its own second output terminal (Q not), and the second output terminal (Q not) of each stage of the trigger is connected to the clock terminal (CK) of the next stage of the trigger, and the clock terminal (CK) of the first stage of the trigger is connected to the first clock signal.
  • the counting module 3021 includes eight flip-flops.
  • the flip-flop may be a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF).
  • DFF Data Flip-Flop or Delay Flip-Flop
  • the D-type flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit constituting a variety of sequential circuits and an important unit circuit in digital logic circuits.
  • the D-type flip-flop has two stable states, namely "0" and "1". Under the action of the signal received at the clock end of the flip-flop, it can flip from one stable state to another stable state.
  • the trigger may include an input terminal (D), a clock terminal (CK), a first output terminal (Q), and a second output terminal (Q is not, represented by /Q), and may even include a reset terminal (RST).
  • the first output terminal (Q) of each level of trigger is used to sequentially output the corresponding bits in the counting signal.
  • the first output terminals (Q) from the first level to the last level correspond to: Code ⁇ 0>, Code ⁇ 1>, Code ⁇ 2>, ..., Code ⁇ 7>; and the reset terminal (RST) of each level of trigger is used to receive a counting reset signal (represented by ECS_RST), which can realize the reset and clearing operation of the counting module 3021, and then restart the counting.
  • ECS_RST counting reset signal
  • the counting module 3021 may include a synchronous binary counter, the synchronous binary counter may include a plurality of counting submodules cascaded in sequence, and each counting submodule includes a trigger, and the clock end of each trigger is connected to the counting clock signal, wherein:
  • a plurality of counting submodules are configured to receive a counting clock signal, perform clock sampling processing through triggers contained in each of them, and output a counting signal; wherein the counting signal includes a plurality of bits, and there is a corresponding relationship between the plurality of counting submodules and the plurality of bits contained in the counting signal.
  • the synchronous binary counter may include a plurality of triggers cascaded in sequence, and the clock ends of the plurality of triggers are all connected to the counting clock signal.
  • several counting submodules may include:
  • the first counting submodule may include a first trigger, an input terminal (D) of the first trigger is connected to a second output terminal (/Q) of the first trigger, a clock terminal (CK) of the first trigger is used to receive a counting clock signal, and a first output terminal (Q) of the first trigger is used to output a first count, and the first count signal is the 0th bit in the count signal;
  • the second counting submodule may include a second trigger and a second XOR gate, wherein the first input terminal of the second XOR gate is connected to the first output terminal (Q) of the first trigger, the second input terminal of the second XOR gate is connected to the first output terminal (Q) of the second trigger, the output terminal of the second XOR gate is connected to the input terminal (D) of the second trigger, the clock terminal (CK) of the second trigger is used to receive the counting clock signal, and the first output terminal (Q) of the second trigger is used to output a second counting signal, and the second counting signal is the first bit in the counting signal;
  • the i-th counting submodule may include an i-th trigger, an i-th NAND gate, an i-th NOR gate and an i-th XOR gate, wherein the first input terminal of the i-th NAND gate is connected to the first output terminal (Q) of the i-1-th trigger, the second input terminal of the i-th NAND gate is connected to the first input terminal of the i-1-th XOR gate, the output terminal of the i-th NAND gate is connected to the input terminal of the i-th NAND gate, the output terminal of the i-th NAND gate is connected to the first input terminal of the i-th XOR gate, the second input terminal of the i-th XOR gate is connected to the first output terminal (Q) of the i-th trigger, the output terminal of the i-th XOR gate is connected to the input terminal (D) of the i-th trigger, the clock terminal (CK) of the i-th trigger is used to receive a counting clock signal
  • the counting module 3021 may include eight counting submodules cascaded in sequence, and each counting submodule includes at least one trigger.
  • the eight counting submodules are specifically: a first counting submodule a, a second counting submodule b, a third counting submodule c, a fourth counting submodule d, a fifth counting submodule e, a sixth counting submodule f, a seventh counting submodule g, and an eighth counting submodule h.
  • the first counting submodule a may include a first trigger a1, and the first counting signal output by the first counting submodule a is represented by Code ⁇ 0>, which corresponds to the 0th bit of the counting signal;
  • the second counting submodule b may include a second trigger b1 and a second XOR gate b2, and the second counting signal output by the second counting submodule b is represented by Code ⁇ 1>, which corresponds to the 1st bit of the counting signal;
  • the third counting submodule c may include a third trigger c1, a third NAND gate c2, a third NOR gate c3, and a third XOR gate c4, and the third counting signal output by the third counting submodule c is represented by Code ⁇ 2>.
  • the fourth counting submodule d may include a fourth trigger d1, a fourth NAND gate d2, a fourth NOT gate d3 and a fourth XOR gate d4.
  • the fourth counting signal output by the fourth counting submodule d is represented by Code ⁇ 3>, which corresponds to the third bit of the counting signal.
  • the eighth counting submodule h may include an eighth trigger h1, an eighth NAND gate h2, an eighth NOT gate h3 and an eighth XOR gate h4.
  • the eighth counting signal output by the eighth counting submodule h is represented by Code ⁇ 7>, which corresponds to the seventh bit of the counting signal.
  • the eight counting submodules all receive the counting clock signal, perform clock sampling processing through the triggers they contain, and output a counting signal including eight bits. Moreover, there is a corresponding relationship between the eight counting submodules and the eight bits included in the counting signal.
  • the first counting submodule is configured to output the 0th bit Code ⁇ 0> of the counting signal
  • the second counting submodule is configured to output the 1st bit Code ⁇ 1> of the counting signal
  • the third counting submodule is configured to output the 2nd bit Code ⁇ 2> of the counting signal
  • ... and the eighth counting submodule is configured to output the 7th bit Code ⁇ 7> of the counting signal.
  • the reset terminal (RST) of each stage of the trigger in the eight counting submodules is used to receive a counting reset signal (represented by ECS_RST), which can also implement the reset and clear operation of the counting module 3021, thereby restarting the counting.
  • ECS_RST counting reset signal
  • the counting module 3021 can be an asynchronous binary counter or a synchronous binary counter.
  • the circuit implementation of the former is simple, but the use of an asynchronous binary counter will cause a delay in the output of each level of the counter, especially when the refresh frequency is high and the number of counter levels is high, the delay problem is more serious; if the first level has changed again before the last level changes due to the delay problem of the counter, it will cause the counter to have an erroneous decoding situation, affecting the accuracy of the decoding output result, and thus causing the subsequent functions completed according to the decoding output result to be unable to execute normally; while the circuit implementation of the latter is relatively complex, but the use of a synchronous binary counter can align the output of each level, ensuring that the counter output has no erroneous decoding process, thereby reducing the impact of the counter delay on the first identification signal.
  • the embodiment of the present disclosure can use a synchronous binary counter to align the output of each level, thereby improving the impact of the counter delay on the first identification signal.
  • the counting and statistics module 302 may further include a latch module 3023, and the latch module 3023 is connected to the output end of the decoding module 3022, wherein:
  • the counting module 3021 is configured to receive a counting clock signal, count according to the counting clock signal, and generate a counting signal, where the counting signal is used to represent a counting value;
  • the decoding module 3022 is configured to receive the counting signal, decode the counting signal, and generate a target counting signal;
  • the latch module 3023 is configured to receive the target counting signal, and when the target counting signal is in a valid state, latch the target counting signal to generate a first identification signal in a valid state.
  • the target count signal when the count value meets the preset condition (that is, the count value reaches the preset value), the target count signal can be put in a valid state.
  • the count signal can be represented by Code ⁇ N:0>
  • the target count signal can be represented by ECS_CNT.
  • the level value of the ECS_CNT signal can also include a first value and a second value.
  • the first value is a logic 1 indicating a high level and the second value is a logic 0 indicating a low level
  • the level value of the ECS_CNT signal is a logic 1
  • a latch module 3023 is introduced.
  • a target counting signal can be generated, and the target counting signal can generate a first identification signal after passing through the latch module 3023.
  • a command signal for executing the ECS operation can be generated to ensure that all error checks and clearing are completed within 24 hours.
  • the counting and statistics module 302 may further include a latch module 3023 and an automatic pulse module 3024, and the input end of the automatic pulse module 3024 is connected to the output end of the decoding module 3022, and the output end of the automatic pulse module 3024 is connected to the set end (SET) of the latch module 3023, wherein:
  • the counting module 3021 is configured to receive a counting clock signal, count according to the counting clock signal, and generate a counting signal, where the counting signal is used to represent a counting value;
  • the decoding module 3022 is configured to receive the counting signal, decode the counting signal, and generate a target counting signal;
  • the automatic pulse module 3024 is configured to generate a set signal according to the target count signal; wherein when the target count signal is in a valid state, the set signal is in a valid state;
  • the latch module 3023 is configured to receive a set signal, and when the set signal is in a valid state, generate a first identification signal in a valid state according to the set signal.
  • the latch module described in the embodiment of the present disclosure may be an SR latch (SR Latch), and the SR latch may be composed of two two-input NAND gates.
  • the SR latch includes a set terminal, a reset terminal and an output terminal. Among them, the set terminal of the SR latch is used to receive a set signal, the reset terminal of the SR latch is used to receive a reset signal, and the output terminal of the SR latch is used to output a first identification signal.
  • the set signal can be in a valid state; if the target count signal is in an invalid state, the set signal can be in an invalid state. Only when the set signal is in a valid state can the first identification signal in a valid state be generated.
  • the set signal can be represented by SET, wherein the level value of the SET signal can also include a first value and a second value.
  • the first value is a logic 1 indicating a high level and the second value is a logic 0 indicating a low level
  • the level value of the SET signal is a logic 1
  • it is determined that the SET signal is in a valid state; otherwise, if the level value of the SET signal is a logic 0, it is determined that the SET signal is in an invalid state.
  • the automatic pulse module 3024 may include a second delay inversion module 221 and a first AND gate 222, wherein:
  • the second delay inversion module 221 is configured to delay and invert the target counting signal to obtain a target counting inversion signal
  • the first AND gate 222 is used to perform an AND logic operation on the target count inversion signal and the target count signal to obtain a set signal.
  • the input end of the second delayed inversion module 221 is used to receive the target counting signal
  • the first input end of the first AND gate 222 is connected to the output end of the decoding module 3022
  • the second input end of the first AND gate 222 is connected to the output end of the second delayed inversion module 221
  • the output end of the first AND gate 222 (as the output end of the automatic pulse module 3024) is connected to the set end (SET) of the latch module 3023.
  • the target count inverted signal can be generated by a signal generator, and the target count inverted signal generated here has a delayed and inverted relationship with the target count signal; or, the target count signal can be delayed and inverted by a second delayed inverting module to obtain a target count inverted signal, and then the target count inverted signal and the target count signal are subjected to an AND logic operation, so as to obtain a SET signal.
  • Auto Pulse is a target count inversion signal obtained after the target count signal is delayed and inverted, and then a smaller pulse signal is formed by performing AND logic with the target count signal, which is used as the SET signal of the latch module 3023; wherein, the SET can be used to generate the first identification signal.
  • the target count signal here needs to meet certain conditions (specifically, change from an invalid state to a valid state, such as from a low level state to a high level state), at which time Auto Pulse can form a smaller pulse signal, and the pulse width is equal to the delay time of the second delay inversion module.
  • the set signal is a high-level valid pulse signal. If the delay time of the delayed inverting module to the target count signal is longer, the pulse width of the set signal is wider; if the delay time of the delayed inverting module to the target count signal is shorter, the pulse width of the set signal is narrower. It can be seen that the pulse width of the set signal has a corresponding relationship with the delay time of the delayed inverting module to the target count signal.
  • the delay inversion module can be composed of a delay module and an inversion module connected in series, and the inversion module can be an inverter, a NOT gate, etc., so as to achieve delay and inversion effects on the target counting signal.
  • the automatic pulse module 3024 in addition to being composed of a delayed inverting module and an AND gate, can also be composed of a delayed inverting module and an NOR gate, wherein the input end of the delayed inverting module is used to receive the target count signal, the output end of the delayed inverting module is connected to the first input end of the NOR gate, the second input end of the NOR gate is used to receive the target count signal, and the output end of the NOR gate is used to output a set signal; or, the automatic pulse module 3024 can also be composed of a delayed inverting module, an OR gate and a NOR gate, wherein the input end of the delayed inverting module is used to receive the target count signal, the output end of the delayed inverting module is connected to the first input end of the OR gate, the second input end of the OR gate is used to receive the target count signal, the output end of the OR gate is connected to the input end of the NOR gate,
  • the counting control circuit 30 can also include a command control module 303, wherein:
  • the command control module 303 is configured to receive a first identification signal and a refresh command signal, and to generate a first command signal according to the refresh command signal when the first identification signal is in a valid state; or to generate a second command signal according to the refresh command signal when the first identification signal is in an invalid state.
  • the command control module 303 after receiving the first identification signal, if the first identification signal is in a valid state, a refresh command signal will be obtained at this time, and a first command signal will be generated according to the refresh command signal; if the first identification signal is in an invalid state, the refresh command signal will be directly output as a second command signal at this time.
  • the first command signal and the second command signal are different.
  • the first command signal is an ECS command signal for performing an ECS operation;
  • the second command signal is an internal refresh signal for performing a refresh operation.
  • the ECS command signal can be represented by ECS_CMD, and the internal refresh signal can be represented by REF_NEW.
  • the level value of the first identification signal may include a first value and a second value.
  • the first value may be a logic 1 indicating a high level
  • the second value may be a logic 0 indicating a low level
  • the first value may be a logic 0 indicating a low level
  • the second value may be a logic 1 indicating a high level
  • the level value of the first identification signal is logic 1
  • the ECS_CMD signal is generated according to the acquired refresh command signal; otherwise, if the level value of the first identification signal is logic 0, then it can be determined that the first identification signal is in an invalid state, and the REF_NEW signal can be output according to the acquired refresh command signal.
  • the counting and statistics module 302 is required to plan the interval time of the ECS operation in the automatic ECS operation mode. Specifically, when the count value meets the preset conditions, a valid first identification signal can be generated, which can be represented by ECS_Flag; the ECS_Flag signal will be transmitted to the command control module 303; in this module, if the ECS_Flag signal is in a valid state, then the next refresh command can be stolen to generate an ECS_CMD signal to perform the ECS operation, and the corresponding stolen refresh command will disappear; if the ECS_Flag signal is in an invalid state, then the refresh command will not be stolen and will be directly transmitted as a REF_NEW signal to perform a normal refresh operation.
  • ECS_Flag a valid first identification signal
  • the ECS_Flag signal will be transmitted to the command control module 303; in this module, if the ECS_Flag signal is in a valid state, then the next refresh command can be stolen to generate an ECS_CMD signal to perform the ECS operation
  • the command control module 303 may include a sampling module 3031, a delay module 3032 and a logic processing module 3033, wherein:
  • the sampling module 3031 is configured to receive a refresh command signal and an ECS identification signal, and perform sampling processing on the first identification signal according to the refresh command signal to obtain a sampling signal;
  • the delay module 3032 is configured to delay the refresh command signal to obtain a delayed refresh signal
  • the logic processing module 3033 is configured to perform logic operations on the sampling signal and the delayed refresh signal, and when the sampling signal is in a valid state, select to output an ECS command signal for performing an ECS operation; and when the sampling signal is in an invalid state, select to output an internal refresh signal for performing a refresh operation.
  • the sampling signal when the first identification signal is in a valid state, the sampling signal is in a valid state; when the first identification signal is in an invalid state, the sampling signal is in an invalid state.
  • the level value of the sampling signal may also include a first value and a second value. Exemplarily, when the first value is a logic 1 indicating a high level and the second value is a logic 0 indicating a low level, if the level value of the sampling signal is a logic 1, it is determined that the sampling signal is in a valid state; otherwise, if the level value of the sampling signal is a logic 0, it is determined that the sampling signal is in an invalid state.
  • the sampling module 3031 may be a D-type flip-flop.
  • the input terminal (D) of the D-type flip-flop is used to receive the ECS identification signal
  • the clock terminal (CK) of the D-type flip-flop is used to receive the refresh command signal
  • the output terminal (Q) of the D-type flip-flop is used to output the sampling signal.
  • the logic processing module 3033 includes a second logic module 231 and a third logic module 232, wherein:
  • the second logic module 231 is configured to perform a first logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in a valid state, and output an ECS command signal to perform an ECS operation;
  • the third logic module 232 is configured to perform a second logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in an invalid state, and output an internal refresh signal to perform a refresh operation.
  • whether to select the second logic module 231 to output the ECS_CMD signal in the valid state or the third logic module 232 to output the REF_NEW signal in the valid state can be determined according to the valid state of the sampling signal. Specifically, if the ECS_CMD signal is output, the refresh operation will not be performed, and the ECS operation will be performed to ensure that all error checks and clearing are completed within 24 hours; if the REF_NEW signal is output, the refresh operation is not affected, but the ECS operation will not be performed at this time.
  • the second logic module 231 includes a second NAND gate U6 and a fifth NAND gate U7, and a first input end of the second NAND gate U6 is connected to the output end of the sampling module 3031, a second input end of the second NAND gate U6 is connected to the output end of the delay module 3032, and an output end of the second NAND gate U6 is connected to an input end of the fifth NAND gate U7, wherein:
  • the second NAND gate U6 is used to perform a NAND logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in a valid state to obtain a first intermediate signal;
  • the fifth NOT gate U7 is used to perform a NOT logic operation on the first intermediate signal to obtain an ECS command signal.
  • the ECS_CMD signal when the sampling signal is in a valid state, can be generated by the second logic module 231, specifically, by stealing the next refresh command REF_AB, and the stolen refresh command will disappear.
  • the third logic module 232 may include a third NAND gate U8, a sixth NAND gate U9, and a seventh NAND gate U10, and the input end of the sixth NAND gate U9 is connected to the output end of the sampling module 3031, the first input end of the third NAND gate U8 is connected to the output end of the sixth NAND gate U9, the second input end of the third NAND gate U8 is connected to the output end of the delay module 3032, and the output end of the third NAND gate U8 is connected to the input end of the seventh NAND gate U10, wherein:
  • the sixth NOT gate U9 is used to perform a NOT logic operation on the sampling signal when the sampling signal is in an invalid state to obtain a second intermediate signal;
  • a third NAND gate U8 is used to perform a NAND logic operation on the second intermediate signal and the delayed refresh signal to obtain a third intermediate signal;
  • the seventh NOT gate U10 is used to perform a NOT logic operation on the third intermediate signal to obtain an internal refresh signal.
  • the internal refresh signal can be obtained through the third logic module 232, specifically, the refresh command REF_AB is directly output as the REF_NEW signal. At this time, the refresh command will not be stolen, and the executed refresh operation will not be affected.
  • the delay time of the delay module is greater than the sum of the delay times of the sampling module and the sixth NOT gate.
  • the delay time of the delay module 3032 needs to be greater than the sum of the delay times of the sampling module 3031 and the sixth NOT gate U9.
  • the delay module 3032 needs to make the delayed refresh signal later than the second intermediate signal after the sampling signal is inverted.
  • the ECS_Flag signal is in a valid state (i.e., logic 1)
  • the output of the sampling module 3031 is also logic 1
  • the output of the refresh command REF_AB can be blocked by the sixth NOT gate U9 (whose output is logic 0); however, there is a delay in both the sampling module 3031 and the sixth NOT gate U9.
  • the refresh command REF_AB If the refresh command REF_AB reaches the third NAND gate U8 earlier than the output of the sixth NOT gate U9 (the output when the level value of the ECS_Flag signal is logic 1), the refresh command REF_AB cannot be blocked at this time; therefore, the refresh command REF_AB needs to be delayed by the delay module 3032 so that the refresh command REF_AB reaches the third NAND gate U8 slightly later than the output of the sixth NOT gate U9.
  • the refresh command signal here may include at least one of the following: a refresh signal and a self-refresh signal.
  • the automatic ECS operation needs to plan and generate ECS_CMD signals in refresh and self-refresh to detect error information and perform internal read and write error detection and repair at the same time. Since it is necessary to count the number of refreshes and self-refreshes when generating automatic ECS operation commands with the help of refresh command signals, but there is no external clock during self-refresh; therefore, the first clock signal of the embodiment of the present disclosure can be a signal with an inherent frequency as a counting clock signal, which not only solves the technical problem in the related art that the ECS command signal cannot be generated with the help of self-refresh, but also solves the technical problem that the complete ECS operation cannot be completed within 24 hours if other refresh commands are sent.
  • the count control circuit 30 can further include a reset logic module 304, wherein:
  • the reset logic module 304 is configured to receive the first command signal and the external reset signal, perform logic operations on the first command signal and the external reset signal, and generate a count reset signal, which is used to be sent to the count statistics module 302 .
  • the reset logic module 304 when the first identification signal is in a valid state, it can be used to indicate the generation of the first command signal.
  • the reset logic module 304 after receiving the count reset signal, sends the count reset signal to the count statistics module 302, specifically, the reset end of each level of trigger in the internal count module 3021, so as to realize the reset and clear operation of the count module 3021.
  • the reset logic module 304 may include a first OR gate U11, wherein: the first input terminal of the first OR gate U11 is used to receive an external reset signal, the second input terminal of the first OR gate U11 is used to receive a first command signal, and the output terminal of the first OR gate U11 is used to output a counting reset signal.
  • the level value of the generated counting reset signal may include a first value and a second value.
  • the first value is a logic 1 indicating a high level
  • the second value is a logic 0 indicating a low level. If the level value of the counting reset signal is a logic 1, it is determined that the counting reset signal is in a valid state; otherwise, if the level value of the counting reset signal is a logic 0, it is determined that the counting reset signal is in an invalid state.
  • a count reset signal is sent to the count statistics module 302 so that the count statistics module 302 restarts counting and controls the ECS_Flag signal to be in an invalid state.
  • the ECS_Flag signal and the ECS_CLK signal are logically operated to obtain a CNT_CLK signal for counting.
  • the count statistics module 302 can be stopped to reduce power consumption; on the other hand, after the first command signal is generated, the first command signal and the external reset signal are logically operated to generate a count reset signal as the count statistics module 302, so that the count statistics module is reset; at the same time, after the first command signal is generated, the ECS_Flag signal is also in an invalid state.
  • a count clock signal can be generated by the logic control module 301 to start counting the count statistics module.
  • the counter reset operation needs to be completed before the time when the count clock signal is generated, so as to ensure that counting starts after the reset is completed, and there will be no technical problem of conflict caused by simultaneous counting and reset operations.
  • the ECS_Flag signal can be directly controlled to be in an invalid state according to the first command signal ECS_CMD; or, a counting reset signal can be generated according to the first command signal ECS_CMD to reset the counter to zero, and then the ECS_Flag signal can be in an invalid state according to the count value after clearing.
  • the counting control circuit 30 may further include a clock generating circuit 305, wherein:
  • the clock generating circuit 305 is configured to generate a first clock signal.
  • the clock generating circuit 305 may include an oscillating module 3051 and a frequency dividing module 3052, wherein:
  • An oscillation module 3051 is configured to output a second clock signal of a preset frequency
  • the frequency division module 3052 is configured to perform n-frequency division processing on the second clock signal to obtain the first clock signal.
  • the frequency of the first clock signal is one nth of the preset frequency, where n is an integer greater than zero.
  • the frequency of the first clock signal is one nth of the preset frequency, where n is an integer greater than zero.
  • the oscillation module 3051 may be an oscillator (OSC), such as a ring oscillator (Ring OSC), a crystal oscillator (Crystal OSC), etc.
  • OSC oscillator
  • the oscillation module 3051 is a Ring OSC, which is used to generate a second clock signal with a fixed frequency; then the second clock signal is divided by the frequency division module 3052 to obtain a first clock signal for counting.
  • the second clock signal can be represented by OSC_CLK
  • the first clock signal can be represented by ECS_CLK.
  • Ring OSC can be used to generate a fixed frequency OSC_CLK signal, assuming that the clock frequency is 1818kHz, the corresponding clock period is 550ns; then after the frequency division process, the output clock frequency is 227kHz ECS_CLK signal, and the corresponding clock period is 4.4us.
  • the counting control circuit 30 includes a clock generating circuit 305, the first clock signal required for counting can be generated, which not only solves the technical problem of no external clock during self-refresh, but also solves the problem that the count will not increase when the controller sends a refresh command in other ways, thereby causing the problem that the complete ECS operation cannot be completed within 24 hours.
  • the design of its internal circuit can be implemented according to the instruction decoding rules.
  • the decoding rules may be different, so the specific structure of the decoding module can also be adjusted accordingly, and the embodiments of the present disclosure do not specifically limit it.
  • the disclosed embodiment provides a counting control circuit, which includes a logic control module and a counting statistics module.
  • a counting clock signal for counting can be obtained by performing a logic operation in combination with the first identification signal, and a first identification signal can be generated according to the counting clock signal, so as to generate a first command signal for performing an ECS operation.
  • counting does not need to consider the limitation of the refresh command, which solves the technical problem that the ECS command signal can only be generated by counting with the help of REF_AB in the related art, and can ensure that a complete ECS operation is completed in 24 hours; in addition, there is a logical relationship between the counting clock signal and the first identification signal.
  • the counting statistics module is controlled to stop counting according to the state of the first identification signal, thereby achieving the purpose of reducing power consumption and ultimately improving the performance of the memory.
  • FIG15 shows a schematic diagram of the composition structure of another counting control circuit 30 provided by the embodiment of the present disclosure.
  • the counting control circuit 30 may include an asynchronous counter 1501, a decoding module 1502, a command control module 1503 and a reset logic module 1504, and the reset logic module 1504 includes a first OR gate U11.
  • the counting clock signal of the asynchronous counter 1501 is the refresh command REF_AB
  • the counting signal output by the asynchronous counter 1501 is The signal is represented by REF ⁇ 7:0>
  • the REF ⁇ 7:0> signal is used to characterize the count value; when the count value meets the preset condition, the REF ⁇ 7:0> signal at this time can be decoded by the decoding module 1502 to obtain the first identification signal in the valid state (represented by ECS_Flag); the ECS_Flag signal is sent to the command control module 1503, in which the refresh command REF_AB received at the next moment can be obtained, and the first command signal is generated according to the refresh command REF_AB; at this time, the external reset signal (represented by RESET) and the first command signal (represented by ECS_CMD) can also be input to the reset logic module 1504, and after the internal first OR gate U11 performs an OR logic operation, the count reset signal (represented by ECS_RST) can be output, and the ECS_RST signal
  • the ECS_Flag signal will also be in an invalid state.
  • the command control module 1503 if the ECS_Flag signal is in an invalid state, then the acquired refresh command REF_AB is directly output as a second command signal (ie, an internal refresh signal, represented by REF_NEW).
  • FIG16 shows a signal timing diagram of a counting control circuit provided by an embodiment of the present disclosure.
  • REF ⁇ 0>, REF ⁇ 1>, REF ⁇ 2>, REF ⁇ 3>, REF ⁇ 4>, REF ⁇ 5>, REF ⁇ 6>, and REF ⁇ 7> are eight bits included in the counting signal. Due to the inherent characteristics of the asynchronous counter, the counting output of the asynchronous counter will be delayed and misaligned. At this time, if the refresh frequency is too fast and the counter level is high, it will cause counting errors.
  • the binary number corresponding to the eight-bit count signal is 01111111; at the next moment, the count under normal circumstances is 10000000, but due to the excessively fast refresh frequency, REF ⁇ 0> has changed again before REF ⁇ 7> changes, that is, at time t2, the binary number corresponding to the eight-bit count signal is 10000001, that is, the asynchronous counter has a counting error, which causes the decoding module 1502 to have an error decoding situation, and thus cannot generate a valid ECS_Flag signal, and cannot generate an ECS_CMD signal according to the valid ECS_Flag signal, and cannot generate an ECS_RST signal through the reset logic module 1504, as shown by the dotted line in FIG16 .
  • the subsequent functions completed according to the decoding result cannot be executed normally.
  • the refresh command REF_AB is used as the clock signal of the counter. If the controller uses other methods such as REFsb to refresh, the counter will not increase, resulting in the problem that the entire ECS operation cannot be completed within 24 hours. On the other hand, the use of an asynchronous counter will cause an output delay at each level of the counter, which may cause an erroneous decoding process before the count changes at the last level, which may affect the next count. On the other hand, when the ECS_Flag signal is generated, the counter will continue to count the refresh command REF_AB until it starts counting again after ECS_RST, and there will be a conflicting time between the work of ECS_RST and the counter. Therefore, the counting control circuit can be further improved in the disclosed embodiment.
  • FIG17 shows a schematic diagram of the composition structure of another counting control circuit 30 provided in the embodiment of the present disclosure.
  • the counting control circuit 30 may include a synchronous counter 1701, a decoding module 1702, a command control module 1703, a reset logic module 1704 and a logic control module 1705, and the logic control module 1705 is composed of a first NOT gate U1, a second NOT gate U2, a third NOT gate U3, a first NAND gate U4 and a fourth NOT gate U5, and the reset logic module 1504 is composed of a first OR gate U11.
  • the counting clock signal of the synchronous counter 1701 is the CNT_CLK signal, which is no longer the refresh command REF_AB, but is generated by the logic control module 1705 after performing a logical operation on the ECS_CLK signal and the ECS_Flag signal; in this way, the counting clock signal is controlled by the ECS_Flag signal through a logical operation.
  • the ECS_Flag signal is at a high level, the counter can stop working, thereby reducing power consumption.
  • the synchronous counter 1701 counts according to the CNT_CLK signal, and the output counting signal can be represented by Code ⁇ 7:0> or REF ⁇ 7:0>; taking REF ⁇ 7:0> as an example, the REF ⁇ 7:0> signal is used here to represent the counting value; when the counting value meets the preset condition, the REF ⁇ 7:0> signal at this time can be decoded by the decoding module 1702 to obtain the ECS_Flag signal in a valid state; the ECS_Flag signal is sent to the command control module 1703, in which the refresh command REF_AB received at the next moment can be obtained, and the ECS_CMD signal is generated according to the refresh command REF_AB; at this time, the external reset signal RESET and the ECS_CMD signal can also be input into the reset logic module 1704, and after the internal first OR gate U11 performs an OR logic operation, the counting reset signal ECS_RST can be output, so that the synchronous counter 1701 restarts counting, and
  • FIG18 shows a signal timing diagram of another counting control circuit provided by an embodiment of the present disclosure.
  • REF ⁇ 0>, REF ⁇ 1>, REF ⁇ 2>, REF ⁇ 3>, REF ⁇ 4>, REF ⁇ 5>, REF ⁇ 6>, and REF ⁇ 7> are eight bits included in the counting signal. Due to the inherent characteristics of the synchronous counter, the counting output edge of the synchronous counter is aligned.
  • the decoding module When the count value meets the preset condition (i.e., the count reaches a specific value) at time t1, the decoding module generates a valid ECS_Flag signal; during the period when ECS_Flag is at a high level, the ECS_Flag signal will pass through the logic control counting clock signal, so that the counting clock signal is at a low level, thereby stopping the counter from counting at time t2; at the same time, when ECS_Flag is at a high level, a REF_AB command will be selected to generate an ECS_CMD command, and the selected REF_AB command will not be transmitted as a REF_NEW command. Then, according to the ECS_CMD command, a count reset signal ECS_RST can be generated.
  • the REF ⁇ 7:0> signal can be decoded and reset to 0, that is, REF ⁇ 7:0> is 00000000, and then the ECS_Flag signal can be reset to a low level.
  • the refresh command will not be stolen, but directly transmitted to the REF_NEW signal, and the refresh operation will not be affected.
  • the ECS_Flag signal can be directly controlled to be in an invalid state according to the ECS_CMD signal; or, the ECS_RST signal can be generated according to the ECS_CMD signal to reset the counter to zero, and then the ECS_Flag signal is in an invalid state according to the count value after clearing.
  • the OSC_CLK signal with a fixed frequency generated by the oscillator is used, and then the ECS_CLK signal is generated by the frequency divider as the clock signal of the synchronous counter. Then, when the characteristic value is counted, the output of the synchronous counter can generate the ECS_Flag signal through the decoder. Subsequently, the ECS_Flag signal will select the next refresh command REF_AB to generate the ECS command through the command control module, and the corresponding selected REF_AB will not be refreshed.
  • the command control module After that, the command control module generates a count reset signal to restart the counter, and the ECS_Flag signal is reset to a low level. During the period when the ECS_Flag signal is at a low level, the refresh command REF_AB will not be selected and will be directly transmitted to the REF_NEW signal for a normal refresh operation.
  • the disclosed embodiment provides a counting control circuit.
  • the specific implementation of the aforementioned embodiment is elaborated in detail through the aforementioned embodiment. It can be seen that based on the technical solution of the aforementioned embodiment, on the one hand, it can solve the problem that the controller sends other commands other than REF_AB, resulting in the inability to complete the complete ECS operation within 24 hours; on the other hand, the use of a synchronous counter can align the output of each level to ensure that there is no erroneous decoding process in the counter output, thereby reducing the impact of the counter delay on the ECS_Flag signal; on the other hand, the ECS_Flag signal is passed through some logic control counting clock signals, specifically when ECS_Flag is at a high level, the counter can be stopped, thereby reducing power consumption; on the other hand, after the ECS_CMD signal is generated, the counter can also be reset. Since the counter has stopped working, there will be no conflict between counting and resetting at the same time.
  • FIG19 a flow chart of a counting control method provided by an embodiment of the present disclosure is shown. As shown in FIG19, the flow chart may include:
  • S1901 Receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under the control of the first identification signal.
  • S1902 Counting is performed according to the counting clock signal to generate a first identification signal, where the first identification signal is used to indicate the generation of a command signal for executing a first operation; wherein when the count value meets a preset condition, the first identification signal is put into a valid state.
  • the method can be applied to the counting control circuit 30 or the semiconductor memory integrated with the counting control circuit 30 in any of the aforementioned embodiments.
  • the counting control circuit 30 can include a logic control module and a counting statistics module, and the output end of the logic control module is connected to the input end of the counting statistics module.
  • step S1901 is performed by the logic control module
  • step S1902 is performed by the counting statistics module.
  • the method may further include:
  • the counting statistics module stops counting.
  • the logic control module may include a first driving module and a first logic module. Accordingly, in some embodiments, for S1901, receiving the first clock signal and the first identification signal through the logic control module, and generating a counting clock signal according to the first clock signal under the control of the first identification signal may include:
  • the first clock signal is driven and processed by the first driving module to obtain a first intermediate signal
  • a first logic module performs a logic operation on the first intermediate signal and the first identification signal to obtain a counting clock signal.
  • the first driving module may include an even number of cascaded third NOT gates.
  • the first logic module may include a first delayed inversion module, a first NAND gate, and a second NOT gate. Accordingly, in some embodiments, performing a logic operation on the first intermediate signal and the first identification signal by the first logic module to obtain a counting clock signal may include:
  • a non-logic operation is performed on the third intermediate signal through the second non-gate to obtain a counting clock signal.
  • the first delayed inversion module includes an odd number of cascaded third NOT gates.
  • the counting and statistics module may include a counting module and a decoding module. Accordingly, in some embodiments, for S1902, receiving a counting clock signal through the counting and statistics module, counting according to the counting clock signal, and generating a first identification signal may include:
  • the counting module receives a counting clock signal, performs counting according to the counting clock signal, and generates a counting signal, wherein the counting signal is used to represent the counting value;
  • the counting signal is received through a decoding module, and the counting signal is decoded to generate a first identification signal; wherein, when the counting value meets a preset condition, the first identification signal is in a valid state.
  • the counting module may include a synchronous binary counter, the synchronous binary counter includes a plurality of counting submodules cascaded in sequence, and each counting submodule includes a trigger, and the clock end of each trigger is connected to the counting clock signal. Accordingly, in some embodiments, the method may also include:
  • the counting clock signal is received by a plurality of counting submodules, and clock sampling processing is performed through the triggers contained in each of them to output a counting signal; wherein the counting signal includes a plurality of bits, and there is a corresponding relationship between the plurality of counting submodules and the plurality of bits contained in the counting signal.
  • several counting submodules may include:
  • the first counting submodule includes a first trigger, an input terminal (D) of the first trigger is connected to a second output terminal (/Q) of the first trigger, a clock terminal (CK) of the first trigger is used to receive a counting clock signal, and a first output terminal (Q) of the first trigger is used to output a first counting signal, and the first counting signal is the 0th bit in the counting signal;
  • the second counting submodule includes a second trigger and a second XOR gate, wherein the first input terminal of the second XOR gate is connected to the first output terminal (Q) of the first trigger, the second input terminal of the second XOR gate is connected to the first output terminal (Q) of the second trigger, the output terminal of the second XOR gate is connected to the input terminal (D) of the second trigger, the clock terminal (CK) of the second trigger is used to receive a counting clock signal, and the first output terminal (Q) of the second trigger is used to output a second counting signal, and the second counting signal is the first bit in the counting signal;
  • the i-th counting submodule includes an i-th trigger, an i-th NAND gate, an i-th NOT gate and an i-th XOR gate, wherein the first input terminal of the i-th NAND gate is connected to the first output terminal (Q) of the i-1-th trigger, the second input terminal of the i-th NAND gate is connected to the first input terminal of the i-1-th XOR gate, the output terminal of the i-th NAND gate is connected to the input terminal of the i-th NAND gate, the output terminal of the i-th NOT gate is connected to the first input terminal of the i-th XOR gate, the second input terminal of the i-th XOR gate is connected to the first output terminal (Q) of the i-th trigger, the output terminal of the i-th XOR gate is connected to the input terminal (D) of the i-th trigger, the clock terminal (CK) of the i-th trigger is used to receive a counting clock signal, and the
  • the counting control circuit can also include a command control module. Accordingly, in some embodiments, the method can also include:
  • the command control module receives a first identification signal and a refresh command signal, and generates a first command signal according to the refresh command signal when the first identification signal is in a valid state; or generates a second command signal according to the refresh command signal when the first identification signal is in an invalid state.
  • the first command signal is an ECS command signal for executing an ECS operation
  • the second command signal is an internal refresh signal for executing a refresh operation.
  • the refresh command signal may include at least one of the following: a refresh signal and a self-refresh signal.
  • the method may also include:
  • a count reset signal is received through the count statistics module, the count is cleared according to the count reset signal, and the first identification signal is placed in an invalid state.
  • the counting control circuit can also include a reset logic module. Accordingly, in some embodiments, the method can also include:
  • the first command signal and the external reset signal are received through the reset logic module, and a logic operation is performed on the first command signal and the external reset signal to generate a counting reset signal, and the counting reset signal is used to send to the counting statistics module; wherein, when the first identification signal is in a valid state, it is used to indicate the generation of the first command signal, and the first command signal is used to characterize the command signal generated when the first operation is an ECS operation.
  • the reset logic module may include a first OR gate, wherein a first input terminal of the first OR gate is used to receive an external reset signal, a second input terminal of the OR gate is used to receive a first command signal, and an output terminal of the OR gate is used to output a count reset signal.
  • the counting control circuit can also include a clock generating circuit. Accordingly, in some embodiments, the method can also include: generating a first clock signal by the clock generating circuit.
  • the clock generating circuit may include an oscillation module and a frequency division module. Accordingly, in some embodiments, the method may further include:
  • the second clock signal is frequency-divided by n through the frequency-division module to obtain the first clock signal.
  • the frequency of the first clock signal is one nth of the preset frequency, where n is an integer greater than zero.
  • the disclosed embodiment provides a counting control method, which can not only solve the problem that the controller sends other commands other than REF_AB (when counting and generating ECS command signals using REF_AB commands) and thus the complete ECS operation cannot be completed within 24 hours, but also adopts a synchronous counter to align the output of each level, ensuring that there is no erroneous decoding process in the counter output, thereby reducing the impact of the counter delay on the ECS_Flag signal.
  • the counter is controlled to stop working through logical operations on the ECS_Flag signal, thereby reducing power consumption.
  • the counter can also be reset. Since the counter has stopped working, there will be no conflict between counting and resetting at the same time.
  • Fig. 20 a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present disclosure is shown.
  • the semiconductor memory 200 at least includes the counting control circuit 30 described in any one of the above embodiments.
  • the semiconductor memory 200 may include DRAM.
  • DRAM may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., without any limitation here.
  • the semiconductor memory 200 it mainly involves the relevant circuits of integrated circuit counter counting and command decoding, and in particular, in the DRAM chip, the oscillator outputs the OSC_CLK signal and after being processed by the frequency divider, can generate the ECS_CLK signal as the clock signal of the counter, the external input RESET is used as the initial value of the counter, and the counter is reset when the ECS command is generated.
  • the disclosed embodiment optimizes the original use of the refresh command REF_AB as the clock, and uses a synchronous counter instead of an asynchronous counter. The counter will not be affected by the change of the refresh command, and the use of synchronization instead of asynchronous avoids the counting error caused by the delay of the asynchronous counter output.
  • the decoding module is optimized so that the decoding module will not cause the ECS command to generate errors due to the change of the refresh command.
  • the counting control circuit is applied to the relevant circuits in the DRAM chip that generate ECS commands by counting, but it is not limited to this scope, and other circuits that generate commands by counting can adopt this design.
  • the embodiments of the present disclosure provide a counting control circuit, a counting control method and a semiconductor memory, wherein the counting control circuit includes a logic control module and a counting statistics module, and the output end of the logic control module is connected to the clock end of the counting statistics module, wherein the logic control module is configured to receive a first clock signal and a first identification signal, and under the control of the first identification signal, generate a counting clock signal according to the first clock signal; the counting statistics module is configured to receive the counting clock signal, count according to the counting clock signal, and generate a first identification signal, wherein the first identification signal is used to indicate the generation of a command signal for executing a first operation; wherein when the count value meets a preset condition, the first identification signal is put into a valid state.
  • the counting control circuit includes a logic control module and a counting statistics module, and the output end of the logic control module is connected to the clock end of the counting statistics module, wherein the logic control module is configured to receive a first clock signal and a first identification signal, and under the
  • the logic control module can obtain a counting clock signal for counting by performing a logical operation in combination with the first identification signal.
  • the first identification signal can be generated based on the counting clock signal to generate a command signal for executing the first operation.
  • the command generation for executing the ECS operation is not restricted by the refresh command, which solves the technical problem in the related technology that the ECS command signal can only be generated by counting with the help of REF_AB, and can ensure that the complete ECS operation is completed in 24 hours.

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Abstract

本公开实施例提供了一种计数控制电路、计数控制方法以及半导体存储器，该计数控制电路包括逻辑控制模块和计数统计模块，且逻辑控制模块的输出端与计数统计模块的时钟端连接；逻辑控制模块，配置为接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号；计数统计模块，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。

Description

计数控制电路、计数控制方法以及半导体存储器
相关申请的交叉引用
本公开基于申请号为202211230198.3、申请日为2022年10月08日、发明名称为“计数控制电路、计数控制方法以及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种计数控制电路、计数控制方法以及半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
在相关技术中，由于存储器的传输速度越来越快、行锤击(Row hammer)等一些原因，存储器中可能会发生错误，这就需要对存储器进行错误检查并及时纠正检查到的错误。以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，需要在至少每24小时对DRAM进行一次完整的错误检查与清除(Error Check and Scrub，ECS)。然而，对于相关技术中的ECS来说，有可能出现24小时内无法完成整个ECS操作的情况，甚至还有可能产生额外功耗，影响了存储器的性能。
发明内容
本公开实施例提供了一种计数控制电路、计数控制方法以及半导体存储器。
第一方面，本公开实施例提供了一种计数控制电路，该计数控制电路包括逻辑控制模块和计数统计模块，且逻辑控制模块的输出端与计数统计模块的时钟端连接，其中：
逻辑控制模块，配置为接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号；
计数统计模块，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
在一些实施例中，逻辑控制模块，配置为在第一标识信号处于无效状态时，根据第一时钟信号生成计数时钟信号，使计数统计模块对计数时钟信号进行计数；或者，在第一标识信号处于有效状态时，屏蔽第一时钟信号以阻止计数时钟信号的生成，使计数统计模块停止计数。
在一些实施例中，逻辑控制模块包括第一驱动模块和第一逻辑模块，其中：
第一驱动模块，配置为对第一时钟信号进行驱动处理，得到第一中间信号；
第一逻辑模块，配置为对第一中间信号和第一标识信号进行逻辑运算，得到计数时钟信号。
在一些实施例中，所述第一驱动模块包括偶数个级联的第一非门。
在一些实施例中，第一逻辑模块包括第一延迟反相模块、第一与非门和第二非门，其中：
第一延迟反相模块，配置为对第一标识信号进行延迟及反相处理，得到第二中间信号；
第一与非门，用于对第一中间信号和第二中间信号进行与非逻辑运算，得到第三中间信号；
第二非门，用于对第三中间信号进行非逻辑运算，得到计数时钟信号。
在一些实施例中，第一延迟反相模块包括奇数个级联的第三非门。
在一些实施例中，计数统计模块，还配置为接收计数复位信号，根据计数复位信号进行计数清零，并使第一标识信号处于无效状态。
在一些实施例中，计数控制电路还包括复位逻辑模块；其中，复位逻辑模块，配置为接收第一命令信号和外部复位信号，对第一命令信号和外部复位信号进行逻辑运算，生成计数复位信号，计数复位信号用于发送给计数统计模块；其中，第一标识信号处于有效状态时，用于指示生成第一命令信号。
在一些实施例中，复位逻辑模块包括第一或门；其中，第一或门的第一输入端用于接收外部复位信 号，第一或门的第二输入端用于接收第一命令信号，第一或门的输出端用于输出计数复位信号。
在一些实施例中，计数统计模块包括计数模块和译码模块，且计数模块的输出端与译码模块的输入端连接，其中：
计数模块，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
译码模块，配置为接收计数信号，对计数信号进行译码处理，生成第一标识信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
在一些实施例中，计数模块包括同步二进制计数器，同步二进制计数器包括若干个依次级联的计数子模块，且每个计数子模块均包括触发器，每个触发器的时钟端均与计数时钟信号连接，其中：
若干个计数子模块，配置为接收计数时钟信号，通过各自包含的触发器进行时钟采样处理，输出计数信号；
其中，计数信号包括若干个比特位，且若干个计数子模块与计数信号包含的若干个比特位之间具有对应关系。
在一些实施例中，在若干个计数子模块中：
第一个计数子模块包括第一触发器，第一触发器的输入端与第一触发器的第二输出端连接，第一触发器的时钟端用于接收计数时钟信号，且第一触发器的第一输出端用于输出第一计数信号，且第一计数信号是计数信号中的第0比特位；
第二个计数子模块包括第二触发器和第二异或门，第二异或门的第一输入端与第一触发器的第一输出端连接，第二异或门的第二输入端与第二触发器的第一输出端连接，第二异或门的输出端与第二触发器的输入端连接，第二触发器的时钟端用于接收计数时钟信号，且第二触发器的第一输出端用于输出第二计数信号，且第二计数信号是计数信号中的第1比特位；
第i个计数子模块包括第i触发器、第i与非门、第i非门和第i异或门，第i与非门的第一输入端与第i-1触发器的第一输出端连接，第i与非门的第二输入端与第i-1异或门的第一输入端连接，第i与非门的输出端与第i非门的输入端连接，第i非门的输出端与第i异或门的第一输入端连接，第i异或门的第二输入端与第i触发器的第一输出端连接，第i异或门的输出端与第i触发器的输入端连接，第i触发器的时钟端用于接收计数时钟信号，且第i触发器的第一输出端用于输出第i计数信号，且第i计数信号是计数信号中的第i-1比特位；其中，i为大于或等于3且小于或等于M的整数，M为正整数。
在一些实施例中，计数控制电路还包括命令控制模块，其中：
命令控制模块，配置为接收第一标识信号和刷新命令信号，以及在第一标识信号处于有效状态时，根据刷新命令信号生成第一命令信号；或者，在第一标识信号处于无效状态时，根据刷新命令信号生成第二命令信号。
在一些实施例中，第一命令信号为错误检查与清除ECS命令信号，用于执行ECS操作；第二命令信号为内部刷新信号，用于执行刷新操作。
在一些实施例中，刷新命令信号包括下述至少之一：刷新信号和自刷新信号。
在一些实施例中，计数控制电路还包括时钟产生电路，其中：
时钟产生电路，用于产生第一时钟信号。
在一些实施例中，时钟产生电路包括振荡模块和分频模块，其中：
振荡模块，配置为输出预设频率的第二时钟信号；
分频模块，配置为对第二时钟信号进行n分频处理，得到第一时钟信号；
其中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
第二方面，本公开实施例提供了一种计数控制方法，该方法包括：
接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号；
根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
第三方面，本公开实施例提供了一种半导体存储器，该半导体存储器包括如第一方面所述的计数控制电路。
在一些实施例中，半导体存储器包括动态随机存取存储器DRAM。
本公开实施例提供了一种计数控制电路、计数控制方法以及半导体存储器，该计数控制电路包括逻辑控制模块和计数统计模块，且逻辑控制模块的输出端与计数统计模块的时钟端连接，其中，逻辑控制模块，配置为接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号；计数统计模块，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。这样，逻辑控制模块在接收第一时钟信号之后，结合第一标识信号进行逻辑运算可以得到用于计数的计数时钟信号，根据该计数时钟信号可以产生第一标识信号，以此产生执行第一 操作的命令信号，这时候执行ECS操作的命令产生不受刷新命令的限制，解决了相关技术中只能借助REF_AB进行计数来产生ECS命令信号的技术问题，能够确保24小时完成完整的ECS操作；另外，该计数时钟信号与第一标识信号之间具有逻辑关系，根据第一标识信号的状态可以控制计数统计模块是否停止计数，从而还能够达到减小功耗的目的，最终提升存储器的性能。
附图说明
图1为一种ECS模式的信号时序示意图；
图2为一种产生ECS命令的框架示意图；
图3为本公开实施例提供的一种计数控制电路的组成结构示意图一；
图4为本公开实施例提供的一种计数控制电路的组成结构示意图二；
图5为本公开实施例提供的一种计数控制电路的组成结构示意图三；
图6为本公开实施例提供的一种计数控制电路的组成结构示意图四；
图7为本公开实施例提供的一种异步二进制计数器的组成结构示意图；
图8为本公开实施例提供的一种同步二进制计数器的组成结构示意图；
图9为本公开实施例提供的一种计数控制电路的组成结构示意图五；
图10为本公开实施例提供的一种计数控制电路的组成结构示意图六；
图11为本公开实施例提供的一种计数控制电路的组成结构示意图七；
图12为本公开实施例提供的一种计数控制电路的组成结构示意图八；
图13为本公开实施例提供的一种计数控制电路的组成结构示意图九；
图14为本公开实施例提供的一种计数控制电路的组成结构示意图十；
图15为本公开实施例提供的一种计数控制电路的组成结构示意图十一；
图16为本公开实施例提供的一种计数控制电路的信号时序示意图；
图17为本公开实施例提供的一种计数控制电路的组成结构示意图十二；
图18为本公开实施例提供的另一种计数控制电路的信号时序示意图；
图19为本公开实施例提供的一种计数控制方法的流程示意图；
图20为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
对本公开实施例进行进一步详细说明之前，先对本公开实施例中涉及的名词和术语进行说明，本公开实施例中涉及的名词和术语适用于如下的解释：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)；
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)；
双倍速率(Double Data Rate，DDR)；
第5代DDR标准(DDR5 Specification，DDR5SPEC)；
多用途命令(Multi-Purpose Command，MPC)；
错误检查与清除(Error Check and Scrub，ECS)。
以DDR5 DRAM为例，ECS模式可以分为自动ECS操作模式和手动ECS操作模式。其中，在手动ECS操作模式下，利用内存控制器(Controller)发送的MPC命令来产生ECS命令信号；在自动ECS操作模式下，可以利用刷新或自刷新来产生ECS命令信号。虽然特定的MPC命令可以产生ECS操作，但在自动ECS操作模式下没有MPC命令，因此需要借助刷新和自刷新来产生自动ECS操作的ECS命令。具体地，本公开实施例需要至少在24小时内对DRAM进行一次完整的ECS操作，因此需要规划好ECS操作的时间。为了实现对DRAM进行完整的错误检查与清除，这里需要对DRAM中所有行(Row)、列(Column，Col)、存储块(Bank，BA)、存储组(Bank Group，BG)均进行错误检查，所以在24小时 内需要执行多次ECS操作，平均的间隔时间为tECSint，以16吉字节(Gigabyte，Gb)内存为例大约是644微秒(microsecond，us)。其中，该间隔时间是24小时内完成整个16Gb内存ECS操作的最小时间，具体计算方式为24小时×60分钟/小时×60秒/分钟/2^(3+2+16+6)。其中，2^3为BG个数，2^2为每个BG中Bank个数，2^16为一个Bank内Row的数目，2^6为一个Row上需要访问(Access)所有Col的操作次数。图1示出了一种ECS模式(ECS Mode)的信号时序示意图。如图1所示，CK_t与CK_c表示一对互补的时钟信号，CA[13:0]表示命令地址信号，CMD表示命令信号，CS0表示低电平有效的片选信号，valid表示有效命令地址，DES表示无效命令。其中，在t0时刻，这时候的命令信号为MPC命令，对应的命令地址为OP00001100，此时将由常规模式(Normal Mode)切换到进入ECS模式(ECS Mode Entry)。在经过一段延迟时间(如tMPC Delay)之后，然后处于ECS模式。对于ECS模式而言，在执行一次ECS操作时，DRAM内部自产生命令信号的顺序为激活信号(Active，ACT)、读信号(Read，RD)、写信号(Write，WR)和预充电信号(Precharge，PRE)，tRCD表示ACT到RD之间的间隔时间，WL表示RD到WR之间的间隔时间，tWR表示WR到PRE之间的间隔时间。也就是说，DDR5SPEC规定每次执行ECS操作的最小时间为tECSc，在此时间段内，一个ECS操作需要对某个BG中的某个Bank中的某个Row对应的某个Col进行内部读写检错修改，因此需要自产生内部命令ACT-RD-WR-PRE，每相邻两个命令之间满足时序tRCD、WL、tWR，从而使得执行一次ECS命令的内部操作能够在tECSc内完成。示例性地，表1示出了在16Gb内存下平均ECS间隔的时间规定。
表1
Figure PCTCN2022126387-appb-000001
可以理解地，在平均ECS间隔的时间段内，需要计数刷新命令的个数，当计数到预设数值时会偷取下一个刷新命令用来做自动ECS操作的ECS命令。其中，刷新命令的平均间隔时间为tREFI，示例性地，DDR5中tREFI的取值可以为3.9us，具体参见表2。假定tECSint的取值为644us，tREFI的取值可以为3.9us，那么所需刷新命令的个数为644/3.9＝165；因此，需要计数至少165个刷新命令才能够产生ECS命令。
表2
Figure PCTCN2022126387-appb-000002
进一步地，图2示出了一种产生ECS命令的框架示意图。如图2所示，该框架可以包括计数统计模块201和命令控制模块202。其中，对于计数统计模块201而言，通过对刷新命令REF_AB的个数进行计数，输出计数信号CNT<N:0>；当计数达到预设数值(如165)时，可以产生ECS标识信号ECS_Flag；最后在ECS_Flag信号处于有效状态时，命令控制模块202会偷取下一个刷新命令REF_AB来产生ECS命令信号ECS_CMD。
基于图2所示的框架，在自动ECS操作模式下需要计数刷新命令的个数，然后偷取一个刷新命令来产生ECS命令。在这里，刷新命令REF_AB既可以作为计数模块第一级的时钟，也可以作为命令控制模块的输入。以计数设定的预设数值为165为例，当计数到预设数值之后，译码模块通过译码产生ECS_Flag信号，然后经过命令控制模块偷取下一个刷新命令用来做ECS命令，同时对应被偷取的刷新命令会消失，其他的刷新命令不受影响。当计数完成时，在ECS命令产生后计数模块会重置，开始重新计数。
然而，在相关技术中，采用刷新命令REF_AB作为计数模块的时钟信号，如果控制器利用REFsb等其他方式来刷新，此时计数不会增加，并且导致指示执行ECS操作的ECS命令滞后，从而可能出现24小时内无法完成整个ECS操作的情况；另外，在产生ECS_Flag信号时，目前的计数模块仍然可能存在持续计数REF_AB，直到接收到计数复位信号ECS_RST后才会重新计数，导致ECS_RST和计数模块的工作会出现冲突的时间，同时还会产生额外功耗。
基于此，本公开实施例提供了一种计数控制电路，该计数控制电路包括逻辑控制模块和计数统计模块。逻辑控制模块在接收第一时钟信号之后，结合第一标识信号进行逻辑运算可以得到用于计数的计数时钟信号，根据该计数时钟信号可以产生第一标识信号，以此产生执行第一操作的命令信号，这时候执行ECS操作的命令产生不受刷新命令的限制，解决了相关技术中只能借助REF_AB进行计数来产生ECS命令信号的技术问题，能够确保24小时完成完整的ECS操作；另外，该计数时钟信号与第一标识信号之间具有逻辑关系，根据第一标识信号的状态可以控制计数统计模块是否停止计数，从而还能够达到减小功耗的目的，最终提升存储器的性能。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图3，其示出了本公开实施例提供的一种计数控制电路30的组成结构示意图。如图3所示，该计数控制电路30可以包括逻辑控制模块301和计数统计模块302，且逻辑控制模 块301的输出端与计数统计模块302的时钟端连接，其中：
逻辑控制模块301，配置为接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号；
计数统计模块302，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
需要说明的是，在本公开实施例中，该计数控制电路30可以应用于执行ECS操作的相关电路，具体可以是适用于所有自动ECS操作的计数电路，但是并不局限于此，这里也可以适用于其他计数产生命令信号的电路。
以DDR5 DRAM为例，由于DRAM要求至少在24小时内进行一次完整的错误检查与清除，那么通过计数统计模块302来规划命令信号产生的间隔时间，以确保24小时内能够对存储器完成所有的错误检查与清除。也就是说，计数统计模块302对接收到的计数时钟信号进行计数，并且在计数值满足预设条件时，使得第一标识信号处于有效状态，以便产生用于执行第一操作的命令信号；如此，当第一操作是ECS操作时，根据该计数控制电路30所产生的命令信号，能够确保24小时完成所有的错误检查与清除。
还需要说明的是，在本公开实施例中，由于计数时钟信号是由第一时钟信号和第一标识信号进行逻辑运算生成的，而这里的第一时钟信号可以是采用固定频率的时钟信号，此时计数无需考虑刷新命令的限制，解决了相关技术中(利用REF_AB命令进行计数产生ECS命令信号时)控制器发送非REF_AB的其他刷新命令而导致24小时内无法完成完整ECS操作的问题；另外，由于计数时钟信号与第一标识信号之间具有逻辑关系，在使用计数时钟信号进行计数时，根据第一标识信号的状态来控制计数统计模块302是否停止计数，从而还能够达到减小功耗的目的，最终提升存储器的性能。
在一些实施例中，逻辑控制模块301，配置为在第一标识信号处于无效状态时，根据第一时钟信号生成计数时钟信号，使计数统计模块302对计数时钟信号进行计数；或者，在第一标识信号处于有效状态时，屏蔽第一时钟信号以阻止计数时钟信号的生成，使计数统计模块302停止计数。
也就是说，对于逻辑控制模块301而言，计数时钟信号与第一标识信号之间具有逻辑关系。其中，如果第一标识信号处于无效状态，这时候会根据第一时钟信号来生成计数时钟信号，以便根据计数时钟信号控制计数统计模块302进行计数；否则，如果第一标识信号处于有效状态，这时候会阻止计数时钟信号的生成，使得计数统计模块302停止工作，从而达到减小功耗的目的。
进一步地，在一些实施例中，对于逻辑控制模块301而言，在图3所示的计数控制电路30的基础上，参见图4，该逻辑控制模块301可以包括第一驱动模块3011和第一逻辑模块3012，其中：
第一驱动模块3011，配置为对第一时钟信号进行驱动处理，得到第一中间信号；
第一逻辑模块3012，配置为对第一中间信号和第一标识信号进行逻辑运算，得到计数时钟信号。
在这里，第一时钟信号可以用ECS_CLK表示，第一标识信号可以用ECS_Flag表示，计数时钟信号可以用CNT_CLK表示。
需要说明的是，在本公开实施例中，第一驱动模块3011可以包括偶数个级联的第一非门，用于增强第一时钟信号的驱动能力；但是由于第一非门自身存在的延迟，同时还会对第一时钟信号起到一定的延迟作用。示例性地，第一驱动模块3011所包括的第一非门数量可以是2个、4个、6个、8个等，这里对此不作具体限定。
在一些实施例中，在图4所示的计数控制电路30的基础上，参见图5，第一驱动模块3011可以包括两个第一非门(U1和U2)。
需要说明的是，在本公开实施例中，对于这两个第一非门而言，U1的输入端(作为第一驱动模块3011的输入端)用于接收第一时钟信号，U1的输出端与U2的输入端连接，U2的输出端(作为第一驱动模块3011的输出端)用于输出第一中间信号。
还需要说明的是，在本公开实施例中，第一驱动模块3011可以是由两个非门组成，也可以是由1个或多个缓冲器(Buffer)组成等等。在这里，对于第一驱动模块3011而言，只要能够对第一时钟信号起到驱动作用即可，其内部结构并不作具体限定。
进一步地，在一些实施例中，对于第一逻辑模块3012而言，参见图5，第一逻辑模块3012可以包括第一延迟反相模块U3、第一与非门U4和第二非门U5，其中：
第一延迟反相模块U3，配置为对第一标识信号进行延迟及反相处理，得到第二中间信号；
第一与非门U4，用于对第一中间信号和第二中间信号进行与非逻辑运算，得到第三中间信号；
第二非门U5，用于对第三中间信号进行非逻辑运算，得到计数时钟信号。
需要说明的是，在本公开实施例中，第一延迟反相模块U3的输入端用于接收第一标识信号，第一延迟反相模块U3的输出端与第一与非门U4的第一输入端连接；第一驱动模块3011的输入端用于接收第一时钟信号，第一驱动模块3011的输出端与第一与非门U4的第二输入端连接，第一与非门U4的输出端与第二非门U5的输入端连接，第二非门U5的输出端用于输出计数时钟信号。
还需要说明的是，在本公开实施例中，第一延迟反相模块U3可以包括奇数个级联的第三非门，用于 对第一标识信号起到延迟及反相的作用。示例性地，第一延迟反相模块U3所包括的第三非门数量可以是1个、3个、5个、7个等，这里对此也不作任何限定。具体如图5所示，第一延迟反相模块U3仅包括一个第三非门，此时通过第三非门能够对第一标识信号进行延迟及反相处理。
还需要说明的是，在本公开实施例中，第一逻辑模块3012可以实现根据第一标识信号来生成计数时钟信号的功能。其中，第一逻辑模块3012可以是由两个非门和一个与非门的逻辑器件组合，也可以是由一个非门和一个与门的逻辑器件组合等等。在这里，对于第一逻辑模块3012而言，只要能够实现该第一逻辑模块3012的相同功能，其内部结构并不作具体限定。
可以理解地，对于计数统计模块302而言，其不仅能够对计数时钟信号进行计数；而且还可以进行计数清零，以便重新计数。因此，在一些实施例中，计数统计模块302，还配置为接收计数复位信号，根据计数复位信号进行计数清零，并使第一标识信号处于无效状态。
需要说明的是，在本公开实施例中，重新计数开始之前，需要完成计数统计模块302的复位，即计数统计模块302需先接收到计数复位信号。在这里，通过第一延迟反相模块U3，可以调整生成计数复位信号的时刻与生成计数时钟信号的时刻之间的时间间隔。根据该时间间隔，能够保证计数统计模块302复位完成后，再根据计数时钟信号开始重新计数。
还需要说明的是，对于第一标识信号的无效状态，可以是计数统计模块302接收到计数复位信号之后，根据计数复位信号进行计数清零，并根据清零后的计数值使得第一标识信号复位为无效状态。或者，对于第一标识信号的无效状态，也可以是在根据第一标识信号用于指示生成执行ECS操作的第一命令信号之后，同时也会使得第一标识信号处于无效状态。
如此，在本公开实施例中，第一标识信号可以是处于有效状态，也可以是处于无效状态。其中，计数统计模块302会在每间隔一段时间(即计数值达到预设条件)后产生处于有效状态的第一标识信号，用于指示生成执行ECS操作的第一命令信号，同时在生成第一命令信号之后会使得第一标识信号处于无效状态；而在第一标识信号处于无效状态时，通过逻辑控制模块301能够生成计数时钟信号，这时候根据计数时钟信号可以使得计数统计模块302进行计数。
在一些实施例中，对于计数统计模块302而言，在图4所示的计数控制电路30的基础上，参见图6，该计数统计模块302可以包括计数模块3021和译码模块3022，且计数模块3021的输出端与译码模块3022的输入端连接，其中：
计数模块3021，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
译码模块3022，配置为接收计数信号，对计数信号进行译码处理，生成第一标识信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
需要说明的是，在图6中，计数信号可以用N+1位二进制数据Code<N:0>表示。其中，计数信号并不是仅为一个信号，其代表一组信号。在这里，计数信号可以包括N+1个比特位，每一个比特位各自对应一个信号，具体可以为：Code<0>、Code<1>、Code<2>、…、Code<N>；其中，N的取值与预设条件的计数值具有关联关系。示例性地，假设预设条件的计数值为146，对应的二进制数为10001010，那么至少需要8位二进制的计数信号对计数时钟信号进行计数；假设预设条件的计数值为60，对应的二进制数为111100，那么至少需要6位二进制的计数信号对计数时钟信号进行计数。
还需要说明的是，计数模块3021可以由依次级联的若干个触发器组成，触发器的数量等于计数信号的比特位数(N+1)。示例性地，假定计数信号为8位比特的二进制信号，那么计数模块3021中的触发器数量为8个。以16Gb的内存配置为例，为了满足24小时内对DRAM完成一次完整的错误检查与清除，ECS操作的时间间隔为644us，计数时钟信号的周期为4.4us，那么需要计数大约644/4.4＝146次时表示一次计数完成。也就是说，根据计数时钟信号进行计数，可以得到用于表征计数值的计数信号Code<7:0>；然后通过对计数信号Code<7:0>的译码处理，可以得到译码输出结果(即第一标识信号)。其中，只有在计数信号Code<7:0>满足10010010，即计数值达到146(这里，2^1+2^4+2^7＝146)时，此时可以译码生成处于有效状态的第一标识信号。也就是说，计数信号可以包括若干个比特位，而且比特位数量与触发器数量之间具有对应关系；这若干个比特位可以用来表征计数值，且触发器数量能够决定计数值的上限值。示例性地，若这里的触发器数量为8个，则计数信号可以包括8个比特位，如Code<7:0>；此时计数信号Code<7:0>对应的计数值范围是00000000～11111111。
进一步地，对于计数模块3021而言，在一种可能的实施例中，计数模块3021可以包括异步二进制计数器，其中：
异步二进制计数器包括若干个依次级联的触发器，每一级触发器的输入端(D)与其自身的第二输出端(Q非)连接，且每一级触发器的第二输出端(Q非)与下一级触发器的时钟端(CK)连接，第一级触发器的时钟端(CK)与第一时钟信号连接。
在本公开实施例中，以图7所示的异步二进制计数器为例，该计数模块3021包括八个触发器。在这里，触发器可以为D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)，D型触发器是一个具有记忆功能的、具有两个稳定状态的信息存储器件，是构成多种时序电路的最基本逻辑单元，也是数字逻辑电路 中一种重要的单元电路。D型触发器具有两个稳定状态，即“0”和“1”，在该触发器的时钟端所接收的信号作用下，可以从一个稳定状态翻转到另一个稳定状态。
在本公开实施例中，触发器可以包括输入端(D)、时钟端(CK)、第一输出端(Q)和第二输出端(Q非，用/Q表示)，甚至也可以包括复位端(RST)。在这里，每一级触发器的第一输出端(Q)用于依次输出计数信号中的对应比特位，如图7所示，从第一级到最后一级的第一输出端(Q)依次对应：Code<0>、Code<1>、Code<2>、…、Code<7>；而每一级触发器的复位端(RST)用于接收计数复位信号(用ECS_RST表示)，可以实现计数模块3021的复位清零操作，进而重新开始计数。
进一步地，对于计数模块3021而言，在另一种可能的实施例中，计数模块3021可以包括同步二进制计数器，同步二进制计数器可以包括若干个依次级联的计数子模块，且每个计数子模块均包括触发器，每个触发器的时钟端均与计数时钟信号连接，其中：
若干个计数子模块，配置为接收计数时钟信号，通过各自包含的触发器进行时钟采样处理，输出计数信号；其中，计数信号包括若干个比特位，且若干个计数子模块与计数信号包含的若干个比特位之间具有对应关系。
简单来说，在本公开实施例中，同步二进制计数器可以包括若干个依次级联的触发器，且这若干个触发器的时钟端均与计数时钟信号连接。
进一步地，在一些实施例中，对于同步二进制计数器而言，在若干个计数子模块中，可以包括：
第一个计数子模块可以包括第一触发器，第一触发器的输入端(D)与第一触发器的第二输出端(/Q)连接，第一触发器的时钟端(CK)用于接收计数时钟信号，且第一触发器的第一输出端(Q)用于输出第一计数，且第一计数信号是计数信号中的第0比特位；
第二个计数子模块可以包括第二触发器和第二异或门，第二异或门的第一输入端与第一触发器的第一输出端(Q)连接，第二异或门的第二输入端与第二触发器的第一输出端(Q)连接，第二异或门的输出端与第二触发器的输入端(D)连接，第二触发器的时钟端(CK)用于接收计数时钟信号，且第二触发器的第一输出端(Q)用于输出第二计数信号，且第二计数信号是计数信号中的第1比特位；
第i个计数子模块可以包括第i触发器、第i与非门、第i非门和第i异或门，第i与非门的第一输入端与第i-1触发器的第一输出端(Q)连接，第i与非门的第二输入端与第i-1异或门的第一输入端连接，第i与非门的输出端与第i非门的输入端连接，第i非门的输出端与第i异或门的第一输入端连接，第i异或门的第二输入端与第i触发器的第一输出端(Q)连接，第i异或门的输出端与第i触发器的输入端(D)连接，第i触发器的时钟端(CK)用于接收计数时钟信号，且第i触发器的第一输出端(Q)用于输出第i计数信号，且第i计数信号是计数信号中的第i-1比特位；其中，i为大于或等于3且小于或等于M的整数，M为正整数。
在本公开实施例中，以图8所示的同步二进制计数器为例，该计数模块3021可以包括八个依次级联的计数子模块，且每个计数子模块均至少包括一个触发器。其中，这八个计数子模块具体为：第一个计数子模块a、第二个计数子模块b、第三个计数子模块c、第四个计数子模块d、第五个计数子模块e、第六个计数子模块f、第七个计数子模块g、第八个计数子模块h。具体地，第一个计数子模块a可以包括第一触发器a1，第一个计数子模块a输出的第一计数信号用Code<0>表示，其对应为计数信号的第0个比特位；第二个计数子模块b可以包括第二触发器b1和第二异或门b2，第二个计数子模块b输出的第二计数信号用Code<1>表示，其对应为计数信号的第1个比特位；第三个计数子模块c可以包括第三触发器c1、第三与非门c2、第三非门c3和第三异或门c4，第三个计数子模块c输出的第三计数信号用Code<2>表示，其对应为计数信号的第2个比特位；第四个计数子模块d可以包括第四触发器d1、第四与非门d2、第四非门d3和第四异或门d4，第四个计数子模块d输出的第四计数信号用Code<3>表示，其对应为计数信号的第3个比特位；以此类推，对于第八个计数子模块h而言，第八个计数子模块h可以包括第八触发器h1、第八与非门h2、第八非门h3和第八异或门h4，第八个计数子模块h输出的第八计数信号用Code<7>表示，其对应为计数信号的第7个比特位。这样，这八个计数子模块均接收计数时钟信号，通过各自包含的触发器进行时钟采样处理，输出包括八个比特位的计数信号，而且这八个计数子模块与计数信号包含的八个比特位之间具有对应关系。示例性地，第一个计数子模块配置为输出计数信号的第0个比特位Code<0>，第二个计数子模块配置为输出计数信号的第1个比特位Code<1>，第三个计数子模块配置为输出计数信号的第2个比特位Code<2>，…，第八个计数子模块配置为输出计数信号的第7个比特位Code<7>。
另外，在图8所示的同步二进制计数器中，这八个计数子模块中每一级触发器的复位端(RST)用于接收计数复位信号(用ECS_RST表示)，也可以实现计数模块3021的复位清零操作，进而重新开始计数。
综上可知，对于计数模块3021而言，其可以是异步二进制计数器，也可以是同步二进制计数器。其中，前者的电路实现简单，但是采用异步二进制计数器会导致计数器每一级输出均存在延迟，尤其是在刷新频率较高且计数器级数较高时，该延迟问题更为严重；如果因计数器的延迟问题而使最后一级变化之前第一级就已经再次改变，从而会导致计数器出现错误译码情况，影响译码输出结果的准确性，进而造成根据译码输出结果完成的后续功能无法正常执行；而后者的电路实现相对复杂，但是采用同步二进 制计数器可以使每一级的输出对齐，保证计数器输出没有错误的译码过程，从而减少计数器延迟对第一标识信号产生的影响。在这里，为了保证计数器输出没有错误的译码过程，避免影响下一次计数，本公开实施例可以采用同步二进制计数器，使得每一级输出对齐，进而改善计数器延迟对第一标识信号产生的影响。
进一步地，在一些实施例中，对于计数统计模块302而言，在图6所示计数控制电路30的基础上，参见图9，该计数统计模块302还可以包括锁存模块3023，且锁存模块3023与译码模块3022的输出端连接，其中：
计数模块3021，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
译码模块3022，配置为接收计数信号，对计数信号进行译码处理，生成目标计数信号；
锁存模块3023，配置为接收目标计数信号，以及在目标计数信号处于有效状态时，对目标计数信号进行锁存处理，生成处于有效状态的第一标识信号。
需要说明的是，在本公开实施例中，在计数值满足预设条件(即计数值达到预设数值)时，可以使目标计数信号处于有效状态。另外，在图9中，计数信号可以用Code<N:0>表示，目标计数信号可以用ECS_CNT表示。其中，ECS_CNT信号的电平值也可以包括第一值和第二值。示例性地，在第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0的情况下，若ECS_CNT信号的电平值为逻辑1，则确定ECS_CNT信号处于有效状态；否则，若ECS_CNT信号的电平值为逻辑0，则确定ECS_CNT信号处于无效状态。
还需要说明的是，在本公开实施例中，这里引入了锁存模块3023。其中，当计数完成时可以产生目标计数信号，而目标计数信号经过锁存模块3023后会产生第一标识信号，在第一标识信号处于有效状态时可以产生执行ECS操作的命令信号，以确保24小时完成所有的错误检查与清除。
进一步地，在一些实施例中，对于计数统计模块302而言，在图6所示计数控制电路30的基础上，参见图10，计数统计模块302还可以包括锁存模块3023和自动脉冲模块3024，且自动脉冲模块3024的输入端与译码模块3022的输出端连接，自动脉冲模块3024的输出端与锁存模块3023的置位端(SET)连接，其中：
计数模块3021，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
译码模块3022，配置为接收计数信号，对计数信号进行译码处理，生成目标计数信号；
自动脉冲模块3024，配置为根据目标计数信号生成置位信号；其中，在目标计数信号处于有效状态时，使置位信号处于有效状态；
锁存模块3023，配置为接收置位信号，以及在置位信号处于有效状态时，根据置位信号生成处于有效状态的第一标识信号。
需要说明的是，本公开实施例所述的锁存模块可以是SR型锁存器(SR Latch)，且SR型锁存器可以是由两个二输入与非门组成的。另外，在本公开实施例中，SR型锁存器包括置位端、复位端和输出端。其中，SR型锁存器的置位端用于接收置位信号，SR型锁存器的复位端用于接收复位信号，SR型锁存器的输出端用于输出第一标识信号。
还需要说明的是，在本公开实施例中，若目标计数信号处于有效状态，则可以使置位信号处于有效状态；若目标计数信号处于无效状态，则可以使置位信号处于无效状态。其中，只有置位信号处于有效状态时，才可以产生处于有效状态的第一标识信号。
还需要说明的是，在本公开实施例中，置位信号可以用SET表示，其中，SET信号的电平值也可以包括第一值和第二值。示例性地，在第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0的情况下，若SET信号的电平值为逻辑1，则确定SET信号处于有效状态；否则，若SET信号的电平值为逻辑0，则确定SET信号处于无效状态。
进一步地，在一些实施例中，对于自动脉冲模块3024而言，如图10所示，自动脉冲模块3024可以包括第二延迟反相模块221和第一与门222，其中：
第二延迟反相模块221，配置为对目标计数信号进行延迟及反相处理，得到目标计数反相信号；
第一与门222，用于对目标计数反相信号和目标计数信号进行与逻辑运算，得到置位信号。
需要说明的是，在本公开实施例中，第二延迟反相模块221的输入端用于接收目标计数信号，第一与门222的第一输入端与译码模块3022的输出端连接，第一与门222的第二输入端与第二延迟反相模块221的输出端连接，第一与门222的输出端(作为自动脉冲模块3024的输出端)与锁存模块3023的置位端(SET)连接。
还需要说明的是，在本公开实施例中，对于目标计数反相信号而言，可以是通过信号发生器来产生目标计数反相信号，这里所产生的目标计数反相信号与目标计数信号之间具有延迟及反相关系；或者，也可以是通过第二延迟反相模块对目标计数信号进行延迟及反相处理，得到目标计数反相信号，然后再对目标计数反相信号和目标计数信号进行与逻辑运算，从而能够得到SET信号。
也就是说，在本公开实施例中，对于自动脉冲(Auto Pulse)模块而言，Auto Pulse是目标计数信号经过延迟反相后得到的目标计数反相信号再和目标计数信号进行与逻辑所形成的一个较小的脉冲信号，以此作为锁存模块3023的SET信号；其中，该SET可以用于产生第一标识信号。另外，需要注意的是，这里的目标计数信号需要满足一定的条件(具体是由无效状态变为有效状态，例如由低电平状态变为高电平状态)，这时候Auto Pulse才可以形成一个较小的脉冲信号，而且脉冲宽度等于第二延迟反相模块的延迟时间。
具体来说，在本公开实施例中，置位信号为高电平有效的脉冲信号。其中，如果延迟反相模块对目标计数信号的延迟时间越大，那么置位信号的脉冲宽度越宽；如果延迟反相模块对目标计数信号的延迟时间越小，那么置位信号的脉冲宽度越窄。由此可见，置位信号的脉冲宽度与延迟反相模块对目标计数信号的延迟时间具有对应关系。
还需要说明的是，在本公开实施例中，对于延迟反相模块而言，其可以是由延迟模块和反相模块串联构成的，而反相模块可以是反相器、非门等，从而对目标计数信号能够实现延迟及反相作用。
还需要说明的是，在本公开实施例中，对于自动脉冲模块3024而言，除了可以是由延迟反相模块和一个与门组成之外，自动脉冲模块3024还可以是延迟反相模块和一个或非门组成，其中，延迟反相模块的输入端用于接收目标计数信号，延迟反相模块的输出端和或非门的第一输入端连接，或非门的第二输入端用于接收目标计数信号，或非门的输出端用于输出置位信号；或者，自动脉冲模块3024还可以是延迟反相模块、一个或门和一个非门组成，其中，延迟反相模块的输入端用于接收目标计数信号，延迟反相模块的输出端和或门的第一输入端连接，或门的第二输入端用于接收目标计数信号，或门的输出端与非门的输入端连接，该非门的输出端用于输出置位信号；自动脉冲模块3024甚至也可以是其他逻辑器件组合，只要能够产生一个较小的脉冲信号即可，其内部结构并不作任何限定。
还可以理解地，在一些实施例中，在图3所示计数控制电路30的基础上，参见图11，该计数控制电路30还可以包括命令控制模块303，其中：
命令控制模块303，配置为接收第一标识信号和刷新命令信号，以及在第一标识信号处于有效状态时，根据刷新命令信号生成第一命令信号；或者，在第一标识信号处于无效状态时，根据刷新命令信号生成第二命令信号。
需要说明的是，对于命令控制模块303而言，在接收到第一标识信号之后，若第一标识信号处于有效状态，则此时会获取刷新命令信号，根据该刷新命令信号生成第一命令信号；若第一标识信号处于无效状态，则此时将刷新命令信号直接输出为第二命令信号。
还需要说明的是，在本公开实施例中，第一命令信号和第二命令信号不同。其中，第一命令信号为ECS命令信号，用于执行ECS操作；第二命令信号为内部刷新信号，用于执行刷新操作。在这里，ECS命令信号可以用ECS_CMD表示，内部刷新信号可以用REF_NEW表示。
还需要说明的是，在本公开实施例中，第一标识信号的电平值可以包括第一值和第二值。其中，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
示例性地，如果第一标识信号的电平值为逻辑1，那么可以确定第一标识信号处于有效状态，此时根据获取的刷新命令信号产生ECS_CMD信号；否则，如果第一标识信号的电平值为逻辑0，那么可以确定第一标识信号处于无效状态，此时根据获取的刷新命令信号可以输出REF_NEW信号。
简单来说，以DDR5DRAM为例，由于DRAM要求至少在24小时内进行一次完整的错误检查与清除，那么在自动ECS操作模式下就需要计数统计模块302规划ECS操作的间隔时间，具体是在计数值满足预设条件时可以产生一个有效的第一标识信号，可以用ECS_Flag表示；该ECS_Flag信号会传输到命令控制模块303；在该模块中，如果ECS_Flag信号处于有效状态，那么可以偷取下一个刷新命令来产生ECS_CMD信号，以执行ECS操作，同时对应被偷取的刷新命令会消失；如果ECS_Flag信号处于无效状态，那么可以刷新命令不会被偷取，直接传输为REF_NEW信号，以执行正常的刷新操作。
进一步地，在一些实施例中，对于命令控制模块303而言，参见图12，该命令控制模块303可以包括采样模块3031、延迟模块3032和逻辑处理模块3033，其中：
采样模块3031，配置为接收刷新命令信号和ECS标识信号，根据刷新命令信号对第一标识信号进行采样处理，得到采样信号；
延迟模块3032，配置为对刷新命令信号进行延迟处理，得到延迟刷新信号；
逻辑处理模块3033，配置为对采样信号和延迟刷新信号进行逻辑运算，在采样信号处于有效状态时，选择输出用于执行ECS操作的ECS命令信号；以及在采样信号处于无效状态时，选择输出用于执行刷新操作的内部刷新信号。
需要说明的是，在本公开实施例中，在第一标识信号处于有效状态时，使采样信号处于有效状态；在第一标识信号处于无效状态时，使采样信号处于无效状态。其中，采样信号的电平值也可以包括第一值和第二值。示例性地，在第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0的情况下，若采样信号的电平值为逻辑1，则确定采样信号处于有效状态；否则，若采样信号的电平值为逻辑0，则确定 采样信号处于无效状态。
还需要说明的是，在本公开实施例中，采样模块3031可以为D型触发器。在这里，该D型触发器的输入端(D)用于接收ECS标识信号，该D型触发器的时钟端(CK)用于接收刷新命令信号，该D型触发器的输出端(Q)用于输出采样信号。
进一步地，在一些实施例中，如图12所示，逻辑处理模块3033包括第二逻辑模块231和第三逻辑模块232，其中：
第二逻辑模块231，配置为在采样信号处于有效状态时，对采样信号和延迟刷新信号进行第一逻辑运算，输出ECS命令信号，以执行ECS操作；
第三逻辑模块232，配置为在采样信号处于无效状态时，对采样信号和延迟刷新信号进行第二逻辑运算，输出内部刷新信号，以执行刷新操作。
还需要说明的是，在本公开实施例中，可以根据采样信号的有效状态与否来确定是选择第二逻辑模块231来输出处于有效状态的ECS_CMD信号，还是选择第三逻辑模块232来输出处于有效状态的REF_NEW信号。具体地，如果输出ECS_CMD信号，那么就不会再执行刷新操作，这时候会通过ECS操作以确保24小时完成所有的错误检查与清除；如果输出REF_NEW信号，那么刷新操作不受影响，但是这时候不会执行ECS操作。
在一种可能的实施例中，如图12所示，第二逻辑模块231包括第二与非门U6和第五非门U7，且第二与非门U6的第一输入端与采样模块3031的输出端连接，第二与非门U6的第二输入端与延迟模块3032的输出端连接，第二与非门U6的输出端与第五非门U7的输入端连接，其中：
第二与非门U6，用于在采样信号处于有效状态时，对采样信号和延迟刷新信号进行与非逻辑运算，得到第一中间信号；
第五非门U7，用于对第一中间信号进行非逻辑运算，得到ECS命令信号。
在本公开实施例中，在采样信号处于有效状态时，通过第二逻辑模块231可以产生ECS_CMD信号，具体是偷取下一个刷新命令REF_AB来产生的，而且被偷取的刷新命令会消失。
在一种可能的实施例中，如图12所示，第三逻辑模块232可以包括第三与非门U8、第六非门U9和第七非门U10，且第六非门U9的输入端与采样模块3031的输出端连接，第三与非门U8的第一输入端与第六非门U9的输出端连接，第三与非门U8的第二输入端与延迟模块3032的输出端连接，第三与非门U8的输出端与第七非门U10的输入端连接，其中：
第六非门U9，用于在采样信号处于无效状态时，对采样信号进行非逻辑运算，得到第二中间信号；
第三与非门U8，用于对第二中间信号和延迟刷新信号进行与非逻辑运算，得到第三中间信号；
第七非门U10，用于对第三中间信号进行非逻辑运算，得到内部刷新信号。
在本公开实施例中，在采样信号处于无效状态时，通过第三逻辑模块232可以得到内部刷新信号，具体是刷新命令REF_AB直接输出为REF_NEW信号，这时候的刷新命令不会被偷取，而且所执行的刷新操作也不受影响。
进一步地，如图12所示，在一些实施例中，延迟模块的延迟时间大于采样模块与第六非门的延迟时间之和。
在本公开实施例中，以图12为例，延迟模块3032的延迟时间需要大于采样模块3031与第六非门U9的延迟时间之和。换句话说，延迟模块3032需要使得延迟刷新信号晚于采样信号反相后的第二中间信号。其中，在ECS_Flag信号处于有效状态(即为逻辑1)时，采样模块3031的输出也为逻辑1，可以通过第六非门U9(其输出为逻辑0)来阻断刷新命令REF_AB的输出；但是采样模块3031与第六非门U9均存在有延迟，如果刷新命令REF_AB到达第三与非门U8的时间早于第六非门U9的输出(在ECS_Flag信号的电平值为逻辑1时的输出)，此时就不能起到阻断刷新命令REF_AB的作用；因此，对于刷新命令REF_AB需经过延迟模块3032进行延迟，以使得刷新命令REF_AB到达第三与非门U8的时间稍晚于第六非门U9的输出。
在一些实施例中，这里的刷新命令信号可以包括下述至少之一：刷新信号和自刷新信号。
需要说明的是，在自动ECS操作模式下，DDR5SPEC中规定自动ECS操作需要在刷新和自刷新中规划并产生ECS_CMD信号，用来检测错误信息并同时执行内部读写检错和修复。由于借助刷新命令信号生成自动ECS操作命令时需要计数刷新和自刷新的个数，但是在自刷新时外部没有时钟；因此，本公开实施例的第一时钟信号可以是采用固有频率的信号作为计数的时钟信号，从而不仅解决了相关技术中无法借助自刷新来生成ECS命令信号的技术问题，也解决了如果发送的是其他方式的刷新命令而导致24小时内无法完成完整ECS操作的技术问题。
还可以理解地，在一些实施例中，对于前述的计数复位信号而言，在图11所示计数控制电路30的基础上，参见图13，该计数控制电路30还可以包括复位逻辑模块304，其中：
复位逻辑模块304，配置为接收第一命令信号和外部复位信号，对第一命令信号和外部复位信号进行逻辑运算，生成计数复位信号，计数复位信号用于发送给计数统计模块302。
需要说明的是，在本公开实施例中，第一标识信号处于有效状态时，可以用于指示生成该第一命令 信号。另外，复位逻辑模块304在得到计数复位信号后，会将计数复位信号发送给计数统计模块302，具体是内部的计数模块3021中每一级触发器的复位端，以实现计数模块3021的复位清零操作。
在一种具体的实施例中，参见图13，该复位逻辑模块304可以包括第一或门U11，其中：第一或门U11的第一输入端用于接收外部复位信号，第一或门U11的第二输入端用于接收第一命令信号，第一或门U11的输出端用于输出计数复位信号。
需要说明的是，在本公开实施例中，计数控制电路30在刚开始工作时，需要外部复位信号进行复位操作。在首次复位之后，外部复位信号会持续为逻辑0的低电平信号。另外，在本公开实施例中，根据外部复位信号和第一命令信号的逻辑运算，所生成的计数复位信号的电平值可以包括第一值和第二值。示例性地，第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0，若计数复位信号的电平值为逻辑1，则确定计数复位信号处于有效状态；否则，若计数复位信号的电平值为逻辑0，则确定计数复位信号处于无效状态。
还需要说明的是，在本公开实施例中，将计数复位信号发送给计数统计模块302，以使得计数统计模块302重新开始计数并且控制ECS_Flag信号处于无效状态。具体来说，在通过计数统计模块302生成处于有效状态的ECS_Flag信号之后，一方面，ECS_Flag信号和ECS_CLK信号经过逻辑运算后，得到用于计数的CNT_CLK信号，在ECS_Flag信号处于有效状态的时候，可以使得计数统计模块302停止工作，减小功耗；另一方面，在生成第一命令信号后，第一命令信号与外部复位信号经过逻辑运算之后生成作为计数统计模块302的计数复位信号，以使计数统计模块被复位；同时在生成第一命令信号后，还会使得ECS_Flag信号处于无效状态，此时通过逻辑控制模块301可以产生计数时钟信号，以使计数统计模块开始计数。在这里，计数器复位操作完成需要先于产生计数时钟信号的时间，从而保证复位完成后再开始计数，也就不会出现计数和复位同时操作而出现冲突的技术问题。
另外，还需要注意的是，对于ECS_Flag信号的无效状态，可以是根据第一命令信号ECS_CMD直接控制ECS_Flag信号处于无效状态；或者，也可以是根据第一命令信号ECS_CMD产生计数复位信号，使得计数器复位清零，然后根据清零后的计数值以使ECS_Flag信号处于无效状态。
还可以理解地，在一些实施例中，对于前述的第一时钟信号而言，在图3所示计数控制电路30的基础上，参见图14，计数控制电路30还可以包括时钟产生电路305，其中：
时钟产生电路305，用于产生第一时钟信号。
在一种具体的实施例中，参见图14，时钟产生电路305可以包括振荡模块3051和分频模块3052，其中：
振荡模块3051，配置为输出预设频率的第二时钟信号；
分频模块3052，配置为对第二时钟信号进行n分频处理，得到第一时钟信号。
其中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
需要说明的是，在本公开实施例中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
还需要说明的是，在本公开实施例中，振荡模块3051可以是振荡器(Oscillator，OSC)，例如环形振荡器(Ring OSC)、晶体振荡器(Crystal OSC)等。在这里，振荡模块3051为Ring OSC，用于产生固定频率的第二时钟信号；然后通过分频模块3052对第二时钟信号进行分频处理，可以得到用于计数的第一时钟信号。其中，第二时钟信号可以用OSC_CLK表示，第一时钟信号可以用ECS_CLK表示。
示例性地，可以采用Ring OSC产生固定频率的OSC_CLK信号，假定时钟频率为1818kHz，对应的时钟周期为550ns；那么在经过分频处理之后，输出时钟频率为227kHz的ECS_CLK信号，其对应的时钟周期为4.4us。这样，由于计数控制电路30中包括有时钟产生电路305，可以产生计数所需的第一时钟信号，从而不仅解决了在自刷新时没有外部时钟的技术问题，而且还解决了控制器发送其他方式的刷新命令时计数不会增加，进而导致24小时内无法完成完整ECS操作的问题。
还需要说明的是，在本公开实施例中，对于计数统计模块中的译码模块而言，其内部电路的设计具体可以是根据指令译码规则实现的。对于不同的产品，不同的应用场景，不同的指令，译码规则可能不同，那么该译码模块的具体结构也可进行相应调整，本公开实施例不作具体限定。
本公开实施例提供了一种计数控制电路，该计数控制电路包括逻辑控制模块和计数统计模块。其中，在逻辑控制模块接收到第一时钟信号之后，结合第一标识信号进行逻辑运算可以得到用于计数的计数时钟信号，根据该计数时钟信号可以产生第一标识信号，以此能够产生执行ECS操作的第一命令信号，此时计数无需考虑刷新命令的限制，解决了相关技术中只能借助REF_AB进行计数来产生ECS命令信号的技术问题，能够确保24小时完成完整的ECS操作；另外，该计数时钟信号与第一标识信号之间具有逻辑关系，在使用计数时钟信号进行计数时，根据第一标识信号的状态来控制计数统计模块是否停止计数，从而还能够达到减小功耗的目的，最终提升存储器的性能。
本公开的另一实施例中，基于前述实施例所述的计数控制电路30，参见图15，其示出了本公开实施例提供的另一种计数控制电路30的组成结构示意图。如图15所示。该计数控制电路30可以包括异步计数器1501、译码模块1502、命令控制模块1503和复位逻辑模块1504，而复位逻辑模块1504包括第一或门U11。其中，异步计数器1501的计数时钟信号为刷新命令REF_AB，异步计数器1501输出的计数信 号用REF<7:0>表示，REF<7:0>信号用于表征计数值；当计数值满足预设条件时，此时的REF<7:0>信号经过译码模块1502的译码处理后，可以得到处于有效状态的第一标识信号(用ECS_Flag表示)；将该ECS_Flag信号发送到命令控制模块1503，在该模块中可以获取下一时刻接收到的刷新命令REF_AB，并根据刷新命令REF_AB来生成第一命令信号；这时候还可以将外部复位信号(用RESET表示)和第一命令信号(用ECS_CMD表示)输入到复位逻辑模块1504，通过内部的第一或门U11进行或逻辑运算后，可以输出计数复位信号(用ECS_RST表示)，该ECS_RST信号发送至异步计数器1501中每一级触发器的复位端(RST)，使异步计数器1501进行计数清零。另外，在产生ECS_CMD信号之后，还会使得ECS_Flag信号处于无效状态。这时候的命令控制模块1503中，如果为无效状态的ECS_Flag信号，那么根据获取到的刷新命令REF_AB直接输出为第二命令信号(即内部刷新信号，用REF_NEW表示)。
基于图15所示的计数控制电路，图16示出了本公开实施例提供的一种计数控制电路的信号时序示意图。如图16所示，REF<0>、REF<1>、REF<2>、REF<3>、REF<4>、REF<5>、REF<6>、REF<7>为计数信号中包括的八个比特位。由于异步计数器的自身特性，使得异步计数器计数输出会存在延迟没有对齐，此时如果刷新频率过快且计数器级数较高时将会导致计数错误。在图16中，假定在t1时刻，这时候的八位计数信号对应的二进制数为01111111；在下一时刻，正常情况下的计数为10000000，但是由于刷新频率过快导致REF<7>变化之前REF<0>就已经再次改变，即在t2时刻，这时候的八位计数信号对应的二进制数为10000001，即异步计数器发生计数错误，从而使得译码模块1502出现错误译码情况，进而导致无法产生有效的ECS_Flag信号，也就无法根据有效的ECS_Flag信号来产生ECS_CMD信号，进而无法通过复位逻辑模块1504来产生ECS_RST信号，如图16中的虚线所示。简言之，由于译码结果的不准确性，造成根据译码结果完成的后续功能均无法正常执行。
进一步地，对于图15所示的计数控制电路而言，一方面，采用刷新命令REF_AB当做计数器的时钟信号，如果控制器利用REFsb等其他方式来刷新，计数器就不会增加，从而导致出现24小时内无法完成整个ECS操作的问题。另一方面，采用异步计数器会导致计数器每一级的输出延迟，可能导致计数在最后一级变化之前出现错误译码过程，从而有可能影响下一次计数。又一方面，在产生ECS_Flag信号时，该计数器仍然会持续计数刷新命令REF_AB，直到ECS_RST后会重新计数，ECS_RST和计数器的工作会出现冲突的时间。因此，本公开实施例还可以对计数控制电路做进一步改进。
本公开的又一实施例中，基于前述实施例所述的计数控制电路30，参见图17，其示出了本公开实施例提供的又一种计数控制电路30的组成结构示意图。如图17所示。该计数控制电路30可以包括同步计数器1701、译码模块1702、命令控制模块1703、复位逻辑模块1704和逻辑控制模块1705，而逻辑控制模块1705是由第一非门U1、第二非门U2、第三非门U3、第一与非门U4和第四非门U5组成，复位逻辑模块1504是由第一或门U11组成。
在这里，同步计数器1701的计数时钟信号为CNT_CLK信号，其不再是刷新命令REF_AB，而是由逻辑控制模块1705对ECS_CLK信号和ECS_Flag信号进行逻辑运算后产生的；这样，由ECS_Flag信号经过逻辑运算控制计数时钟信号，当ECS_Flag信号为高电平的时候，可以使得计数器停止工作，从而减小功耗。另外，在计数过程中，同步计数器1701根据CNT_CLK信号进行计数，输出的计数信号可以用Code<7:0>或者REF<7:0>表示；以REF<7:0>为例，这里使用REF<7:0>信号用于表征计数值；当计数值满足预设条件时，此时的REF<7:0>信号经过译码模块1702的译码处理后，可以得到处于有效状态的ECS_Flag信号；将该ECS_Flag信号发送到命令控制模块1703，在该模块中可以获取下一时刻接收到的刷新命令REF_AB，并根据刷新命令REF_AB来产生ECS_CMD信号；这时候还可以将外部复位信号RESET和ECS_CMD信号输入到复位逻辑模块1704，通过内部的第一或门U11进行或逻辑运算后，可以输出计数复位信号ECS_RST，以使得同步计数器1701重新开始计数，同时使ECS_Flag信号复位为无效状态。另外，还需要注意的是，在命令控制模块1703中，如果为无效状态的ECS_Flag信号，那么这时候根据获取到的刷新命令REF_AB可以直接输出为内部刷新信号REF_NEW。
基于图17所示的计数控制电路，图18示出了本公开实施例提供的另一种计数控制电路的信号时序示意图。如图18所示，REF<0>、REF<1>、REF<2>、REF<3>、REF<4>、REF<5>、REF<6>、REF<7>为计数信号中包括的八个比特位。由于同步计数器的自身特性，使得同步计数器的计数输出边沿对齐。当计数值满足预设条件(即计数到特定数值)的t1时刻，译码模块会产生有效的ECS_Flag信号；在ECS_Flag为高电平期间，此时ECS_Flag信号会经过逻辑控制计数时钟信号，使得计数时钟信号为低电平，从而在t2时刻就使得计数器停止计数；同时在ECS_Flag为高电平的情况下还会选取一个REF_AB命令来产生ECS_CMD命令，被选取的REF_AB命令不会传输为REF_NEW命令。然后再根据ECS_CMD命令还可以产生计数复位信号ECS_RST，具体是在t3时刻，此时根据ECS_RST可以使得REF<7:0>信号译码复位为0，即REF<7:0>为00000000，随后还可以使ECS_Flag信号复位为低电平。在ECS_Flag信号为低电平期间，刷新命令不会被偷取，直接传输到REF_NEW信号，并且进行的刷新操作也不受影响。在这里，对于ECS_Flag信号的无效状态(低电平状态)，可以是根据ECS_CMD信号直接控制ECS_Flag信号处于无效状态；或者，也可以是根据ECS_CMD信号产生ECS_RST信号，使得计数器复位清零，然后根据清零后的计数值以使ECS_Flag信号处于无效状态。
也就是说，对于图17所示的计数控制电路而言，通过将异步计数器变为同步计数器，用振荡器产生的固定频率的OSC_CLK信号后，再经过分频器产生ECS_CLK信号作为同步计数器的时钟信号，然后在计数到特性数值时，同步计数器的输出经过译码器可以产生ECS_Flag信号。随后，ECS_Flag信号经过命令控制模块会选取下一个刷新命令REF_AB用来产生ECS命令，同时对应被选取的REF_AB不会进行刷新操作。之后命令控制模块产生一个计数复位信号使计数器重新开始计数，同时ECS_Flag信号复位为低电平。在ECS_Flag信号为低电平期间，刷新命令REF_AB不会被选取，直接传输到REF_NEW信号，进行的正常的刷新操作。
本公开实施例提供了一种计数控制电路，通过上述实施例对前述实施例的具体实现进行详细阐述，从中可以看出，基于前述实施例的技术方案，一方面，能够解决控制器发送非REF_AB的其他命令而导致24小时内无法完成完整ECS操作的问题；另一方面，采用同步计数器可以使每一级输出对齐，保证计数器输出没有错误的译码过程，从而减少计数器延迟对ECS_Flag信号产生的影响；又一方面，将ECS_Flag信号经过一些逻辑控制计数时钟信号，具体是ECS_Flag为高电平的时候，可以使得计数器停止工作，从而还能够减小功耗；又一方面，在产生ECS_CMD信号后，还可以复位计数器，由于计数器已经停止工作，这时候还不会出现计数和复位同时操作出现冲突的问题。
本公开的再一实施例中，参见图19，其示出了本公开实施例提供的一种计数控制方法的流程示意图。如图19所示，该流程可以包括：
S1901：接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号。
S1902：根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
需要说明的是，在本公开实施例中，该方法可以应用于前述实施例中任一项所述的计数控制电路30或者集成有计数控制电路30的半导体存储器。对于计数控制电路30而言，其可以包括逻辑控制模块和计数统计模块，而且逻辑控制模块的输出端与计数统计模块的输入端连接。其中，步骤S1901是由逻辑控制模块执行的，步骤S1902是由计数统计模块执行的。
在一些实施例中，该方法还可以包括：
在所述第一标识信号处于无效状态时，根据所述第一时钟信号生成所述计数时钟信号，使所述计数统计模块对所述计数时钟信号进行计数；或者，
在所述第一标识信号处于有效状态时，屏蔽所述第一时钟信号以阻止所述计数时钟信号的生成，使所述计数统计模块停止计数。
在本公开实施例中，逻辑控制模块可以包括第一驱动模块和第一逻辑模块。相应地，在一些实施例中，对于S1901而言，通过逻辑控制模块接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号，可以包括：
通过第一驱动模块对第一时钟信号进行驱动处理，得到第一中间信号；
通过第一逻辑模块对第一中间信号和第一标识信号进行逻辑运算，得到计数时钟信号。
在本公开实施例中，第一驱动模块可以包括偶数个级联的第三非门。
在本公开实施例中，第一逻辑模块可以包括第一延迟反相模块、第一与非门和第二非门。相应地，在一些实施例中，通过第一逻辑模块对第一中间信号和第一标识信号进行逻辑运算，得到计数时钟信号，可以包括：
通过第一延迟反相模块对第一标识信号进行延迟及反相处理，得到第二中间信号；
通过第一与非门对第一中间信号和第二中间信号进行与非逻辑运算，得到第三中间信号；
通过第二非门对第三中间信号进行非逻辑运算，得到计数时钟信号。
在本公开实施例中，第一延迟反相模块包括奇数个级联的第三非门。
可以理解地，在本公开实施例中，计数统计模块可以包括计数模块和译码模块。相应地，在一些实施例中，对于S1902来说，通过计数统计模块接收计数时钟信号，根据计数时钟信号进行计数，生成第一标识信号，可以包括：
通过计数模块接收计数时钟信号，根据计数时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
通过译码模块接收计数信号，对计数信号进行译码处理，生成第一标识信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。
还可以理解地，在本公开实施例中，计数模块可以包括同步二进制计数器，同步二进制计数器包括若干个依次级联的计数子模块，且每个计数子模块均包括触发器，每个触发器的时钟端均与计数时钟信号连接。相应地，在一些实施例中，该方法还可以包括：
通过若干个计数子模块接收计数时钟信号，通过各自包含的触发器进行时钟采样处理，输出计数信号；其中，计数信号包括若干个比特位，且若干个计数子模块与计数信号包含的若干个比特位之间具有对应关系。
进一步地，在一些实施例中，对于若干个计数子模块而言，可以包括：
第一个计数子模块包括第一触发器，第一触发器的输入端(D)与第一触发器的第二输出端(/Q)连接，第一触发器的时钟端(CK)用于接收计数时钟信号，且第一触发器的第一输出端(Q)用于输出第一计数信号，且第一计数信号是计数信号中的第0比特位；
第二个计数子模块包括第二触发器和第二异或门，第二异或门的第一输入端与第一触发器的第一输出端(Q)连接，第二异或门的第二输入端与第二触发器的第一输出端(Q)连接，第二异或门的输出端与第二触发器的输入端(D)连接，第二触发器的时钟端(CK)用于接收计数时钟信号，且第二触发器的第一输出端(Q)用于输出第二计数信号，且第二计数信号是计数信号中的第1比特位；
第i个计数子模块包括第i触发器、第i与非门、第i非门和第i异或门，第i与非门的第一输入端与第i-1触发器的第一输出端(Q)连接，第i与非门的第二输入端与第i-1异或门的第一输入端连接，第i与非门的输出端与第i非门的输入端连接，第i非门的输出端与第i异或门的第一输入端连接，第i异或门的第二输入端与第i触发器的第一输出端(Q)连接，第i异或门的输出端与第i触发器的输入端(D)连接，第i触发器的时钟端(CK)用于接收计数时钟信号，且第i触发器的第一输出端(Q)用于输出第i计数信号，且第i计数信号是计数信号中的第i-1比特位；其中，i为大于或等于3且小于或等于M的整数，M为正整数。
还可以理解地，在本公开实施例中，计数控制电路还可以包括命令控制模块。相应地，在一些实施例中，该方法还可以包括：
通过命令控制模块接收第一标识信号和刷新命令信号，以及在第一标识信号处于有效状态时，根据刷新命令信号生成第一命令信号；或者，在第一标识信号处于无效状态时，根据刷新命令信号生成第二命令信号。
在本公开实施例中，第一命令信号为ECS命令信号，用于执行ECS操作；第二命令信号为内部刷新信号，用于执行刷新操作。
在本公开实施例中，刷新命令信号可以包括下述至少之一：刷新信号和自刷新信号。
进一步地，在一些实施例中，该方法还可以包括：
通过计数统计模块接收计数复位信号，根据计数复位信号进行计数清零，并使第一标识信号处于无效状态。
还可以理解地，在本公开实施例中，计数控制电路还可以包括复位逻辑模块。相应地，在一些实施例中，该方法还可以包括：
通过复位逻辑模块接收第一命令信号和外部复位信号，对第一命令信号和外部复位信号进行逻辑运算，生成计数复位信号，计数复位信号用于发送给计数统计模块；其中，第一标识信号处于有效状态时，用于指示生成第一命令信号，该第一命令信号用于表征第一操作为ECS操作时产生的命令信号。
进一步地，在一些实施例中，复位逻辑模块可以包括第一或门。其中，第一或门的第一输入端用于接收外部复位信号，或门的第二输入端用于接收第一命令信号，或门的输出端用于输出计数复位信号。
还可以理解地，在本公开实施例中，计数控制电路还可以包括时钟产生电路。相应地，在一些实施例中，该方法还可以包括：通过时钟产生电路产生第一时钟信号。
进一步地，时钟产生电路可以包括振荡模块和分频模块，相应地，在一些实施例中，该方法还可以包括：
通过振荡模块输出预设频率的第二时钟信号；
通过分频模块对第二时钟信号进行n分频处理，得到第一时钟信号。
在本公开实施例中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
本公开实施例提供了一种计数控制方法，不仅能够解决(利用REF_AB命令进行计数产生ECS命令信号时)控制器发送非REF_AB的其他命令而导致24小时内无法完成完整ECS操作的问题，而且采用同步计数器可以使每一级输出对齐，保证计数器输出没有错误的译码过程，从而减少计数器延迟对ECS_Flag信号产生的影响，同时ECS_Flag为高电平的时候，通过对ECS_Flag信号的逻辑运算来控制计数器停止工作，从而还能够减小功耗；另外，在产生ECS_CMD信号后，还可以复位计数器，由于计数器已经停止工作，这时候还不会出现计数和复位同时操作出现冲突的问题。
本公开的再一实施例中，参见图20，其示出了本公开实施例提供的一种半导体存储器的组成结构示意图。如图20所示，该半导体存储器200至少包括前述实施例任一项所述的计数控制电路30。
在一些实施例中，半导体存储器200可以包括DRAM。其中，对于DRAM来说，不仅可以符合DDR、DDR2、DDR3、DDR4、DDR5等内存规格，还可以符合LPDDR、LPDDR2、LPDDR3、LPDDR4、LPDDR5等内存规格，这里不作任何限定。
在本公开实施例中，对于该半导体存储器200而言，其主要涉及集成电路计数器计数及命令译码的相关电路，尤其涉及在DRAM芯片中，振荡器输出OSC_CLK信号并且经过分频器的处理，可以产生ECS_CLK信号作为计数器的时钟信号，外部输入RESET作为计数器的初始值，当产生ECS命令时计数器被重置。本公开实施例优化了原有采用刷新命令REF_AB作为时钟，同时采用同步计数器代替异步计 数器。使得计数器不会因为刷新命令的改变影响计数，用同步代替异步避免了异步计数器输出延迟导致的计数错误，同时还优化了译码模块，使译码模块不会因为刷新命令的改变而导致ECS命令产生错误。在本公开实施例中，该计数控制电路应用于DRAM芯片中通过计数产生ECS命令的相关电路，但不局限于此范围，其他计数产生命令的电路均可采用此设计。
这样，对于该半导体存储器200而言，不仅能够解决控制器发送非REF_AB的其他命令而导致24小时内无法完成完整ECS操作的问题，而且采用同步计数器可以使每一级输出对齐，保证计数器输出没有错误的译码过程，从而减少计数器延迟对ECS_Flag信号产生的影响，同时ECS_Flag为高电平的时候，通过对ECS_Flag信号的逻辑运算来控制计数器停止工作，从而还能够减小功耗；另外，在产生ECS_CMD信号后，还可以复位计数器，由于计数器已经停止工作，这时候还不会出现计数和复位同时操作出现冲突的问题。
以上所述，仅为本公开的示例性的实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或电路实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或电路实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种计数控制电路、计数控制方法以及半导体存储器，该计数控制电路包括逻辑控制模块和计数统计模块，且逻辑控制模块的输出端与计数统计模块的时钟端连接，其中，逻辑控制模块，配置为接收第一时钟信号和第一标识信号，并在第一标识信号的控制下，根据第一时钟信号生成计数时钟信号；计数统计模块，配置为接收计数时钟信号，根据计数时钟信号进行计数，生成第一标识信号，第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使第一标识信号处于有效状态。这样，逻辑控制模块在接收第一时钟信号之后，结合第一标识信号进行逻辑运算可以得到用于计数的计数时钟信号，根据该计数时钟信号可以产生第一标识信号，以此产生执行第一操作的命令信号，这时候执行ECS操作的命令产生不受刷新命令的限制，解决了相关技术中只能借助REF_AB进行计数来产生ECS命令信号的技术问题，能够确保24小时完成完整的ECS操作；另外，该计数时钟信号与第一标识信号之间具有逻辑关系，根据第一标识信号的状态可以控制计数统计模块是否停止计数，从而还能够达到减小功耗的目的，最终提升存储器的性能。

Claims (20)

  1. 一种计数控制电路，包括逻辑控制模块和计数统计模块，且所述逻辑控制模块的输出端与所述计数统计模块的时钟端连接，其中：
    所述逻辑控制模块，配置为接收第一时钟信号和第一标识信号，并在所述第一标识信号的控制下，根据所述第一时钟信号生成计数时钟信号；
    所述计数统计模块，配置为接收所述计数时钟信号，根据所述计数时钟信号进行计数，生成所述第一标识信号，所述第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使所述第一标识信号处于有效状态。
  2. 根据权利要求1所述的计数控制电路，其中，
    所述逻辑控制模块，配置为在所述第一标识信号处于无效状态时，根据所述第一时钟信号生成所述计数时钟信号，使所述计数统计模块对所述计数时钟信号进行计数；或者，在所述第一标识信号处于有效状态时，屏蔽所述第一时钟信号以阻止所述计数时钟信号的生成，使所述计数统计模块停止计数。
  3. 根据权利要求1所述的计数控制电路，其中，所述逻辑控制模块包括第一驱动模块和第一逻辑模块，其中：
    所述第一驱动模块，配置为对所述第一时钟信号进行驱动处理，得到第一中间信号；
    所述第一逻辑模块，配置为对所述第一中间信号和所述第一标识信号进行逻辑运算，得到所述计数时钟信号。
  4. 根据权利要求3所述的计数控制电路，其中，所述第一驱动模块包括偶数个级联的第一非门。
  5. 根据权利要求3所述的计数控制电路，其中，所述第一逻辑模块包括第一延迟反相模块、第一与非门和第二非门，其中：
    所述第一延迟反相模块，配置为对所述第一标识信号进行延迟及反相处理，得到第二中间信号；
    所述第一与非门，用于对所述第一中间信号和所述第二中间信号进行与非逻辑运算，得到第三中间信号；
    所述第二非门，用于对所述第三中间信号进行非逻辑运算，得到所述计数时钟信号。
  6. 根据权利要求5所述的计数控制电路，其中，所述第一延迟反相模块包括奇数个级联的第三非门。
  7. 根据权利要求1所述的计数控制电路，其中，
    所述计数统计模块，还配置为接收计数复位信号，根据所述计数复位信号进行计数清零，并使所述第一标识信号处于无效状态。
  8. 根据权利要求7所述的计数控制电路，其中，所述计数控制电路还包括复位逻辑模块，其中：
    所述复位逻辑模块，配置为接收第一命令信号和外部复位信号，对所述第一命令信号和所述外部复位信号进行逻辑运算，生成所述计数复位信号，所述计数复位信号用于发送给所述计数统计模块；其中，所述第一标识信号处于有效状态时，用于指示生成所述第一命令信号。
  9. 根据权利要求8所述的计数控制电路，其中，所述复位逻辑模块包括第一或门，其中：
    所述第一或门的第一输入端用于接收所述外部复位信号，所述第一或门的第二输入端用于接收所述第一命令信号，所述第一或门的输出端用于输出所述计数复位信号。
  10. 根据权利要求1所述的计数控制电路，其中，所述计数统计模块包括计数模块和译码模块，且所述计数模块的输出端与所述译码模块的输入端连接，其中：
    所述计数模块，配置为接收所述计数时钟信号，根据所述计数时钟信号进行计数，生成计数信号，所述计数信号用于表征计数值；
    所述译码模块，配置为接收所述计数信号，对所述计数信号进行译码处理，生成所述第一标识信号；其中，在所述计数值满足预设条件时，使所述第一标识信号处于有效状态。
  11. 根据权利要求10所述的计数控制电路，其中，所述计数模块包括同步二进制计数器，所述同步二进制计数器包括若干个依次级联的计数子模块，且每个所述计数子模块均包括触发器，每个所述触发器的时钟端均与所述计数时钟信号连接，其中：
    若干个所述计数子模块，配置为接收所述计数时钟信号，通过各自包含的所述触发器进行时钟采样处理，输出所述计数信号；
    其中，所述计数信号包括若干个比特位，且若干个所述计数子模块与所述计数信号包含的若干个比特位之间具有一一对应关系。
  12. 根据权利要求11所述的计数控制电路，其中，在若干个所述计数子模块中：
    第一个所述计数子模块包括第一触发器，所述第一触发器的输入端与所述第一触发器的第二输出端连接，所述第一触发器的时钟端用于接收所述计数时钟信号，且所述第一触发器的第一输出端用于输出第一计数信号，且所述第一计数信号是所述计数信号中的第0比特位；
    第二个所述计数子模块包括第二触发器和第二异或门，所述第二异或门的第一输入端与所述第一触 发器的第一输出端连接，所述第二异或门的第二输入端与所述第二触发器的第一输出端连接，所述第二异或门的输出端与所述第二触发器的输入端连接，所述第二触发器的时钟端用于接收所述计数时钟信号，且所述第二触发器的第一输出端用于输出第二计数信号，且所述第二计数信号是所述计数信号中的第1比特位；
    第i个所述计数子模块包括第i触发器、第i与非门、第i非门和第i异或门，所述第i与非门的第一输入端与第i-1触发器的第一输出端连接，所述第i与非门的第二输入端与第i-1异或门的第一输入端连接，所述第i与非门的输出端与所述第i非门的输入端连接，所述第i非门的输出端与所述第i异或门的第一输入端连接，所述第i异或门的第二输入端与所述第i触发器的第一输出端连接，所述第i异或门的输出端与所述第i触发器的输入端连接，所述第i触发器的时钟端用于接收所述计数时钟信号，且所述第i触发器的第一输出端用于输出第i计数信号，且所述第i计数信号是所述计数信号中的第i-1比特位；其中，i为大于或等于3且小于或等于M的整数，M为正整数。
  13. 根据权利要求1所述的计数控制电路，其中，所述计数控制电路还包括命令控制模块，其中：
    所述命令控制模块，配置为接收所述第一标识信号和刷新命令信号，以及在所述第一标识信号处于有效状态时，根据所述刷新命令信号生成第一命令信号；或者，在所述第一标识信号处于无效状态时，根据所述刷新命令信号生成第二命令信号。
  14. 根据权利要求13所述的计数控制电路，其中，
    所述第一命令信号为错误检查与清除ECS命令信号，用于执行ECS操作；
    所述第二命令信号为内部刷新信号，用于执行刷新操作。
  15. 根据权利要求13所述的计数控制电路，其中，所述刷新命令信号包括下述至少之一：刷新信号和自刷新信号。
  16. 根据权利要求1至15任一项所述的计数控制电路，其中，所述计数控制电路还包括时钟产生电路，其中：
    所述时钟产生电路，用于产生所述第一时钟信号。
  17. 根据权利要求16所述的计数控制电路，其中，所述时钟产生电路包括振荡模块和分频模块，其中：
    所述振荡模块，配置为输出预设频率的第二时钟信号；
    所述分频模块，配置为对所述第二时钟信号进行n分频处理，得到所述第一时钟信号；
    其中，所述第一时钟信号的频率为所述预设频率的n分之一，n为大于零的整数。
  18. 一种计数控制方法，所述方法包括：
    接收第一时钟信号和第一标识信号，并在所述第一标识信号的控制下，根据所述第一时钟信号生成计数时钟信号；
    根据所述计数时钟信号进行计数，生成所述第一标识信号，所述第一标识信号用于指示生成执行第一操作的命令信号；其中，在计数值满足预设条件时，使所述第一标识信号处于有效状态。
  19. 一种半导体存储器，所述半导体存储器包括如权利要求1至17任一项所述的计数控制电路。
  20. 根据权利要求19所述的半导体存储器，其中，所述半导体存储器包括动态随机存取存储器DRAM。
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