WO2024067590A1 - 一种基于延迟锁相环路的电容检测方法及电容检测电路 - Google Patents

一种基于延迟锁相环路的电容检测方法及电容检测电路 Download PDF

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WO2024067590A1
WO2024067590A1 PCT/CN2023/121579 CN2023121579W WO2024067590A1 WO 2024067590 A1 WO2024067590 A1 WO 2024067590A1 CN 2023121579 W CN2023121579 W CN 2023121579W WO 2024067590 A1 WO2024067590 A1 WO 2024067590A1
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Prior art keywords
signal
capacitor
delay
path
locked loop
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PCT/CN2023/121579
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English (en)
French (fr)
Inventor
白颂荣
范硕
张海越
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深圳曦华科技有限公司
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Priority claimed from CN202211187934.1A external-priority patent/CN115616294B/zh
Application filed by 深圳曦华科技有限公司 filed Critical 深圳曦华科技有限公司
Publication of WO2024067590A1 publication Critical patent/WO2024067590A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches

Definitions

  • the present disclosure relates to the field of electronic equipment, and in particular to a capacitance detection method and a capacitance detection circuit based on a delay locked loop.
  • the function of the delay-locked loop is to eliminate clock delay, achieve zero transmission delay, and minimize the deviation between the input clock signal and the global clock network inside the entire chip.
  • the delay-locked loop is mainly composed of a phase detector, a charge pump, and a sampler.
  • the output of the sampler and the phase detector form an elimination path, and the clock signal of the global clock network is synchronized with the input clock signal through the feedback signal.
  • the input clock signal is delayed by the delay capacitor in the signal path, and the delayed signal is determined by the capacitor in the elimination path. Therefore, it is necessary to detect and adjust the delay capacitor in the signal path and the capacitor size in the feedback loop so that the input clock signal is synchronized with the output clock signal after the delay.
  • the capacitor in the elimination path is an array composed of many switches and capacitors, as shown in Figure 1. Each switch is controlled by a separate control word to control whether it is connected. When the switch is closed, there will be an on-resistance, as shown in Rp in Figure 1. At the same time, the routing and the device will also have additional capacitance to ground, as shown in Cp in Figure 1. This brings up a problem: there may be multiple combinations or multiple output signals Dout, so that the delay caused by the capacitor array in the elimination path under its control is the same, then the delay locked loop may stabilize at several different Dout values, causing the delay locked loop to fail for capacitor detection, reducing the detection accuracy. Therefore, the method of capacitor detection based on the delay locked loop has the problem of low accuracy.
  • the disclosed embodiment provides a capacitance detection method based on a delay phase-locked loop, in which the output signal obtained when the main path is stable in a closed-loop state is used as the input signal of the second capacitor in the elimination path in an open-loop state, so that the elimination path is independent of the output signal of the main path in the previous time step, so that the control word of the second capacitor of the elimination path is fixed, and even if there are multiple output signals corresponding to the main path in the closed-loop state, the change amount of the first capacitor of the signal path in the open-loop state is not affected, thereby improving the accuracy of capacitance detection based on the delay phase-locked loop.
  • an embodiment of the present disclosure provides a capacitance detection method based on a delay locked loop, which is applied to a capacitance detection circuit
  • the capacitance detection circuit includes: a main path, a signal path, and an elimination path, wherein the output end of the signal path is electrically connected to the first input end of the main path, the output end of the elimination path is electrically connected to the second input end of the main path, and the input end of the elimination path is electrically connected to the output end of the main path so that the main path and the elimination path form a delay locked loop, wherein the signal path includes a first capacitor, and the elimination path includes a second capacitor, and the method includes the following steps:
  • the reference clock signal is delayed through the first capacitor to obtain a first delayed signal
  • the change value of the first capacitance is calculated according to the output signal of the main path at the current time step.
  • an embodiment of the present disclosure provides a capacitance detection circuit, the capacitance detection circuit comprising: a main path, a signal path and an elimination path, the output end of the signal path is electrically connected to the input end of the main path, the output end of the elimination path is electrically connected to the input end of the main path, the output end of the elimination path is electrically connected to the output end of the main path, wherein the signal path comprises a first capacitor, the elimination path comprises a second capacitor, and the delay locked loop is used to implement the steps in the capacitance detection method based on a delay locked loop as described in any one of the embodiments of the present disclosure.
  • FIG1 is a structural diagram of a method for eliminating capacitance in a path provided by an embodiment of the present disclosure
  • FIG2 is a structural diagram of a capacitance detection circuit in an open-loop state provided by an embodiment of the present disclosure
  • FIG3 is a structural diagram of another capacitance detection circuit in an open-loop state provided by an embodiment of the present disclosure.
  • FIG4 is a structural diagram of a capacitance detection circuit in a closed-loop state provided by an embodiment of the present disclosure
  • FIG5 is an equivalent circuit diagram of a capacitor charging process of an inverter provided by an embodiment of the present disclosure
  • FIG6 is a schematic diagram of a response process of an RC network to a step signal provided by an embodiment of the present disclosure
  • FIG7 is a schematic diagram of the structure of a MUX circuit provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the structure of another MUX circuit provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of a signal with the same phase provided by an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of signals with different phases provided by an embodiment of the present disclosure.
  • FIG11 is a structural diagram of another capacitance detection circuit provided in an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of a method for delaying a reference clock signal provided by an embodiment of the present disclosure
  • FIG13 is a structural diagram of another capacitance detection circuit provided in an embodiment of the present disclosure.
  • FIG14 is a schematic diagram of a method for delaying a reference clock signal provided by an embodiment of the present disclosure
  • FIG. 15 is a flow chart of a capacitance detection method based on a delay-locked loop provided in an embodiment of the present disclosure.
  • Figure 2 is a structural diagram of a capacitance detection circuit in an open-loop state provided by an embodiment of the present disclosure
  • Figure 3 is a structural diagram of another capacitance detection circuit in an open-loop state provided by an embodiment of the present disclosure.
  • the capacitance detection circuit includes: a main path, a signal path, and an elimination path.
  • the output end of the signal path is electrically connected to the first input end of the main path
  • the output end of the elimination path is electrically connected to the second input end of the main path
  • the input end of the elimination path is electrically connected to the output end of the main path
  • the signal path includes a first capacitor
  • the elimination path includes a second capacitor.
  • the main path and the elimination path construct a delay phase-locked loop
  • the first capacitor can also be referred to as a capacitor to be detected.
  • the input of the signal path is the reference clock signal Vosc
  • the first capacitor Cx in the signal path delays the reference clock signal Vosc to obtain the first delayed signal Vosc_Cx output by the signal path.
  • the input of the elimination path includes the first input signal and the reference clock signal, and the first input signal is loaded on the second capacitor.
  • the reference clock signal is delayed by the second capacitor loaded with the first input signal to obtain the second delayed signal Vosc_Cc.
  • the first input signal is the output signal of the main path when the capacitance detection circuit is stable in the closed-loop state.
  • the input end of the main path is electrically connected to a selection switch, and the control signal of the selection switch is a frequency-divided signal of the reference clock signal.
  • the first delayed signal and the second delayed signal are selected by the selection switch to obtain a target signal; the target signal is input into the main path to obtain an output signal of the main path at the current time step.
  • the main path includes a phase frequency detector (PFD), a charge pump (CP) and an ADC sampler.
  • the selection switch can be set at the input or output of the phase frequency detector. In FIG. 2 , the selection switch is set at the input of the phase frequency detector. In FIG. 3 , the selection switch is set at the output of the phase frequency detector.
  • FIG4 is a structural diagram of a capacitance detection circuit in a closed-loop state provided by an embodiment of the present disclosure.
  • the input of the signal path is a reference clock signal Vosc
  • the first capacitor Cx in the signal path delays the reference clock signal Vosc to obtain a third delayed signal Vosc_Cx output by the signal path.
  • the input of the elimination path is a second input signal, which may be a reference clock signal Vosc.
  • the second capacitor Cc in the elimination path is loaded with the output signal Dout of the main path in the previous time step, and the second capacitor Cc in the elimination path delays the reference clock signal Vosc to obtain a fourth delayed signal Vosc_Cc output by the elimination path.
  • the third delayed signal Vosc_Cx and the fourth delayed signal Vosc_Cc are input into the main path to obtain the output signal Dout of the main path at the current time step. It can be seen that since it takes time to charge the first capacitor Cx, the reference clock signal Vosc is delayed to obtain the first delayed signal Vosc_Cx. When the size of the first capacitor Cx changes, the time required for charging will also change, and therefore, the delay time will also change. After the first delay signal Vosc_Cx and the third delay signal Vosc_Cx are input into the main path, the corresponding output signal Dout is output. The output signal Dout will be fed back to control the size of the second capacitor Cc on the elimination path.
  • the third delay signal Vosc_Cx has the same phase as the fourth delay signal Vosc_Cc, and the output signal of the main path will stabilize to a certain value.
  • the value of the second capacitor Cc at the current time step can be deduced from the output signal Dout of the main path.
  • the delay time of the elimination channel is positively correlated with the delay time of the signal path. Therefore, by analyzing the output signal Dout of the main path, the specific change of the first capacitor Cx can be obtained, thereby realizing the detection of the first capacitor Cx.
  • the size change of the first capacitor Cx can be a size change caused by biological touch.
  • the second input signal may be a fifth delayed signal Vosc_delay
  • the fifth delayed signal Vosc_delay is input into the elimination path
  • the second capacitor Cc in the elimination path delays the fifth delayed signal Vosc_delay
  • the fifth delayed signal Vosc_delay is a signal delayed relative to the signal path
  • the fifth delayed signal may be a preset adjustable signal.
  • the switching between the open-loop state and the closed-loop state can be controlled by a state switch.
  • the state switch can be set between the input end of the second capacitor and the output end of the main path. When the state switch connects the input end of the second capacitor and the output end of the main path, it switches to the closed-loop state. When the state switch disconnects the input end of the second capacitor and the output end of the main path, it switches to the open-loop state.
  • the signal path includes a first inverter and a second inverter, and a first capacitor Cx is coupled between the first inverter and the second inverter.
  • the main path includes a phase frequency detector PFD, a charge pump CP (charge pump), and an ADC sampler.
  • the elimination path includes a third inverter and a fourth inverter, and a second capacitor Cc is coupled between the third inverter and the fourth inverter.
  • the reference clock signal Vosc is input into the first capacitor Cx through the first inverter to charge the first capacitor Cx, so that the voltage of the first capacitor Cx rises from 0 to The voltage value of the power supply is VDD.
  • the output of the second inverter will drop from VDD to 0. Since it takes time to charge the first capacitor Cx, the reference clock signal Vosc is delayed, and the first delayed signal Vosc_Cx is obtained. When the size of the first capacitor Cx changes, the time required for charging will also change, so the delay time also changes.
  • the signal path includes a fifth inverter and a first voltage comparator, and a first capacitor Cx is coupled between the fifth inverter and the first voltage comparator.
  • the main path includes a phase frequency detector PFD, a charge pump CP (charge pump) and an ADC sampler.
  • the elimination path includes a sixth inverter and a second voltage comparator, and a second capacitor Cc is coupled between the sixth inverter and the second voltage comparator. Since it takes time to charge the first capacitor Cx, the reference clock signal Vosc is delayed, and a first delay signal Vosc_Cx1 is obtained. When the size of the first capacitor Cx changes, the time required for charging will also change, so the delay time also changes.
  • the flipping point of the voltage comparator can be controlled by a threshold voltage Vref.
  • the above-mentioned first voltage comparator includes two inputs, one input is a threshold voltage Vref, and the other input is a reference clock signal Vosc after passing through the first capacitor Cx.
  • the above-mentioned second voltage comparator includes two inputs, one input is a threshold voltage Vref, and the other input is a reference clock signal Vosc after passing through the second capacitor Cc.
  • the flip point of the first voltage comparator and the flip point of the second voltage comparator may be of the same size.
  • the threshold voltage Vref of the first voltage comparator may be equal to the threshold voltage Vref of the second voltage comparator.
  • the charging process of the capacitor by the inverter can be equivalent to the response process of the RC network to the step signal.
  • Figure 5 is an equivalent circuit diagram of the charging process of the capacitor by the inverter provided in the embodiment of the present disclosure
  • Figure 6 is a schematic diagram of the response process of the RC network to the step signal provided in the embodiment of the present disclosure.
  • Step Input is the signal source of the reference clock signal Vref
  • the signal strength is the voltage value VDD of the power supply
  • R is the equivalent output impedance of the inverter
  • C is the load capacitance
  • Vout is the output signal of the equivalent circuit.
  • the delay time can be changed to:
  • the above-mentioned a can represent the coefficient of the flip point relative to the voltage value VDD of the power supply.
  • the closer a is to 1 the greater the change in delay time, so that the signal amount of the delay time change is greater.
  • the closer the flip point aVDD is to the voltage value VDD of the power supply, the greater the change in delay time, so that the signal amount of the delay time change is greater.
  • the signal amount of the delay time change is positively correlated with the equivalent resistance.
  • the equivalent resistance R of the inverter should be increased.
  • the equivalent resistance cannot be increased infinitely, because the inverter needs to work and the signal needs to be basically established. If R is too large and the signal establishment time is too long, the signal path and elimination path composed of the entire inverter will not flip, and the work will no longer be normal.
  • the value of the second capacitor Cc in the cancellation path is generally smaller than the value of the first capacitor Cx in the signal path, which requires that the equivalent resistance Rcc of the cancellation path be greater than the equivalent resistance Rcx of the signal path.
  • the value of the second capacitor Cc in the cancellation path can be dynamically adjusted to fix the equivalent resistance Rcc of the cancellation path.
  • the value range of the first capacitor Cx in the signal path is very large, for example, the first capacitor Cx in the signal path is close to 0pF.
  • the first capacitor Cx in the signal path is small, even if the second capacitor Cc in the elimination path is also small, under the condition that Rcc is greater than Rcx , the delays of the signal path and the elimination path may never be equal, resulting in inaccurate clock synchronization. Therefore, Rcx cannot be set too large, which reduces the signal amount of the delay time.
  • the equivalent resistance R cc of the elimination path is decoupled from the equivalent resistance R cx of the signal path.
  • the decoupling of the equivalent resistance Rcc of the elimination path and the equivalent resistance Rcx of the signal path can also decouple the first capacitor Cx in the signal path and the second capacitor Cc in the elimination path, and the value range of the second capacitor Cc in the elimination path no longer needs to cover the value range of the first capacitor Cx in the signal path.
  • the size of the second capacitor Cc in the elimination path can be reduced.
  • the second capacitor Cc in the elimination path is composed of on-chip capacitors, and its size is positively correlated with the chip area. Reducing the size of the second capacitor Cc in the elimination path also reduces the chip area and reduces the chip cost.
  • the above-mentioned selection switch can be a MUX circuit, please refer to Figures 7 and 8, wherein Figure 7 is a structural schematic diagram of a MUX circuit provided in the embodiment of the present disclosure, and Figure 8 is a structural schematic diagram of another MUX circuit provided in the embodiment of the present disclosure.
  • the input A in Figure 8 can be a first delayed signal
  • the input B can be a second delayed signal.
  • the output signal waveform of the phase frequency detector PFD in the main path is shown in Figure 9, in which Vosc is the waveform of the reference clock signal, Mux_Sel is the waveform of the two-frequency signal of the reference clock signal, Mux_Sel is also the control signal of the MUX circuit, Vosc_Cx is the waveform of the first delay signal, Vosc_Cc is the waveform of the second delay signal, and the PFD output is the waveform of the output signal of the phase frequency detector PFD.
  • the output of the phase frequency detector PFD is a straight line, which means that the phases of the first delay signal and the second delay signal are exactly the same, and there is no need to adjust the output of the charge pump CP.
  • the delay time of the first delay signal Vosc_Cx also changes relative to the second delay signal Vosc_Cc. For example, when the first capacitor Cx becomes smaller, the delay time of the first delay signal Vosc_Cx becomes shorter relative to the second delay signal Vosc_Cc, as shown in Figure 10.
  • the output of the charge pump CP or the input signal of the ADC sampler will change in amplitude at the 1/2Vosc frequency.
  • the MUX circuit is controlled by the two-frequency signal of the reference clock signal, so that the first delay signal Vosc_Cx and the second delay signal Vosc_Cc exchange the positive and negative access ports once every two-frequency division cycle, so that when the first capacitor Cx changes, the change amplitude is distributed on both the positive and negative sides, which is convenient for detecting the change amount of the first capacitor Cx.
  • one two-frequency division cycle of the reference clock signal is equal to two cycles of the reference clock signal.
  • the capacitance detection circuit includes: a main path, a signal path, and an elimination path.
  • the output end of the signal path is electrically connected to the first input end of the main path
  • the output end of the elimination path is electrically connected to the second input end of the main path
  • the input end of the elimination path is electrically connected to the output end of the main path, wherein the signal path includes a first capacitor
  • the elimination path includes a second capacitor.
  • the main path and the elimination path construct a delay phase-locked loop
  • the first capacitor can also be called a capacitor to be detected.
  • the input of the signal path is a reference clock signal Vosc
  • the first capacitor Cx in the signal path delays the reference clock signal Vosc to obtain the sixth delayed signal Vosc_Cx output by the signal path.
  • the sixth delayed signal Vosc_delay is input into the elimination path, and the second capacitor Cc in the elimination path delays the sixth delayed signal Vosc_delay to obtain the seventh delayed signal Vosc_Cc output by the elimination path.
  • the sixth delayed signal Vosc_delay is a signal delayed relative to the signal path, and the sixth delayed signal can be a preset adjustable signal.
  • the signal path includes a first inverter and a second inverter, and a first capacitor Cx is coupled between the first inverter and the second inverter.
  • the main path includes a phase frequency detector PFD, a charge pump CP (charge pump) and an ADC sampler.
  • the elimination path includes a third inverter and a fourth inverter, and a second capacitor Cc is coupled between the third inverter and the fourth inverter.
  • FIG12 is a schematic diagram of a delay of a reference clock signal provided by an embodiment of the present disclosure.
  • the reference clock signal Vosc is input into the first capacitor Cx through the first inverter, and the first capacitor Cx is charged, so that the voltage of the first capacitor Cx rises from 0 to the voltage value VDD of the power supply.
  • the voltage of the first capacitor Cx exceeds the threshold voltage of the second inverter, the output of the second inverter will drop from VDD to 0. Since it takes time to charge the first capacitor Cx, the reference clock signal Vosc is delayed, and the first delayed signal Vosc_Cx is obtained.
  • the size of the first capacitor Cx changes, the time required for charging will also change, so the delay time also changes.
  • the sixth delayed signal is used as the input signal of the elimination path, which is different from the input signal of the signal path, when the output of the delay phase-locked loop is stable, it is not required that the delay time of the elimination path is equal to the delay time of the signal path. Therefore, when the output of the delay phase-locked loop is stable, it is not necessary to require that the equivalent resistance Rcc of the elimination path is greater than the equivalent resistance Rcx of the signal path.
  • the first capacitor Cx in the signal path is small, even if the second capacitor Cc in the elimination path is also small, the delay of the signal path and the elimination path will never be equal, thereby improving the accuracy of clock synchronization.
  • the equivalent resistance Rcc of the elimination path is decoupled from the equivalent resistance Rcx of the signal path.
  • the equivalent resistance Rcx of the signal path it is not necessary to consider the loop locking range, and the signal amount of the delay time is also enhanced.
  • the first capacitor Cx in the signal path and the second capacitor Cc in the elimination path can also be decoupled, and the value range of the second capacitor Cc in the elimination path no longer needs to cover the value range of the first capacitor Cx in the signal path.
  • the size of the second capacitor Cc in the elimination path can be reduced.
  • the second capacitor Cc in the elimination path is composed of on-chip capacitors, and its size is positively correlated with the chip area. Reducing the size of the second capacitor Cc in the elimination path also reduces the chip area and reduces the chip cost.
  • FIG13 is a structural diagram of a capacitance detection circuit provided by an embodiment of the present disclosure.
  • the capacitance detection circuit includes: a main path, a signal path, and an elimination path.
  • the output end of the signal path is electrically connected to the first input end of the main path
  • the output end of the elimination path is electrically connected to the second input end of the main path
  • the input end of the elimination path is electrically connected to the output end of the main path
  • the signal path includes a first capacitor and a first voltage comparator
  • the elimination path includes a second capacitor and a second voltage comparator.
  • the main path and the elimination path constitute a delay phase-locked loop
  • the first capacitor can also be referred to as a capacitor to be detected.
  • the input of the signal path is a reference clock signal Vosc
  • the first capacitor Cx in the signal path delays the reference clock signal Vosc to obtain the eighth delayed signal Vosc_Cx output by the signal path.
  • the input of the elimination path is the reference clock signal Vosc
  • the second capacitor Cc in the elimination path is loaded with the output signal Dout of the main path in the previous time step.
  • the second capacitor Cc in the elimination path delays the reference clock signal Vosc to obtain the ninth delayed signal Vosc_Cc output by the elimination path.
  • the eighth delayed signal Vosc_Cx and the ninth delayed signal Vosc_Cc are input into the main path to obtain the output signal Dout of the main path at the current time step. It can be seen that since it takes time to charge the first capacitor Cx, the reference clock signal Vosc is delayed to obtain the eighth delayed signal Vosc_Cx.
  • the eighth delayed signal Vosc_Cx and the ninth delayed signal Vosc_Cc are connected to the main path and then output the corresponding output signal Dout.
  • the output signal Dout will be fed back to control the size of the second capacitor Cc on the elimination path.
  • the eighth delay signal Vosc_Cx has the same phase as the ninth delay signal Vosc_Cc, and the output stability of the main path will stabilize to a certain value.
  • the value of the second capacitor Cc of the current time step can be deduced from the output signal Dout of the main path.
  • Figure 14 is another schematic diagram of delaying a reference clock signal provided by an embodiment of the present disclosure.
  • the signal path includes a first inverter and a first voltage comparator, and the first inverter and the first voltage comparator are coupled to the first capacitor Cx.
  • the main path includes a phase frequency detector PFD, a charge pump CP (chargepump) and an ADC sampler.
  • the elimination path includes a second inverter and a second voltage comparator, and the second inverter and the second voltage comparator are coupled to the second capacitor Cc. Since it takes time to charge the first capacitor Cx, the reference clock signal Vosc is delayed to obtain the eighth delayed signal Vosc_Cx. When the size of the first capacitor Cx changes, the time required for charging will also change, so the delay time will also change.
  • the reversal point of the voltage comparator can be controlled by the threshold voltage Vref.
  • the first voltage comparator includes two inputs, one input is the threshold voltage Vref, and the other input is the reference clock signal after passing through the first capacitor.
  • the second voltage comparator includes two inputs, one input is the threshold voltage Vref, and the other input is the reference clock signal after passing through the second capacitor.
  • the flip point of the first voltage comparator and the flip point of the second voltage comparator may be of the same size.
  • the threshold voltage of the first voltage comparator may be equal to the threshold voltage of the second voltage comparator.
  • the tenth delayed signal Vosc_delay is input into the elimination path, and the second capacitor Cc in the elimination path delays the tenth delayed signal Vosc_delay to obtain the second delayed signal output by the elimination path, the ninth delayed signal Vosc_Cc.
  • the tenth delayed signal Vosc_delay is a signal delayed relative to the signal path, and the tenth delayed signal can be a pre-set adjustable signal.
  • the above-mentioned second voltage comparator includes two inputs, one input is the threshold voltage Vref, and the other input is the tenth delayed signal Vosc_delay after passing through the second capacitor.
  • the tenth delayed signal is used as the input signal of the elimination path, which is different from the input signal of the signal path, when the output of the delay phase-locked loop is stable, it is not required that the delay time of the elimination path is equal to the signal path.
  • the delay time of the path Therefore, when the output of the delay locked loop is stable, it is not necessary to require the equivalent resistance R_cc of the elimination path to be greater than the equivalent resistance R_cx of the signal path.
  • the equivalent resistance R_cc of the elimination path is decoupled from the equivalent resistance R_cx of the signal path.
  • the equivalent resistance R_cx of the signal path is set, it is not necessary to consider the loop locking range, and the signal amount of the delay time is also enhanced.
  • the decoupling of the equivalent resistance R_cc of the elimination path and the equivalent resistance R_cx of the signal path can also decouple the first capacitor Cx in the signal path and the second capacitor Cc in the elimination path, and the value range of the second capacitor Cc in the elimination path does not need to cover the value range of the first capacitor Cx in the signal path. Then the size of the second capacitor Cc in the elimination path can be reduced.
  • the second capacitor Cc in the elimination path is composed of on-chip capacitors, and its size is positively correlated with the chip area. Reducing the size of the second capacitor Cc in the elimination path also reduces the chip area and reduces the chip cost.
  • FIG15 is a flow chart of a capacitance detection method based on a delay-locked loop provided in an embodiment of the present disclosure. As shown in FIG15 , the capacitance detection method based on a delay-locked loop includes the following steps: steps 1101 - 1104 .
  • a reference clock signal is delayed through a first capacitor to obtain a first delayed signal.
  • a capacitance detection method based on a delay-locked loop is applied to a capacitance detection circuit, wherein the capacitance detection circuit includes: a main path, a signal path, and an elimination path, wherein the output end of the signal path is electrically connected to the first input end of the main path, the output end of the elimination path is electrically connected to the second input end of the main path, and the input end of the elimination path is electrically connected to the output end of the main path, wherein the signal path includes a first capacitor, and the elimination path includes a second capacitor.
  • the main path and the elimination path constitute a delay-locked loop.
  • the reference clock signal may be a clock signal generated from a clock signal source.
  • a master clock device and a slave clock device may be included.
  • the master clock device may send its own system clock as a reference clock signal to the slave clock device, so that the slave clock device and the master clock device have synchronized clocks.
  • the master clock device may be used as a clock signal source.
  • the delay phase-locked loop in the embodiment of the present disclosure may utilize the clock synchronization between the slave clock device and the master clock device to calculate the value of the first capacitor.
  • the first capacitor may be applied to a capacitance control device, such as a capacitance control device such as a capacitive touch screen or a capacitive signal generator.
  • the above-mentioned delay processing process is the process of charging the first capacitor. Since it takes time to charge the first capacitor, the reference clock signal is delayed and a first delayed signal is obtained. When the size of the first capacitor changes, the charging time will also change, so the delay time also changes.
  • the signal path includes a first inverter and a second inverter, and a first capacitor is coupled between the first inverter and the second inverter.
  • the reference clock signal is input to the first capacitor through the first inverter, delayed by charging the first capacitor, and flipped through the second inverter to obtain a first delayed signal.
  • the signal path includes an inverter and a voltage comparator, and a first capacitor is coupled between the inverter and the voltage comparator.
  • the reference clock signal is input to the first capacitor through the inverter, delayed by charging the first capacitor, and flipped through the voltage comparator to obtain a first delayed signal.
  • the reference clock signal can be delayed through the inverter and the first capacitor to obtain a first signal to be flipped; when the first signal to be flipped reaches the flipping point of the voltage comparator, the first signal to be flipped is flipped to obtain a first delayed signal.
  • the above-mentioned first signal to be flipped is the input signal of the voltage comparator.
  • the first signal to be flipped When the first signal to be flipped reaches the flipping point of the first voltage comparator, the first signal to be flipped is flipped through the voltage comparator to obtain a first delay time. Since the flipping point of the voltage comparator can be controlled by the threshold voltage of the voltage comparator, the threshold voltage of the voltage comparator can be adjusted to be close to the rising edge end point or the falling edge end point of the first signal to be flipped, and the signal amount of the delay time can be increased.
  • the first input signal is the output signal of the main path when the capacitor detection circuit is stable in a closed-loop state.
  • the elimination path also includes a third inverter and a fourth inverter, and a second capacitor is coupled between the third inverter and the fourth inverter.
  • the open-loop state in the process of delaying the reference clock signal and the first input signal through the second capacitor, the first input signal is loaded on the second capacitor in the elimination path, and the reference clock signal is input to the second capacitor through the third inverter.
  • the second delayed signal is charged and delayed by the second capacitor loaded with the first input signal to obtain a second delayed signal.
  • the main path includes a phase frequency detector PFD, a charge pump CP, and an ADC sampler.
  • the first delayed signal and the second delayed signal are input into the main path, and are simultaneously input into the phase frequency detector PFD of the main path, and then input into the charge pump CP after passing through the phase frequency detector PFD, and then sampled by the ADC sampler after passing through the charge pump CP to output the output signal of the current time step.
  • the output signal of the ADC sampler can be loaded onto the second capacitor after digital processing to change the size of the second capacitor.
  • the phase frequency detector PFD when the phases of the first delay signal and the second delay signal are the same, the output of the charge pump CP is stable and unchanged, and the delay time of the first delay signal and the second delay signal are equal.
  • the first capacitor changes, the phases of the first delay signal and the second delay signal change, resulting in a delay time change. Since the second capacitor is loaded with the first input signal as a fixed control word, the second delay signal will not change in phase, and the detected change is the change of the first delay signal, so that the change of the first capacitor can be detected. Therefore, when the first capacitor changes due to external influences, the specific change of the first capacitor can be obtained by analyzing the output signal of the main path of the current time step, thereby realizing the detection of the first capacitor.
  • the first delayed signal and the second delayed signal are input into the main path to obtain the output signal of the main path at the current time step. Since it takes time to charge the first capacitor, the reference clock signal is delayed and the first delayed signal is obtained. When the size of the first capacitor changes, the time required for charging will also change, so the delay time also changes. It is controlled by a fixed control word, and the first input signal loaded therein is a stable output in a closed-loop state. After the first capacitor changes, the second delay signal generated based on the second capacitor does not change, so that the first delay signal and the second delay signal are outputted through the main path and the corresponding output signal only includes the change information of the first delay signal. By analyzing the output signal of the main path at the current time step, the specific change amount of the first capacitor can be obtained, thereby realizing the detection of the first capacitor.
  • the reference clock signal when the capacitance detection circuit is in an open-loop state, the reference clock signal is delayed through the first capacitor to obtain a first delayed signal; the first input signal of the elimination path and the reference clock signal are delayed through the second capacitor to obtain a second delayed signal, the first input signal of the elimination path is the output signal of the main path when the capacitance detection circuit is stable in a closed-loop state; the first delayed signal and the second delayed signal are input into the main path to obtain the output signal of the main path at the current time step; the change value of the first capacitor is calculated according to the output signal of the main path at the current time step.
  • the elimination path is not dependent on the output signal of the main path in the previous time step, so that the control word of the second capacitor of the elimination path is fixed, even if the main path corresponds to multiple output signals in the closed-loop state, it does not affect the change amount of the first capacitor of the signal path in the open-loop state, thereby improving the accuracy of capacitance detection based on the delay phase-locked loop.
  • a candidate output signal of the main path of the capacitance detection circuit when it is stable can be obtained; and the first input signal of the elimination path can be determined from the candidate output signal.
  • the signal loaded by the second capacitance in the elimination path is the output signal of the main path in the previous time step.
  • the capacitance detection circuit is in a closed-loop state, when the loop is stable, there will be multiple stable output signals in the main path, and these stable output signals can all lock the loop so that the main path outputs a stable output signal.
  • the output signal corresponding to the maximum number of loop locks can be selected from the candidate output signals as the first input signal of the elimination path.
  • the reference clock signal can be delayed through the first capacitor to obtain a third delayed signal; the second input signal of the elimination path and the output signal of the main path at the previous time step can be delayed through the second capacitor to obtain a fourth delayed signal.
  • the second input signal of the elimination path is the reference clock signal, or the delayed signal relative to the reference clock signal when the loop is locked in the calibration link; the third delayed signal and the fourth delayed signal are input into the main path, and when the output signal of the main path is stable, the candidate output signal of the main path when the capacitance detection circuit is stable in the closed-loop state is obtained.
  • a fourth delayed signal is obtained, and the third delayed signal and the fourth delayed signal are input into the main path together to obtain the output signal of the current time step.
  • the delayed signal of the reference clock signal is used to replace the reference clock signal and the output signal of the previous time step for delay processing, thereby avoiding clock synchronization errors caused by using the reference clock signal. Accurate, so that the clock synchronization accuracy of the delay locked loop in the closed loop state is improved.
  • the second input signal is a delayed signal relative to the reference clock signal when the loop is locked during the calibration phase.
  • the above calibration link is a link for automatic calibration and delay time calibration before formally detecting the first capacitor and the second capacitor in the delay locked loop.
  • the delayed signal of the reference clock signal obtained through the calibration link replaces the reference clock signal as the second input signal of the elimination path in the closed-loop state, so that when the output of the delay-locked loop is stable, the delay time of the elimination path is not required to be equal to the delay time of the signal path. Therefore, when the output of the delay-locked loop is stable, it is not necessary to require the equivalent resistance of the elimination path to be greater than the equivalent resistance of the signal path.
  • the first capacitor in the signal path is small, even if the second capacitor in the elimination path is also small, the delay of the signal path and the elimination path will not be forever equal, thereby improving the accuracy of clock synchronization.
  • the previous time step refers to the time step corresponding to the previous detection of the first capacitor and the second capacitor. For example, when the first capacitor and the second capacitor are detected at time t, the output signal of the main path at the previous time step is the output signal of the main path at time t-1.
  • the elimination path includes a third inverter and a fourth inverter, and a second capacitor is coupled between the third inverter and the fourth inverter.
  • the output signal of the main path at the previous time step is directly loaded on the second capacitor, and the second input signal is input to the second capacitor through the third inverter.
  • the second delayed signal is charged and delayed by the second capacitor loaded with the output signal of the main path at the previous time step to obtain a fourth delayed signal.
  • the third delayed signal corresponding to the previous time step and the fourth delayed signal of the previous time step are simultaneously input into the phase frequency detector PFD of the main path, and then input into the charge pump CP after passing through the phase frequency detector PFD. After passing through the charge pump CP, the output signal of the previous time step is sampled by the ADC sampler and output.
  • the delay phase-locked loop can also be calibrated before the step of delaying the second input signal and the output signal of the main path at the previous time step through the second capacitor to obtain a fourth delayed signal.
  • the delay phase-locked loop can also be calibrated.
  • the loop when the loop is locked, the delayed signal of the reference clock signal is obtained as the second input signal.
  • the delay locked loop before formally detecting the first capacitor and the second capacitor in the delay locked loop, can be automatically calibrated and the delay time calibrated to determine the delay time of the second input signal relative to the reference clock signal when the loop is locked.
  • the second input signal is the reference clock signal plus the delay time obtained by automatic calibration and delay time calibration.
  • a suitable second input signal can be used to help the delay locked loop to quickly reach a stable state when the first capacitor and the second capacitor are formally detected, thereby increasing the loop locking speed.
  • a target operating point for loop locking can be set; when the loop is locked at the target operating point, a delayed signal of the reference clock signal is acquired as the second input signal.
  • the target operating point of the loop lock refers to the operating point when the delay phase-locked loop is stable.
  • the phase frequency detector PFD when the phase of the third delay signal is the same as the phase of the fourth delay signal, the output of the charge pump CP is stable and unchanged, and the output of the ADC sampler is also stable at a certain value, which is the operating point when the delay phase-locked loop is stable.
  • the delay phase-locked loop is controlled to be locked, and the values of the first capacitor and the second capacitor are locked so that they no longer change.
  • the phase of the third delay signal and the fourth delay signal no longer changes, and the phase remains the same, thereby completing the synchronization of the clock signal at this operating point.
  • the delay locked loop can be automatically calibrated and the delay time can be calibrated first to determine the operating point of the delay locked loop when the loop is locked as the target operating point. At this time, the acquired delay time is added to the reference clock signal to obtain the delayed signal of the reference clock signal as the second input signal.
  • the delay locked loop can be quickly locked at the target operating point through the second input signal, thereby improving the locking speed of the delay locked loop.
  • the initial value of the second capacitor of the target delay locked loop can be predicted by the historical change value of the second capacitor.
  • the historical change value of the second capacitor can be input into the pre-trained first timing network prediction to obtain the initial value of the second capacitor of the target delay locked loop by default.
  • the initial value of the second capacitor of the target delay phase-locked loop is predicted by using the historical change value of the second capacitor. By adjusting the initial value of the second capacitor, the delay phase-locked loop can be quickly stabilized during the calibration phase, thereby helping the delay phase-locked loop to quickly lock the loop.
  • the predicted delay time of the target delay-locked loop can be predicted by the historical delay time.
  • the historical change value of the first capacitor and the historical change value of the second capacitor can be input into the pre-trained second timing network prediction to obtain the predicted delay time of the target delay-locked loop by default.
  • the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same operating environment parameters, the reference delay phase-locked loop and the target delay phase-locked loop have similar operating parameters.
  • the historical delay time is used to predict the predicted delay time of the target delay phase-locked loop, and the predicted delay time is added to the reference signal to obtain a predicted second input signal.
  • the predicted second input signal can help the delay phase-locked loop to quickly stabilize during the calibration phase, thereby helping the delay phase-locked loop to quickly lock the loop.
  • the change value of the second capacitor can be calculated according to the output signal of the current time step, and the second capacitor can be adjusted according to the change value of the second capacitor, so that the delay locked loop is loop locked.
  • the delay time obtained during the automatic calibration is added to the reference clock signal to obtain the second delay signal, which can help the delay locked loop to quickly stabilize, thereby helping the delay locked loop to quickly lock the loop.
  • the output signal of the main path will also change.
  • the size of the second capacitor is adjusted by the change of the output signal of the main path, so that the output of the delay locked loop is stabilized again, and the delay locked loop is loop locked.
  • the input signal of the elimination channel is delayed relative to the input signal of the signal channel, that is, there is a delay time between the second delayed signal and the reference clock signal, and the delay time is determined in the calibration link before the formal capacitance detection.
  • the elimination path further includes a state switch
  • the state switch is electrically connected to the input end of the second capacitor, and before the step of delaying the reference clock signal through the first capacitor to obtain the first delayed signal when the capacitor detection circuit is in an open-loop state, the state switch can also be adjusted to switch the capacitor detection circuit from a closed-loop state to an open-loop state, or to switch the capacitor detection circuit from an open-loop state to a closed-loop state.
  • the switching between the open-loop state and the closed-loop state can be controlled by the state switch, and the state switch can be set between the input end of the second capacitor and the output end of the main path.
  • the state switch When the state switch connects the input end of the second capacitor and the output end of the main path, it switches to a closed-loop state, and when the state switch disconnects the input end of the second capacitor and the output end of the main path, it switches to an open-loop state.
  • the input end of the main path is electrically connected to a selection switch.
  • the first delay signal and the second delay signal can be selected by the selection switch to obtain the target signal; the target signal is input into the main path to obtain the output signal of the main path at the current time step.
  • the selection switch includes positive and negative access ports, and the positive and negative access ports of the first delay signal and the second delay signal can be switched by the selection switch. It can be understood that the input signal of the charge pump CP is reversed at the positive and negative access ports according to a preset period by the selection switch.
  • a divided signal of the reference clock signal can be obtained; the first delayed signal and the second delayed signal are selected by controlling the selection switch through the divided signal to obtain the target signal.
  • the frequency-divided signal may be an N-times-divided signal, and one period of the N-times-divided signal is equal to N periods of the reference clock signal.
  • the frequency division signal can be a two-frequency division signal.
  • One cycle of the two-frequency division signal is equal to two cycles of the reference clock signal.
  • the selection switch is controlled by the two-frequency division signal, and the positive and negative access ports of the first delay signal and the second delay signal are switched once in each two-frequency division signal cycle.
  • the input signal of the charge pump CP (equivalent to the output signal of the phase frequency detector PFD) is a straight line, and when the first delay signal and the second delay signal are in different phases, the adjacent changes are distributed on both sides of the straight line, which is convenient for measuring the change of the first delay signal.
  • the selection switch includes a first selector and a second selector.
  • the first selector and the second selector can be controlled by the binary frequency-division signal, and the first delayed signal and the second delayed signal can be selected by the first selector and the second selector to obtain the target signal.
  • input A may be the first delayed signal
  • input B may be the second delayed signal
  • input A delayed signal is connected to the access port No. 1 of the first selector and the second selector respectively
  • a second delayed signal is connected to the access port No. 2 of the first selector and the second selector respectively.
  • the input A is connected to the positive access port of the charge pump CP, and the input B is connected to the negative access port of the charge pump CP;
  • the above-mentioned target signal refers to the first delayed signal and the second delayed signal as signals of the input states corresponding to different access ports.
  • the main path includes a frequency detector and a charge pump
  • the output end of the frequency detector is electrically connected to the input end of the charge pump
  • the output end of the selection switch is electrically connected to the input end of the frequency detector
  • the output end of the selection switch is electrically connected to the input end of the charge pump.
  • phase difference between the first delay signal and the second delay signal in the output signal of the frequency detector is not 0, since the control word of the second capacitor is fixed by the first input signal, the phase of the second delay signal will not change, and it can be obtained that the phase difference between the first delay signal and the second delay signal is caused by the change of the first delay signal, so it can be determined that the first capacitor has changed.
  • the phase difference between the first delay signal and the second delay signal is caused by the change of the first capacitor, so the change of the first capacitor can be calculated by the phase difference between the first delay signal and the second delay signal.
  • the target frequency in the output signal of the charge pump can be predetermined; when the phase difference between the first delay signal and the second delay signal in the output signal of the frequency detector is not 0, the signal amplitude is detected at the target frequency in the output signal of the charge pump to obtain the change value of the first capacitance.
  • the above-mentioned target frequency can be the 1/2Vosc frequency of the charge pump CP output signal, and the change of the first capacitance can be obtained by detecting the signal amplitude at the 1/2Vosc frequency of the charge pump CP output signal.
  • Another capacitance detection method based on a delay locked loop is provided in an embodiment of the present disclosure, and includes steps 601-604.
  • a capacitance detection method based on a delay-locked loop is applied to a capacitance detection circuit, wherein the capacitance detection circuit includes: a main path, a signal path, and an elimination path, wherein the output end of the signal path is electrically connected to the first input end of the main path, the output end of the elimination path is electrically connected to the second input end of the main path, and the input end of the elimination path is electrically connected to the output end of the main path, wherein the signal path includes a first capacitor, and the elimination path includes a second capacitor.
  • the main path and the elimination path form a delay-locked loop.
  • the limitation of the reference clock signal and the description of the delay processing process can refer to the corresponding description in step 1101 of the above-mentioned capacitance detection method based on the delay locked loop, and will not be repeated here.
  • the signal path includes a first inverter and a second inverter, and a first capacitor is coupled between the first inverter and the second inverter.
  • the reference clock signal is input to the first capacitor through the first inverter, delayed by charging the first capacitor, and flipped through the second inverter to obtain a first delayed signal.
  • the sixth delayed signal is a delayed signal relative to the reference clock signal when the loop is locked in the calibration link.
  • the sixth delayed signal obtained through the calibration link replaces the reference clock signal as the input signal of the elimination path, so that when the output of the delay phase-locked loop is stable, it is not required that the delay time of the elimination path is equal to the delay time of the signal path. Therefore, when the output of the delay phase-locked loop is stable, it is not necessary to require that the equivalent resistance of the elimination path is greater than the equivalent resistance of the signal path.
  • the first capacitor in the signal path is small, even if the second capacitor in the elimination path is also small, the delay of the signal path and the elimination path will never be equal, thereby improving the accuracy of clock synchronization.
  • the previous time step refers to the time step corresponding to the previous detection of the first capacitor and the second capacitor. For example, when the first capacitor and the second capacitor are detected at time t, the output signal of the main path at the previous time step is the output signal of the main path at time t-1.
  • the elimination path includes a third inverter and a fourth inverter, and a second capacitor is coupled between the third inverter and the fourth inverter.
  • the output signal of the main path at the previous time step is directly loaded on the second capacitor, and the sixth delayed signal is input to the second capacitor through the third inverter.
  • the sixth delayed signal is charged and delayed by the second capacitor loaded with the output signal of the main path at the previous time step to obtain a seventh delayed signal.
  • the fifth delayed signal corresponding to the previous time step and the seventh delayed signal of the previous time step are simultaneously input into the phase frequency detector PFD of the main path, and then input into the charge pump CP after passing through the phase frequency detector PFD. After passing through the charge pump CP, the output signal of the previous time step is sampled by the ADC sampler and output.
  • the main path includes a phase frequency detector PFD, a charge pump CP, and an ADC sampler.
  • the fifth delayed signal and the seventh delayed signal are input into the main path, and are simultaneously input into the phase frequency detector PFD of the main path, and then input into the charge pump CP after passing through the phase frequency detector PFD, and then sampled and output by the ADC sampler after passing through the charge pump CP to output the output signal of the current time step.
  • the output signal of the ADC sampler can be loaded onto the second capacitor after digital processing to change the size of the second capacitor.
  • the charge pump The output of CP is stable and unchanged, and the output of ADC sampler is also stable at a certain value.
  • the control delay phase-locked loop is locked, and the value of the second capacitor is locked and no longer changes.
  • the phase of the fifth delay signal and the seventh delay signal no longer changes, and the phase remains the same, completing the synchronization of the clock signal.
  • the specific change of the first capacitor can be obtained by analyzing the output signal of the main path of the current time step, thus realizing the detection of the first capacitor.
  • the fifth delay signal and the seventh delay signal are input into the main path to obtain the output signal of the main path at the current time step. Since it takes time to charge the first capacitor, the reference clock signal is delayed to obtain the fifth delay signal. When the size of the first capacitor changes, the time required for charging will also change, so the delay time also changes.
  • the fifth delay signal and the seventh delay signal pass through the main path and output the corresponding output signal. The output signal will be fed back to control the size of the second capacitor on the elimination path.
  • the fifth delay signal has the same phase as the phase, and the output stability of the main path will stabilize to a certain value.
  • the value of the second capacitor at the current time step can be deduced from the output signal of the main path.
  • the delay time of the elimination channel is positively correlated with the delay time of the signal path. Therefore, by analyzing the output signal of the main path, the specific change amount of the first capacitor can be obtained, so that the detection of the first capacitor is realized.
  • a reference clock signal is delayed through the first capacitor to obtain a fifth delayed signal; a sixth delayed signal and an output signal of the main path at a previous time step are delayed through the second capacitor to obtain a seventh delayed signal, wherein the sixth delayed signal is a delayed signal relative to the reference clock signal when the loop is locked in a calibration link; the fifth delayed signal and the seventh delayed signal are input into the main path to obtain the output signal of the main path at a current time step; when the output signal of the main path at the current time step is stable, the value of the first capacitor is calculated according to the output signal of the current time step.
  • the change value of the first capacitor and the change value of the second capacitor are calculated according to the output signal of the current time step, the second capacitor can be adjusted according to the change value of the second capacitor, and the sixth delayed signal is used to replace the reference clock signal and the output signal of the previous time step for delay processing, so as to improve the capacitance detection range of the delay phase-locked loop while avoiding the situation that the delay of the signal path and the elimination path cannot be equal due to the use of the reference clock signal, so that the delay phase-locked loop fails to lock.
  • the delay phase-locked loop can also be calibrated before the step of delaying the sixth delayed signal and the output signal of the main path in the previous time step through the second capacitor to obtain the seventh delayed signal.
  • the delay phase-locked loop can also be calibrated.
  • the delayed signal of the reference clock signal is obtained as the sixth delayed signal.
  • the delay locked loop before formally detecting the first capacitor and the second capacitor in the delay locked loop, can be automatically calibrated and the delay time calibrated to determine the delay time of the sixth delay signal relative to the reference clock signal when the loop is locked.
  • the sixth delay signal is the reference clock signal plus the delay time obtained by the automatic calibration and the delay time calibration.
  • a suitable sixth delay signal can be used to help the delay locked loop to quickly reach a stable state when the first capacitor and the second capacitor are formally detected, thereby improving the loop locking speed.
  • a target operating point for loop locking can be set; when the loop is locked at the target operating point, the delayed signal of the reference clock signal is obtained as the sixth delayed signal.
  • the target operating point of the loop lock refers to the operating point when the delay phase-locked loop is stable.
  • the phase frequency detector PFD when the phase of the fifth delayed signal is the same as the phase of the seventh delayed signal, the output of the charge pump CP is stable, and the output of the ADC sampler is also stable at a certain value, which is the operating point when the delay phase-locked loop is stable.
  • the delay phase-locked loop is controlled to be locked, and the values of the locked first capacitor and the second capacitor no longer change, then the phase of the fifth delayed signal and the seventh delayed signal no longer changes, and the phase remains the same, completing the synchronization of the clock signal at this operating point.
  • the delay locked loop can be automatically calibrated and the delay time can be calibrated first to determine the operating point of the delay locked loop when the loop is locked as the target operating point. At this time, the acquired delay time is added to the reference clock signal to obtain a delayed signal of the reference clock signal as the sixth delayed signal.
  • the delay locked loop can be quickly locked at the target operating point through the sixth delayed signal, thereby improving the locking speed of the delay locked loop.
  • the target working point for loop locking may be determined by a preset search method.
  • the preset search method can be one of a binary search method, a traversal search method and an exhaustive search method, preferably a binary search method.
  • an ordered table of delay times can be pre-set, and a suitable delay time can be found in the ordered table by the binary search method, so that the delay-locked loop performs loop locking at a better working point. Searching for delay time in the ordered table of delay times by the binary search method has the advantages of fewer comparisons, faster search speed, better average performance, and less system memory occupation.
  • the delay time in the above-mentioned ordered table can be arranged in ascending order, and the delay time recorded in the middle position of the table is used for the calibration link. If the delay phase-locked loop performs loop locking at the same working point, the search is successful; otherwise, the table is divided into two sub-tables, front and rear, using the middle position record. If the working point of the delay time recorded in the middle position is greater than the working point of the delay phase-locked loop in the calibration link, the front sub-table is further searched, otherwise the rear sub-table is further searched. Repeat the above process until a delay time that meets the conditions is found, making the search successful, or until the sub-table does not exist, in which case the search is unsuccessful.
  • the delay time whose working point is closest to the working point of the delay phase-locked loop in the calibration link can be selected and added to the reference clock signal to obtain the sixth delay signal, and then the target working point of the loop lock in the calibration link is determined by the sixth delay signal.
  • the main path includes a third capacitor, and in the step of setting the target operating point of the loop lock, the voltage of the power supply can be obtained. value; with the voltage value of the third capacitor being close to half the voltage value of the power supply when the loop is locked as the target, the target operating point of the loop lock is determined.
  • the voltage value VDD of the power supply is the target operating point when the loop is locked and the voltage value of the third capacitor is close to 1/2VDD in the calibration link.
  • the delay time of the delay locked loop at the target operating point is calculated, and the delay time is added to the reference clock signal to obtain the sixth delay signal.
  • the delay time obtained in the calibration link is added to the reference clock signal, which can help the delay locked loop to stabilize quickly.
  • the main path includes a third capacitor.
  • the voltage value of the third capacitor can be analyzed based on the voltage value of the power supply with the goal of increasing the signal amount; the target operating point of the loop lock is determined based on the voltage value of the third capacitor.
  • the above signal quantity is the signal quantity of the delay time
  • the data of the delay phase-locked loop with the same structure can be used for big data analysis to analyze the relationship between the voltage value of the third capacitor, the voltage value of the power supply, and the signal quantity of the delay time, so as to find the best voltage value of the third capacitor that maximizes the signal quantity of the delay time, so that in the calibration link, when the delay phase-locked loop is locked in the loop, the voltage value of the third capacitor is at the best voltage value.
  • Adding the delay time obtained in the calibration link to the reference clock signal can help the delay phase-locked loop to stabilize quickly.
  • the value of the second capacitor when the value of the first capacitor changes, the value of the second capacitor can be adjusted by changing the output signal of the main path, so that the loop is locked.
  • the value of the second capacitor can be adjusted so that the delay phase-locked loop is loop-locked at different operating points. At this time, multiple candidate delay times can be obtained.
  • the delay time at this time is determined to be the target candidate delay time.
  • the target candidate delay time and the reference clock signal can be added to obtain a sixth delay signal. Adding the delay time obtained by the calibration link to the reference clock signal can help the delay phase-locked loop to stabilize quickly.
  • the current usage environment parameters in the target delay phase-locked loop can be obtained; based on the current usage environment parameters, the historical change value of the second capacitor of the reference delay phase-locked loop is obtained, and the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same usage environment parameters; based on the historical change value of the second capacitor, the initial value of the second capacitor of the target delay phase-locked loop is predicted; and by adjusting the initial value of the second capacitor, multiple candidate delay times are obtained.
  • the above-mentioned current use environment parameters may be the operating conditions to be applied by the delay locked loop, such as operating frequency, operating temperature, master clock device parameters and slave clock device parameters, etc.
  • the initial value of the second capacitor of the target delay locked loop can be predicted by the historical change value of the second capacitor.
  • the historical change value of the second capacitor can be input into the pre-trained first timing network prediction to preset the initial value of the first capacitor and the initial value of the second capacitor of the target delay locked loop.
  • the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same usage environment parameters, the reference delay phase-locked loop and the target delay phase-locked loop have similar operating parameters.
  • the initial value of the second capacitor of the target delay phase-locked loop is predicted based on the historical change value of the second capacitor. By adjusting the initial value of the second capacitor, the delay phase-locked loop can be quickly stabilized during the calibration phase, thereby helping the delay phase-locked loop to quickly lock the loop.
  • the current use environment parameters in the target delay phase-locked loop can be obtained; according to the current use environment parameters, the historical delay time of the reference delay phase-locked loop is obtained, and the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same use environment parameters; according to the historical delay time, the delay time of the target delay phase-locked loop is predicted by a pre-trained prediction network to obtain a predicted delay time; with the predicted delay time as the initial delay time, the value of the second capacitor is adjusted to obtain multiple candidate delay times; according to when the loop is locked at the target operating point, the target candidate delay time is determined from multiple candidate delay times or initial delay times; according to the target candidate delay time and the reference clock signal, the sixth delay signal is determined.
  • step of obtaining the sixth delay signal in the embodiment of the present disclosure can also be used to obtain the second input signal of the delay signal relative to the above-mentioned reference clock signal when the loop is locked in the calibration link in the above-mentioned embodiment.
  • the predicted delay time of the target delay-locked loop can be predicted by the historical delay time.
  • the historical change value of the second capacitor can be input into the pre-trained second timing network prediction to obtain the predicted delay time of the target delay-locked loop by default.
  • the historical delay time is used to predict the predicted delay time of the target delay phase-locked loop, and the predicted delay time is added to the reference signal to obtain a predicted sixth delay signal.
  • the predicted sixth delay signal can help the delay phase-locked loop to quickly stabilize during the calibration phase, thereby helping the delay phase-locked loop to quickly lock the loop.
  • the change value of the first capacitor and the change value of the second capacitor can be calculated according to the output signal of the current time step, and the second capacitor can be adjusted according to the change value of the second capacitor, so that the delay locked loop is loop locked.
  • the delay time obtained during the automatic calibration is added to the reference clock signal to obtain the sixth delay signal, which can help the delay locked loop to quickly stabilize, thereby helping the delay locked loop to quickly lock the loop.
  • the present disclosure provides another capacitance detection method based on a delay locked loop, including steps 501 - 504 .
  • capacitance detection based on a delay-locked loop is applied to a capacitance detection circuit, the capacitance detection circuit comprising: a main path, a signal path and an elimination path, the output end of the signal path is electrically connected to the first input end of the main path, the output end of the elimination path is electrically connected to the second input end of the main path, the input end of the elimination path is electrically connected to the output end of the main path, wherein the signal path comprises a first capacitor, and the elimination path comprises a second capacitor.
  • the main path and the elimination path constitute a delay-locked loop.
  • the above-mentioned delay processing process is the process of charging the first capacitor. Since it takes time to charge the first capacitor, the reference clock signal is delayed, and the eighth delayed signal is obtained. When the size of the first capacitor changes, the charging time will also change, so the delay time also changes.
  • the signal path includes a first inverter and a first voltage comparator, and a first capacitor is coupled between the first inverter and the first voltage comparator.
  • the reference clock signal is input to the first capacitor through the first inverter, delayed by charging the first capacitor, and flipped by the first voltage comparator to obtain an eighth delayed signal.
  • the flip point of the first voltage comparator is adjusted according to the threshold voltage of the first voltage comparator, and the threshold voltage of the first voltage comparator can be set near the voltage value VDD of the power supply.
  • the reference clock signal in the step of delaying the reference clock signal through the first capacitor and the first voltage comparator in sequence to obtain an eighth delayed signal, can be delayed through the first capacitor to obtain a second signal to be flipped; when the second signal to be flipped reaches the flipping point of the first voltage comparator, the second signal to be flipped is flipped to obtain the eighth delayed signal.
  • the input signal of the elimination path and the output signal of the main path in the previous time step are delayed in turn through the second capacitor and the second voltage comparator to obtain a ninth delayed signal
  • the output signal of the main path in the previous time step is loaded onto the second capacitor
  • the input signal of the elimination path is delayed through the second capacitor loaded with the output signal of the main path in the previous time step to obtain a third signal to be flipped; when the third signal to be flipped reaches the flipping point of the second voltage comparator, the third signal to be flipped is flipped to obtain a ninth delayed signal.
  • the second signal to be flipped is an input signal of the first voltage comparator.
  • the second signal to be flipped is flipped by the first voltage comparator to obtain the first delay time. Since the flipping point of the first voltage comparator can be controlled by the threshold voltage of the first voltage comparator, the threshold voltage of the first voltage comparator can be adjusted to connect to the rising edge end point or the falling edge end point of the second signal to be flipped, and the signal amount of the delay time can be increased.
  • the target flipping point of the first voltage comparator can be determined by taking the rising edge endpoint of the first capacitor or the falling edge endpoint of the first capacitor or the voltage value of the power supply as the approach point; and the flipping point of the first voltage comparator can be adjusted to the target flipping point of the first voltage comparator by controlling the threshold voltage of the first voltage comparator.
  • the threshold voltage of the first voltage comparator can be controlled to adjust the flip point of the first voltage comparator so that the first voltage comparator works at a better flip point.
  • the rising edge end point of the above-mentioned first capacitor can be understood as the rising edge end point of the second signal to be flipped, and the second signal to be flipped no longer changes at the rising edge
  • the falling edge end point of the above-mentioned first voltage can be understood as the falling edge end point of the second signal to be flipped, and the second signal to be flipped no longer changes at the falling edge.
  • the approach point refers to the signal point that the adjustment flip point approaches from the rising edge or the falling edge in the process of adjusting the flip point of the first voltage comparator. It should be noted that in the working principle of the inverter, by setting the approach point to VDD/2, in the actual application of the inverter, the flip point is usually set near VDD/2.
  • the phase difference detection type of the main path can be determined first, and the type of the approach point can be determined according to the phase difference detection type of the main path.
  • the types of the approach points include the rising edge endpoint of the first capacitor, the falling edge endpoint of the first capacitor, and the voltage value of the power supply.
  • the type of the proximity point when the phase difference detection type of the main path is to detect the phase difference of the rising edge, the type of the proximity point can be the rising edge end point of the first capacitor; when the phase difference detection type of the main path is to detect the phase difference of the falling edge, the type of the proximity point can be the falling edge end point of the first capacitor; when the rising edge of the first comparator corresponds to the rising edge of the second signal to be flipped, and the phase difference detection type of the main path is to detect the phase difference between the rising edges of the two signals, then the type of the proximity point can be the voltage value of the power supply.
  • the main path includes a phase frequency detector (PFD), a charge pump (CP), and an ADC sampler.
  • PFD phase frequency detector
  • CP charge pump
  • ADC sampler an ADC sampler
  • the type of the proximity point is determined according to the phase difference detection type of the main path, and the flip point of the first voltage comparator can be adjusted more accurately so that the flip point of the first voltage comparator is set near the proximity point, thereby increasing the signal amount of the delay time.
  • the signal amount of the delay time can be determined; according to the signal amount of the delay time, the distance value between the flipping point and the approach point of the first voltage comparator is adjusted; according to the distance value between the flipping point and the approach point of the first voltage comparator, the target flipping point of the first voltage comparator is determined.
  • the target switching point of the first voltage comparator is determined.
  • the signal amount of the delay time can be determined according to the specific use environment. For example, for a use environment with high accuracy requirements, the signal amount of the delay time can be set larger, and for a use environment with low accuracy requirements, the signal amount of the delay time can be set smaller.
  • the threshold voltage corresponding to the flip point can be calculated based on the signal amount of the delay time, so as to adjust the flip point of the first voltage comparator by adjusting the threshold voltage of the first voltage comparator.
  • the threshold voltage of the first voltage comparator may be adjusted manually by a user, or may be automatically adjusted according to a precision level selected by a user.
  • the signal amount of the delay time can be determined; according to the signal amount of the delay time, the ratio value of the flipping point and the approach point of the first voltage comparator is adjusted; according to the ratio value of the flipping point and the approach point of the first voltage comparator, the target flipping point of the first voltage comparator is determined.
  • the above a can represent the ratio of the flip point to the voltage value VDD of the power supply. Under the condition of a certain equivalent resistance, the closer a is to 1, the greater the change in delay time, so that the signal amount of the delay time change is greater. It can be further understood that the closer the flip point aVDD is to the voltage value VDD of the power supply, the greater the change in delay time, so that the signal amount of the delay time change is greater.
  • the signal amount of the above delay time can be determined by a specific use environment or user use requirements.
  • the signal amount of the above delay time can be set larger, and for a use environment with low accuracy requirements or user use requirements, the signal amount of the above delay time can be set smaller.
  • the ratio of the flip point of the first voltage comparator to the close point can be calculated based on the signal amount of the delay time, so as to calculate the threshold voltage corresponding to the flip point, so as to adjust the flip point of the first voltage comparator by adjusting the threshold voltage of the first voltage comparator.
  • the input signal of the cancellation path may be a reference clock signal, that is, the input signal of the cancellation path is the same as the input signal of the signal path.
  • the flipping point of the second voltage comparator is the same as the flipping point of the first voltage comparator.
  • the threshold voltage of the second voltage comparator is equal to the threshold voltage of the first voltage comparator.
  • the first voltage comparator and the second voltage comparator can be adjusted by the same threshold voltage control signal so that the first voltage comparator and the second voltage comparator operate at the same flipping point.
  • the above calibration link is a link for automatic calibration and delay time calibration before formally detecting the first capacitor and the second capacitor in the delay locked loop.
  • the tenth delayed signal obtained through the calibration link replaces the reference clock signal as the input signal of the elimination path, so that when the output of the delay-locked loop is stable, the delay time of the elimination path is not required to be equal to the delay time of the signal path. Therefore, when the output of the delay-locked loop is stable, it is not necessary to require the equivalent resistance of the elimination path to be greater than the equivalent resistance of the signal path.
  • the first capacitor in the signal path is small, even if the second capacitor in the elimination path is also small, the delay of the signal path and the elimination path will not be forever equal, thereby improving the accuracy of clock synchronization.
  • the previous time step refers to the time step corresponding to the previous detection of the first capacitor and the second capacitor. For example, when the first capacitor and the second capacitor are detected at time t, the output signal of the main path at the previous time step is the output signal of the main path at time t-1.
  • the elimination path includes a second inverter and a second voltage comparator, and a second capacitor is coupled between the second inverter and the second voltage comparator.
  • the output signal of the main path in the previous time step is directly loaded on the second capacitor, and the input signal of the elimination path is input to the second capacitor through the second inverter.
  • the input signal of the elimination path is charged and delayed by the second capacitor loaded with the output signal of the main path in the previous time step to obtain a ninth delayed signal.
  • the eighth delayed signal corresponding to the previous time step and the ninth delayed signal of the previous time step are simultaneously input into the phase frequency detector PFD of the main path, and then input into the charge pump CP after passing through the phase frequency detector PFD. After passing through the charge pump CP, the output signal of the previous time step is sampled by the ADC sampler and output.
  • the main path includes a phase frequency detector PFD, a charge pump CP, and an ADC sampler.
  • the eighth delayed signal and the ninth delayed signal are input into the main path, and are simultaneously input into the phase frequency detector PFD of the main path, and then input into the charge pump CP after passing through the phase frequency detector PFD, and then sampled by the ADC sampler after passing through the charge pump CP to output the output signal of the current time step.
  • the output signal of the ADC sampler can be loaded onto the second capacitor after digital processing to change the size of the second capacitor.
  • the value of the first capacitor is calculated according to the output signal at the current time step.
  • the phase frequency detector PFD when the eighth delay signal and the ninth delay signal have the same phase, the output of the charge pump CP remains stable, and the output of the ADC sampler also remains stable at a certain value. At this time, the control delay phase-locked loop is locked, and the values of the first capacitor and the second capacitor are locked so that they no longer change. Then, the phases of the eighth delay signal and the ninth delay signal also no longer change, and the phases remain the same, completing the synchronization of the clock signal.
  • the specific change amount of the first capacitor can be obtained by analyzing the output signal of the main path of the current time step, thereby realizing the detection of the first capacitor.
  • the eighth delay signal and the ninth delay signal are input into the main path to obtain the output signal of the main path at the current time step. Since it takes time to charge the first capacitor, the reference clock signal is delayed to obtain the eighth delay signal. When the size of the first capacitor changes, the time required for charging will also change, so the delay time also changes.
  • the eighth delay signal and the ninth delay signal pass through the main path and output the corresponding output signal. The output signal will be fed back to control the size of the second capacitor on the elimination path.
  • the eighth delay signal has the same phase as the ninth delay signal, and the output stability of the main path will stabilize to a certain value.
  • the value of the second capacitor at the current time step can be deduced from the output signal of the main path.
  • the delay time of the elimination channel is positively correlated with the delay time of the signal path. Therefore, by analyzing the output signal of the main path, the specific change amount of the first capacitor can be obtained, so that the detection of the first capacitor is realized.
  • the reference clock signal is delayed through the first capacitor and the first voltage comparator in sequence to obtain an eighth delayed signal; the reference clock signal and the output signal of the main path in the previous time step are delayed through the second capacitor and the second voltage comparator in sequence to obtain a ninth delayed signal; the eighth delayed signal and the ninth delayed signal are input into the main path to obtain the output signal of the main path in the current time step; when the output signal of the main path in the current time step is stable, the value of the first capacitor is calculated according to the output signal of the current time step.
  • the tenth delayed signal is used instead of the reference clock signal and the output signal of the previous time step for delay processing, thereby avoiding the inaccurate clock synchronization caused by using the reference clock signal, so that the clock synchronization accuracy of the delay locked loop is improved.
  • the delay phase-locked loop can also be calibrated before the step of delaying the tenth delayed signal and the output signal of the main path in the previous time step through the second capacitor to obtain the ninth delayed signal.
  • the delay phase-locked loop can also be calibrated.
  • the delayed signal of the reference clock signal is obtained as the tenth delayed signal.
  • the delay locked loop before formally detecting the first capacitor and the second capacitor in the delay locked loop, can be automatically calibrated and the delay time calibrated to determine the delay time of the tenth delay signal relative to the reference clock signal when the loop is locked.
  • the tenth delay signal is the reference clock signal plus the delay time obtained by the automatic calibration and the delay time calibration.
  • a suitable tenth delay signal can be used to help the delay locked loop to quickly reach a stable state when the first capacitor and the second capacitor are formally detected, thereby improving the loop locking speed.
  • a target operating point for loop locking can be set; when the loop is locked at the target operating point, the delayed signal of the reference clock signal is obtained as the ninth delayed signal.
  • the target operating point of the loop lock refers to the operating point when the delay phase-locked loop is stable.
  • the phase frequency detector PFD when the phase of the eighth delayed signal is the same as the phase of the ninth delayed signal, the output of the charge pump CP is stable and unchanged, and the output of the ADC sampler is also stable at a certain value, which is the operating point when the delay phase-locked loop is stable.
  • the delay phase-locked loop is controlled to be locked, and the values of the locked first capacitor and the second capacitor no longer change, then the phase of the eighth delayed signal and the ninth delayed signal no longer changes, and the phase remains the same, thereby completing the synchronization of the clock signal at this operating point.
  • the delay locked loop can be automatically calibrated and the delay time can be calibrated first to determine the operating point of the delay locked loop when the loop is locked as the target operating point. At this time, the acquired delay time is added to the reference clock signal to obtain the delayed signal of the reference clock signal as the tenth delay signal.
  • the delay locked loop can be quickly locked at the target operating point through the tenth delay signal, thereby improving the locking speed of the delay locked loop.
  • the above-mentioned current use environment parameters may be the operating conditions to be applied by the delay locked loop, such as operating frequency, operating temperature, master clock device parameters and slave clock device parameters, etc.
  • the predicted delay time of the target delay-locked loop can be predicted by the historical delay time.
  • the historical change value of the first capacitor and the historical change value of the second capacitor can be input into the pre-trained second timing network prediction to obtain the predicted delay time of the target delay-locked loop by default.
  • the change value of the first capacitor and the change value of the second capacitor can be calculated according to the output signal of the current time step, and the first capacitor and the second capacitor can be adjusted according to the change value of the first capacitor and the change value of the second capacitor, so that the delay locked loop is loop locked.
  • the delay time obtained during the automatic calibration is added to the reference clock signal to obtain the tenth delay signal, which can help the delay locked loop to quickly stabilize, thereby helping the delay locked loop to quickly perform loop locking.
  • the output signal of the main path will also change. Through the change of the output signal of the main path, the size of the second capacitor is adjusted, so that the output of the delay locked loop is stabilized again, so that the delay locked loop is loop locked.
  • the input signal of the elimination channel is delayed relative to the input signal of the signal channel, that is, there is a delay time between the tenth delayed signal and the reference clock signal, and the delay time is determined in the calibration link before the formal capacitance detection.
  • the embodiments of the present disclosure also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the capacitance detection optimization methods based on a delay-locked loop as recorded in the above method embodiments.
  • An embodiment of the present disclosure also provides an electronic device, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any one of the capacitance detection methods based on a delay-locked loop as recorded in the above method embodiments.
  • each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.
  • the disclosed device can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation.
  • multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some access ports, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software program module.
  • the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a single-chip microcomputer, a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure.
  • the aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

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Abstract

一种基于延迟锁相环路的电容检测方法及电容检测电路，方法包括：当电容检测电路处于开环状态时，将参考时钟信号通过第一电容(Cx)进行延迟处理，得到第一延迟信号；将消除通路的第一输入信号与参考时钟信号通过第二电容(Cc)进行延迟处理，得到第二延迟信号，第一输入信号为电容检测电路在闭环状态下稳定时主通路的输出信号；将第一延迟信号与第二延迟信号输入主通路，得到并根据主通路在当前时间步的输出信号计算第一电容(Cx)的变化值。

Description

一种基于延迟锁相环路的电容检测方法及电容检测电路
相关申请
本申请要求2022年09月28日申请的，申请号为202211187935.6，名称为“一种基于延迟锁相环路的电容检测方法及电容检测电路”的中国专利申请的优先权，在此将其全文引入作为参考；2022年09月28日申请的，申请号为202211187746.9，名称为“一种基于延迟锁相环路的电容检测方法及电容检测电路”的中国专利申请的优先权，在此将其全文引入作为参考；2022年09月28日申请的，申请号为202211187934.1，名称为“一种基于延迟锁相环路的电容检测方法及电容检测电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本公开涉及电子设备领域，尤其涉及一种基于延迟锁相环路的电容检测方法及电容检测电路。
背景技术
延迟锁相环的作用是消除时钟延迟，实现零传输延迟，使输入的时钟信号与整个芯片内部全局时钟网络之间偏差最小，延迟锁相环主要由鉴相器、电荷泵和采样器组成，通过采样器的输出和鉴相器形成消除通路，通过反馈信号来使全局时钟网络的时钟信号与输入的时钟信号同步。在现有电容检测电路中，是通过信号通路中的延迟电容对输入的时钟信号进行延迟，通过消除通路中的电容确定延迟信号，因此，需要对信号通路的延迟电容和反馈环中的电容大小进行检测和调整，使输入的时钟信号在延迟后与输出的时钟信号的相同同步，在输出的时钟信号稳定时，计算出信号通路中的延迟电容的值。在消除通路中的电容是一个由很多开关跟电容组成的阵列，如图1所示，每个开关由单独的控制字控制是否接入，开关闭合时有会有导通电阻，如图1中的Rp所示，同时走线跟器件也会有额外的对地电容，如图1中的Cp。这样就带来一个问题：可能存在多种组合或者说多个输出信号Dout，使得在其控制下消除通路中的电容阵列产生的延时是相同的，那延迟锁相环就有可能稳定在好几个不同的Dout值，导致采用延迟锁相环来做电容检测就有可能失效，降低了检测准确率，因此，采用基于延迟锁相环进行电容检测的方法存在准确率低的问题。
发明内容
本公开实施例提供一种基于延迟锁相环路的电容检测方法，通过在闭环状态下主通路稳定时得到的输出信号，作为开环状态下消除通路中第二电容的输入信号，使得消除通路不依赖于主通路在上一时间步的输出信号，使得消除通路的第二电容的控制字被固定，即使在闭环状态下主通路对应有多个输出信号，也不影响开环状态下信号通路的第一电容的变化量，从而提高了基于延迟锁相环进行电容检测的准确率。
第一方面，本公开实施例提供一种基于延迟锁相环路的电容检测方法，应用于电容检测电路，所述电容检测电路包括：主通路、信号通路以及消除通路，所述信号通路的输出端与所述主通路的第一输入端电连接，所述消除通路的输出端与所述主通路的第二输入端电连接，所述消除通路的输入端与所述主通路的输出端电连接以使所述主通路与所述消除通路构成延迟锁相环路，其中，所述信号通路包括第一电容，所述消除通路包括第二电容，所述方法包括以下步骤：
当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号；
将所述消除通路的第一输入信号与所述参考时钟信号通过所述第二电容进行延迟处理，得到第二延迟信号，所述第一输入信号为所述电容检测电路在闭环状态下稳定时所述主通路的输出信号；
将所述第一延迟信号与所述第二延迟信号输入所述主通路，得到所述主通路在当前时间步的输出信号；以及
根据所述主通路在当前时间步的输出信号计算所述第一电容的变化值。
第二方面，本公开实施例提供一种电容检测电路，所述电容检测电路包括：主通路、信号通路以及消除通路，所述信号通路的输出端与所述主通路的输入端电连接，所述消除通路的输出端与所述主通路的输入端电连接，所述消除通路的输出端与所述主通路的输出端电连接，其中，所述信号通路包括第一电容，所述消除通路包括第二电容，所述延迟锁相环路用于实现如本公开实施例中任一项所述的基于延迟锁相环路的电容检测方法中的步骤。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和有点将从说明书、附图以及权利要求变得明显。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种消除通路中电容的结构图；
图2图2是本公开实施例提供的一种开环状态下电容检测电路的结构图；
图3是本公开实施例提供的另一种开环状态下电容检测电路的结构图；
图4是本公开实施例提供的一种闭环状态下电容检测电路的结构图；
图5是本公开实施例提供的一种反向器对电容充电过程的等效电路图；
图6是本公开实施例提供的一种RC网络对阶跃信号的响应过程示意图；
图7是本公开实施例提供的一种MUX电路的结构示意图；
图8是本公开实施例提供的另一种MUX电路的结构示意图；
图9是本公开实施例提供的一种相位相同的信号示意图；
图10是本公开实施例提供的一种相位不相同的信号示意图；
图11是本公开实施例提供的又一种电容检测电路的结构图；
图12是本公开实施例提供的一种对参考时钟信号进行延迟的原理图；
图13是本公开实施例提供的再一种电容检测电路的结构图；
图14是本公开实施例提供的一种对参考时钟信号进行延迟的原理图；
图15是本公开实施例提供的一种基于延迟锁相环路的电容检测方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
请参见图2和图3，图2是本公开实施例提供的一种开环状态下电容检测电路的结构图，图3是本公开实施例提供的另一种开环状态下电容检测电路的结构图，如图2和图3所示，该电容检测电路包括：主通路、信号通路以及消除通路。
在本公开实施例中，信号通路的输出端与主通路的第一输入端电连接，消除通路的输出端与主通路的第二输入端电连接，消除通路的输入端与主通路的输出端电连接，其中，信号通路包括第一电容，消除通路包括第二电容。其中，主通路与消除通路构建延迟锁相环，第一电容也可以称为待检测电容。当主通路的输出信号实时加载在第二电容上时，电容检测电路为闭环状态，当主通路的输出信号不实时加载在第二电容上时，电容检测电路为开环状态。
在开环状态下，信号通路的输入为参考时钟信号Vosc，信号通路中的第一电容Cx对参考时钟信号Vosc进行延迟，得到信号通路输出的第一延迟信号Vosc_Cx。消除通路的输入包括第一输入信号和参考时钟信号，上述第一输入信号加载于第二电容，通过加载了第一输入信号的第二电容对参考时钟信号进行延迟，得到第二延迟信号Vosc_Cc。其中，第一输入信号为电容检测电路在闭环状态下稳定时主通路的输出信号。
上述主通路的输入端与一选择开关电连接，上述选择开关的控制信号为参考时钟信号的二分频信号。通过选择开关，对第一延迟信号与第二延迟信号进行选择，得到目标信号；将目标信号输入主通路，得到主通路在当前时间步的输出信号。
具体的，上述主通路包括鉴频鉴相器PFD、电荷泵CP以及ADC采样器，上述选择开关可以设置在鉴频鉴相器的输入端或输出端，在图2中，选择开关设置在鉴频鉴相器的输入端，在图3中，选择开关设置在鉴频鉴相器的输出端。
图4是本公开实施例提供的一种闭环状态下电容检测电路的结构图，如图4所示，在闭环状态下，信号通路的输入为参考时钟信号Vosc，信号通路中的第一电容Cx对参考时钟信号Vosc进行延迟，得到信号通路输出的第三延迟信号Vosc_Cx。消除通路的输入为第二输入信号，第二输入信号可以是参考时钟信号Vosc，消除通路中的第二电容Cc中加载有主通路在上一时间步的输出信号Dout，消除通路中的第二电容Cc对参考时钟信号Vosc进行延迟，得到消除通路输出的第四延迟信号Vosc_Cc。在当前时间步，将第三延迟信号Vosc_Cx与第四延迟信号Vosc_Cc输入到主通路中，得到主通路在当前时间步的输出信号Dout。可以看出，由于第一电容Cx上充电需要时间，所以参考时钟信号Vosc就产生了延迟，得到第一延迟信号Vosc_Cx，当第一电容Cx的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。第一延迟信号Vosc_Cx跟第三延迟信号Vosc_Cx输入主通路后输出对应的输出信号Dout。输出信号Dout又会反馈去控制消除通路上第二电容Cc的大小。当环路稳定时，第三延迟信号Vosc_Cx跟第四延迟信号Vosc_Cc的相位相同，主通路的输出信号会稳定到某个值。当主通路的输出稳定时，可以从主通路的输出信号Dout推出当前时间步的第二电容Cc的值。而消除通道的延迟时间跟信号通路的延迟时间是正相关的。所以通过分析主通路的输出信号Dout，就可以得到第一电容Cx的具体变化量，这样就实现了对第一电容Cx的检测。需要说明的是，第一电容Cx的大小变化可以是通过生物触摸产生的大小变化。
在一种可能的实施例中，为加快闭环状态下主通路的输出信号稳定速度，第二输入信号可以是第五延迟信号Vosc_delay，将第五延迟信号Vosc_delay输入到消除通路中，消除通路中的第二电容Cc对第五延迟信号Vosc_delay进行延迟，得到消除通路输出的第四延迟信号Vosc_Cc。第五延迟信号Vosc_delay为相对信号通路延迟后的信号，第五延迟信号可以是预先设置的可调节的信号。
上述开环状态与闭环状态的切换可以通过状态开关进行控制，上述状态开关可以设置在第二电容的输入端与主通路的输出端之间，当状态开关连接第二电容的输入端与主通路的输出端时，则切换到闭环状态，当状态开关断开第二电容的输入端与主通路的输出端时，则切换到开环状态。
如图4所示，在一种可能的实施例中，信号通路包括第一反向器和第二反向器，第一反向器和第二反向器之间耦接第一电容Cx。主通路包括鉴频鉴相器PFD、电荷泵CP(chargepump)以及ADC采样器。消除通路包括第三反向器和第四反向器，第三反向器和第四反向器之间耦接第二电容Cc。参考时钟信号Vosc通过第一反向器输入第一电容Cx，对第一电容Cx进行充电，使第一电容Cx的电压从0上升到 供电电源的电压值VDD，当第一电容Cx的电压超过第二反向器阈值电压的时候，第二反向器的输出会从VDD降到0。由于第一电容Cx上充电需要时间，所以参考时钟信号Vosc就产生了延迟，得到第一延迟信号Vosc_Cx，当第一电容Cx的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。
如图2所示，在另一种可能的实施例中，信号通路包括第五反向器和第一电压比较器，第五反向器和第一电压比较器之间耦接第一电容Cx。主通路包括鉴频鉴相器PFD、电荷泵CP(chargepump)以及ADC采样器。消除通路包括第六反向器和第二电压比较器，第六反向器和第二电压比较器之间耦接第二电容Cc。由于第一电容Cx上充电需要时间，所以参考时钟信号Vosc就产生了延迟，得到第一延迟信号Vosc_Cx1，当第一电容Cx的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。由于采用电压比较器替换反向器来进行电压翻转，可以通过阈值电压Vref对电压比较器的翻转点进行控制。其中，上述第一电压比较器与反向器相比，包括两个输入，一个输入为阈值电压Vref，一个输入为经过第一电容Cx后的参考时钟信号Vosc。上述第二电压比较器与反向器相比，包括两个输入，一个输入为阈值电压Vref，一个输入为经过第二电容Cc后的参考时钟信号Vosc。需要说明的是，上述第一电压比较器的翻转点与上述第二电压比较器的翻转点可以是相同大小，进一步的，上述第一电压比较器的阈值电压Vref可以等于第二电压比较器的阈值电压Vref。
进一步的，可以通过增加延迟时间的信号量来提高电容检测的准确率，在本公开实施例中，反向器对电容充电过程可以等效成RC网络对阶跃信号的响应过程，请参考图5和图6，图5是本公开实施例提供的一种反向器对电容充电过程的等效电路图，图6是本公开实施例提供的一种RC网络对阶跃信号的响应过程示意图，如图5所示，Step Input是参考时钟信号Vref的信号源，信号强度为供电电源的电压值VDD，R为反向器的等效输出阻抗，C为负载电容，Vout为等效电路的输出信号。请结合图6，以从0开始的阶跃为例，相当于反向器输出从0到供电电源的电压值VDD的建立过程。当输出电压超过一级翻转点后，可以寻找一个时间点Tp，在这个时间点Tp上，电容C上的电压达到第二级翻转点。可以假定第二级翻转点是VDD/2，Tp满足下面等式：
在等式中，τ＝RC＝时间常数(time comstant)。
当Vout等于VDD/2，时间为Tp，从上述等式中，可以得到VDD/2＝(1-e-Tp/τ)VDD，进而可以得到Tp＝ln(2)τ＝0.69τ，由于τ＝RC＝时间常数，则可以得到Tp＝0.69RC。
进一步可以看出，当电容发生微小变化时，引起的延迟时间变化为：
更进一步的，当翻转点为aVDD时，可以得到延迟时间变化为：


其中，上述a可以表示翻转点相对于供电电源的电压值VDD的系数，在等效电阻一定的条件下，a越接近1，则延迟时间变化量越大，从而使得延迟时间变化的信号量越大。进一步可以理解为翻转点aVDD越接近供电电源的电压值VDD，则延迟时间变化量越大，从而使得延迟时间变化的信号量越大。同样的，可以看出，延迟时间变化的信号量与等效电阻正相关，为了提高延迟时间变化的信号量要提高反向器的等效电阻R。但是等效电阻不能无限提高，因为反向器要工作，需要信号基本建立。如果R过于大，信号建立时间过长，那整个反向器组成的信号通路和消除通路就不翻转了，工作就不再正常。另外，由于信号通路和消除通路的输入信号都是时钟参考信号，当延迟锁相环路的输出稳定时，要求消除通路的延迟时间等于信号通路的延迟时间：ΔTcc＝ΔTcx。而消除通路中第二电容Cc的值一般是小于信号通路中第一电容Cx的值的，这就要求消除通路的等效电阻Rcc要大于信号通路的等效电阻Rcx。可以动态的去调整消除通路中第二电容Cc的值，使消除通路的等效电阻Rcc固定下来。
实际应用中，信号通路中第一电容Cx的取值范围会非常大，比如支持信号通路中第一电容Cx接近0pF的情况。这样，当信号通路中第一电容Cx较小的时候，消除通路中第二电容Cc即使也很小，在满足Rcc大于Rcx的条件下，可能会出现信号通路和消除通路的延迟永远无法相等的情况，导致时钟同步不准确。所以Rcx不能设置得太大，这样就降低了延迟时间的信号量。
在本公开的可能实施例中，在闭环状态下，由于采用第二延迟信号作为消除通路的输入信号，与信号通路的输入信号不同，所以当延迟锁相环路的输出稳定时，不要求消除通路的延迟时间等于信号通路的延迟时间。因此，当延迟锁相环路的输出稳定时，不需要要求消除通路的等效电阻Rcc要大于信号通路的等效电阻Rcx，当信号通路中第一电容Cx较小的时候，消除通路中第二电容Cc即使也很小，也不会出现信号通路和消除通路的延迟永远无法相等的情况，提高了时钟同步的准确率。将消除通路的等效电阻Rcc与信号通路的等效电阻Rcx进行解耦，信号通路的等效电阻Rcx在设置时，不需要考虑环 路锁定范围，延迟时间的信号量也得到了增强。另外，将消除通路的等效电阻Rcc与信号通路的等效电阻Rcx的解耦，也可以使得信号通路中第一电容Cx与消除通路中第二电容Cc也得到解耦，消除通路中第二电容Cc的取值范围不用再去覆盖信号通路中第一电容Cx的取值范围。进而可以降低消除通路中第二电容Cc的大小，消除通路中第二电容Cc是由片上电容组成，其大小跟芯片面积正相关。降低消除通路中第二电容Cc的大小，也就降低的芯片的面积，降低了芯片成本。
在本公开实施例中，上述选择开关可以是MUX电路，请参考图7和图8，其中图7是本公开实施例提供的一种MUX电路的结构示意图，图8是本公开实施例提供的另一种MUX电路的结构示意图。在图7中，控制信号SEL为0时，输出Y＝输入A；SEL＝1时，输出Y＝输入B。在图8中，当控制信号SEL＝0时，输出Y0＝输入A，输出Y1＝输入B；当控制信号SEL＝1时，输出Y0＝输入B，输出Y1＝输入A。其中，图8中的输入A可以是第一延迟信号，输入B可以是第二延迟信号。当消除通路的延时跟信号通路的延时完全相同时，即第一延迟信号与第二延迟信号完全同步时，主通路中的鉴频鉴相器PFD的输出信号波形如图9所示，在图9中，Vosc为参考时钟信号的波形，Mux_Sel为参考时钟信号的二分频信号的波形，Mux_Sel也是MUX电路的控制信号，Vosc_Cx为第一延迟信号的波形，Vosc_Cc为第二延迟信号的波形，PFD输出为鉴频鉴相器PFD的输出信号的波形。当消除通路的延时跟信号通路的延时完全相同时，即第一延迟信号与第二延迟信号完全同步时，鉴频鉴相器PFD的输出是一条直线，代表第一延迟信号与第二延迟信号的相位完全相同，不需要对电荷泵CP的输出进行调整。若第一电容Cx发生变化，则第一延迟信号Vosc_Cx的延迟时间相对于第二延迟信号Vosc_Cc也发生变化，比如当第一电容Cx变小，则第一延迟信号Vosc_Cx的延迟时间相对于第二延迟信号Vosc_Cc变短，如图10所示。在第一电容Cx发生变化时，电荷泵CP的输出或者说ADC采样器的输入信号，在1/2Vosc频率处会出现幅度的变化。通过对该频点信号幅度的检测，就可以得到第一电容Cx的变化情况。通过参考时钟信号的二分频信号对MUX电路的进行控制，使得第一延迟信号Vosc_Cx与第二延迟信号Vosc_Cc每间隔一个二分频周期交换一次正负接入端口，从而在第一电容Cx发生变化时，变化幅度分布在正负两侧，便于对第一电容Cx的变化量进行检测。需要说明的是，参考时钟信号的一个二分频周期等于参考时钟信号的两个周期。
请参见图11，图11是本公开实施例提供的另一种电容检测电路的结构图，如图11所示，该电容检测电路包括：主通路、信号通路以及消除通路。信号通路的输出端与主通路的第一输入端电连接，消除通路的输出端与主通路的第二输入端电连接，消除通路的输入端与主通路的输出端电连接，其中，信号通路包括第一电容，消除通路包括第二电容。其中，主通路与消除通路构建延迟锁相环，第一电容也可以称为待检测电容。信号通路的输入为参考时钟信号Vosc，信号通路中的第一电容Cx对参考时钟信号Vosc进行延迟，得到信号通路输出的第六延迟信号Vosc_Cx。
在本公开实施例中，采用第六延迟信号Vosc_delay输入到消除通路中，消除通路中的第二电容Cc对第六延迟信号Vosc_delay进行延迟，得到消除通路输出的第七延迟信号Vosc_Cc。第六延迟信号Vosc_delay为相对信号通路延迟后的信号，第六延迟信号可以是预先设置的可调节的信号。
如图11所示，具体的，在本公开实施例中，信号通路包括第一反向器和第二反向器，第一反向器和第二反向器之间耦接第一电容Cx。主通路包括鉴频鉴相器PFD、电荷泵CP(chargepump)以及ADC采样器。消除通路包括第三反向器和第四反向器，第三反向器和第四反向器之间耦接第二电容Cc。请参考图12，图12是本公开实施例提供的一种对参考时钟信号进行延迟的原理图，如图12所示，参考时钟信号Vosc通过第一反向器输入第一电容Cx，对第一电容Cx进行充电，使第一电容Cx的电压从0上升到供电电源的电压值VDD，当第一电容Cx的电压超过第二反向器阈值电压的时候，第二反向器的输出会从VDD降到0。由于第一电容Cx上充电需要时间，所以参考时钟信号Vosc就产生了延迟，得到第一延迟信号Vosc_Cx，当第一电容Cx的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。
在本公开实施例中，由于采用第六延迟信号作为消除通路的输入信号，与信号通路的输入信号不同，所以当延迟锁相环路的输出稳定时，不要求消除通路的延迟时间等于信号通路的延迟时间。因此，当延迟锁相环路的输出稳定时，不需要要求消除通路的等效电阻Rcc要大于信号通路的等效电阻Rcx，当信号通路中第一电容Cx较小的时候，消除通路中第二电容Cc即使也很小，也不会出现信号通路和消除通路的延迟永远无法相等的情况，提高了时钟同步的准确率。将消除通路的等效电阻Rcc与信号通路的等效电阻Rcx进行解耦，信号通路的等效电阻Rcx在设置时，不需要考虑环路锁定范围，延迟时间的信号量也得到了增强。另外，将消除通路的等效电阻Rcc与信号通路的等效电阻Rcx的解耦，也可以使得信号通路中第一电容Cx与消除通路中第二电容Cc也得到解耦，消除通路中第二电容Cc的取值范围不用再去覆盖信号通路中第一电容Cx的取值范围。进而可以降低消除通路中第二电容Cc的大小，消除通路中第二电容Cc是由片上电容组成，其大小跟芯片面积正相关。降低消除通路中第二电容Cc的大小，也就降低的芯片的面积，降低了芯片成本。
图13是本公开实施例提供的一种电容检测电路的结构图，如图13所示，该电容检测电路包括：主通路、信号通路以及消除通路。在本公开实施例中，信号通路的输出端与主通路的第一输入端电连接，消除通路的输出端与主通路的第二输入端电连接，消除通路的输入端与主通路的输出端电连接，其中，信号通路包括第一电容和第一电压比较器，消除通路包括第二电容和第二电压比较器。其中，主通路与消除通路构成延迟锁相环，第一电容也可以称为待检测电容。信号通路的输入为参考时钟信号Vosc，信号通路中的第一电容Cx对参考时钟信号Vosc进行延迟，得到信号通路输出的第八延迟信号Vosc_Cx。
在本公开实施例中，消除通路的输入为参考时钟信号Vosc，消除通路中的第二电容Cc中加载有主通路在上一时间步的输出信号Dout，消除通路中的第二电容Cc对参考时钟信号Vosc进行延迟，得到消除通路输出的第九延迟信号Vosc_Cc。在当前时间步，将第八延迟信号Vosc_Cx与第九延迟信号Vosc_Cc输入到主通路中，得到主通路在当前时间步的输出信号Dout。可以看出，由于第一电容Cx上充电需要时间，所以参考时钟信号Vosc就产生了延迟，得到第八延迟信号Vosc_Cx，当第一电容Cx的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。第八延迟信号Vosc_Cx跟第九延迟信号Vosc_Cc主通路后输出对应的输出信号Dout。输出信号Dout又会反馈去控制消除通路上第二电容Cc的大小。当环路锁定稳定时，第八延迟信号Vosc_Cx跟第九延迟信号Vosc_Cc的相位相同，主通路的输出稳定会稳定到某个值。当主通路的输出稳定时，可以从主通路的输出信号Dout推出当前时间步的第二电容Cc的值。而消除通道的延迟时间跟信号通路的延迟时间是正相关的。所以通过分析主通路的输出信号Dout，就可以得到第一电容Cx的具体变化量，这样就实现了对第一电容Cx的检测。具体的，请参考图14图14是本公开实施例提供的另一种对参考时钟信号进行延迟的原理图，如图14所示，信号通路包括第一反向器和第一电压比较器，第一反向器和第一电压比较器之间耦接第一电容Cx。主通路包括鉴频鉴相器PFD、电荷泵CP(chargepump)以及ADC采样器。消除通路包括第二反向器和第二电压比较器，第二反向器和第二电压比较器之间耦接第二电容Cc。由于第一电容Cx上充电需要时间，所以参考时钟信号Vosc就产生了延迟，得到第八延迟信号Vosc_Cx，当第一电容Cx的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。
在本公开实施例中，由于采用电压比较器替换反向器来进行电压翻转，可以通过阈值电压Vref对电压比较器的翻转点进行控制。其中，上述第一电压比较器与现有的反向器相比，包括两个输入，一个输入为阈值电压Vref，一个输入为经过第一电容后的参考时钟信号。上述第二电压比较器与现有的反向器相比，包括两个输入，一个输入为阈值电压Vref，一个输入为经过第二电容后的参考时钟信号。
需要说明的是，上述第一电压比较器的翻转点与上述第二电压比较器的翻转点可以是相同大小，进一步的，上述第一电压比较器的阈值电压可以等于第二电压比较器的阈值电压。
在一种可能的实施例中，采用第十延迟信号Vosc_delay输入到消除通路中，消除通路中的第二电容Cc对第十延迟信号Vosc_delay进行延迟，得到消除通路输出的第二延迟信号第九延迟信号Vosc_Cc。第十延迟信号Vosc_delay为相对信号通路延迟后的信号，第十延迟信号可以是预先设置的可调节的信号。上述第二电压比较器与现有的反向器相比，包括两个输入，一个输入为阈值电压Vref，一个输入为经过第二电容后的第十延迟信号Vosc_delay。由于采用第十延迟信号作为消除通路的输入信号，与信号通路的输入信号不同，所以当延迟锁相环路的输出稳定时，不要求消除通路的延迟时间等于信号通 路的延迟时间。因此，当延迟锁相环路的输出稳定时，不需要要求消除通路的等效电阻R_cc要大于信号通路的等效电阻R_cx，当信号通路中第一电容Cx较小的时候，消除通路中第二电容Cc即使也很小，也不会出现信号通路和消除通路的延迟永远无法相等的情况，提高了时钟同步的准确率。将消除通路的等效电阻R_cc与信号通路的等效电阻R_cx进行解耦，信号通路的等效电阻R_cx在设置时，不需要考虑环路锁定范围，延迟时间的信号量也得到了增强。另外，将消除通路的等效电阻R_cc与信号通路的等效电阻R_cx的解耦，也可以使得信号通路中第一电容Cx与消除通路中第二电容Cc也得到解耦，消除通路中第二电容Cc的取值范围不用再去覆盖信号通路中第一电容Cx的取值范围。进而可以降低消除通路中第二电容Cc的大小，消除通路中第二电容Cc是由片上电容组成，其大小跟芯片面积正相关。降低消除通路中第二电容Cc的大小，也就降低的芯片的面积，降低了芯片成本。
图15是本公开实施例提供的一种基于延迟锁相环路的电容检测方法的流程图，如图15所示，该基于延迟锁相环路的电容检测方法包括以下步骤：步骤1101-1104。
1101、当电容检测电路处于开环状态时，将参考时钟信号通过第一电容进行延迟处理，得到第一延迟信号。
在本公开实施例中，基于延迟锁相环路的电容检测方法应用于电容检测电路，上述电容检测电路包括：主通路、信号通路以及消除通路，上述信号通路的输出端与上述主通路的第一输入端电连接，上述消除通路的输出端与上述主通路的第二输入端电连接，上述消除通路的输入端与上述主通路的输出端电连接，其中，上述信号通路包括第一电容，上述消除通路包括第二电容。其中，上述主通路与上述消除通路构成延迟锁相环路。
上述参考时钟信号可以是从时钟信号源产生的时钟信号，在一个时钟网络中，可以包括主时钟设备和从时钟设备，主时钟设备可以将自身系统时钟作为参考时钟信号发送到从时钟设备中，使从时钟设备与主时钟设备具有同步的时钟。上述主时钟设备可以作为时钟信号源。而本公开实施例中的延迟锁相环路可以利用从时钟设备与主时钟设备的时钟同步，计算出第一电容的值，第一电容可以是应用于电容控制设备，比如电容式触摸屏或电容式信号发生器等电容控制设备。
上述延迟处理过程为对第一电容进行充电的过程，由于第一电容上充电需要时间，所以参考时钟信号就产生了延迟，得到第一延迟信号，当第一电容的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。
具体的，信号通路包括第一反向器和第二反向器，第一反向器和第二反向器之间耦接第一电容。参考时钟信号通过第一反向器输入到第一电容，通过第一电容的充电进行延迟，通过第二反向器进行翻转后得到第一延迟信号。
在一种可能的实施例中，信号通路包括一个反向器和一个电压比较器，反向器和电压比较器之间耦接第一电容。参考时钟信号通过反向器输入到第一电容，通过第一电容的充电进行延迟，通过电压比较器进行翻转后得到第一延迟信号。可以将参考时钟信号通过反向器和第一电容进行延迟处理，得到第一待翻转信号；当第一待翻转信号达到电压比较器的翻转点时，对第一待翻转信号进行翻转，得到第一延迟信号。上述第一待翻转信号为电压比较器的输入信号，在第一待翻转信号达到第一电压比较器的翻转点时，通过电压比较器对第一待翻转信号进行翻转，得到第一延迟时间。由于电压比较器的翻转点可以通过电压比较器的阈值电压进行控制，因此，可以将电压比较器的阈值电压调整得接近第一待翻转信号的上升沿终点或下降沿终点，可以增加延迟时间的信号量。
1102、将消除通路的第一输入信号与参考时钟信号通过第二电容进行延迟处理，得到第二延迟信号。
在本公开实施例中，第一输入信号为电容检测电路在闭环状态下稳定时主通路的输出信号。具体的，消除通路还包括第三反向器和第四反向器，第三反向器和第四反向器之间耦接第二电容。在开环状态下，将参考时钟信号与第一输入信号通过第二电容进行延迟处理的过程中，第一输入信号加载于消除通路中的第二电容，参考时钟信号则是通过第三反向器输入到第二电容的，第二延迟信号通过加载了第一输入信号的第二电容进行充电延迟，得到第二延迟信号。
1103、将第一延迟信号与第二延迟信号输入主通路，得到主通路在当前时间步的输出信号。
在本公开实施例中，主通路包括鉴频鉴相器PFD、电荷泵CP以及ADC采样器。在当前时间步，第一延迟信号与第二延迟信号输入主通路中，同时输入到主通路的鉴频鉴相器PFD，通过鉴频鉴相器PFD后输入到电荷泵CP，通过电荷泵CP后经过ADC采样器采样输出当前时间步的输出信号。可以将ADC采样器的输出信号通过数字处理后加载到第二电容上，用来改变第二电容的大小。
1104、根据主通路在当前时间步的输出信号计算第一电容的变化值。
在本公开实施例中，在鉴频鉴相器PFD中，当第一延迟信号与第二延迟信号的相位相同时，电荷泵CP的输出稳定不变，第一延迟信号与第二延迟信号的延迟时间相等，当第一电容发生变化时，第一延迟信号与第二延迟信号的相位发生变化，产生延迟时间变化，由于第二电容加载了第一输入信号做为固定的控制字，使得第二延迟信号不会发生相位变化，则检测到的变化量为第一延迟信号的变化量，从而可以检测到第一电容的变化量。因此，当第一电容受外界影响产生变化时，通过分析当前时间步主通路的输出信号，就可以得到第一电容的具体变化量，这样就实现了对第一电容的检测。
具体的，在当前时间步，将第一延迟信号与第二延迟信号输入到主通路中，得到主通路在当前时间步的输出信号。由于第一电容上充电需要时间，所以参考时钟信号就产生了延迟，得到第一延迟信号，当第一电容的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。由于第二电容通 过固定控制字进行控制，其加载的第一输入信号为闭环状态下的稳定输出，在第一电容发生变化后，基于第二电容产生的第二延迟信号并不会发生变化，使得第一延迟信号跟第二延迟信号通过主通路后输出对应的输出信号中仅包括了第一延迟信号的变化信息，通过分析当前时间步主通路的输出信号，就可以得到第一电容的具体变化量，这样就实现了对第一电容的检测。
本公开实施例中，当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号；将所述消除通路的第一输入信号与所述参考时钟信号通过所述第二电容进行延迟处理，得到第二延迟信号，所述消除通路的第一输入信号为所述电容检测电路在闭环状态下稳定时所述主通路的输出信号；将所述第一延迟信号与所述第二延迟信号输入所述主通路，得到所述主通路在当前时间步的输出信号；根据所述主通路在当前时间步的输出信号计算所述第一电容的变化值。通过在闭环状态下主通路稳定时得到的输出信号，作为开环状态下消除通路中第二电容的输入信号，使得消除通路不依赖于主通路在上一时间步的输出信号，使得消除通路的第二电容的控制字被固定，即使在闭环状态下主通路对应有多个输出信号，也不影响开环状态下信号通路的第一电容的变化量，从而提高了基于延迟锁相环进行电容检测的准确率。
可选的，在闭环状态下，可以获取电容检测电路在稳定时主通路的候选输出信号；从候选输出信号中确定消除通路的第一输入信号。
当电容检测电路处于闭环状态时，消除通路中的第二电容加载的信号为上一时间步主通路的输出信号。在电容检测电路处于闭环状态情况下，环路稳定时，主通路会存在多个稳定的输出信号，这些稳定的输出信号均可以使得环路锁定，以使得主通路输出稳定的输出信号。可以从候选输出信号中选择环路锁定次数最多时对应的输出信号作为消除通路的第一输入信号。
可选的，在当电容检测电路处于闭环状态时，获取电容检测电路在稳定时主通路的候选输出信号的步骤中，可以当电容检测电路处于闭环状态时，将参考时钟信号通过第一电容进行延迟处理，得到第三延迟信号；将消除通路的第二输入信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理，得到第四延迟信号。其中，消除通路的第二输入信号为参考时钟信号，或校准环节中，当环路锁定时相对于参考时钟信号的延迟信号；将第三延迟信号与第四延迟信号输入到主通路，在主通路的输出信号稳定时，得到电容检测电路在闭环状态下稳定时主通路的候选输出信号。
通过将在校准环节中，当环路锁定时相对参考时钟信号的延迟信号作为第二输入信号，并在第二输入信号与上一时间步的输出信号的基础上，通过第二电容进行延迟处理，得到第四延迟信号，并第三延迟信号与第四延迟信号共同输入主通路，得到当前时间步输出信号。使用参考时钟信号的延迟信号替代参考时钟信号与上一时间步的输出信号进行延迟处理，从而避免使用参考时钟信号造成的时钟同步不 准确，使得闭环状态下延迟锁相环路的时钟同步准确率提高。
在本公开实施例中，上述第二输入信号为校准环节中，当环路锁定时相对于上述参考时钟信号的延迟信号。
需要说明的是，上述校准环节是在正式对延迟锁相环路中的第一电容和第二电容进行检测之前进行自动校准及延迟时间校准的环节。
通过校准环节得到参考时钟信号的延迟信号替代参考时钟信号作为闭环状态下消除通路的第二输入信号，可以使得延迟锁相环路的输出稳定时，不要求消除通路的延迟时间等于信号通路的延迟时间。因此，当延迟锁相环路的输出稳定时，不需要要求消除通路的等效电阻要大于信号通路的等效电阻，当信号通路中第一电容较小的时候，消除通路中第二电容即使也很小，也不会出现信号通路和消除通路的延迟永远无法相等的情况，从而提高时钟同步的准确率。
上一时间步指的是第一电容和第二电容的上一次检测对应的时间步，比如，在t时刻对第一电容和第二电容进行检测时，主通路在上一时间步的输出信号则为主通路在t－1时刻的输出信号。
具体的，消除通路包括第三反向器和第四反向器，第三反向器和第四反向器之间耦接第二电容。将第二输入信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理的过程中，主通路在上一时间步的输出信号是直接加载于第二电容的，第二输入信号则是通过第三反向器输入到第二电容的，第二延迟信号通过加载了主通路在上一时间步的输出信号的第二电容进行充电延迟，得到第四延迟信号。
上一时间步对应的第三延迟信号与上一时间步的第四延迟信号同时输入到主通路的鉴频鉴相器PFD，通过鉴频鉴相器PFD后输入到电荷泵CP，通过电荷泵CP后经过ADC采样器采样输出上一时间步的输出信号。
可选的，在将第二输入信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理，得到第四延迟信号的步骤之前，还可以对延迟锁相环路进行校准，在校准环节中，当环路锁定时，获取参考时钟信号的延迟信号作为第二输入信号。
在本公开实施例中，在正式对延迟锁相环路中的第一电容和第二电容进行检测之前，可以先对延迟锁相环路进行自动校准以及延迟时间校准，来确定环路锁定时，第二输入信号相对于参考时钟信号的延迟时间。
需要说明的是，第二输入信号为参考时钟信号加上自动校准以及延迟时间校准所得到的延迟时间。在本公开实施例中，可以通过一个适合的第二输入信号来帮助延迟锁相环路在正式对第一电容和第二电容进行检测时，使主通路的输出信号快速达到稳定状态，使环路锁定速度提高。
可选的，在校准环节中，当环路锁定时，获取参考时钟信号的延迟信号作为第二输入信号的步骤中， 可以设置环路锁定的目标工作点；当环路锁定在目标工作点时，获取参考时钟信号的延迟信号作为第二输入信号。
在本公开实施例中，环路锁定的目标工作点指的是延迟锁相环路稳定时的工作点，具体的，在鉴频鉴相器PFD中，当第三延迟信号与第四延迟信号的相位相同时，电荷泵CP的输出稳定不变，而ADC采样器的输出也会稳定在某个值，该某个值则为延迟锁相环路稳定时的工作点，此时，控制延迟锁相环路进行锁定，锁定第一电容和第二电容的值不再变化，则第三延迟信号与第四延迟信号的相位也不再变化，依然保持相位的相同，完成时钟信号在该个工作点的同步。
在校准环节中，可以先对延迟锁相环路进行自动校准以及延迟时间校准，来确定延迟锁相环路在环路锁定时的工作点作为目标工作点，此时，将获取到的延迟时间与参考时钟信号进行相加，得到参考时钟信号的延迟信号作为第二输入信号。在正式对延迟锁相环路进行电容检测时，可以通过第二输入信号延迟锁相环路快速锁定在目标工作点，提高延迟锁相环路的锁定速度。
在得到参考延迟锁相环路的历史第二电容的变化值后，可以通过历史第二电容的变化值，预测目标延迟锁相环路的第二电容的初始值。具体的，可以将历史第二电容的变化值输入预先训练好的第一时序网络预测中，预设得到目标延迟锁相环路的第二电容的初始值。
由于参考延迟锁相环路与目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数，因此，参考延迟锁相环路与目标延迟锁相环路具有相似的工作参数，以历史第二电容的变化值，预测目标延迟锁相环路的第二电容的初始值，通过调整第二电容的初始值，可以在校准环节，帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。
在得到参考延迟锁相环路的历史延迟时间后，可以通过历史延迟时间，预测目标延迟锁相环路的预测延迟时间。具体的，可以将历史第一电容的变化值与历史第二电容的变化值输入预先训练好的第二时序网络预测中，预设得到目标延迟锁相环路的预测延迟时间。
由于参考延迟锁相环路与目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数，因此，参考延迟锁相环路与目标延迟锁相环路具有相似的工作参数，以历史延迟时间，预测目标延迟锁相环路的预测延迟时间，并将预测延迟时间与参考信号进行相加，得到预测的第二输入信号，通过预测的第二输入信号，可以在校准环节，帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。
在校准环节完成后，正式检测延迟锁相环路中的第一电容和第二电容的变化时，可以根据当前时间步的输出信号，计算第二电容的变化值，可以根据第二电容的变化值调整第二电容，使得延迟锁相环路进行环路锁定。在本公开实施例中，使用自动校准时得到的延迟时间与参考时钟信号进行相加，得到第二延迟信号，可以帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。在检测到第 一电容发生变化时，主通路的输出信号也会发生变化，通过主通路的输出信号的变化，调整第二电容的大小，从而使延迟锁相环路的输出再次稳定下来，使延迟锁相环路进行环路锁定。
在本公开实施例中，需要说明的是，消除通道的输入信号相对于信号通道的输入信号有延迟，即第二延迟信号与参考时钟信号之间存在延迟时间，延迟时间为正式做电容检测前的校准环节进行确定。
可选的，消除通路还包括状态开关，状态开关与第二电容的输入端电连接，在当所述电容检测电路处于开环状态时，将参考时钟信号通过第一电容进行延迟处理，得到第一延迟信号的步骤之前，还可以调整状态开关，将电容检测电路从闭环状态切换到开环状态，或者将电容检测电路从开环状态切换到闭环状态。具体的，上述开环状态与闭环状态的切换可以通过状态开关进行控制，上述状态开关可以设置在第二电容的输入端与主通路的输出端之间，当状态开关连接第二电容的输入端与主通路的输出端时，则切换到闭环状态，当状态开关断开第二电容的输入端与主通路的输出端时，则切换到开环状态。
可选的，主通路的输入端与一选择开关电连接，在将第一延迟信号与第二延迟信号输入主通路，得到主通路在当前时间步的输出信号的步骤中，可以通过选择开关，对第一延迟信号与第二延迟信号进行选择，得到目标信号；将目标信号输入主通路，得到主通路在当前时间步的输出信号。具体的，选择开关包括正负接入端口，通过选择开关，可以将第一延迟信号与第二延迟信号的正负接入端口进行切换。可以理解为通过选择开关，将电荷泵CP的输入信号按预设周期进行正负接入端口反接。
可选的，在通过选择开关，对第一延迟信号与第二延迟信号进行选择，得到目标信号的步骤中，可以获取参考时钟信号的分频信号；通过分频信号控制选择开关对第一延迟信号与第二延迟信号进行选择，得到目标信号。
具体的，上述分频信号可以是N次分频信号，上述N次分频信号的一个周期等于参考时钟信号的N个周期。
优选的，上述分频信号可以是二分频信号。二分频信号的一个周期等于参考时钟信号的两个周期，通过二分频信号控制选择开关，每个二分频信号周期切换一次第一延迟信号与第二延迟信号的正负接入端口。从而使得第一延迟信号与第二延迟信号在相位相同时，电荷泵CP的输入信号(相当于鉴频鉴相器PFD的输出信号)是一条直线，第一延迟信号与第二延迟信号在相位不同时，相邻变化量分布在直线的两侧，便于第一延迟信号的变化量测量。
可选的，选择开关包括第一选择器与第二选择器，在通过二分频信号控制选择开关对第一延迟信号与第二延迟信号进行选择，得到目标信号的步骤中，可以通过二分频信号控制第一选择器和第二选择器，通过第一选择器和第二选择器对第一延迟信号与第二延迟信号进行选择，得到目标信号。
具体的，请同时参考图8，图8中的输入A可以是第一延迟信号，输入B可以是第二延迟信号，第 一延迟信号分别连接在第一选择器和第二选择器的1号接入端口，第二延迟信号分别连接在第一选择器和第二选择器的2号接入端口，当控制信号SEL＝0时，输出Y0＝输入A，输出Y1＝输入B，此时，输入A接电荷泵CP的正接入端口，输入B接电荷泵CP的负接入端口；当控制信号SEL＝1时，输出Y0＝输入B，输出Y1＝输入A，此时，输入A接电荷泵CP的负接入端口，输入B接电荷泵CP的正接入端口。需要说明的是，上述目标信号指的是第一延迟信号与第二延迟信号作为不同接入端口对应的输入状态的信号。
可选的，主通路包括鉴频鉴相器以及电荷泵，鉴频鉴相器的输出端与电荷泵的输入端电连接，选择开关的输出端与鉴频鉴相器的输入端电连接，或者选择开关的输出端与所述电荷泵的输入端电连接，在根据主通路在当前时间步的输出信号计算第一电容的变化值的步骤中，当鉴频鉴相器的输出信号中第一延迟信号与第二延迟信号之间的相位差不为0时，对电荷泵的输出信号进行检测，得到第一电容的变化值。
具体的，当鉴频鉴相器的输出信号中第一延迟信号与第二延迟信号之间的相位差不为0时，由于第二电容的控制字通过第一输入信号进行固定，所以第二延迟信号的相位不会发生变化，可以得到第一延迟信号与第二延迟信号之间的相位差是由第一延迟信号变化产生的，因此，可以确定第一电容发生了变化。第一延迟信号与第二延迟信号之间的相位差是由第一电容的变化量产生，因此，可以通过第一延迟信号与第二延迟信号之间的相位差计算得到第一电容的变化量。
可选的，在当鉴频鉴相器的输出信号中第一延迟信号与第二延迟信号之间的相位差不为0时，对电荷泵的输出信号进行检测，得到第一电容的变化值的步骤中，可以预先确定电荷泵的输出信号中的目标频点；当鉴频鉴相器的输出信号中第一延迟信号与第二延迟信号之间的相位差不为0时，在电荷泵的输出信号中的目标频点处进行信号幅度检测，得到第一电容的变化值。具体的，上述目标频点可以是电荷泵CP输出信号的1/2Vosc频率处，通过对电荷泵CP输出信号的1/2Vosc频率处进行信号幅度的检测，可以得到第一电容的变化情况。
本公开实施例提供的又一种基于延迟锁相环路的电容检测方法，包括步骤601-604。
601、将参考时钟信号通过第一电容进行延迟处理，得到第五延迟信号。
在本公开实施例中，基于延迟锁相环路的电容检测方法应用于电容检测电路，对上述电容检测电路包括：主通路、信号通路以及消除通路，上述信号通路的输出端与上述主通路的第一输入端电连接，上述消除通路的输出端与上述主通路的第二输入端电连接，上述消除通路的输入端与上述主通路的输出端电连接，其中，上述信号通路包括第一电容，上述消除通路包括第二电容。其中，上述主通路与上述消除通路构成延迟锁相环路。
对参考时钟信号的限定和对延迟处理过程的描述可以参照上述基于延迟锁相环路的电容检测方法中步骤1101中对应的描述，在此不做赘述。
信号通路包括第一反向器和第二反向器，第一反向器和第二反向器之间耦接第一电容。参考时钟信号通过第一反向器输入到第一电容，通过第一电容的充电进行延迟，通过第二反向器进行翻转后得到第一延迟信号。
602、将第六延迟信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理，得到第七延迟信号。
在本公开实施例中，上述第六延迟信号为校准环节中，当环路锁定时相对于上述参考时钟信号的延迟信号。通过校准环节得到第六延迟信号替代参考时钟信号作为消除通路的输入信号，可以使得延迟锁相环路的输出稳定时，不要求消除通路的延迟时间等于信号通路的延迟时间。因此，当延迟锁相环路的输出稳定时，不需要要求消除通路的等效电阻要大于信号通路的等效电阻，当信号通路中第一电容较小的时候，消除通路中第二电容即使也很小，也不会出现信号通路和消除通路的延迟永远无法相等的情况，从而提高时钟同步的准确率。
上一时间步指的是第一电容和第二电容的上一次检测对应的时间步，比如，在t时刻对第一电容和第二电容进行检测时，主通路在上一时间步的输出信号则为主通路在t－1时刻的输出信号。
具体的，消除通路包括第三反向器和第四反向器，第三反向器和第四反向器之间耦接第二电容。将第六延迟信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理的过程中，主通路在上一时间步的输出信号是直接加载于第二电容的，第六延迟信号则是通过第三反向器输入到第二电容的，第六延迟信号通过加载了主通路在上一时间步的输出信号的第二电容进行充电延迟，得到第七延迟信号。
上一时间步对应的第五延迟信号与上一时间步的第七延迟信号同时输入到主通路的鉴频鉴相器PFD，通过鉴频鉴相器PFD后输入到电荷泵CP，通过电荷泵CP后经过ADC采样器采样输出上一时间步的输出信号。
603、将第五延迟信号与第七延迟信号输入主通路，得到主通路在当前时间步的输出信号。
在本公开实施例中，主通路包括鉴频鉴相器PFD、电荷泵CP以及ADC采样器。在当前时间步，第五延迟信号与第七延迟信号输入主通路中，同时输入到主通路的鉴频鉴相器PFD，通过鉴频鉴相器PFD后输入到电荷泵CP，通过电荷泵CP后经过ADC采样器采样输出当前时间步的输出信号。可以将ADC采样器的输出信号通过数字处理后加载到第二电容上，用来改变第二电容的大小。
604、在主通路在当前时间步的输出信号稳定时，根据当前时间步的输出信号计算第一电容的值。
在本公开实施例中，在鉴频鉴相器PFD中，当第五延迟信号与第七延迟信号的相位相同时，电荷泵 CP的输出稳定不变，而ADC采样器的输出也会稳定在某个值，此时，控制延迟锁相环路进行锁定，锁定第二电容的值不再变化，则第五延迟信号与第七延迟信号的相位也不再变化，依然保持相位的相同，完成时钟信号的同步。当第一电容受外界影响产生变化时，通过分析当前时间步主通路的输出信号，就可以得到第一电容的具体变化量，这样就实现了对第一电容的检测。
具体的，在当前时间步，将第五延迟信号与第七延迟信号输入到主通路中，得到主通路在当前时间步的输出信号。由于第一电容上充电需要时间，所以参考时钟信号就产生了延迟，得到第五延迟信号，当第一电容的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。第五延迟信号跟第七延迟信号通过主通路后输出对应的输出信号。输出信号又会反馈去控制消除通路上第二电容的大小。当环路锁定稳定时，第五延迟信号跟的相位相同，主通路的输出稳定会稳定到某个值。当主通路的输出稳定时，可以从主通路的输出信号推出当前时间步的第二电容的值。而消除通道的延迟时间跟信号通路的延迟时间是正相关的。所以通过分析主通路的输出信号，就可以得到第一电容的具体变化量，这样就实现了对第一电容的检测。
本公开实施例中，将参考时钟信号通过所述第一电容进行延迟处理，得到第五延迟信号；将第六延迟信号与所述主通路在上一时间步的输出信号通过所述第二电容进行延迟处理，得到第七延迟信号，其中，所述第六延迟信号为校准环节中，当环路锁定时相对于所述参考时钟信号的延迟信号；将所述第五延迟信号与第七延迟信号输入主通路，得到所述主通路在当前时间步的输出信号；在主通路在当前时间步的输出信号稳定时，根据当前时间步的输出信号计算第一电容的值。通过将在校准环节中，当环路锁定时相对参考时钟信号的延迟信号作为第六延迟信号，并在第六延迟信号与上一时间步的输出信号的基础上，通过第二电容进行延迟处理，得到第七延迟信号第，并第七延迟信号与第五延迟信号共同输入主通路，得到当前时间步输出信号，根据当前时间步的输出信号，计算第一电容的变化值和第二电容的变化值，可以根据第二电容的变化值调整第二电容，使用第六延迟信号第六延迟信号替代参考时钟信号与上一时间步的输出信号进行延迟处理，从而在使得延迟锁相环路的能在提高电容检测范围的同时，避免使用参考时钟信号造成信号通路与消除通路的延迟无法相等，使得延迟锁相环锁定失败的情况。
可选的，在将第六延迟信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理，得到第七延迟信号的步骤之前，还可以对延迟锁相环路进行校准，在校准环节中，当环路锁定时，获取参考时钟信号的延迟信号作为六延迟信号。
在本公开实施例中，在正式对延迟锁相环路中的第一电容和第二电容进行检测之前，可以先对延迟锁相环路进行自动校准以及延迟时间校准，来确定环路锁定时，第六延迟信号相对于参考时钟信号的延迟时间。
需要说明的是，第六延迟信号为参考时钟信号加上自动校准以及延迟时间校准所得到的延迟时间。在本公开实施例中，可以通过一个适合的第六延迟信号来帮助延迟锁相环路在正式对第一电容和第二电容进行检测时，使主通路的输出信号快速达到稳定状态，使环路锁定速度提高。
可选的，在校准环节中，当环路锁定时，获取参考时钟信号的延迟信号作为第六延迟信号的步骤中，可以设置环路锁定的目标工作点；当环路锁定在目标工作点时，获取参考时钟信号的延迟信号作为第六延迟信号。
在本公开实施例中，环路锁定的目标工作点指的是延迟锁相环路稳定时的工作点，具体的，在鉴频鉴相器PFD中，当第五延迟信号与第七延迟信号的相位相同时，电荷泵CP的输出稳定不变，而ADC采样器的输出也会稳定在某个值，该某个值则为延迟锁相环路稳定时的工作点，此时，控制延迟锁相环路进行锁定，锁定第一电容和第二电容的值不再变化，则第五延迟信号与第七延迟信号号的相位也不再变化，依然保持相位的相同，完成时钟信号在该个工作点的同步。
在校准环节中，可以先对延迟锁相环路进行自动校准以及延迟时间校准，来确定延迟锁相环路在环路锁定时的工作点作为目标工作点，此时，将获取到的延迟时间与参考时钟信号进行相加，得到参考时钟信号的延迟信号作为第六延迟信号。在正式对延迟锁相环路进行电容检测时，可以通过第六延迟信号延迟锁相环路快速锁定在目标工作点，提高延迟锁相环路的锁定速度。
可选的，在设置环路锁定的目标工作点的步骤中，可以通过预设的查找方法，确定环路锁定的目标工作点。
在本公开实施例中，上述预设的查找法可以是二分查找法、遍历查找法以及穷举法中的一种，优选为二分查找法，具体的，可以预先设置延迟时间的有序表，通过二分查找法在有序表中查找到合适的延迟时间，使得延迟锁相环路在一个较好的工作点上进行环路锁定。通过二分查找法对延迟时间的有序表进行延迟时间查找，具有比较次数少、查找速度快、平均性能好、占用系统内存较少的优点。
在本公开实施例中，上述有序表中延迟时间可以是按升序排列，将表中间位置记录的延迟时间用于校准环节，如果延迟锁相环路在相同的工作点上进行环路锁定，则查找成功；否则利用中间位置记录将表分成前、后两个子表，如果中间位置记录的延迟时间的工作点大于延迟锁相环路在校准环节的工作点，则进一步查找前一子表，否则进一步查找后一子表。重复以上过程，直到找到满足条件的延迟时间，使查找成功，或直到子表不存在为止，此时查找不成功。查找不成功时，可以选择延迟时间的工作点与延迟锁相环路在校准环节的工作点最相近的延迟时间与参考时钟信号进行相加，得到第六延迟信号，再通过第六延迟信号确定校准环节中环路锁定的目标工作点。
可选的，主通路包括第三电容，在设置环路锁定的目标工作点的步骤中，可以获取供电电源的电压 值；以环路锁定时第三电容的电压值接近二分之一供电电源的电压值为目标，确定环路锁定的目标工作点。
在本公开实施例中，供电电源的电压值VDD，在校准环节中，当环路锁定，且第三电容的电压值接近1/2VDD时延迟锁相环路的工作点为目标工作点。计算延迟锁相环路在该个目标工作点下的延迟时间，将延迟时间与参考时钟信号进行相加，得到第六延迟信号。在检测延迟锁相环路中第一电容和第二电容时，使用校准环节得到的延迟时间与参考时钟信号进行相加，可以帮助延迟锁相环路快速稳定下来。
可选的，主通路包括第三电容，设置环路锁定的目标工作点的步骤中，可以根据供电电源的电压值，以提高信号量为目标，分析第三电容的电压值；根据第三电容的电压值，确定环路锁定的目标工作点。
在本公开实施例中，上述信号量为延迟时间的信号量，可以通过相同结构的延迟锁相环路的数据进行大数据分析，分析第三电容的电压值、供电电源的电压值以及延迟时间的信号量三者之间的关系，从而找到使延迟时间信号量最大的第三电容的最佳电压值，使得校准环节中，延迟锁相环路在环路锁定时，第三电容的电压值处于最佳电压值。使用校准环节得到的延迟时间与参考时钟信号进行相加，可以帮助延迟锁相环路快速稳定下来。
可选的，在当环路锁定在目标工作点时，获取参考时钟信号的延迟信号作为第六延迟信号的步骤中，可以通过调整第二电容的值，得到多个候选延迟时间；根据环路锁定在目标工作点时，从多个候选延迟时间中确定目标候选延迟时间；根据目标候选延迟时间和参考时钟信号，确定第六延迟信号。
在本公开实施例中，当第一电容的值发生变化时，可以通过主通路输出信号的变化，调整第二电容的值大小，从而使环路锁定。在校准环节中，确定目标工作点后，可以通过调整第二电容的值，使得延迟锁相环路在不同工作点进行环路锁定，此时，可以得到多个候选延迟时间。当延迟锁相环路在目标工作点进行环路锁定时，确定此时延迟时间为目标候选延迟时间。可以将目标候选延迟时间和参考时钟信号进行相加，得到第六延迟信号。使用校准环节得到的延迟时间与参考时钟信号进行相加，可以帮助延迟锁相环路快速稳定下来。
可选的，在通过调整第二电容的值，得到多个候选延迟时间的步骤中，可以获取目标延迟锁相环路中的当前使用环境参数；根据当前使用环境参数，获取参考延迟锁相环路的第二电容历史变化值，参考延迟锁相环路与目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数；根据第二电容历史变化值，预测目标延迟锁相环路的第二电容的初始值；通过调整第二电容的初始值，得到多个候选延迟时间。
在本公开实施例中，上述当前使用环境参数可以是延迟锁相环路所要应用的工况条件，比如工作频率、工作温度、主时钟设备参数和从时钟设备参数等。
在得到参考延迟锁相环路的第二电容历史变化值后，可以通过第二电容历史变化值，预测目标延迟锁相环路的第二电容的初始值。具体的，可以将第二电容历史变化值输入预先训练好的第一时序网络预测中，预设得到目标延迟锁相环路的第一电容的初始值和第二电容的初始值。
由于参考延迟锁相环路与目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数，因此，参考延迟锁相环路与目标延迟锁相环路具有相似的工作参数，以第二电容历史变化值，预测目标延迟锁相环路的第二电容的初始值，通过调整第二电容的初始值，可以在校准环节，帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。
可选的，在当环路锁定在目标工作点时，获取参考时钟信号的延迟信号作为第六延迟信号的步骤中，可以获取目标延迟锁相环路中的当前使用环境参数；根据当前使用环境参数，获取参考延迟锁相环路的历史延迟时间，参考延迟锁相环路与目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数；根据历史延迟时间，通过预训练的预测网络对目标延迟锁相环路的延迟时间进行预测，得到预测延迟时间；以预测延迟时间为初始延迟时间，对第二电容的值进行调整，得到多个候选延迟时间；根据环路锁定在目标工作点时，从多个候选延迟时间或初始延迟时间中，确定目标候选延迟时间；根据目标候选延迟时间和参考时钟信号，确定第六延迟信号。可以理解的是，本公开实施例中获取第六延迟信号的步骤同样可以用来获取上述实施例中为校准环节中，当环路锁定时相对于上述参考时钟信号的延迟信号的第二输入信号。
在得到参考延迟锁相环路的历史延迟时间后，可以通过历史延迟时间，预测目标延迟锁相环路的预测延迟时间。具体的，可以将第二电容历史变化值输入预先训练好的第二时序网络预测中，预设得到目标延迟锁相环路的预测延迟时间。
由于参考延迟锁相环路与目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数，因此，参考延迟锁相环路与目标延迟锁相环路具有相似的工作参数，以历史延迟时间，预测目标延迟锁相环路的预测延迟时间，并将预测延迟时间与参考信号进行相加，得到预测的第六延迟信号，通过预测的第六延迟信号，可以在校准环节，帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。
在校准环节完成后，正式检测延迟锁相环路中的第一电容和第二电容的变化时，可以根据当前时间步的输出信号，计算第一电容的变化值和第二电容的变化值，可以根据第第二电容的变化值调整第二电容，使得延迟锁相环路进行环路锁定。在本公开实施例中，使用自动校准时得到的延迟时间与参考时钟信号进行相加，得到第六延迟信号，可以帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。在检测到第一电容发生变化时，主通路的输出信号也会发生变化，通过主通路的输出信号的变化，调整第二电容的大小，从而使延迟锁相环路的输出再次稳定下来，使延迟锁相环路进行环路锁定。 在本公开实施例中，需要说明的是，消除通道的输入信号相对于信号通道的输入信号有延迟，即第六延迟信号与参考时钟信号之间存在延迟时间，延迟时间为正式做电容检测前的校准环节进行确定。
在一些实施例中，本公开实施例提供再一种基于延迟锁相环路的电容检测方法包括步骤501-504。
501、将参考时钟信号依次通过第一电容和第一电压比较器进行延迟处理，得到第八延迟信号。
在本公开实施例中，基于延迟锁相环路的电容检测应用于电容检测电路，上述电容检测电路包括：主通路、信号通路以及消除通路，上述信号通路的输出端与上述主通路的第一输入端电连接，上述消除通路的输出端与上述主通路的第二输入端电连接，上述消除通路的输入端与上述主通路的输出端电连接，其中，上述信号通路包括第一电容，上述消除通路包括第二电容。其中，上述主通路与上述消除通路构成延迟锁相环路。
上述延迟处理过程为对第一电容进行充电的过程，由于第一电容上充电需要时间，所以参考时钟信号就产生了延迟，得到第八延迟信号，当第一电容的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。
具体的，信号通路包括第一反向器和第一电压比较器，第一反向器和第一电压比较器之间耦接第一电容。参考时钟信号通过第一反向器输入到第一电容，通过第一电容的充电进行延迟，通过第一电压比较器进行翻转后得到第八延迟信号。
其中，第一电压比较器的翻转点根据第一电压比较器的阈值电压进行调整，上述第一电压比较器的阈值电压可以设置在供电电源的电压值VDD的附近。
可选的，在将参考时钟信号依次通过第一电容和第一电压比较器进行延迟处理，得到第八延迟信号的步骤中，可以将参考时钟信号通过第一电容进行延迟处理，得到第二待翻转信号；当第二待翻转信号达到第一电压比较器的翻转点时，对第二待翻转信号进行翻转，得到第八延迟信号。
可选的，将消除通路的输入信号与所述主通路在上一时间步的输出信号依次通过所述第二电容和所述第二电压比较器进行延迟处理，得到第九延迟信号的步骤中，将主通路在上一时间步的输出信号加载到第二电容，并通过加载了主通路在上一时间步的输出信号的第二电容对消除通路的输入信号进行延迟处理，得到第三待翻转信号；当第三待翻转信号达到第二电压比较器的翻转点时，对第三待翻转信号进行翻转，得到第九延迟信号。
上述第二待翻转信号为第一电压比较器的输入信号，在第二待翻转信号达到第一电压比较器的翻转点时，通过第一电压比较器对第二待翻转信号进行翻转，得到第一延迟时间。由于第一电压比较器的翻转点可以通过第一电压比较器的阈值电压进行控制，因此，可以将第一电压比较器的阈值电压调整得接第二待翻转信号的上升沿终点或下降沿终点，可以增加延迟时间的信号量。
可选的，在将参考时钟信号依次通过第一电容和第一电压比较器进行延迟处理，得到第八延迟信号的步骤之前，还可以以第一电容的上升沿终点或者第一电容的下降沿终点或者供电电源的电压值为接近点，确定第一电压比较器的目标翻转点；通过控制第一电压比较器的阈值电压，调整第一电压比较器的翻转点到第一电压比较器的目标翻转点。
具体的，在对第一电容进行电容检测前，可以控制第一电压比较器的阈值电压来调整第一电压比较器的翻转点，使第一电压比较器工作在一个较好的翻转点上。上述第一电容的上升沿终点可以理解为第二待翻转信号的上升沿终点，第二待翻转信号在上升沿时不再变化，上述第一电压的下降沿终点可以理解为第二待翻转信号的下降沿终点，第二待翻转信号在下降沿时不再变化。
上述接近点指的是在对第一电压比较器的翻转点进行调整的过程中，调整翻转点从上升沿或下降沿的一侧去接近的信号点。需要说明的是，在反向器的工作原理中，通过将接近点设置为VDD/2，在反向器的实际应用中，翻转点通常设置在VDD/2附近。
可选的，在以第一电容的上升沿终点或者第一电容的下降沿终点或者电源电压为接近点，确定第一电压比较器的目标翻转点的步骤之前，还可以先确定主通路的相位差检测类型，根据主通路的相位差检测类型，确定接近点的类型，接近点的类型包括第一电容的上升沿终点、第一电容的下降沿终点以及供电电源的电压值。
具体的，当主通路的相位差检测类型为检测上升沿的相位差，则接近点的类型可以第一电容的上升沿终点；当主通路的相位差检测类型为检测下降沿的相位差，则接近点的类型可以第一电容的下降沿终点；当第一比较器的上升沿对应第二待翻转信号的上升沿时，且主通路的相位差检测类型是检测两个信号上升沿的相位差，则接近点的类型可以是供电电源的电压值。
可选的，主通路包括鉴频鉴相器PFD、电荷泵CP以及ADC采样器。在根据主通路的相位差检测类型，确定接近点的类型的步骤中，可以当鉴频鉴相器PFD检测的是上升沿的相位差时，确定接近点的类型为所述第一电容的上升沿终点；当鉴频鉴相器PFD检测的是下降沿的相位差时，确定接近点的类型为第一电容的下降沿终点；当第一电压比较器的上升沿对应于参考时钟信号的上升沿，且鉴频鉴相器PFD检测上升沿的相位差时，确定接近点的类型为供电电源的电压值。
在本公开实施例中，根据主通路的相位差检测类型来确定接近点的类型，可以更准确的调整第一电压比较器的翻转点，使得第一电压比较器的翻转点设置在接近点附近，从而提高延迟时间的信号量。
可选的，在以第一电容的上升沿终点或者第一电容的下降沿终点或者供电电源的电压值为接近点，确定第一电压比较器的目标翻转点的步骤中，可以确定延迟时间的信号量；根据延迟时间的信号量，调整第一电压比较器的翻转点与接近点的距离值；根据第一电压比较器的翻转点与接近点的距离值，确定 第一电压比较器的目标翻转点。
具体的，上述延迟时间的信号量可以根据具体的使用环境进行确定，比如，对于精确度要求较高的使用环境，上述延迟时间的信号量可以设置得大一些，对于精确度要求较低的使用环境，上述延迟时间的信号量可以设置得小一些。可以根据延迟时间的信号量，计算出翻转点对应的阈值电压，从而通过调整第一电压比较器的阈值电压来调整第一电压比较器的翻转点。
在一种可能的实施例中，上述第一电压比较器的阈值电压可以通过用户手动进行调整，也可以根据用户选择的精确度档位自动进行调整。
可选的，在以第一电容的上升沿终点或者第一电容的下降沿终点或者供电电源的电压值为接近点，确定第一电压比较器的目标翻转点的步骤中，可以确定延迟时间的信号量；根据延迟时间的信号量，调整第一电压比较器的翻转点与接近点的比例值；根据第一电压比较器的翻转点与接近点的比例值，确定第一电压比较器的目标翻转点。
具体的，当翻转点为aVDD时，上述a可以表示翻转点相对于供电电源的电压值VDD的比例值，在等效电阻一定的条件下，a越接近1，则延迟时间变化量越大，从而使得延迟时间变化的信号量越大。进一步可以理解为翻转点aVDD越接近供电电源的电压值VDD，则延迟时间变化量越大，从而使得延迟时间变化的信号量越大。上述延迟时间的信号量可以具体的使用环境或者用户使用需求进行确定，比如，对于精确度要求较高的使用环境或用户使用需求，上述延迟时间的信号量可以设置得大一些，对于精确度要求较低的使用环境或用户使用需求，上述延迟时间的信号量可以设置得小一些。可以根据延迟时间的信号量，计算出第一电压比较器的翻转点与接近点的比例值，从而计算出翻转点对应的阈值电压，从而通过调整第一电压比较器的阈值电压来调整第一电压比较器的翻转点。
502、将消除通路的输入信号与主通路在上一时间步的输出信号依次通过第二电容和第二电压比较器进行延迟处理，得到第九延迟信号。
在本公开实施例中，消除通路的输入信号可以是参考时钟信号，即消除通路的输入信号与信号通路的输入信号相同。
可选的，上述第二电压比较器的翻转点与上述第一电压比较的翻转点相同，具体可以理解为上述第二电压比较器的阈值电压等于上述第一电压比较器的阈值电压，上述第一电压比较器与上述第二电压比较器可以通过同一个阈值电压控制信号进行调整，使得第一电压比较器与第二电压比较器工作在相同的翻转点。
在一种可能的实施例中，上述消除通路的输入信号可以是第十延迟信号，上述第十延迟信号为校准环节中，当环路锁定时相对于上述参考时钟信号的延迟信号。
需要说明的是，上述校准环节是在正式对延迟锁相环路中的第一电容和第二电容进行检测之前进行自动校准及延迟时间校准的环节。
通过校准环节得到第十延迟信号替代参考时钟信号作为消除通路的输入信号，可以使得延迟锁相环路的输出稳定时，不要求消除通路的延迟时间等于信号通路的延迟时间。因此，当延迟锁相环路的输出稳定时，不需要要求消除通路的等效电阻要大于信号通路的等效电阻，当信号通路中第一电容较小的时候，消除通路中第二电容即使也很小，也不会出现信号通路和消除通路的延迟永远无法相等的情况，从而提高时钟同步的准确率。
上一时间步指的是第一电容和第二电容的上一次检测对应的时间步，比如，在t时刻对第一电容和第二电容进行检测时，主通路在上一时间步的输出信号则为主通路在t－1时刻的输出信号。
具体的，消除通路包括第二反向器和第二电压比较器，第二反向器和第二电压比较器之间耦接第二电容。
在将消除通路的输入信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理的过程中，主通路在上一时间步的输出信号是直接加载于第二电容的，消除通路的输入信号则通过第二反向器输入到第二电容，消除通路的输入信号通过加载了主通路在上一时间步的输出信号的第二电容进行充电延迟，得到第九延迟信号。
上一时间步对应的第八延迟信号与上一时间步的第九延迟信号同时输入到主通路的鉴频鉴相器PFD，通过鉴频鉴相器PFD后输入到电荷泵CP，通过电荷泵CP后经过ADC采样器采样输出上一时间步的输出信号。
503、将第八延迟信号与第九延迟信号输入主通路，得到主通路在当前时间步的输出信号。
在本公开实施例中，主通路包括鉴频鉴相器PFD、电荷泵CP以及ADC采样器。在当前时间步，第八延迟信号与第九延迟信号输入主通路中，同时输入到主通路的鉴频鉴相器PFD，通过鉴频鉴相器PFD后输入到电荷泵CP，通过电荷泵CP后经过ADC采样器采样输出当前时间步的输出信号。可以将ADC采样器的输出信号通过数字处理后加载到第二电容上，用来改变第二电容的大小。
504、当主通路在当前时间步的输出信号稳定时，根据当前时间步的输出信号计算第一电容的值。
在本公开实施例中，在鉴频鉴相器PFD中，当第八延迟信号与第九延迟信号的相位相同时，电荷泵CP的输出稳定不变，而ADC采样器的输出也会稳定在某个值，此时，控制延迟锁相环路进行锁定，锁定第一电容和第二电容的值不再变化，则第八延迟信号与第九延迟信号的相位也不再变化，依然保持相位的相同，完成时钟信号的同步。当第一电容受外界影响产生变化时，通过分析当前时间步主通路的输出信号，就可以得到第一电容的具体变化量，这样就实现了对第一电容的检测。
具体的，在当前时间步，将第八延迟信号与第九延迟信号输入到主通路中，得到主通路在当前时间步的输出信号。由于第一电容上充电需要时间，所以参考时钟信号就产生了延迟，得到第八延迟信号，当第一电容的大小变化时，充电需要时间也会发生变化，因此，延迟时间也发生变化。第八延迟信号跟第九延迟信号通过主通路后输出对应的输出信号。输出信号又会反馈去控制消除通路上第二电容的大小。当环路锁定稳定时，第八延迟信号跟第九延迟信号的相位相同，主通路的输出稳定会稳定到某个值。当主通路的输出稳定时，可以从主通路的输出信号推出当前时间步的第二电容的值。而消除通道的延迟时间跟信号通路的延迟时间是正相关的。所以通过分析主通路的输出信号，就可以得到第一电容的具体变化量，这样就实现了对第一电容的检测。
本公开实施例中，将参考时钟信号依次通过所述第一电容和所述第一电压比较器进行延迟处理，得到第八延迟信号；将所述参考时钟信号与所述主通路在上一时间步的输出信号依次通过所述第二电容和所述第二电压比较器进行延迟处理，得到第九延迟信号；将所述第八延迟信号与第九延迟信号输入主通路，得到所述主通路在当前时间步的输出信号；当所述主通路在当前时间步的输出信号稳定时，根据所述当前时间步的输出信号计算所述第一电容的值。通过在信号通路和消除通路中设置第一电压比较器和第二电压比较器，并对第一电压比较器与第二电压比较器的翻转点进行调整，可以使第一电压比较器与第二电压比较器工作在较高的翻转点，从而可以提高延迟时间的信号量，提高锁定范围，进而提高电容检测的精确度。
同时，通过将在校准环节中，当环路锁定时相对参考时钟信号的延迟信号作为第十延迟信号，并在第十延迟信号与上一时间步的输出信号的基础上，通过第二电容进行延迟处理，得到第九延迟信号，并将第九延迟信号与第八延迟信号共同输入主通路，得到当前时间步输出信号，根据当前时间步的输出信号，计算第一电容的变化值和第二电容的变化值，可以根据第一电容的变化值和第二电容的变化值调整第一电容和第二电容，与现有技术相比，使用第十延迟信号替代参考时钟信号与上一时间步的输出信号进行延迟处理，从而避免使用参考时钟信号造成的时钟同步不准确，使得延迟锁相环路的时钟同步准确率提高。
可选的，在将第十延迟信号与主通路在上一时间步的输出信号通过第二电容进行延迟处理，得到第九延迟信号的步骤之前，还可以对延迟锁相环路进行校准，在校准环节中，当环路锁定时，获取参考时钟信号的延迟信号作为第十延迟信号。
在本公开实施例中，在正式对延迟锁相环路中的第一电容和第二电容进行检测之前，可以先对延迟锁相环路进行自动校准以及延迟时间校准，来确定环路锁定时，第十延迟信号相对于参考时钟信号的延迟时间。
需要说明的是，第十延迟信号为参考时钟信号加上自动校准以及延迟时间校准所得到的延迟时间。在本公开实施例中，可以通过一个适合的第十延迟信号来帮助延迟锁相环路在正式对第一电容和第二电容进行检测时，使主通路的输出信号快速达到稳定状态，使环路锁定速度提高。
可选的，在校准环节中，当环路锁定时，获取参考时钟信号的延迟信号作为第十延迟信号的步骤中，可以设置环路锁定的目标工作点；当环路锁定在目标工作点时，获取参考时钟信号的延迟信号作为第九延迟信号。
在本公开实施例中，环路锁定的目标工作点指的是延迟锁相环路稳定时的工作点，具体的，在鉴频鉴相器PFD中，当第八延迟信号与第九延迟信号的相位相同时，电荷泵CP的输出稳定不变，而ADC采样器的输出也会稳定在某个值，该某个值则为延迟锁相环路稳定时的工作点，此时，控制延迟锁相环路进行锁定，锁定第一电容和第二电容的值不再变化，则第八延迟信号与第九延迟信号的相位也不再变化，依然保持相位的相同，完成时钟信号在该个工作点的同步。
在校准环节中，可以先对延迟锁相环路进行自动校准以及延迟时间校准，来确定延迟锁相环路在环路锁定时的工作点作为目标工作点，此时，将获取到的延迟时间与参考时钟信号进行相加，得到参考时钟信号的延迟信号作为第十延迟信号。在正式对延迟锁相环路进行电容检测时，可以通过第十延迟信号延迟锁相环路快速锁定在目标工作点，提高延迟锁相环路的锁定速度。
在本公开实施例中，上述当前使用环境参数可以是延迟锁相环路所要应用的工况条件，比如工作频率、工作温度、主时钟设备参数和从时钟设备参数等。
在得到参考延迟锁相环路的历史延迟时间后，可以通过历史延迟时间，预测目标延迟锁相环路的预测延迟时间。具体的，可以将历史第一电容的变化值与历史第二电容的变化值输入预先训练好的第二时序网络预测中，预设得到目标延迟锁相环路的预测延迟时间。
在校准环节完成后，正式检测延迟锁相环路中的第一电容和第二电容的变化时，可以根据当前时间步的输出信号，计算第一电容的变化值和第二电容的变化值，可以根据第一电容的变化值和第二电容的变化值调整第一电容和第二电容，使得延迟锁相环路进行环路锁定。在本公开实施例中，使用自动校准时得到的延迟时间与参考时钟信号进行相加，得到第十延迟信号，可以帮助延迟锁相环路快速稳定，从而帮助延迟锁相环路快速进行环路锁定。在检测到第一电容发生变化时，主通路的输出信号也会发生变化，通过主通路的输出信号的变化，调整第二电容的大小，从而使延迟锁相环路的输出再次稳定下来，使延迟锁相环路进行环路锁定。
在本公开实施例中，需要说明的是，消除通道的输入信号相对于信号通道的输入信号有延迟，即第十延迟信号与参考时钟信号之间存在延迟时间，延迟时间为正式做电容检测前的校准环节进行确定。
本公开实施例还提供一种计算机存储介质，其中，该计算机存储介质存储用于电子数据交换的计算机程序，该计算机程序使得计算机执行如上述方法实施例中记载的任何一种基于延迟锁相环路的电容检测优化方法的部分或全部步骤。
本公开实施例还提供一种电子设备，所述电子设备包括存储了计算机程序的非瞬时性计算机可读存储介质，所述计算机程序可操作来使计算机执行如上述方法实施例中记载的任何一种基于延迟锁相环路的电容检测方法的部分或全部步骤。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本公开并不受所描述的动作顺序的限制，因为依据本公开，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于可选实施例，所涉及的动作和模块并不一定是本公开所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接入端口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件程序模块的形式实现。
所述集成的单元如果以软件程序模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储器中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器中，包括若干指令用以使得一台计算机设备(可为单片机、个人计算机、服务器或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储器包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

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  1. 一种基于延迟锁相环路的电容检测方法，应用于电容检测电路，所述电容检测电路包括：主通路、信号通路以及消除通路，所述信号通路的输出端与所述主通路的第一输入端电连接，所述消除通路的输出端与所述主通路的第二输入端电连接，所述消除通路的输入端与所述主通路的输出端电连接，以使所述主通路与所述消除通路构成延迟锁相环路，其中，所述信号通路包括第一电容，所述消除通路包括第二电容，所述方法包括以下步骤：
    当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号；
    将所述消除通路的第一输入信号与所述参考时钟信号通过所述第二电容进行延迟处理，得到第二延迟信号，所述第一输入信号为所述电容检测电路在闭环状态下稳定时所述主通路的输出信号；
    将所述第一延迟信号与所述第二延迟信号输入所述主通路，得到所述主通路在当前时间步的输出信号；以及
    根据所述主通路在当前时间步的输出信号计算所述第一电容的变化值。
  2. 如权利要求1所述的基于延迟锁相环路的电容检测方法，其中在所述当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号的步骤之前，所述方法还包括：
    当所述电容检测电路处于闭环状态时，获取所述电容检测电路在稳定时所述主通路的候选输出信号；以及
    从所述候选输出信号中确定所述消除通路的第一输入信号。
  3. 如权利要求2所述的基于延迟锁相环路的电容检测方法，其中所述当所述电容检测电路处于闭环状态时，获取所述电容检测电路在稳定时所述主通路的候选输出信号的步骤包括：
    当所述电容检测电路处于闭环状态时，将所述参考时钟信号通过所述第一电容进行延迟处理，得到第三延迟信号；
    将所述消除通路的第二输入信号与所述主通路在上一时间步的输出信号通过所述第二电容进行延迟处理，得到第四延迟信号，其中，所述消除通路的第二输入信号为所述参考时钟信号，或校准环节中当环路锁定时相对于所述参考时钟信号的延迟信号；以及
    将所述第三延迟信号与所述第四延迟信号输入到所述主通路，在所述主通路的输出信号稳定时，得到所述电容检测电路在闭环状态下稳定时所述主通路的候选输出信号。
  4. 如权利要求3所述的基于延迟锁相环路的电容检测方法，其中所述消除通路还包括状态开关，所述状态开关与所述第二电容的输入端电连接，在所述当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号的步骤之前，所述方法还包括：
    调整所述状态开关，将所述电容检测电路从闭环状态切换到开环状态，或者将所述电容检测电路从开环状态切换到闭环状态。
  5. 如权利要求4所述的基于延迟锁相环路的电容检测方法，其中所述主通路的输入端与一选择开关电连接，所述将所述第一延迟信号与所述第二延迟信号输入所述主通路，得到所述主通路在当前时间步的输出信号的步骤包括：
    通过所述选择开关，对所述第一延迟信号与所述第二延迟信号的接入端口进行选择，得到目标信号；以及
    将目标信号输入所述主通路，得到所述主通路在当前时间步的输出信号。
  6. 如权利要求5所述的基于延迟锁相环路的电容检测方法，其中所述通过所述选择开关，对所述第一延迟信号与所述第二延迟信号进行选择，得到目标信号的步骤包括：
    获取所述参考时钟信号的分频信号；以及
    通过所述分频信号控制所述选择开关对所述第一延迟信号与所述第二延迟信号进行选择，得到目标信号。
  7. 如权利要求6所述的基于延迟锁相环路的电容检测方法，其中所述选择开关包括第一选择器与 第二选择器，所述通过所述分频信号控制所述选择开关对所述第一延迟信号与所述第二延迟信号的接入端口进行选择，得到目标信号的步骤包括：
    通过所述分频信号控制所述第一选择器和所述第二选择器，通过所述第一选择器和所述第二选择器对所述第一延迟信号与所述第二延迟信号的接入端口进行选择，得到目标信号。
  8. 如权利要求7所述的基于延迟锁相环路的电容检测方法，其中所述主通路包括鉴频鉴相器以及电荷泵，所述鉴频鉴相器的输出端与所述电荷泵的输入端电连接，所述选择开关的输出端与所述鉴频鉴相器的输入端电连接，或者所述选择开关的输出端与所述电荷泵的输入端电连接，所述根据所述主通路在当前时间步的输出信号计算所述第一电容的变化值的步骤包括：
    对所述电荷泵的输出信号进行检测，得到所述第一电容的变化值。
  9. 如权利要求8所述的基于延迟锁相环路的电容检测方法，其中所述对所述电荷泵的输出信号进行检测，得到所述第一电容的变化值的步骤包括：
    预先确定所述电荷泵的输出信号中的目标频点；以及
    在所述电荷泵的输出信号中的目标频点处进行信号幅度检测，得到所述第一电容的变化值。
  10. 如权利要求1所述的基于延迟锁相环路的电容检测方法，其中当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号之前，所述方法还包括：
    将参考时钟信号通过所述第一电容进行延迟处理，得到第五延迟信号；
    将第六延迟信号与所述主通路在上一时间步的输出信号通过所述第二电容进行延迟处理，得到第七延迟信号，所述第七延迟信号为校准环节中，当环路锁定时相对于所述参考时钟信号的延迟信号；
    将所述第五延迟信号与第七延迟信号输入所述主通路，得到所述主通路在当前时间步的输出信号；以及
    在所述主通路在当前时间步的输出信号稳定时，根据所述当前时间步的输出信号计算所述第一电容的值。
  11. 如权利要求10所述的基于延迟锁相环路的电容检测方法，其中在所述将第六延迟信号与所述主通路在上一时间步的输出信号通过所述第二电容进行延迟处理，得到第七延迟信号的步骤之前，所述方法还包括：
    对所述延迟锁相环路进行校准；以及
    在所述校准环节中，当环路锁定时，获取所述参考时钟信号的延迟信号作为所述第六延迟信号。
  12. 如权利要求11所述的基于延迟锁相环路的电容检测方法，其中所述在所述校准环节中，当环路锁定时，获取所述参考时钟信号的延迟信号作为所述第六延迟信号的步骤包括：
    设置环路锁定的目标工作点；以及
    当环路锁定在所述目标工作点时，获取所述参考时钟信号的延迟信号作为所述第六延迟信号。
  13. 如权利要求12所述的基于延迟锁相环路的电容检测方法，其中所述设置环路锁定的目标工作点的步骤包括：
    通过预设的查找方法，确定环路锁定的目标工作点。
  14. 如权利要求12所述的基于延迟锁相环路的电容检测方法，其中所述主通路包括第三电容，所述设置环路锁定的目标工作点的步骤包括：
    获取供电电源的电压值；以及
    以环路锁定时所述第三电容的电压值接近二分之一所述供电电源的电压值为目标，确定环路锁定的目标工作点。
  15. 如权利要求12所述的基于延迟锁相环路的电容检测方法，其中所述主通路包括第三电容，所述设置环路锁定的目标工作点的步骤包括：
    根据供电电源的电压值，以提高信号量为目标，分析所述第三电容的电压值；
    根据所述第三电容的电压值，确定环路锁定的目标工作点。
  16. 如权利要求12所述的基于延迟锁相环路的电容检测方法，其中所述当环路锁定在所述目标工作点时，获取所述参考时钟信号的延迟信号作为所述第六延迟信号的步骤包括：
    通过调整所述第二电容的值，得到多个候选延迟时间；以及
    根据环路锁定在所述目标工作点时，从所述多个候选延迟时间中确定目标候选延迟时间；
    根据所述目标候选延迟时间和所述参考时钟信号，确定第六延迟信号。
  17. 如权利要求16所述的基于延迟锁相环路的电容检测方法，其中所述通过所述第二电容的值，得到多个候选延迟时间的步骤包括：
    获取目标延迟锁相环路中的当前使用环境参数；
    根据所述当前使用环境参数，获取参考延迟锁相环路的第二电容历史变化值，所述参考延迟锁相环路与所述目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数；
    根据所述第二电容历史变化值，预测所述目标延迟锁相环路的第二电容的初始值；
    通过调整所述第二电容的初始值，得到多个候选延迟时间。
  18. 如权利要求12所述的基于延迟锁相环路的电容检测方法，其中所述当环路锁定在所述目标工作点时，获取所述参考时钟信号的延迟信号作为所述第六延迟信号的步骤包括:
    获取目标延迟锁相环路中的当前使用环境参数；
    根据所述当前使用环境参数，获取参考延迟锁相环路的历史延迟时间，所述参考延迟锁相环路与所述目标延迟锁相环路具有相同的电路结构以及相同的使用环境参数；
    根据所述历史延迟时间，通过预训练的预测网络对所述目标延迟锁相环路的延迟时间进行预测，得到预测延迟时间；
    以所述预测延迟时间为初始延迟时间，对所述第二电容的值进行调整，得到多个候选延迟时间；
    根据环路锁定在所述目标工作点时，从所述多个候选延迟时间或初始延迟时间中，确定目标候选延迟时间；以及
    根据所述目标候选延迟时间和所述参考时钟信号，确定第六延迟信号。
  19. 如权利要求12所述的基于延迟锁相环路的电容检测方法，其中所述信号通路还包括第一电压比较器，所述消除通路还包括第二电压比较器，所述第一电压比较器的翻转点根据所述第一电压比较器的阈值电压进行调整，所述第二电压比较器的翻转点根据所述第二电压比较器的阈值电压进行调整，当所述电容检测电路处于开环状态时，将参考时钟信号通过所述第一电容进行延迟处理，得到第一延迟信号之前，所述方法还包括：
    将参考时钟信号依次通过所述第一电容和所述第一电压比较器进行延迟处理，得到第八延迟信号；
    将消除通路的输入信号与所述主通路在上一时间步的输出信号依次通过所述第二电容和所述第二电压比较器进行延迟处理，得到第九延迟信号；
    将所述第八延迟信号与第九延迟信号输入主通路，得到所述主通路在当前时间步的输出信号；以及
    当所述主通路在当前时间步的输出信号稳定时，根据所述当前时间步的输出信号计算所述第一电容的值。
  20. 如权利要求19所述的基于延迟锁相环路的电容检测方法，其中所述将参考时钟信号依次通过所述第一电容和所述第一电压比较器进行延迟处理，得到第八延迟信号的步骤包括：
    将所述参考时钟信号通过所述第一电容进行延迟处理，得到第二待翻转信号；以及
    当所述第二待翻转信号达到所述第一电压比较器的翻转点时，对所述第二待翻转信号进行翻转，得到第八延迟信号。
  21. 如权利要求19所述的基于延迟锁相环路的电容检测方法，其中所述将消除通路的输入信号与所述主通路在上一时间步的输出信号依次通过所述第二电容和所述第二电压比较器进行延迟处理，得到第九延迟信号的步骤包括：
    将所述主通路在上一时间步的输出信号加载到所述第二电容，并通过加载了所述主通路在上一时间步的输出信号的所述第二电容对所述消除通路的输入信号进行延迟处理，得到第三待翻转信号；以及
    当所述第三待翻转信号达到所述第二电压比较器的翻转点时，对所述第三待翻转信号进行翻转，得到第九延迟信号。
  22. 如权利要求19所述的基于延迟锁相环路的电容检测方法，其中在所述将参考时钟信号依次通 过所述第一电容和所述第一电压比较器进行延迟处理，得到第八延迟信号的步骤之前，所述方法还包括：
    以所述第一电容的上升沿终点或者所述第一电容的下降沿终点或者供电电源的电压值为接近点，确定所述第一电压比较器的目标翻转点；以及
    通过控制所述第一电压比较器的阈值电压，调整所述第一电压比较器的翻转点到所述第一电压比较器的目标翻转点。
  23. 如权利要求22所述的基于延迟锁相环路的电容检测方法，其中在所述以所述第一电容的上升沿终点或者所述第一电容的下降沿终点或者电源电压为接近点，确定所述第一电压比较器的目标翻转点的步骤之前，所述方法还包括：
    确定主通路的相位差检测类型；以及
    根据所述主通路的相位差检测类型，确定所述接近点的类型，所述接近点的类型包括所述第一电容的上升沿终点、所述第一电容的下降沿终点以及所述供电电源的电压值。
  24. 如权利要求23所述的基于延迟锁相环路的电容检测方法，其中所述主通路包括鉴频鉴相器，所述根据所述主通路的相位差检测类型，确定所述接近点的类型的步骤包括：
    当所述鉴频鉴相器检测的是上升沿的相位差时，确定所述接近点的类型为所述第一电容的上升沿终点；
    当所述鉴频鉴相器检测的是下降沿的相位差时，确定所述接近点的类型为所述第一电容的下降沿终点；以及
    当所述第一电压比较器的上升沿对应于所述参考时钟信号的上升沿，且所述鉴频鉴相器检测上升沿的相位差时，确定所述接近点的类型为供电电源的电压值。
  25. 如权利要求24所述的基于延迟锁相环路的电容检测方法，其中所述以所述第一电容的上升沿终点或者所述第一电容的下降沿终点或者电源电压为接近点，确定所述第一电压比较器的目标翻转点的步骤包括：
    确定延迟时间的信号量；
    根据所述延迟时间的信号量，调整所述第一电压比较器的翻转点与所述接近点的距离值；以及
    根据所述第一电压比较器的翻转点与所述接近点的距离值，确定所述第一电压比较器的目标翻转点。
  26. 如权利要求24所述的基于延迟锁相环路的电容检测方法，其中所述以所述第一电容的上升沿终点或者所述第一电容的下降沿终点或者电源电压为接近点，确定所述第一电压比较器的目标翻转点的步骤包括：
    确定延迟时间的信号量；
    根据所述延迟时间的信号量，调整所述第一电压比较器的翻转点与所述接近点的比例值；以及
    根据所述第一电压比较器的翻转点与所述接近点的比例值，确定所述第一电压比较器的目标翻转点。
  27. 如权利要求19所述的基于延迟锁相环路的电容检测方法，其中所述第一电压比较器的翻转点与所述第二电压比较器的翻转点相同，所述第一电压比较器的阈值电压与所述第二电压比较器的阈值电压通过同一个调整信号进行调整。
  28. 一种电容检测电路，其中所述延迟锁相环路包括：主通路、信号通路以及消除通路，所述信号通路的输出端与所述主通路的第一输入端电连接，所述消除通路的输出端与所述主通路的第二输入端电连接，所述消除通路的输入端与所述主通路的输出端电连接，以使所述主通路与所述消除通路构成延迟锁相环路，其中，所述信号通路包括第一电容，所述消除通路包括第二电容，所述延迟锁相环路用于实现如权利要求1至18中任一项所述的基于延迟锁相环路的电容检测方法中的步骤。
  29. 如权利要求28所述的电容检测电路，其中，所述信号通路还包括第一电压比较器，所述消除通路还包括第二电压比较器，所述第一电压比较器的翻转点根据所述第一电压比较器的阈值电压进行调整，所述第二电压比较器的翻转点根据所述第二电压比较器的阈值电压进行调整，所述延迟锁相环路用于实现如权利要求19至27中任一项所述的基于延迟锁相环路的电容检测方法中的步骤。
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