WO2024066230A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024066230A1
WO2024066230A1 PCT/CN2023/082034 CN2023082034W WO2024066230A1 WO 2024066230 A1 WO2024066230 A1 WO 2024066230A1 CN 2023082034 W CN2023082034 W CN 2023082034W WO 2024066230 A1 WO2024066230 A1 WO 2024066230A1
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WIPO (PCT)
Prior art keywords
spacer
contact hole
layer
planarization layer
insulating layer
Prior art date
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PCT/CN2023/082034
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English (en)
French (fr)
Inventor
吴铁将
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长鑫存储技术有限公司
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Publication of WO2024066230A1 publication Critical patent/WO2024066230A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • mobile devices such as mobile phones and tablets due to its advantages of small size, high integration and fast transmission speed.
  • DRAM Dynamic Random Access Memory
  • people have put forward huge demands for small size and integration of memory.
  • the intervals between adjacent contact plugs and adjacent conductive structures in dynamic random access memory are also continuously compressed, which increases the probability of short circuit between contact plugs and adjacent conductive structures.
  • the present disclosure provides a semiconductor structure, comprising: a substrate, a first planarization layer, a first spacer, a second spacer, a second planarization layer, a contact hole and a contact plug.
  • the substrate comprises a substrate and two adjacent gate structures located on the substrate.
  • the substrate has a doped region located between the two adjacent gate structures.
  • the first planarization layer covers the substrate.
  • the first spacer and the second spacer are located on the first planarization layer.
  • the space between the first spacer and the second spacer is substantially aligned with the space between the two adjacent gate structures.
  • the second planarization layer is located on a side of the first planarization layer away from the substrate and covers the first spacer and the second spacer.
  • the contact hole penetrates the second planarization layer and the first planarization layer and at least partially exposes the doped region. A portion of the contact hole is located between the first spacer and the second spacer, and another portion of the contact hole is located between the two adjacent gate structures.
  • the contact plug is disposed in the contact hole and is electrically connected to the doped region.
  • the first spacer and the second spacer are formed of a conductive material
  • the contact plug is electrically connected to the first spacer
  • the contact plug and the second spacer are insulated from each other.
  • At least one of the first spacer and the second spacer is formed as a conductive line.
  • the first spacer and the second spacer are formed of an insulating material.
  • the contact plug is in direct contact with a side surface of the first spacer adjacent to the second spacer and a portion of a top surface of the first spacer adjacent to the side surface.
  • the portion of the top surface and the side surface of the first spacer contacting the contact plug form a step.
  • the semiconductor structure further includes: an insulating layer located between the first planarization layer and the second planarization layer and covering the second spacer and the surface of the first spacer except the side surface and the part of the top surface.
  • the contact hole also penetrates the insulating layer.
  • the contact plug further covers a portion of the surface of the insulating layer that is above a top surface of the second spacer.
  • the insulating layer includes a first insulating layer and a second insulating layer stacked together, wherein the material of the first insulating layer includes nitride, and the material of the second insulating layer includes oxide.
  • the contact plug includes a diffusion barrier layer and a metal layer, wherein the diffusion barrier layer covers the sidewall and bottom surface of the contact hole, and the metal layer covers the diffusion barrier layer and fills the contact hole.
  • the embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising the following steps.
  • a substrate comprising a substrate and two adjacent gate structures located on the substrate, and the substrate has a doping region located between the two adjacent gate structures.
  • a first planarization layer is formed on the substrate.
  • a first spacer and a second spacer are formed on a surface of the first planarization layer away from the substrate, wherein the space between the first spacer and the second spacer is substantially aligned with the space between the two adjacent gate structures.
  • a second planarization layer is formed on a surface of the first planarization layer away from the substrate, wherein the second planarization layer covers the first spacer and the second spacer.
  • the second planarization layer is etched to form a first contact hole penetrating the second planarization layer.
  • the first contact hole is located between the first spacer and the second spacer.
  • the first planarization layer is self-alignedly etched to form a second contact hole penetrating the first planarization layer between the two adjacent gate structures and at least partially exposing the doped region.
  • Contact plugs are formed in the first contact hole and the second contact hole, wherein the contact plugs are electrically connected to the doped region.
  • etching the second planarization layer to form a first contact hole penetrating the second planarization layer includes: etching the second planarization layer to expose a side surface of the first insulator close to the second insulator and a portion of the top surface of the first insulator close to the side surface to form the first contact hole.
  • the first spacer and the second spacer are formed of insulating material.
  • the first spacer and the second spacer are formed of a conductive material.
  • the preparation method further includes: before forming the second planarization layer, forming an insulating layer on the surface of the first planarization layer away from the substrate, the insulating layer covering the first spacer and the second spacer.
  • the second planarization layer is formed on the surface of the insulating layer away from the substrate; the first contact hole and the second contact hole also penetrate the insulating layer and are connected.
  • the insulating layer includes a first insulating layer and a second insulating layer formed by stacking, wherein the material of the first insulating layer includes nitride, and the material of the second insulating layer includes oxide.
  • the etching of the second planarization layer to form a first contact hole penetrating the second planarization layer further includes the following steps.
  • the second planarization layer is etched to form an initial first contact hole between the first spacer and the second spacer.
  • an oblique ion implantation process is performed on the insulating layer to form a to-be-removed area.
  • the portion of the insulating layer located in the to-be-removed area is removed to expose the side surface of the first spacer close to the second spacer and a portion of the top surface of the first spacer close to the side surface, thereby forming the first contact hole.
  • the initial first contact hole further exposes a portion of the surface of the insulating layer above both the first spacer top surface and the second spacer top surface.
  • performing an inclined ion implantation process on the insulating layer to form a to-be-removed area includes:
  • the portion to be removed of the insulating layer is processed along a direction having an angle with the axis of the initial first contact hole by an ion implantation process to form the region to be removed.
  • the portion to be removed covers a top corner of the first spacer close to the second spacer.
  • the self-aligned etching of the first planarization layer based on the first contact hole further includes: self-aligned etching of a portion of the insulating layer located at the bottom of the first contact hole and the first planarization layer based on the first contact hole.
  • forming contact plugs in the first contact hole and the second contact hole includes the following steps.
  • a diffusion barrier layer is formed to cover the sidewalls of the first contact hole and the sidewalls and bottom surface of the second contact hole.
  • a metal layer is formed covering the diffusion barrier layer and filling the first contact hole and the second contact hole.
  • FIG1 is a schematic structural diagram of a semiconductor structure provided in an embodiment
  • FIG2 is a schematic structural diagram of another semiconductor structure provided in an embodiment
  • FIG3 is a schematic structural diagram of another semiconductor structure provided in an embodiment
  • FIG4 is a schematic structural diagram of another semiconductor structure provided in an embodiment
  • FIG5 is a schematic flow chart of a semiconductor manufacturing method provided in an embodiment
  • FIG6 is a schematic cross-sectional view of a semiconductor substrate provided in an embodiment
  • FIG7 is a schematic cross-sectional view of a structure obtained after forming a first planarization layer provided in one embodiment
  • FIG8 is a schematic cross-sectional view of a structure obtained after forming a first spacer and a second spacer provided in one embodiment
  • FIG9 is a schematic cross-sectional view of a structure obtained after forming a second planarization layer provided in one embodiment
  • FIG10 is a schematic cross-sectional view of a structure obtained after forming a first contact hole provided in an embodiment
  • FIG11 is a schematic cross-sectional view of a structure obtained after forming a second contact hole provided in one embodiment
  • FIG12 is a schematic cross-sectional view of a structure obtained after forming a contact plug according to an embodiment
  • FIG13 is a schematic flow chart of another semiconductor manufacturing method provided in an embodiment
  • FIG14 is a schematic cross-sectional view of a structure obtained after forming a first contact hole and a second contact hole in the preparation method shown in FIG13;
  • FIG15 is a schematic cross-sectional view of a structure obtained after forming an insulating layer in the preparation method shown in FIG13;
  • FIG16 is a schematic diagram of a process of performing oblique ion implantation on an insulating layer provided in one embodiment
  • FIG17 is a schematic cross-sectional view of a structure obtained after oblique ion implantation is performed on an insulating layer to form a region to be removed, provided in one embodiment
  • FIG18 is a cross-sectional schematic diagram of a first contact hole formed after removing the insulating layer provided in an embodiment
  • 19 is a schematic cross-sectional view of a second contact hole formed by etching the bottom of the first contact hole and the first planarization layer provided in one embodiment
  • FIG20 is a schematic diagram of a process for forming a diffusion barrier layer and a metal layer according to an embodiment
  • FIG. 21 is a schematic cross-sectional view of the structure obtained after the diffusion barrier layer and the metal layer are formed in the preparation method shown in FIG. 20 .
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected objects.
  • the formation of metal interconnection structures generally uses a photolithography mask to perform the alignment process before etching. For example, it is necessary to first perform alignment and positioning on the substrate/dielectric layer and form a photolithography pattern, and then use an etching process to perform patterned etching in the direction of the doped region according to the above-formed photolithography pattern to form a contact hole connected to the doped region, and then deposit metal (such as tungsten) in the contact hole to form a contact plug, and finally deposit and etch metal on the isolation layer/dielectric layer to form a conductive layer/line.
  • the end of the contact plug away from the substrate can be electrically connected to the conductive layer/line
  • the end of the contact plug close to the substrate can be electrically connected to the doped region, thereby forming a complete metal interconnection structure.
  • the spacing between adjacent contact plugs and adjacent conductive structures is also constantly compressed, which increases the probability of short circuits between contact plugs and adjacent conductive structures.
  • the embodiments of the present disclosure provide a semiconductor structure to improve the molding accuracy of the contact plug and reduce the process difficulty of the contact plug, thereby facilitating improving the production yield of the semiconductor structure and ensuring the electrical reliability of the semiconductor structure.
  • the semiconductor structure includes: a substrate 10, a first planarization layer 20, a first spacer 30, a second spacer 40, a second planarization layer 50, a contact hole 60, and a contact plug 70.
  • the substrate 10 includes a substrate 11, two adjacent gate structures 13 located on the substrate 11, and a doped region 12 located between the two gate structures 13.
  • the substrate 10 is covered with a first planarization layer 20, a first spacer 30 and a second spacer 40 are located on the first planarization layer 20, and a space between the first spacer 30 and the second spacer 40 is substantially aligned with a space between two adjacent gate structures 13.
  • the second planarization layer 50 is located on a side of the first planarization layer 20 away from the substrate 10, and covers the first spacer 30 and the second spacer 40.
  • the contact hole 60 penetrates the second planarization layer 50 and the first planarization layer 20 and at least partially exposes the doped region 12, wherein a portion of the contact hole 60 is located between the first spacer 30 and the second spacer 40, and another portion of the contact hole 60 is located between the two adjacent gate structures 13.
  • the contact plug 70 is located in the contact hole 60 and is electrically connected to the doped region 12 .
  • the substrate 11 may be made of semiconductor material, insulating material, conductor material or any combination thereof.
  • the substrate 11 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the substrate 11 may be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator.
  • the substrate 11 is a silicon substrate.
  • the following embodiments of the present disclosure are described by taking two adjacent gate structures 13 as an example, but it can be understood that the semiconductor structure provided by the embodiments of the present disclosure can be applied between any two adjacent gate structures 13 of the multiple gate structures 13.
  • a doped region 12 is usually disposed beside the gate structure 13 .
  • the embodiment of the present disclosure takes the example that the doped region 12 is located between adjacent gate structures 13 to illustrate the contact plug 70 used to connect the doped region 12 .
  • the doping region 12 is an N-type doping region. In another example, the doping region 12 is a P-type doping region.
  • the first planarization layer 20 covers the base 10 . That is, the first planarization layer 20 may be formed on the substrate 11 and cover two adjacent gate structures 13 .
  • the distance between the top surface of the first planarization layer 20 and the substrate 11 is greater than the distance between the top surfaces of the two gate structures 13 and the substrate 11.
  • the distance between the top surface of the first planarization layer 20 and the substrate 11 may be between 1.5 times and 5 times, such as 1.5 times, 2 times, 3 times, 4 times, or 5 times, of the distance between the top surfaces of the two gate structures 13 and the substrate 11.
  • the material of the first planarization layer 20 may be a semiconductor material, an insulating material, or a combination thereof having good insulating properties.
  • the first planarization layer 20 is a silicon oxide layer. In another example, the first planarization layer 20 is a silicon nitride layer. In yet another example, the first planarization layer 20 is a silicon oxynitride layer. The embodiments of the present disclosure are not limited thereto.
  • the first spacer 30 and the second spacer 40 are located on the first planarization layer 20 and the first The space between the spacer 30 and the second spacer 40 is substantially aligned with the space between two adjacent gate structures 13 .
  • the distance between the first spacer 30 and the second spacer 40 is smaller than the distance between two adjacent gate structures 13 .
  • the orthographic projection of the space between the first spacer 30 and the second spacer 40 on the substrate 11 is within the range of the orthographic projection of the space between two adjacent gate structures 13 on the substrate 11 .
  • the space between the first spacer 30 and the second spacer 40 is perpendicular to the central axis of the substrate 11 and coincides or approximately coincides with the space between two adjacent gate structures 13 which is perpendicular to the central axis of the substrate 11, and the orthographic projection contour of the space between the first spacer 30 and the second spacer 40 on the substrate 11 and the orthographic projection contour of the space between the two adjacent gate structures 13 on the substrate 11 may have a spacing within an allowable deviation range, and the deviation includes design deviation and/or process deviation.
  • the material of the second planarization layer 50 can be the same as or different from that of the first planarization layer 20.
  • the distance between the top surface of the second planarization layer 50 and the first planarization layer 20 should be greater than the height of the first spacer 30 and the second spacer 40 to effectively cover.
  • the material of the second planarization layer 50 may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the distance between the top surface of the second planarization layer 50 and the first planarization layer 20 is 1.5 to 5 times, such as 1.5, 2, 3, 4 or 5 times, the height of the first spacer 30 and the second spacer 40 .
  • the contact hole 60 passes through the second planarization layer 50 and the first planarization layer 20, and the contact hole 60 can be divided into two parts, one part of the contact hole 60 is located between the first insulator 30 and the second insulator 40, and the other part of the contact hole 60 is located between two adjacent gate structures 13.
  • a portion of the contact hole 60 located between the first spacer 30 and the second spacer 40 may contact opposite side surfaces of the first spacer 30 and the second spacer 40 , respectively.
  • a portion of the contact hole 60 located between two adjacent gate structures 13 may contact opposite side surfaces of the two adjacent gate structures 13 , respectively.
  • a contact plug 70 is disposed in the contact hole 60 , and the contact plug 70 is also electrically connected to the doped region 12 .
  • one end of the contact plug 70 away from the substrate 11 is flush with the top surface of the second planarization layer 50 , and one end of the contact plug 70 close to the substrate 11 can pass through the upper surface of the substrate 11 and penetrate into the doped region 12 to form an electrical connection with the doped region 12 .
  • the material of the contact plug 70 includes metal or metal compound, such as tungsten or copper.
  • the contact plug 70 may be a single-layer structure or a stacked-layer structure.
  • a first spacer 30 and a second spacer 40 are arranged on the first planarization layer 20, and the space between the first spacer 30 and the second spacer 40 is arranged to be roughly aligned with the space between the two adjacent gate structures 13, so that the space between the first spacer 30 and the second spacer 40 can be used for self-aligned etching of the contact hole 60, and the space above the first spacer 30 and the second spacer 40 is used to provide a larger process window for the contact hole 60, so that a part of the contact hole 60 is located between the first spacer 30 and the second spacer 40, and the other part of the contact hole 60 is located between the two adjacent gate structures 13.
  • the embodiment of the present disclosure does not limit the materials of the first spacer 30 and the second spacer 40 , for example, both insulating materials and conductive materials may be used.
  • the materials of the first spacer 30 and the second spacer 40 are insulating materials, such as oxides, nitrides, or oxynitrides, etc.
  • the contact plug 70 can be in direct contact with both the first spacer 30 and the second spacer 40 , thereby utilizing the insulating properties of the first spacer 30 and the second spacer 40 to effectively enhance the insulating protection effect of the contact plug 70 .
  • the material of the first spacer 30 and the second spacer 40 may be a conductive Based on this, the contact plug 70 and the first spacer 30 may be electrically connected, and the contact plug 70 and the second spacer 40 may be insulated from each other.
  • the material of the first spacer 30 and the second spacer 40 may be metal, such as metal aluminum, metal copper, metal tungsten, or copper-aluminum alloy.
  • the semiconductor structure further includes an insulating layer 80.
  • the insulating layer 80 is located between the first planarization layer 20 and the second planarization layer 50, and covers the second spacer 40 and the first spacer 30 except for the side surface and a portion of the top surface that are in contact with the contact plug 70.
  • the contact hole 60 also penetrates the insulating layer 80.
  • the first spacer 30 and the second spacer 40 are made of conductive material, and a contact plug 70 is provided to be electrically connected to the first spacer 30, and the contact plug 70 and the second spacer 40 are insulated from each other.
  • the two ends of the contact plug 70 can respectively connect the first spacer 30 and the doping region 12 to form a complete metal interconnection structure.
  • the contact plug 70 can also be insulated from the second spacer 40 to increase the electrical application of the second spacer 40.
  • the insulating layer 80 covers the second spacer 40 and is located between the contact plug 70 and the second spacer 40, which can also avoid the risk of failure such as short circuit between the contact plug 70 and the second spacer 40, which is conducive to improving the electrical stability of the semiconductor structure.
  • At least one of the first spacer 30 and the second spacer 40 is a conductive wire.
  • the first spacer 30 is a conductive line, such as a bit line conductive line.
  • the first spacer 30 as a conductive line structure also has the function of providing alignment for the contact hole 60 forming the contact plug 70.
  • the second spacer 40 is a conductive line, such as a source conductive line.
  • the second spacer 40 as a conductive line structure also has the function of providing alignment for forming the contact hole 60 of the contact plug 70.
  • the semiconductor structure further includes a plurality of conductive lines formed in the same step as the first spacer 30 and the second spacer 40. That is, the first spacer 30, the second spacer 40 and the plurality of conductive lines are formed simultaneously using the same material layer and the same patterning process; wherein at least one of the first spacer 30 and the second spacer 40 may have the same function as the conductive line.
  • the first insulator 30 and the second insulator 40 can have more functions, so as to realize self-aligned etching of the contact hole 60 and wiring design of the conductive line in the semiconductor structure without increasing the number of components, thereby simplifying the manufacturing process and reducing costs.
  • the contact plug 70 may directly contact the side surface of the first spacer 30 close to the second spacer 40 and a portion of the top surface of the first spacer 30 close to the aforementioned side surface.
  • portions of the top and side surfaces of the first spacer 30 that are in contact with the contact plug 70 form steps.
  • the orthographic projection area of the upper portion of the contact plug 70 on the substrate 11 is larger than the orthographic projection area of the lower portion thereof on the substrate 11.
  • the upper portion of the contact plug 70 refers to a portion thereof that is higher than the top surface of the first spacer 30 or the second spacer 40; the middle and lower portion of the contact plug 70 refers to a portion thereof that is located between the first spacer 30 and the second spacer 40 and up to between two adjacent gate structures 13.
  • the contact plug 70 and the side surface of the first insulator 30 close to the second insulator 40 are completely in contact, and the ratio of the contact area between the contact plug 70 and the top surface of the first insulator 30 to the total top surface area of the first insulator 30 is less than 90%, for example, it can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90%.
  • the contact plug 70 is in direct contact with the side surface of the first spacer 30 close to the second spacer 40 and the part of the top surface connected to the aforementioned side surface.
  • the contact plug 70 and the first spacer 30 in the embodiment of the present disclosure can have a larger contact area. In this way, a more reliable electrical contact can be formed between the contact plug 70 and the first spacer 30, so as to improve the reliability of the semiconductor structure.
  • the semiconductor structure further includes an insulating layer 80.
  • the thickness of the insulating layer 80 is less than 1/3 of the distance between the first spacer 30 and the second spacer 40.
  • the thickness of the insulating layer 80 is equal to 1/3, 1/4 or 1/5 of the distance between the first spacer 30 and the second spacer 40.
  • the insulating layer 80 is an oxide layer, a nitride layer, or an oxynitride layer.
  • a pad oxide layer may be further disposed between the insulating layer 80 and the first planarization layer 20 to improve adhesion of the contact interface between the insulating layer 80 and the first planarization layer 20 .
  • an insulating layer 80 is provided between the first planarization layer 20 and the second planarization layer 50, and the insulating layer 80 covers the first insulator 30 and the second insulator 40.
  • the insulating layer 80 can be used to provide more reliable insulation protection between semiconductor active devices, thereby effectively eliminating the risks of short circuits caused by ion residues in the manufacturing process, too small spacing between components, etc.
  • the insulating layer 80 may be a single-layer structure or a stacked-layer structure.
  • the insulating layer 80 includes a first insulating layer 81 and a second insulating layer 82 which are stacked.
  • the material of the first insulating layer 81 includes an oxide
  • the material of the second insulating layer 82 includes a nitride.
  • the insulating layer 80 is a multilayer structure composed of multiple materials, so that the required insulating layer 80 can be constructed by taking advantage of the different properties of different materials. In this way, it can be flexibly adjusted to adapt to different components to be isolated, thereby achieving the best insulation effect.
  • the first insulating layer 81 is located on a side of the second insulating layer 82 close to the substrate 10 .
  • the contact plug 70 further covers a portion of the surface of the insulating layer 80 that is above the top surface of the second spacer 40 .
  • the orthographic projection area of the upper portion of the contact plug 70 on the substrate 11 is larger than the orthographic projection area of the lower portion thereof on the substrate 11.
  • the ratio of the contact area between the contact plug 70 and the top surface of the second spacer 40 to the total top surface area of the second spacer 40 is less than 90%, for example, it may be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or 90%.
  • the contact plug 70 includes a diffusion barrier layer 71 and a metal layer 72 ; wherein the diffusion barrier layer 71 covers the sidewalls and the bottom surface of the contact hole 60 , and the metal layer 72 covers the diffusion barrier layer 71 and fills the contact hole 60 .
  • the diffusion barrier layer 71 may be made of materials such as titanium nitride to obtain high conductivity, good anti-diffusion properties, and good stability.
  • the diffusion barrier layer 71 is in a thin film shape and covers the sidewalls and bottom surface of the contact hole 60 .
  • the metal layer 72 may be a metal material containing tungsten.
  • the contact plug 70 is a multi-layer structure, including a metal layer 72 and a diffusion barrier layer 71 located between the metal layer 72 and the contact hole 60.
  • the good barrier effect of the diffusion barrier layer 71 on metal atoms can prevent the atoms in the metal from diffusing into the semiconductor material, thereby maintaining the stable performance of the semiconductor structure.
  • the diffusion barrier layer 71 also has good adhesion and can act as a binder between the metal material and other materials (such as semiconductor materials, insulating materials, etc.) to ensure that the contact between the contact plug 70 and the doped region 12 is more stable.
  • the gate structure 13 disposed on the substrate 11 can have a variety of structures to match the requirements of the semiconductor structure.
  • the embodiment of the present disclosure exemplarily provides a possible implementation method. Please continue to refer to Figure 4.
  • the gate structure 13 includes: a gate disposed on the substrate 11 and an isolation barrier wall that wraps the top surface and sidewalls of the gate; wherein the gate includes: a dielectric layer 131, a conductive layer 132 and a gate mask layer 133 stacked on the substrate 11; the isolation barrier wall includes: a first barrier wall 134 covering the top surface and sidewalls of the gate mask layer 133, the sidewalls of the conductive layer 132 and the sidewalls of the dielectric layer 131, and a second barrier wall 135 covering at least part of the sidewalls of the first isolation layer 134.
  • the dielectric layer 131 may be a silicon oxide layer, a high-K material layer, or a combination thereof.
  • the conductive layer 132 may be a polysilicon layer doped with ions.
  • the gate mask layer 133 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or any combination thereof.
  • the first barrier wall 134 may be a silicon oxide layer.
  • the second barrier 135 may be a silicon nitride layer, a silicon oxynitride layer, or any combination thereof.
  • Some embodiments of the present disclosure further provide a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure in some of the above embodiments.
  • the preparation method also has the technical advantages of the above semiconductor structure.
  • the preparation method comprises the following steps:
  • the substrate includes a substrate and two adjacent gate structures located on the substrate, and the substrate has a doping region located between the two adjacent gate structures.
  • the space between the first spacer and the second spacer can be used to perform self-aligned etching of the contact hole, and the space above the first spacer and the second spacer can be used to provide a larger process window for the contact hole, so that a part of the contact hole is located between the first spacer and the second spacer, and the other part of the contact hole is located between the two adjacent gate structures.
  • a substrate 10 is provided, wherein the substrate 10 includes a substrate 11 and two adjacent gate structures 13 located on the substrate 11 , and the substrate 11 has a doping region 12 located between the two adjacent gate structures 13 .
  • the substrate 11 is a silicon substrate.
  • ions to be doped may be diffused or implanted into the region of the silicon substrate between adjacent gate structures 13 to form a doped region 12 between two adjacent gate structures 13 .
  • the ions to be doped may be P-type ions or N-type ions.
  • step S200 referring to FIG. 7 , a first planarization layer 20 is formed on the substrate 10 .
  • the first planarization layer 20 covers the gate structure 13 , and the thickness of the first planarization layer 20 is greater than the height of the gate structure 13 .
  • a dielectric layer may be first formed on the base 10 by a deposition process (such as chemical vapor deposition, physical vapor deposition, evaporation, etc.), and then the surface of the dielectric layer away from the substrate 11 may be planarized by a chemical mechanical polishing process to form the first planarization layer 20.
  • a spin coating process may be used to directly form the first planarization layer 20 with a flat surface.
  • the first planarization layer 20 may be an oxide layer, such as a silicon oxide layer.
  • a photolithography process can be used to perform graphic positioning on the surface of the isolation material layer away from the substrate 10, for example, a photoresist layer with a pattern is formed on the surface of the isolation material layer away from the substrate 10, and then the isolation material layer is etched based on the pattern in the photoresist, thereby forming a first insulator 30 and a second insulator 40.
  • the materials of the first spacer 30 and the second spacer 40 may be conductive materials or insulating materials.
  • a conductive material is used to form the first spacer 30 and the second spacer 40.
  • the conductive material is, for example, a metal, such as aluminum, copper, or a copper-aluminum alloy.
  • the first spacer 30 and the second spacer 40 may be formed by a deposition process (eg, physical vapor deposition, chemical vapor deposition, etc.).
  • a deposition process eg, physical vapor deposition, chemical vapor deposition, etc.
  • the first spacer 30 and the second spacer 40 may be formed by a conductive material, so that at least one of the first spacer 30 and the second spacer 40 may also be reused as a conductive line in the semiconductor structure.
  • the first spacer 30 and the second spacer 40 are formed using an insulating material.
  • a second planarization layer 50 is formed on a surface of the first planarization layer 20 away from the substrate 10 ; wherein the second planarization layer 50 covers the first spacer 30 and the second spacer 40 .
  • a dielectric layer may be formed on the first planarization layer 20 by a deposition process such as chemical vapor deposition, and then the surface of the dielectric layer away from the first planarization layer 20 may be planarized by a process such as chemical mechanical polishing to form the second planarization layer 50 .
  • the second planarization layer 50 may be a nitride layer, such as a silicon nitride layer.
  • step S500 referring to FIG. 10 , the second planarization layer 50 is etched to form a first contact hole 61 penetrating the second planarization layer 50 .
  • the first contact hole 61 is located between the first spacer 30 and the second spacer 40 .
  • photolithography is performed on the second planarization layer using a mask, and the photolithography position is approximately located between the upper surfaces of the first spacer 30 and the second spacer 40.
  • the process window requirement can be met with the help of the self-alignment of the first spacer 30 and the second spacer 30.
  • the upper surfaces of the first spacer 30 and the second spacer 40 and the side surfaces opposite to each other are used as etching barriers, so that the formed first contact hole 61 can be ensured to be located between the first spacer 30 and the second spacer 40. In this way, the central axis of the first contact hole 61 is approximately aligned with the space between the two adjacent gate structures 13 on the substrate 11 and the doped region 12 below the space.
  • step S500 the second planarization layer 50 is etched to form a first contact hole 61 penetrating the second planarization layer 50, and the step also includes: etching the second planarization layer 50 to expose the side surface of the first insulator 30 close to the second insulator 40 and a portion of the top surface of the first insulator 30 close to the aforementioned side surface to form the first contact hole 61.
  • the first contact hole 61 can also cover part of the top surface of the first spacer 30.
  • the corresponding photolithography pattern window will also cover the second planarization layer above part of the top surface of the first spacer 30, thereby facilitating the reduction of the photolithography alignment accuracy, that is, the use of a photolithography device with slightly lower accuracy can also meet the process requirements, thereby helping to reduce the manufacturing cost.
  • the contact plug 70 formed in the first contact hole 61 of the structure can also form contact with one side and part of the top surface of the first spacer 30, which is conducive to increasing the contact area between the contact plug 70 and the first spacer 30, so as to improve the connection reliability between the contact plug 70 and the first spacer 30 when the first spacer 30 is a conductive line.
  • step S600 referring to FIG. 11 , based on the first contact hole 61 , the first planarization layer 20 is self-alignedly etched to form a second contact hole 62 penetrating the first planarization layer 20 between two adjacent gate structures 13 and at least partially exposing the doped region 12 .
  • the central axis of the first contact hole 61 formed in the above step S500 is roughly aligned with the doped region 12 on the substrate 11. Based on the first contact hole 61 continuing to etch toward the substrate 11, the second contact hole 62 formed through the first planarization layer 20 will also be located in the area between two adjacent gate structures 13.
  • a method such as dry plasma etching is adopted, and its anisotropic etching characteristics are utilized to ensure that etching occurs as much as possible in a direction toward the substrate 11, thereby ensuring etching accuracy to the greatest extent.
  • step S700 referring to FIG. 12 , a contact plug 70 is formed in the first contact hole 61 and the second contact hole 62 ; wherein the contact plug 70 is electrically connected to the doped region 12 .
  • a metal material such as metal tungsten, may be filled into the first contact hole 61 and the second contact hole 62 to form a contact plug 70 .
  • the second contact hole 62 formed in the aforementioned step S600 may penetrate the surface of the substrate 11 to reach deep into the doped region 12 .
  • the method for preparing the semiconductor structure further includes the following steps:
  • step S350 referring to FIG. 14 , an insulating layer 80 is formed on a surface of the first planarization layer 20 away from the substrate 10 , and the insulating layer 80 covers the first spacer 30 and the second spacer 40 .
  • the insulating layer 80 may be an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof formed by a deposition process such as chemical vapor deposition.
  • the method for preparing the semiconductor structure needs to etch the second planarization layer 50 by means of the space between the first spacer 30 and the second spacer 40 to form the first contact hole 61, and etch the first planarization layer 20 based on the first contact hole 61 to form the second contact hole 62, and then form the contact plug 70 in the first contact hole 61 and the second contact hole 62.
  • an insulating layer 80 is formed between the first planarization layer 20 and the second planarization layer 50, which is conducive to enhancing the electrical insulation performance of the first spacer 30 and the second spacer 40.
  • forming an insulating layer 80 on a surface of the first planarization layer 20 away from the substrate 10 in step S350 further includes: stacking a first insulating layer 81 and a second insulating layer 82 on a surface of the first planarization layer 20 away from the substrate 10 .
  • the first insulating layer 81 and the second insulating layer 82 may be formed in sequence by using one or more of chemical vapor deposition, atomic layer deposition, high-density plasma deposition, and the like.
  • the material of the first insulating layer 81 includes oxide, such as silicon oxide, and the material of the second insulating layer 82 includes nitride, such as silicon nitride.
  • step S400 ′ a second planarization layer 50 is formed on the surface of the insulating layer 80 away from the substrate 10 .
  • the second planarization layer 50 covers the second insulating layer 82 .
  • a dielectric layer such as silicon oxide or silicon oxynitride may be deposited on the surface of the insulating layer 80 away from the substrate 10 , and then the dielectric layer may be subjected to chemical mechanical polishing to obtain the second planarization layer 50 .
  • step S500 the second planarization layer is etched to form a first contact hole penetrating the second planarization layer, and the following steps are also included:
  • an inclined ion implantation process is performed on the insulating layer on the exposed portion of the top surface and the side surface of the first insulator to form a to-be-removed area, so that the portion of the insulating layer 80 to be removed can be easily removed in subsequent steps and ensure that the surface of the first insulator that meets the requirements is exposed.
  • step S510 referring to FIG. 17 , the second planarization layer 50 is etched to form an initial first contact hole 610 between the first spacer 30 and the second spacer 40 .
  • the initial first contact hole 610 in addition to the portion located between the first insulator 30 and the second insulator 40 , also includes a portion for exposing a portion of the surface of the insulating layer 80 located on both the top surface of the first insulator 30 and the top surface of the second insulator 40 .
  • an inclined ion implantation process is performed on the insulating layer 80 to form an area A to be removed, and the process also includes: using an ion implantation process to process the portion of the insulating layer 80 to be removed along a direction having an angle X with the axis of the initial first contact hole 610 to form the area A to be removed; the portion of the insulating layer 80 to be removed covers the top corner of the first insulator 30 close to the second insulator 40.
  • the area that needs to be treated with ion implantation is mainly located in the area where the insulating layer 80 covers the side surface of the first insulator 30 close to the second insulator 40 and the part of the top surface of the first insulator 30 close to the said side surface, and it is necessary to retain the part of the insulating layer 80 covering the side wall and the top of the second insulator 40. Therefore, performing an inclined ion implantation process on the insulating layer 80 can complete the material processing of the part to be removed of the insulating layer 80 more easily and with higher quality.
  • the insulating layer 80 includes a first insulating layer 81 and a second insulating layer 82 which are stacked. Accordingly, in step S520, after performing an oblique ion implantation process on the second insulating layer 82 and the first insulating layer 81 based on the initial first contact hole 610, a region A to be removed may be formed, so that the second insulating layer 82 and the first insulating layer 81 located in the region A to be removed are removed in step S530, thereby forming the first contact hole 61.
  • the second insulating layer 82 and the first insulating layer 81 are made of different materials.
  • material modification can be achieved by ion bombarding the target regions of the second insulating layer 82 and the first insulating layer 81.
  • the portion of the second insulating layer 82 located in the non-ion bombarded region can be used as an etching barrier when the portion in the to-be-removed region A is subsequently removed, so as to control the formation boundary of the first contact hole 61 and achieve control of the size of the first contact hole 61.
  • germanium ions and/or argon ions can be used to perform oblique ion implantation on the second insulating layer 82 and the first insulating layer 81 to increase the etching rate of the to-be-removed portions of the second insulating layer 82 and the first insulating layer 81 in the subsequent etching process, thereby ensuring that the to-be-removed portions of the second insulating layer 82 and the first insulating layer 81 are more easily removed.
  • step S530 wet etching may be used to remove the portion of the insulating layer 80 located in the to-be-removed area A.
  • a corresponding etching solution may be selected according to different objects to be processed to ensure that a preset etching effect is achieved.
  • step S600 based on the first contact hole 61, the first planarization layer 20 is self-alignedly etched, and further comprising: based on the first contact hole 61, self-alignedly etching the portion of the insulating layer 80 located at the bottom of the first contact hole 61 and the first planarization layer 20. That is, in the example where the semiconductor structure includes the insulating layer 80, the first contact hole 61 also penetrates the insulating layer 80.
  • an anisotropic dry etching process is used to ensure that the etching is performed in a direction perpendicular to the substrate 11 , so as to ensure that the first contact hole 61 accurately penetrates the insulating layer 80 and the first planarization layer 20 .
  • the step S700 of forming a contact plug in the first contact hole and the second contact hole further includes the following steps:
  • the first layer is a diffusion barrier layer
  • the second layer is a metal layer.
  • the diffusion barrier layer can be used to prevent the electrons in the metal layer from diffusing outward to ensure the stable performance of the semiconductor structure.
  • the diffusion barrier layer can act as an adhesive between the metal layer and the spacer and the planarization layer, so that the metal layer and the spacer and the planarization layer maintain good adhesion.
  • a diffusion barrier layer 71 is formed to cover the sidewalls of the first contact hole 61 and the sidewalls and bottom surface of the second contact hole 62 .
  • a layer of tungsten nitride or titanium nitride may be deposited on the sidewall and bottom surface of the contact hole 60 by a deposition process such as physical vapor deposition to serve as the diffusion barrier layer 71 .
  • step S720 please continue to refer to FIG. 21 , a metal layer 72 is formed to cover the diffusion barrier layer 71 and fill the first contact hole 61 and the second contact hole 62 .
  • the metal layer 72 may be a metal material containing tungsten.
  • the execution of the steps described is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

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Abstract

公开了一种半导体结构及其制备方法。在半导体结构中，基底(10)包括衬底(11)和位于衬底(11)上的相邻的两个栅极结构(13)，衬底(11)具有位于相邻的两个栅极结构(13)之间的掺杂区(12)。第一隔离物(30)和第二隔离物(40)之间的空间与相邻的两个栅极结构(13)之间的空间大致对准。接触孔(60)贯穿第二平坦化层(50)和第一平坦化层(20)；接触孔(60)的一部分位于第一隔离物(30)和第二隔离物(40)之间，接触孔(60)的另一部分位于相邻的两个栅极结构(13)之间，且至少部分暴露出掺杂区(12)。接触插塞(70)设置于接触孔(60)中，且与掺杂区(12)电连接。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开要求于2022年9月30日提交中国专利局、申请号为202211207354.4、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，特别是涉及一种半导体结构及制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。随着移动设备的不断发展，人们对存储器的小体积、集成化提出了巨大的需求。但是，随着半导体制造领域中的特征尺寸一再缩小，动态随机存储器中相邻接触插塞以及相邻导电结构之间的间隔也不断被压缩，使得接触插塞与相邻导电结构之间发生短路的几率也随之增加。
发明内容
本公开实施例提供了一种半导体结构，包括：基底、第一平坦化层、第一隔离物、第二隔离物、第二平坦化层、接触孔以及接触插塞。所述基底包括衬底和位于所述衬底上的相邻的两个栅极结构。其中，所述衬底具有位于所述相邻的两个栅极结构之间的掺杂区。所述第一平坦化层覆盖所述基底。所述第一隔离物和所述第二隔离物位于所述第一平坦化层上。其中，所述第一隔离物和所述第二隔离物之间的空间与所述相邻的两个栅极结构之间的空间大致对准。所述第二平坦化层位于所述第一平坦化层的远离所述基底的一侧，且覆盖所述第一隔离物和所述第二隔离物。所述接触孔贯穿所述第二平坦化层和所述第一平坦化层且，至少部分暴露出所述掺杂区。其中，所述接触孔的一部分位于所述第一隔离物和所述第二隔离物之间，所述接触孔的另一部分位于所述相邻的两个栅极结构之间。所述接触插塞设置于所述接触孔中，且与所述掺杂区电连接。
在一些实施例中，所述第一隔离物和所述第二隔离物由导电材料形成。所述接触插塞与所述第一隔离物电连接，所述接触插塞与所述第二隔离物相互绝缘。
在一些实施例中，所述第一隔离物和所述第二隔离物至少之一形成为导电线。
在一些实施例中，所述第一隔离物和所述第二隔离物由绝缘材料形成。
在一些实施例中，所述接触插塞与所述第一隔离物的靠近所述第二隔离物的侧表面和所述第一隔离物的靠近所述侧表面的部分顶表面直接接触。
在一些实施例中，所述第一隔离物与所述接触插塞接触的所述部分顶表面和所述侧表面形成台阶。
在一些实施例中，所述半导体结构还包括：绝缘层，位于所述第一平坦化层和所述第二平坦化层之间，且覆盖所述第二隔离物以及所述第一隔离物的除所述侧表面和所述部分顶表面之外的表面。所述接触孔还贯穿所述绝缘层。
在一些实施例中，所述接触插塞还覆盖所述绝缘层位于所述第二隔离物顶表面上方的部分表面。
在一些实施例中，所述绝缘层包括层叠设置的第一绝缘层和第二绝缘层。其中，所述第一绝缘层的材料包括氮化物，所述第二绝缘层的材料包括氧化物。
在一些实施例中，所述接触插塞包括扩散阻挡层和金属层。其中，所述扩散阻挡层覆盖所述接触孔的侧壁及底面，所述金属层覆盖所述扩散阻挡层并填充所述接触孔。
本公开实施例还提供了一种半导体结构的制备方法，包括如下步骤。
提供基底。其中，所述基底包括衬底和位于所述衬底上的相邻的两个栅极结构，所述衬底具有位于所述相邻的两个栅极结构之间的掺杂区。
于所述基底上形成第一平坦化层。
于所述第一平坦化层远离所述基底的表面形成第一隔离物和第二隔离物。其中，所述第一隔离物和所述第二隔离物之间的空间与所述相邻的两个栅极结构之间的空间大致对准。
于所述第一平坦化层远离所述基底的表面形成第二平坦化层。其中，所述第二平坦化层覆盖所述第一隔离物和所述第二隔离物。
刻蚀所述第二平坦化层，以形成贯穿所述第二平坦化层的第一接触孔。所述第一接触孔位于所述第一隔离物和所述第二隔离物之间。
基于所述第一接触孔，自对准刻蚀所述第一平坦化层，以在所述相邻的两个栅极结构之间形成贯穿所述第一平坦化层的第二接触孔，且至少部分暴露出所述掺杂区。
于所述第一接触孔和所述第二接触孔中形成接触插塞。其中，所述接触插塞与所述掺杂区电连接。
在一些实施例中，所述刻蚀所述第二平坦化层，以形成贯穿所述第二平坦化层的第一接触孔，包括：刻蚀所述第二平坦化层，暴露出所述第一隔离物的靠近所述第二隔离物的侧表面和所述第一隔离物的靠近所述侧表面的部分顶表面，以形成所述第一接触孔。
在一些实施例中，所述第一隔离物和所述第二隔离物采用绝缘材料形成。
在一些实施例中，所述第一隔离物和所述第二隔离物由导电材料形成。所述制备方法还包括：在形成所述第二平坦化层之前，于所述第一平坦化层远离所述基底的表面形成绝缘层，所述绝缘层覆盖所述第一隔离物和所述第二隔离物。其中，所述第二平坦化层形成于所述绝缘层远离所述基底的表面；所述第一接触孔和所述第二接触孔还贯穿所述绝缘层相连通。
在一些实施例中，所述绝缘层包括层叠形成的第一绝缘层和所述第二绝缘层。其中，所述第一绝缘层的材料包括氮化物，所述第二绝缘层的材料包括氧化物。
在一些实施例中，所述刻蚀所述第二平坦化层，以形成贯穿所述第二平坦化层的第一接触孔，还包括如下步骤。
刻蚀所述第二平坦化层，于所述第一隔离物和所述第二隔离物之间形成初始第一接触孔。
基于所述初始第一接触孔，对所述绝缘层执行倾斜离子注入工艺，形成待去除区域。
去除所述绝缘层位于所述待去除区域的部分，暴露出所述第一隔离物的靠近所述第二隔离物的侧表面和所述第一隔离物的靠近所述侧表面的部分顶表面，形成所述第一接触孔。
在一些实施例中，所述初始第一接触孔还暴露出所述绝缘层位于所述第一隔离物顶表面和所述第二隔离物顶表面二者上方的部分表面。
在一些实施例中，所述对所述绝缘层执行倾斜离子注入工艺，形成待去除区域，包括：
采用离子注入工艺，沿与所述初始第一接触孔的轴线具有夹角的方向对所述绝缘层的待去除部分进行处理，以形成所述待去除区域。所述待去除部分覆盖所述第一隔离物的靠近所述第二隔离物的顶部拐角。
在一些实施例中，所述基于所述第一接触孔，自对准刻蚀所述第一平坦化层，还包括：基于所述第一接触孔，自对准刻蚀所述绝缘层位于所述第一接触孔底部的部分以及所述第一平坦化层。
在一些实施例中，所述于所述第一接触孔和所述第二接触孔中形成接触插塞，包括如下步骤。
形成覆盖所述第一接触孔的侧壁及所述第二接触孔的侧壁和底面的扩散阻挡层。
形成覆盖所述扩散阻挡层并填充所述第一接触孔和所述第二接触孔的金属层。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技 术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。
图1为一实施例中提供的一种半导体结构的结构示意图；
图2为一实施例中提供的另一种半导体结构的结构示意图；
图3为一实施例中提供的又一种半导体结构的结构示意图；
图4为一实施例中提供的又一种半导体结构的结构示意图；
图5为一实施例中提供的一种半导体制备方法的流程示意图；
图6为一实施例中提供的一种半导体基底的剖面示意图；
图7为一实施例中提供的形成第一平坦化层后所得结构的剖面示意图；
图8为一实施例中提供的形成第一隔离物和第二隔离物后所得结构的剖面示意图；
图9为一实施例中提供的形成第二平坦化层后所得结构的剖面示意图；
图10为一实施例中提供的形成第一接触孔后所得结构的剖面示意图；
图11为一实施例中提供的形成第二接触孔后所得结构的剖面示意图；
图12为一实施例中提供的形成接触插塞后所得结构的剖面示意图；
图13为一实施例中提供的另一种半导体制备方法的流程示意图；
图14为图13所示制备方法中形成第一接触孔和第二接触孔后所得结构的剖面示意图；
图15为图13所示制备方法中形成绝缘层后所得结构的剖面示意图；
图16为一实施例中提供的对绝缘层进行倾斜离子注入的流程示意图；
图17为一实施例中提供的对绝缘层进行倾斜离子注入以形成待去除区域后所得结构的剖面示意图；
图18为一实施例中提供的对绝缘层去除后形成的第一接触孔的剖面示意图；
图19为一实施例中提供的对第一接触孔底部及第一平坦化层刻蚀形成的第二接触孔的剖面示意图；
图20为一实施例中提供的形成扩散阻挡层和金属层的制备方法的流程示意图；
图21为图20所示制备方法中形成的扩散阻挡层和金属层后所得结构的剖面示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开实施例一部分实施例，而不是全部的实施例。基于本公开实施例中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开实施例保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
需要说明的是，当一个元件被认为是“连接”另一个元件时，它可以是直接连接到另一个元件，或者通过居中元件连接另一个元件。此外，以下实施例中的“连接”，如果被连接的对象之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中使用的术语“和/或”包括相关所列项目的任何及所有组合。
相关技术中，形成金属互连结构一般使用光刻掩膜板来执行刻蚀前地对准工序。例如，需要先在衬底/介质层等之上进行对准定位并形成光刻图案，再利用刻蚀工艺依照上述形成的光刻图案向掺杂区方向进行图形化刻蚀形成连通至掺杂区的接触孔，进而在接触孔中沉积金属(如钨)形成接触插塞，最后在隔离层/介质层之上沉积、刻蚀金属形成导电层/线。 如此，接触插塞远离衬底的一端可以与导电层/线电连接，接触插塞靠近衬底的一端可以与掺杂区电连接，从而构成完整的金属互连结构。
随着半导体行业对半导体特征尺寸的一再压缩(如7纳米甚至3纳米)以及追求元器件堆叠层数(如96层、112层等)等纵向空间的极致利用，相邻接触插塞以及相邻导电结构之间的间隔也不断被压缩，使得接触插塞与相邻导电结构之间发生短路的几率也随之增加。
因此，为了减少此类短路的失效风险发生，需要对接触插塞的制造过程特别是定位对准、绝缘防护等的关键步骤进行结构以及工艺上的改进。
基于此，本公开实施例提供了一种半导体结构，以改善接触插塞的成型精度，并降低接触插塞的工艺难度，从而有利于提高半导体结构的生产良率，并确保半导体结构的电学可靠性。
请参阅图1，在一些实施例中，半导体结构包括：基底10、第一平坦化层20、第一隔离物30、第二隔离物40、第二平坦化层50、接触孔60以及接触插塞70。基底10包括衬底11，以及位于衬底11上的相邻的两个栅极结构13以及位于两个栅极结构13之间的掺杂区12。基底10上覆盖有第一平坦化层20，第一隔离物30和第二隔离物40位于第一平坦化层20上，并且第一隔离物30和第二隔离物40之间的空间与相邻的两个栅极结构13之间的空间大致对准。第二平坦化层50位于第一平坦化层20的远离基底10的一侧，并且覆盖第一隔离物30和第二隔离物40。接触孔60贯穿第二平坦化层50和第一平坦化层20且至少部分暴露所述掺杂区12，其中，接触孔60的一部分位于第一隔离物30和第二隔离物40之间，接触孔60的另一部分位于相邻的两个栅极结构13之间。接触插塞70位于接触孔60之中，且与掺杂区12电连接。
在一些实施例中，衬底11可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。例如，衬底11可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底11可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。
在一个示例中，衬底11为硅衬底。
在一些实施例中，栅极结构13的数量为多个，可以呈阵列状分布于衬底11上或者按照半导体结构的需求进行排列。本公开以下一些实施例以相邻设置的两个栅极结构13为例进行了说明，但可以理解，本公开实施例提供的半导体结构可以应用于多个栅极结构13的任意相邻两个栅极结构13之间。
此外，可以理解，栅极结构13的旁侧通常设有掺杂区12，本公开实施例以掺杂区12位于相邻栅极结构13之间为例对用于连接掺杂区12的接触插塞70进行了说明。
在一个示例中，掺杂区12为N型掺杂区。在另一个示例中，掺杂区12为P型掺杂区。
在一些实施例中，第一平坦化层20覆盖在基底10之上。也即，第一平坦化层20可以形成在衬底11之上且覆盖两个相邻的栅极结构13。
在一个示例中，第一平坦化层20顶表面距离衬底11的距离大于两个栅极结构13顶表面距离衬底11的距离。例如，第一平坦化层20顶表面距离衬底11的距离可以是在两个栅极结构13顶表面距离衬底11的距离的1.5倍至5倍之间，如1.5倍、2倍、3倍、4倍或5倍。
在一些实施例中，第一平坦化层20的材料可以为具有良好绝缘性能的半导体材料、绝缘材料等的一种或者多种的组合。
在一个示例中，第一平坦化层20为氧化硅层。在另一个示例中，第一平坦化层20为氮化硅层。在再一个示例中，第一平坦化层20为氮氧化硅层。本公开的实施例对此不作限制。
上述一些实施例中，第一隔离物30和第二隔离物40位于第一平坦化层20上且第一 隔离物30和第二隔离物40之间的空间与相邻的两个栅极结构13之间的空间大致对准。
在一个示例中，第一隔离物30和第二隔离物40之间的距离小于相邻的两个栅极结构13之间的距离。
在一个示例中，第一隔离物30和第二隔离物40之间的空间在衬底11上的正投影位于相邻两个栅极结构13之间的空间在衬底11上的正投影范围内。
在一个示例中，第一隔离物30和第二隔离物40之间的空间垂直于衬底11的中轴线与相邻两个栅极结构13之间的空间垂直于衬底11的中轴线重合或大致重合，且第一隔离物30和第二隔离物40之间的空间在衬底11上的正投影轮廓与相邻两个栅极结构13之间的空间在衬底11上的正投影轮廓之间可以具有偏差允许范围内的间隔，该偏差包括设计偏差和/或工艺偏差。
在一些实施例中，第二平坦化层50的材料可以和第一平坦化层20保持相同，也可以不同。第二平坦化层50的顶表面距离第一平坦化层20的距离应当大于第一隔离物30和第二隔离物40的高度，以有效覆盖。
在一个示例中，第二平坦化层50的材料可以为氧化硅、氮化硅或者氮氧化硅等。
在一个示例中，第二平坦化层50的顶表面距离第一平坦化层20的距离为第一隔离物30和第二隔离物40的高度的1.5倍至5倍，如1.5倍、2倍、3倍、4倍或5倍。
上述一些实施例中，接触孔60贯穿第二平坦化层50和第一平坦化层20，并且接触孔60可以分为两部分，接触孔60的一部分位于第一隔离物30和第二隔离物40之间，接触孔60的另一部分位于相邻的两个栅极结构13之间。
在一个示例中，接触孔60位于第一隔离物30和第二隔离物40之间的部分，可以分别与第一隔离物30和第二隔离物40二者相对的侧表面接触。
在一个示例中，接触孔60位于相邻的两个栅极结构13之间的部分，可以分别与两个相邻的栅极结构13相对的侧表面接触。
上述一些实施例中，接触孔60内设置有接触插塞70，且接触插塞70还与掺杂区12形成电连接。
在一个示例中，接触插塞70远离衬底11的一端和第二平坦化层50的顶表面平齐，接触插塞70靠近衬底11的一端可以穿过衬底11上表面并深入到掺杂区12内，与掺杂区12形成电连接。
可选地，接触插塞70的材料包括金属或金属化合物。金属包括钨或铜等。
可选地，接触插塞70可以为单层结构或叠层结构。
本公开实施例中，在第一平坦化层20之上设置有第一隔离物30和第二隔离物40，并且设置第一隔离物30和第二隔离物40之间的空间与所述相邻的两个栅极结构13之间的空间大致对准，可以利用第一隔离物30和第二隔离物40之间的空间进行接触孔60的自对准刻蚀，并利用第一隔离物30及第二隔离物40的上方空间为接触孔60提供较大的工艺窗口，从而使得接触孔60的一部分位于第一隔离物30和第二隔离物40之间，接触孔60的另一部分位于相邻的两个栅极结构13之间。如此，不仅可以有效降低接触孔60对准的工艺难度，还能够确保填充接触孔60中形成的接触插塞70能够准确地连通至两个栅极结构13之间的掺杂区12而不与相邻的栅极结构13和/或相邻的接触插塞70(图中未示出)发生短路风险。从而有利于提高半导体结构的生产良率，并确保半导体结构的电学可靠性。
可以理解，本公开实施例对第一隔离物30和第二隔离物40的材料不作限定，例如绝缘材料或导电材料均可。
在一些实施例中，请继续参阅图1，第一隔离物30和第二隔离物40的材料为绝缘材料，例如为氧化物、氮化物或氮氧化物等。这样接触插塞70可以与第一隔离物30和第二隔离物40均直接接触，从而利用第一隔离物30和第二隔离物40的绝缘性能，有效增强接触插塞70的绝缘防护效果。
在另一些实施例中，请参阅图2，第一隔离物30和第二隔离物40的材料可以是导电 材料。基于此，接触插塞70与第一隔离物30之间还可以形成电连接，且接触插塞70与第二隔离物40之间可以相互绝缘。
在一些实施例中，第一个隔离物30和第二隔离物40的材料可以是金属，例如金属铝、金属铜、金属钨或铜铝合金等。
在一个示例中，如图2中所示，半导体结构还包括绝缘层80。绝缘层80位于第一平坦化层20和第二平坦化层50之间，且覆盖第二隔离物40以及第一隔离物30与接触插塞70接触的侧表面和部分顶表面之外的表面。接触孔60还贯穿绝缘层80。
本公开实施例中，第一隔离物30和第二隔离物40由导电材料构成，并设置接触插塞70与第一隔离物30电连接，接触插塞70与第二隔离物40相互绝缘。如此，接触插塞70两端可以分别将第一隔离物30和掺杂区12对应连接起来，构成完整的金属互连结构。并且，接触插塞70还可以与第二隔离物40相互绝缘，以增多第二隔离物40的电学应用。绝缘层80覆盖第二隔离物40，并位于接触插塞70和第二隔离物40之间，还可以避免了接触插塞70和第二隔离物40发生短路等失效风险，有利于提高半导体结构的电学稳定性。
请继续参阅图2，在一些实施例中，第一隔离物30和第二隔离物40至少之一为导电线。
在一个示例中，第一隔离物30为导电线，如位线导电线。如此，作为导电线结构的第一隔离物30同时还兼具为形成接触插塞70的接触孔60提供对准的功能。
在一个示例中，第二隔离物40为导电线，如源极导电线。如此，作为导电线结构的第二隔离物40同时还兼具为形成接触插塞70的接触孔60提供对准的功能。
在一个示例中，半导体结构还包括与第一隔离物30、第二隔离物40同步骤形成的多个导电线。即：采用同一材料层及同一图案化工艺，同步形成第一隔离物30、第二隔离物40以及多个导电线；其中，第一隔离物30和第二隔离物40的至少之一可以具有与导电线相同的功能。
本公开实施例中，将第一隔离物30和第二隔离物40中的至少一者作为导电线，可以使得第一隔离物30和第二隔离物40具有更多功能，以在不增加元器件数量的前提下，实现接触孔60的自对准刻蚀以及半导体结构内导电线的布线设计，从而有利于简化制造工艺、降低成本。
在一些实施例中，请继续参阅图2，接触插塞70与第一隔离物30的靠近第二隔离物40的侧表面和第一隔离物30的靠近前述侧表面的部分顶表面可以直接接触。
在一些实施例中，第一隔离物30与接触插塞70接触的部分顶表面和侧表面形成台阶。
基于此，在一些实施例中，接触插塞70的上部分在衬底11上的正投影面积大于其中下部分在衬底11上的正投影面积。接触插塞70的上部分是指其高于第一隔离物30或第二隔离物40顶表面的部分；接触插塞70的中下部分是指其位于第一隔离物30和第二隔离物40之间直至相邻两个栅极结构13之间的部分。
在一些实施例中，接触插塞70和第一隔离物30的靠近第二隔离物40的侧表面全部接触，接触插塞70和第一隔离物30顶表面接触的接触面积占第一隔离物30全部顶表面面积的比值小于90％，例如可以为10％、20％、30％、40％、50％、60％、70％、80％或90％。
本公开实施例中，接触插塞70和第一隔离物30靠近第二隔离物40的侧表面以及与前述侧表面相连的部分顶表面直接接触。相较于相关技术中，仅有接触插塞70的顶表面与导电线的底部直接接触，本公开实施例接触插塞70和第一隔离物30可以具有更大的接触面积。如此，接触插塞70和第一隔离物30之间可以形成更为可靠的电接触，以利于提升半导体结构的可靠性。
上述一些实施例中，半导体结构还包括绝缘层80。请继续参阅图2，在一些实施例中，绝缘层80的厚度小于第一隔离物30和第二隔离物40之间距离的1/3。例如，绝缘层80的厚度等于第一隔离物30和第二隔离物40之间距离的1/3、1/4或1/5等。
在一些实施例中，绝缘层80为氧化物层或者氮化物层或者氮氧化物层中的一种。
在一些实施例中，绝缘层80和第一平坦化层20之间还可以设置有一层垫氧化层，以改善绝缘层80与第一平坦化层20接触界面的粘附性。
本公开实施例中，在第一平坦化层20和第二平坦化层50之间设置绝缘层80，并使绝缘层80覆盖第一隔离物30和第二隔离物40，可以利用绝缘层80为半导体有源器件之间提供更为可靠的绝缘防护，从而有效杜绝因制造过程中离子残留、元器件间距过小等原因导致的短路等风险。
此外，可选地，绝缘层80可以为单层结构，也可以为叠层结构。
请参阅图3，在一些实施例中，绝缘层80包括层叠设置的第一绝缘层81和第二绝缘层82。其中，第一绝缘层81的材料包括氧化物，第二绝缘层82的材料包括氮化物。但并不仅限于此。例如，绝缘层80是由多种材料组成的多层结构，从而可以通过借助不同材料的不同特性来构建所需要的绝缘层80。如此，可以灵活调整以适应不同的待隔离元器件，从而取得最佳的绝缘效果。
请继续参阅图3，可选地，第一绝缘层81位于第二绝缘层82靠近基底10的一侧。
请继续参阅图3，在一些实施例中，接触插塞70还覆盖绝缘层80位于第二隔离物40顶表面上方的部分表面。
在一些实施例中，接触插塞70的上部分在衬底11上的正投影面积大于其中下部分在衬底11上的正投影面积。接触插塞70和第二隔离物40的顶表面的接触面积占第二隔离物40全部顶表面面积的比值则小于90％，例如可以为10％、20％、30％、40％、50％、60％、70％、80％或90％。
请参阅图4，在一些实施例中，接触插塞70包括扩散阻挡层71和金属层72；其中，扩散阻挡层71覆盖接触孔60的侧壁及底面，金属层72覆盖所述扩散阻挡层71并填充所述接触孔60。
在一个示例中，扩散阻挡层71可以为氮化钛等材料，以获得具有高导电率、良好的防扩散性以及良好稳定性的性能。
在一个示例中，扩散阻挡层71为薄膜状覆盖在接触孔60的侧壁及底面。
在一个示例中，金属层72可以为含钨的金属材料。
本公开实施例中，接触插塞70为多层结构，包括金属层72以及位于金属层72和接触孔60之间的散阻挡层71。如此，利用扩散阻挡层71对金属原子的良好阻挡作用，可以防止金属中的原子扩散至半导体材料中，从而保持半导体结构的性能稳定。并且，扩散阻挡层71还具有良好的附着性，可以充当金属材料和其他材料(例如半导体材料、绝缘材料等)之间的粘结剂，以确保接触插塞70和掺杂区12之间的接触更加稳定。
需要补充的是，上述一些实施例中设置于衬底11上的栅极结构13可以具有多种结构，以匹配半导体结构的需求。本公开实施例示例性地提供了一种可能的实施方式。请继续参阅图4，栅极结构13包括：设置于衬底11上的栅极及包裹栅极顶表面及侧壁的隔离挡墙；其中，栅极包括：层叠设置于衬底11上的介电层131、导电层132和栅极掩膜层133；隔离挡墙包括：覆盖栅极掩膜层133顶表面及侧壁、导电层132侧壁和介电层131侧壁的第一挡墙134，以及覆盖第一隔离层134至少部分侧壁的第二挡墙135。
在一个示例中，介电层131可以是氧化硅层、高K材料层或其组合。
在一个示例中，导电层132可以是掺杂有离子的多晶硅层。
在一个示例中，栅极掩膜层133可以是氧化硅层、氮化硅层、氧氮化硅层或其任意组合。
在一个示例中，第一挡墙134可以是氧化硅层。
在一个示例中，第二挡墙135可以是氮化硅层、氮氧化硅层或其任意组合。
请参阅图5，本公开一些实施例还提供了一种半导体结构的制备方法，用于制备上述一些实施例中的半导体结构。前述半导体结构所具有的技术优势，该制备方法也均具备。该制备方法包括如下步骤：
S100，提供基底，其中，基底包括衬底和位于衬底上的相邻的两个栅极结构，衬底具有位于相邻的两个栅极结构之间的掺杂区。
S200，于基底上形成第一平坦化层。
S300，于第一平坦化层远离基底的表面形成第一隔离物和第二隔离物；其中，第一隔离物和第二隔离物之间的空间与相邻的两个栅极结构之间的空间大致对准。
S400，于第一平坦化层远离基底的表面形成第二平坦化层；其中，第二平坦化层覆盖第一隔离物和第二隔离物。
S500，刻蚀第二平坦化层，以形成贯穿第二平坦化层的第一接触孔，第一接触孔位于第一隔离物和第二隔离物之间。
S600，基于第一接触孔，自对准刻蚀第一平坦化层，以在相邻的两个栅极结构之间形成贯穿第一平坦化层的第二接触孔，且至少部分暴露出掺杂区。
S700，于第一接触孔和第二接触孔中形成接触插塞；其中，接触插塞与掺杂区电连接。
本公开实施例中，通过在第一平坦化层之上形成第一隔离物和第二隔离物，并且设置第一隔离物和第二隔离物之间的空间与相邻的两个栅极结构之间的空间大致对准，可以利用第一隔离物和第二隔离物之间的空间进行接触孔的自对准刻蚀，并利用第一隔离物及第二隔离物的上方空间为接触孔提供较大的工艺窗口，从而使得接触孔的一部分位于第一隔离物和第二隔离物之间，接触孔的另一部分位于相邻的两个栅极结构之间。如此，不仅可以有效降低接触孔对准的工艺难度，还能够确保填充接触孔形成的接触插塞能够准确地连通至两个栅极结构之间的掺杂区而不与相邻的栅极结构发生短路风险。从而有利于提高半导体结构的生产良率，并确保半导体结构的电学可靠性。
在步骤S100中，请参阅图6，提供一基底10，其中，基底10包括衬底11和位于衬底11上的相邻的两个栅极结构13，衬底11具有位于相邻的两个栅极结构13之间的掺杂区12。
在一个示例中，衬底11为硅衬底。可选的，在硅衬底之上形成栅极结构13之后，基于栅极结构13的图案，可以向硅衬底位于相邻栅极结构13之间的区域扩散或者注入待掺杂离子，以形成位于相邻的两个栅极结构13之间的掺杂区12。
可选地，待掺杂离子可以是P型离子，也可以是N型离子。
在步骤S200中，请参阅图7，于基底10上形成第一平坦化层20。
此处，第一平坦化层20覆盖栅极结构13，第一平坦化层20的形成厚度大于栅极结构13的高度。
在一个示例中，可以通过沉积等工艺(如化学气相沉积、物理气相沉积、蒸发等)在基底10之上先形成一介质层，再通过化学机械抛光等工艺将介质层远离衬底11一侧表面平坦化，形成第一平坦化层20。或者，也可以采用旋涂工艺直接形成表面平坦的第一平坦化层20。
可选地，第一平坦化层20可以为氧化物层，如氧化硅层。
在步骤S300中，请参阅图8，于第一平坦化层20远离基底10的表面形成第一隔离物30和第二隔离物40，其中，第一隔离物30和第二隔离物40之间的空间与相邻的两个栅极结构13之间的空间大致对准。
在一个示例中，可以形成隔离材料层之后，使用光刻工艺在隔离材料层远离所基底10的表面进行图形定位，例如在隔离材料层远离基底10的表面形成具有图案的光刻胶层，然后基于光刻胶中的图案刻蚀隔离材料层，从而形成第一隔离物30和第二隔离物40。
可选地，第一隔离物30和第二隔离物40的材料可以是导电材料，也可以是绝缘材料。
在一些示例中，使用导电材料形成第一隔离物30和第二隔离物40。导电材料例如为金属，例如为金属铝、金属铜或铜铝合金等。
在一些示例中，第一隔离物30和第二隔离物40可以通过沉积工艺(如物理气相沉积、化学气相沉积等)形成。
本公开实施例，可以通过导电材料来形成第一隔离物30和第二隔离物40，以使得第一隔离物30和第二隔离物40中的至少之一还可以复用为半导体结构中的导电线。
在另一些示例中，使用绝缘材料来形成第一隔离物30和第二隔离物40。
在步骤S400中，请参阅图9，于第一平坦化层20远离基底10的表面形成第二平坦化层50；其中，第二平坦化层50覆盖第一隔离物30和第二隔离物40。
在一个示例中，可以通过如化学气相沉积等沉积工艺在第一平坦化层20之上形成一介质层，再通过化学机械抛光等工艺将介质层远离第一平坦化层20一侧表面平坦化，形成第二平坦化层50。
可选地，第二平坦化层50可以为氮化物层，例如氮化硅层。
在步骤S500中，请参阅图10，刻蚀第二平坦化层50，以形成贯穿第二平坦化层50的第一接触孔61，第一接触孔61位于第一隔离物30和第二隔离物40之间。
在一个示例中，利用掩膜板在第二平坦化层之上进行光刻，光刻位置大致位于第一隔离物30和第二隔离物40的上表面之间，此时即使掩膜板未精确对准，但借助于第一隔离物30和第二隔离物30的自对准，也可满足工艺窗口的要求。在进行刻蚀时，利用第一隔离物30和第二隔离物40的上表面及二者相对的侧表面的作为刻蚀的阻挡层，如此，可以保证形成的第一接触孔61位于第一隔离物30和第二隔离物40之间。如此，第一接触孔61的中轴线大致对准了衬底11上相邻两个栅极结构13之间的空间以及该空间下方的掺杂区12。
在一些实施例中，请继续参阅图10，步骤S500中刻蚀第二平坦化层50，以形成贯穿第二平坦化层50的第一接触孔61，还包括：刻蚀第二平坦化层50，暴露出第一隔离物30的靠近第二隔离物40的侧表面和第一隔离物30的靠近前述侧表面的部分顶表面，以形成第一接触孔61。
本公开实施例中，第一接触孔61还可以覆盖到第一隔离物30的部分顶表面。如此，在进行第一接触孔61的光刻工序时，相应的光刻图形窗口也会覆盖到第一隔离物30的部分顶表面上方的第二平坦化层，从而利于降低光刻对准精度，也即，使用精度略低的光刻机设备也可满足工艺要求，进而有助于降低制造成本。并且，形成于该结构第一接触孔61内的接触插塞70还可以与第一隔离物30的一个侧面和部分顶表面形成接触，有利于增加接触插塞70和第一隔离物30的接触面积，以在第一隔离物30为导电线时提高接触插塞70和第一隔离物30的连接可靠性。
在步骤S600中，请参阅图11，基于第一接触孔61，自对准刻蚀第一平坦化层20，以在相邻的两个栅极结构13之间形成贯穿第一平坦化层20的第二接触孔62，且至少部分暴露出掺杂区12。
可以理解，在上述S500步骤中形成的第一接触孔61的中轴线大致对准了衬底11上的掺杂区12，基于第一接触孔61继续向衬底11方向进行刻蚀，贯穿第一平坦化层20形成的第二接触孔62也将位于相邻两个栅极结构13之间的区域。
在一个示例中，采取干法等离子刻蚀等方法，利用其各向异性刻蚀的特性，保证刻蚀尽可能地发生在朝向衬底11的方向上，最大程度保证刻蚀的精度。
在步骤S700中，请参阅图12，于第一接触孔61和第二接触孔62中形成接触插塞70；其中，接触插塞70与掺杂区12电连接。
在一个示例中，可以向第一接触孔61和第二接触孔62中填充金属材料，例如金属钨，以形成接触插塞70。
可以理解，为加强接触插塞70和掺杂区12之间的有效电连接，前述S600步骤中，形成的第二接触孔62可以穿透衬底11的表面，以深入至掺杂区12内。
在一些实施例中，请参阅图13，半导体结构的制备方法还包括如下步骤：
S350，于第一平坦化层远离基底的表面形成绝缘层，绝缘层覆盖第一隔离物和第二隔离物。
S400'，于绝缘层远离基底的表面形成第二平坦化层。
在步骤S350中，请参阅图14，于第一平坦化层20远离基底10的表面形成绝缘层80，绝缘层80覆盖第一隔离物30和第二隔离物40。
在一个示例中，绝缘层80可以是通过沉积工艺如化学气相沉积等形成的氧化物层或者氮化物层或者氮氧化物层等多种的一种或者几种组合。
可以理解，本公开实施例提供的半导体结构的制备方法，需要借助第一隔离物30和第二隔离物40之间的空间刻蚀第二平坦化层50以形成第一接触孔61，以及基于第一接触孔61刻蚀第一平坦化层20以形成第二接触孔62，进而于第一接触孔61和第二接触孔62内形成接触插塞70。当第一隔离物30和第二隔离物40均为导电材料时，在第一平坦化层20和第二平坦化层50之间形成绝缘层80，利于增强对第一隔离物30和第二隔离物40的电性绝缘性能。
请参阅图15，在一些实施例中，步骤S350中于第一平坦化层20远离基底10的表面形成绝缘层80，还包括：于第一平坦化层20远离基底10的表面层叠形成第一绝缘层81和第二绝缘层82。
在一个示例中，可以使用化学气相沉积、原子层沉积、高密度等离子沉积等工艺手段中的一种或者多种，依次形成第一绝缘层81和第二绝缘层82。
在一个示例中，第一绝缘层81的材料包括氧化物，例如氧化硅。第二绝缘层82的材料包括氮化物，例如氮化硅。
请继续参阅图15，在步骤S400′中，于绝缘层80远离基底10的表面形成第二平坦化层50。
此处，匹配绝缘层80的结构，第二平坦化层50覆盖第二绝缘层82。
在一个示例中，可以在绝缘层80远离基底10的表面沉积一层氧化硅或者氮氧化硅等介质层，然后对介质层进行化学机械抛光处理后得到第二平坦化层50。
在一些实施例中，请参阅图16，在步骤S500中，刻蚀第二平坦化层，以形成贯穿第二平坦化层的第一接触孔，还包括如下步骤：
S510，刻蚀第二平坦化层，于第一隔离物和第二隔离物之间形成初始第一接触孔。
S520，基于初始第一接触孔，对绝缘层执行倾斜离子注入工艺，形成待去除区域；
S530，去除绝缘层位于待去除区域的部分，暴露出第一隔离物的靠近第二隔离物的侧表面和第一隔离物的靠近侧表面的部分顶表面，形成第一接触孔。
本公开实施例中，在形成初始第一接触孔之后，对暴露出的第一隔离物的部分顶表面和侧表面上的绝缘层执行倾斜离子注入工艺，可以形成待去除区域，以便于在之后的工序中将绝缘层80待去除的部分容易地去除，并确保暴露出满足要求的第一隔离物表面。
在步骤S510中，请参阅图17，刻蚀第二平坦化层50，于第一隔离物30和第二隔离物40之间形成初始第一接触孔610。
在一些实施例中，请参阅图18，初始第一接触孔610除了位于第一隔离物30和第二隔离物40之间的部分外，初始第一接触孔610还包括用于暴露出绝缘层80位于第一隔离物30顶表面和第二隔离物40顶表面二者部分表面的部分。
在一些实施例中，请结合图17和图18理解，步骤S520中对绝缘层80执行倾斜离子注入工艺，形成待去除区域A，还包括：采用离子注入工艺，沿与初始第一接触孔610的轴线具有夹角X的方向对绝缘层80的待去除部分进行处理，以形成待去除区域A；绝缘层80的待去除部分覆盖第一隔离物30的靠近第二隔离物40的顶部拐角。
此处，可以理解，需要进行离子注入处理的区域，主要位于绝缘层80覆盖第一隔离物30的靠近第二隔离物40的侧表面和第一隔离物30的靠近所述侧表面的部分顶表面的区域，并且，需要保留绝缘层80覆盖在第二隔离物40的侧壁和顶部的部分，因此对绝缘层80执行倾斜离子注入工艺，可以较容易且较高质量地完成绝缘层80待去除部分的材料处理。
可选地，绝缘层80包括层叠设置的第一绝缘层81和第二绝缘层82。相应地，在步骤S520中，基于初始第一接触孔610，对第二绝缘层82和第一绝缘层81执行倾斜离子注入工艺之后，可以形成待去除区域A，以在步骤S530中去除第二绝缘层82和第一绝缘层81位于待去除区域A内的部分，从而形成第一接触孔61。
可以理解，在一些实施例中，第二绝缘层82和第一绝缘层81的材料不同，在对第二绝缘层82和第一绝缘层81执行倾斜离子注入工艺时，可以通过对第二绝缘层82和第一绝缘层81目标区域的离子轰击实现材料改性。如此，第二绝缘层82位于非离子轰击区域的部分可以作为后续去除待去除区域A内部分时的刻蚀阻挡层，以控制第一接触孔61的形成边界，实现对第一接触孔61尺寸的控制。
示例地，可以使用锗离子和/或氩离子，对第二绝缘层82和第一绝缘层81进行倾斜离子注入，以增大第二绝缘层82和第一绝缘层81二者待去除部分在后续刻蚀过程中的刻蚀速率，从而可以确保第二绝缘层82和第一绝缘层81二者的待去除部分较为容易的被去除。
此外，在步骤S530中，去除绝缘层80位于待去除区域A内的部分可以采用湿法刻蚀。如此，按照待处理对象的不同可以选用对应的刻蚀溶液，以保证达到预设的刻蚀效果。
在一些实施例中，请参阅图19，在步骤S600中，基于第一接触孔61，自对准刻蚀第一平坦化层20，还包括：基于第一接触孔61，自对准刻蚀绝缘层80位于第一接触孔61底部的部分以及第一平坦化层20。也即，在半导体结构包括绝缘层80的示例中，第一接触孔61还贯穿绝缘层80。
示例地，采用各向异性的干法刻蚀工艺，保证刻蚀在垂直于衬底11的方向上进行，以确保第一接触孔61准确贯穿绝缘层80及第一平坦化层20。
在一些实施例中，请参阅图20，步骤S700中于第一接触孔和第二接触孔中形成接触插塞，还包括如下步骤：
S710，形成覆盖第一接触孔的侧壁及第二接触孔的侧壁和底面的扩散阻挡层。
S720，形成覆盖扩散阻挡层并填充第一接触孔和第二接触孔的金属层。
本实施例中，使用两层不同的材料来构成接触插塞结构，第一层为扩散阻挡层，第二层为金属层。如此，可以通过扩散阻挡层来阻挡金属层中的电子向外扩散，以保证半导体结构的性能稳定。并且扩散阻挡层可以充当金属层和隔离物及平坦化层之间的粘合剂，以使得金属层和隔离物及平坦化层之间维持良好的附着性能。
在步骤S710中，请参阅图21，形成覆盖第一接触孔61的侧壁及第二接触孔62的侧壁和底面的扩散阻挡层71。
示例地，可以通过沉积工艺如物理气相沉积等在接触孔60的侧壁和底面沉积一层氮化钨或者氮化钛以作为扩散阻挡层71。
在步骤S720中，请继续参阅图21，形成覆盖扩散阻挡层71并填充第一接触孔61和第二接触孔62的金属层72。
示例地，金属层72可以为含钨的金属材料。
应该理解的是，除非本文中有明确的说明，所述的步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，所述的步骤的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开实施例的几种实施方式，其描述较为具体和详细，但 并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开实施例构思的前提下，还可以做出若干变形和改进，这些都属于本公开实施例的保护范围。因此，本公开实施例专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体结构，包括：
    基底(10)，包括衬底(11)和位于所述衬底(11)上的相邻的两个栅极结构(13)，其中，所述衬底(11)具有位于所述相邻的两个栅极结构(13)之间的掺杂区(12)；
    第一平坦化层(20)，覆盖所述基底(10)；
    第一隔离物(30)和第二隔离物(40)，位于所述第一平坦化层(20)上；其中，所述第一隔离物(30)和所述第二隔离物(40)之间的空间与所述相邻的两个栅极结构(13)之间的空间大致对准；
    第二平坦化层(50)，位于所述第一平坦化层(20)的远离所述基底(10)的一侧，且覆盖所述第一隔离物(30)和所述第二隔离物(40)；
    接触孔(60)，贯穿所述第二平坦化层(50)和所述第一平坦化层(20)，且至少部分暴露出所述掺杂区(12)；其中，所述接触孔(60)的一部分位于所述第一隔离物(30)和所述第二隔离物(40)之间，所述接触孔(60)的另一部分位于所述相邻的两个栅极结构(13)之间；
    接触插塞(70)，设置于所述接触孔(60)中，且与所述掺杂区(12)电连接。
  2. 根据权利要求1所述的半导体结构，其中，所述第一隔离物(30)和所述第二隔离物(40)由导电材料形成；所述接触插塞(70)与所述第一隔离物(30)电连接，所述接触插塞(70)与所述第二隔离物(40)相互绝缘。
  3. 根据权利要求1或2所述的半导体结构，其中，所述第一隔离物(30)和所述第二隔离物(40)至少之一形成为导电线。
  4. 根据权利要求1所述的半导体结构，其中，所述第一隔离物(30)和所述第二隔离物(40)由绝缘材料形成。
  5. 根据权利要求1～4中任一项所述的半导体结构，其中，所述接触插塞(70)与所述第一隔离物(30)的靠近所述第二隔离物(40)的侧表面和所述第一隔离物(30)的靠近所述侧表面的部分顶表面直接接触。
  6. 根据权利要求5所述的半导体结构，其中，所述第一隔离物(30)与所述接触插塞(70)接触的所述部分顶表面和所述侧表面形成台阶。
  7. 根据权利要求5或6所述的半导体结构，其中，还包括：
    绝缘层(80)，位于所述第一平坦化层(20)和所述第二平坦化层(50)之间，且覆盖所述第二隔离物(40)以及所述第一隔离物(30)的除所述侧表面和所述部分顶表面之外的表面；所述接触孔(60)还贯穿所述绝缘层(80)。
  8. 根据权利要求7所述的半导体结构，其中，所述接触插塞(70)还覆盖所述绝缘层(80)位于所述第二隔离物(40)顶表面上方的部分表面。
  9. 根据权利要求7或8所述的半导体结构，其中，所述绝缘层(80)包括层叠设置的第一绝缘层(81)和第二绝缘层(82)；其中，所述第一绝缘层(81)的材料包括氮化物，所述第二绝缘层(82)的材料包括氧化物。
  10. 根据权利要求1～9中任一项所述的半导体结构，其中，所述接触插塞(70)包括扩散阻挡层(71)和金属层(72)；其中，所述扩散阻挡层(71)覆盖所述接触孔(60)的侧壁及底面，所述金属层(72)覆盖所述扩散阻挡层(71)并填充所述接触孔(60)。
  11. 一种半导体结构的制备方法，包括：
    提供基底(10)，其中，所述基底(10)包括衬底(11)和位于所述衬底(11)上的相邻的两个栅极结构(13)，所述衬底(11)具有位于所述相邻的两个栅极结构(13)之间的掺杂区(12)；
    于所述基底(10)上形成第一平坦化层(20)；
    于所述第一平坦化层(20)远离所述基底(10)的表面形成第一隔离物(30)和第二 隔离物(40)；其中，所述第一隔离物(30)和所述第二隔离物(40)之间的空间与所述相邻的两个栅极结构(13)之间的空间大致对准；
    于所述第一平坦化层(20)远离所述基底(10)的表面形成第二平坦化层(50)；其中，所述第二平坦化层(50)覆盖所述第一隔离物(30)和所述第二隔离物(40)；
    刻蚀所述第二平坦化层(50)，以形成贯穿所述第二平坦化层(50)的第一接触孔(61)，所述第一接触孔(61)位于所述第一隔离物(30)和所述第二隔离物(40)之间；
    基于所述第一接触孔(61)，自对准刻蚀所述第一平坦化层(20)，以在所述相邻的两个栅极结构(13)之间形成贯穿所述第一平坦化层(20)的第二接触孔(62)，且至少部分暴露出所述掺杂区(12)；
    于所述第一接触孔(61)和所述第二接触孔(62)中形成接触插塞(70)；其中，所述接触插塞(70)与所述掺杂区(12)电连接。
  12. 根据权利要求11所述的半导体结构的制备方法，其中，所述刻蚀所述第二平坦化层(50)，以形成贯穿所述第二平坦化层(50)的第一接触孔(61)，包括：
    刻蚀所述第二平坦化层(50)，暴露出所述第一隔离物(30)的靠近所述第二隔离物(40)的侧表面和所述第一隔离物(30)的靠近所述侧表面的部分顶表面，以形成所述第一接触孔(61)。
  13. 根据权利要求11或12所述的半导体结构的制备方法，其中，所述第一隔离物(30)和所述第二隔离物(40)采用绝缘材料形成。
  14. 根据权利要求11或12所述的半导体结构的制备方法，其中，所述第一隔离物(30)和所述第二隔离物(40)由导电材料形成；所述制备方法还包括：
    在形成所述第二平坦化层(50)之前，于所述第一平坦化层(20)远离所述基底(10)的表面形成绝缘层(80)，所述绝缘层(80)覆盖所述第一隔离物(30)和所述第二隔离物(40)；
    其中，所述第二平坦化层(50)形成于所述绝缘层(80)远离所述基底(10)的表面；所述第一接触孔(61)和所述第二接触孔(62)还贯穿所述绝缘层(80)相连通。
  15. 根据权利要求14所述的半导体结构的制备方法，其中，所述绝缘层(80)包括层叠形成的第一绝缘层(81)和所述第二绝缘层(82)；其中，所述第一绝缘层(81)的材料包括氮化物，所述第二绝缘层(82)的材料包括氧化物。
  16. 根据权利要求14或15所述的半导体结构的制备方法，其中，所述刻蚀所述第二平坦化层(50)，以形成贯穿所述第二平坦化层(50)的第一接触孔(61)，还包括：
    刻蚀所述第二平坦化层(50)，于所述第一隔离物(30)和所述第二隔离物(40)之间形成初始第一接触孔(610)；
    基于所述初始第一接触孔(610)，对所述绝缘层(80)执行倾斜离子注入工艺，形成待去除区域；
    去除所述绝缘层(80)位于所述待去除区域的部分，暴露出所述第一隔离物(30)的靠近所述第二隔离物(40)的侧表面和所述第一隔离物(30)的靠近所述侧表面的部分顶表面，形成所述第一接触孔(61)。
  17. 根据权利要求16所述的半导体结构的制备方法，其中，所述初始第一接触孔(610)还暴露出所述绝缘层(80)位于所述第一隔离物(30)顶表面和所述第二隔离物(40)顶表面二者上方的部分表面。
  18. 根据权利要求16或17所述的半导体结构的制备方法，其中，所述对所述绝缘层(80)执行倾斜离子注入工艺，形成待去除区域，包括：
    采用离子注入工艺，沿与所述初始第一接触孔(610)的轴线具有夹角的方向对所述绝缘层(80)的待去除部分进行处理，以形成所述待去除区域；所述待去除部分覆盖所述第一隔离物(30)的靠近所述第二隔离物(40)的顶部拐角。
  19. 根据权利要求14～18中任一项所述的半导体结构的制备方法，其中，所述基于所述 第一接触孔(61)，自对准刻蚀所述第一平坦化层(20)，还包括：基于所述第一接触孔(61)，自对准刻蚀所述绝缘层(80)位于所述第一接触孔(61)底部的部分以及所述第一平坦化层(20)。
  20. 根据权利要求11～19中任一项所述的半导体结构的制备方法，其中，所述于所述第一接触孔(61)和所述第二接触孔(62)中形成接触插塞(70)，包括：
    形成覆盖所述第一接触孔(61)的侧壁及所述第二接触孔(62)的侧壁和底面的扩散阻挡层(71)；
    形成覆盖所述扩散阻挡层(71)并填充所述第一接触孔(61)和所述第二接触孔(62)的金属层(72)。
PCT/CN2023/082034 2022-09-30 2023-03-17 半导体结构及其制备方法 WO2024066230A1 (zh)

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