WO2024065636A1 - 像素电路、驱动方法、显示面板及显示装置 - Google Patents

像素电路、驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2024065636A1
WO2024065636A1 PCT/CN2022/123155 CN2022123155W WO2024065636A1 WO 2024065636 A1 WO2024065636 A1 WO 2024065636A1 CN 2022123155 W CN2022123155 W CN 2022123155W WO 2024065636 A1 WO2024065636 A1 WO 2024065636A1
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Prior art keywords
control signal
coupled
transistor
electrode
sub
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Ceased
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PCT/CN2022/123155
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English (en)
French (fr)
Inventor
郭永林
邱海军
胡明
蒋志亮
宋江
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/692,706 priority Critical patent/US12567359B2/en
Priority to PCT/CN2022/123155 priority patent/WO2024065636A1/zh
Priority to CN202280003458.5A priority patent/CN118140264A/zh
Publication of WO2024065636A1 publication Critical patent/WO2024065636A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, a display panel and a display device.
  • Electroluminescent diodes such as organic light emitting diodes (OLED), quantum dot light emitting diodes (QLED), and micro light emitting diodes (Micro LED) have the advantages of self-luminescence and low energy consumption, and are one of the hot spots in the current research field of electroluminescent display devices.
  • pixel circuits are used in electroluminescent display devices to drive electroluminescent diodes to emit light.
  • a driving transistor coupled to the light emitting device and configured to generate a working current driving the light emitting device according to a data voltage
  • a first control circuit coupled to the gate of the driving transistor and configured to reduce the gate leakage of the driving transistor based on a signal at a leakage adjustment signal terminal;
  • a second control circuit is coupled to the first setting electrode of the driving transistor and is configured to initialize the first setting electrode of the driving transistor before driving the light-emitting device to emit light; wherein the first setting electrode is the first electrode and/or the second electrode of the driving transistor;
  • the third control circuit is coupled to the driving transistor and is configured to reset the gate of the driving transistor, control the data voltage to be input into the gate of the driving transistor, and control the driving transistor to generate the operating current to drive the light-emitting device to emit light.
  • the first control circuit includes: a first transistor and a second transistor;
  • the gate of the first transistor is coupled to the gate of the driving transistor, the first electrode of the first transistor is floating, and the second electrode of the first transistor is coupled to the leakage adjustment signal terminal;
  • the gate of the second transistor is coupled to the gate of the driving transistor, the first electrode of the second transistor is floating, and the second electrode of the second transistor is coupled to the leakage regulating signal terminal.
  • the first control circuit includes: a voltage stabilizing capacitor
  • a first electrode of the voltage-stabilizing capacitor is coupled to the gate of the driving transistor, and a second electrode of the voltage-stabilizing capacitor is coupled to the leakage regulating signal terminal.
  • the voltage of the signal at the leakage adjustment signal terminal is a first voltage
  • the voltage of the signal at the leakage adjustment signal terminal is a second voltage
  • the second voltage is not less than the first voltage.
  • the first voltage is the same in different display frames.
  • the second voltage is greater than the third voltage
  • the third voltage is Vda-Vth; Vda represents the data voltage, and Vth represents the threshold voltage of the driving transistor.
  • the second voltage is the same in different display frames
  • the second voltage increases as the third voltage increases.
  • the second control circuit is further configured to provide a signal at a first initialization signal terminal to the first setting electrode after the input data voltage in response to a signal at a first control signal terminal.
  • the first initialization signal terminal is a high level or a low level.
  • the first initialization signal terminal when the first initialization signal terminal is at a high level, the first initialization signal terminal and the first power supply terminal are the same signal terminal.
  • the second control circuit includes: a third transistor
  • a gate of the third transistor is coupled to the first control signal terminal, a first electrode of the third transistor is coupled to the first initialization signal terminal, and a second electrode of the third transistor is coupled to the first setting electrode.
  • the third control circuit includes:
  • a data writing circuit configured to input a data voltage at a data signal terminal into a first electrode of the driving transistor in response to a signal at a second control signal terminal;
  • a reset circuit is configured to input the signal of the second initialization signal terminal into the second setting electrode of the driving transistor in response to the signal of the third control signal terminal;
  • the second setting electrode is the gate or the second electrode of the driving transistor;
  • an initialization circuit configured to input a signal at a third initialization signal terminal into a first electrode of the light emitting device in response to a signal at the first control signal terminal;
  • a threshold compensation circuit configured to conduct the gate of the driving transistor to the second electrode thereof in response to a signal at a fourth control signal terminal;
  • the light emitting control circuit is configured to connect the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the first electrode of the light emitting device in response to the signal of the light emitting control signal terminal, so as to control the operating current generated by the driving transistor to be input into the light emitting device.
  • the data writing circuit includes a fourth transistor, a gate of the fourth transistor is coupled to the second control signal terminal, a first electrode of the fourth transistor is coupled to the data signal terminal, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;
  • the reset circuit includes a fifth transistor, a gate of the fifth transistor is coupled to the third control signal terminal, a first electrode of the fifth transistor is coupled to the second initialization signal terminal, and a second electrode of the fifth transistor is coupled to the second setting electrode of the driving transistor;
  • the threshold compensation circuit includes a seventh transistor and a storage capacitor, the gate of the seventh transistor is coupled to the fourth control signal terminal, the first electrode of the seventh transistor is coupled to the gate of the driving transistor, the second electrode of the seventh transistor is coupled to the second electrode of the driving transistor, the first electrode of the storage capacitor is coupled to the first power supply terminal, and the second electrode of the storage capacitor is coupled to the gate of the driving transistor;
  • the light-emitting control circuit includes an eighth transistor and a ninth transistor, the gate of the eighth transistor is coupled to the light-emitting control signal terminal, the first electrode of the eighth transistor is coupled to the first power supply terminal, the second electrode of the eighth transistor is coupled to the first electrode of the driving transistor, the gate of the ninth transistor is coupled to the light-emitting control signal terminal, the first electrode of the ninth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the ninth transistor is coupled to the first electrode of the light-emitting device.
  • the second control signal terminal and the fourth control signal terminal are the same signal terminal or independent signal terminals.
  • the effective level of the first control signal terminal is later than the effective level of the second control signal terminal.
  • the embodiment of the present disclosure also provides a driving method for the above pixel circuit, including:
  • the third control circuit resets the gate of the driving transistor
  • the third control circuit controls the data voltage to be input into the gate of the driving transistor
  • the second control circuit initializes the first setting electrode of the driving transistor
  • the first control circuit reduces the gate leakage of the driving transistor based on the signal at the leakage adjustment signal terminal; the third control circuit controls the driving transistor to generate the working current to drive the light-emitting device to emit light.
  • the reset stage includes: the reset circuit responds to the signal at the third control signal terminal and inputs the signal at the second initialization signal terminal into the second setting electrode of the driving transistor;
  • the initialization stage further includes: the initialization circuit responds to the signal of the first control signal terminal and inputs the signal of the third initialization signal terminal into the first electrode of the light emitting device.
  • the data writing stage includes: the data writing circuit responds to the signal of the second control signal terminal, inputs the data voltage of the data signal terminal to the first electrode of the driving transistor; the threshold compensation circuit responds to the signal of the second control signal terminal, connects the gate of the driving transistor to its second electrode;
  • the light-emitting stage includes: the light-emitting control circuit responds to the signal at the light-emitting control signal terminal, connects the first electrode of the driving transistor with the first power supply terminal, and connects the second electrode of the driving transistor with the first electrode of the light-emitting device, and controls the working current generated by the driving transistor to be input into the light-emitting device.
  • the present disclosure also provides a display panel, including:
  • a plurality of sub-pixels each of the plurality of sub-pixels comprising the above-mentioned pixel circuit
  • control signal lines a plurality of control signal lines, at least one of the plurality of control signal lines being coupled to a pixel circuit in a row of sub-pixels;
  • a drive control circuit is coupled to the plurality of control signal lines respectively.
  • the plurality of control signal lines include a plurality of light emitting control signal lines; wherein one row of sub-pixels corresponds to one light emitting control signal line, and each of the light emitting control signal lines is coupled to a light emitting control signal terminal of a pixel circuit in a corresponding row of sub-pixels;
  • the driving control circuit includes: a light-emitting scanning circuit, which includes a plurality of light-emitting scanning shift register units arranged in sequence; wherein the light-emitting control signal line coupled to a row of sub-pixels is coupled to a corresponding light-emitting scanning shift register unit.
  • the plurality of control signal lines include a plurality of first scan signal lines; wherein a row of sub-pixels corresponds to two first scan signal lines, and a first first scan signal line of the two first scan signal lines is coupled to a third control signal terminal of a pixel circuit in the corresponding row of sub-pixels, and a second first scan signal line is coupled to a fourth control signal terminal of a pixel circuit in the corresponding row of sub-pixels;
  • the driving control circuit includes: a first scanning control circuit, the first scanning control circuit includes a plurality of first scanning control shift register units arranged in sequence; wherein, in every two adjacent rows of sub-pixels, the first first scanning control signal line coupled to the next row of sub-pixels and the second first scanning control signal line coupled to the previous row of sub-pixels are coupled to the same first scanning control shift register unit.
  • the plurality of control signal lines further include a plurality of second scan control signal lines and a plurality of third scan control signal lines; a row of sub-pixels corresponds to a second scan control signal line and a third scan control signal line, each of the second scan control signal lines is coupled to a second control signal terminal of a pixel circuit in a corresponding row of sub-pixels, and each of the third scan control signal lines is coupled to a first control signal terminal of a pixel circuit in a corresponding row of sub-pixels;
  • the driving control circuit includes: a second scanning control circuit and a third scanning control circuit;
  • the second scanning control circuit includes a plurality of second scanning control shift register units arranged in sequence; wherein the second scanning control signal line coupled to a row of sub-pixels is coupled to a corresponding second scanning control shift register unit;
  • the third scanning control circuit includes a plurality of third scanning control shift register units arranged in sequence; wherein the third scanning control signal line coupled to a row of sub-pixels is coupled to a corresponding third scanning control shift register unit.
  • the plurality of control signal lines further include a plurality of fourth scan control signal lines and a plurality of fifth scan control signal lines; a row of sub-pixels corresponds to a fourth scan control signal line and a fifth scan control signal line, each of the fourth scan control signal lines is coupled to a second control signal terminal of a pixel circuit in a corresponding row of sub-pixels, and each of the fifth scan control signal lines is coupled to a first control signal terminal of a pixel circuit in a corresponding row of sub-pixels;
  • the driving control circuit includes: a fourth scanning control circuit, and the fourth scanning control circuit includes a plurality of fourth scanning control shift register units arranged in sequence; wherein, in every three adjacent rows of sub-pixels, the fifth scanning control signal line coupled to the third row of sub-pixels and the fourth scanning control signal line coupled to the first row of sub-pixels are coupled correspondingly to the same fourth scanning control shift register unit.
  • the plurality of control signal lines further include a plurality of sixth scan control signal lines, a plurality of seventh scan control signal lines, and a plurality of eighth scan control signal lines; a row of sub-pixels corresponds to a sixth scan control signal line, a seventh scan control signal line, and an eighth scan control signal line, each of the sixth scan control signal lines is coupled to a third control signal terminal of a pixel circuit in a corresponding row of sub-pixels, each of the seventh scan control signal lines is coupled to a second control signal terminal of a pixel circuit in a corresponding row of sub-pixels, and each of the eighth scan control signal lines is coupled to a first control signal terminal of a pixel circuit in a corresponding row of sub-pixels;
  • the driving control circuit includes: a fifth scanning control circuit and a sixth scanning control circuit;
  • the fifth scanning control circuit comprises a plurality of fifth scanning control shift register units arranged in sequence; wherein, in every two adjacent rows of sub-pixels, the sixth scanning control signal line coupled to the next row of sub-pixels and the seventh scanning control signal line coupled to the previous row of sub-pixels are correspondingly coupled to the same fifth scanning control shift register unit;
  • the sixth scanning control circuit includes a plurality of sixth scanning control shift register units arranged in sequence; wherein the eighth scanning control signal line coupled to a row of sub-pixels is coupled to a corresponding sixth scanning control shift register unit.
  • the plurality of control signal lines further include a plurality of ninth scan control signal lines, a plurality of tenth scan control signal lines, and a plurality of eleventh scan control signal lines; a row of sub-pixels corresponds to a ninth scan control signal line, a tenth scan control signal line, and an eleventh scan control signal line, each of the ninth scan control signal lines is coupled to a third control signal terminal of a pixel circuit in a corresponding row of sub-pixels, each of the tenth scan control signal lines is coupled to a second control signal terminal of a pixel circuit in a corresponding row of sub-pixels, and each of the eleventh scan control signal lines is coupled to a first control signal terminal of a pixel circuit in a corresponding row of sub-pixels;
  • the driving control circuit includes: a seventh scanning control circuit, and the seventh scanning control circuit includes a plurality of seventh scanning control shift register units arranged in sequence; wherein, in every two adjacent rows of sub-pixels, the ninth scanning control signal line coupled to the next row of sub-pixels and the tenth scanning control signal line coupled to the previous row of sub-pixels are coupled to the same seventh scanning control shift register unit, and the tenth scanning control signal line coupled to the next row of sub-pixels and the eleventh scanning control signal line coupled to the previous row of sub-pixels are coupled to the same seventh scanning control shift register unit.
  • the plurality of control signal lines further include a plurality of twelfth scanning control signal lines; one row of sub-pixels corresponds to one twelfth scanning control signal line, and each of the twelfth scanning control signal lines is coupled to the fourth control signal terminal of the pixel circuit in the corresponding row of sub-pixels;
  • the driving control circuit includes: an eighth scanning control circuit, the eighth scanning control circuit includes a plurality of eighth scanning control shift register units arranged in sequence; wherein the twelfth scanning control signal line coupled to a row of sub-pixels is coupled to a corresponding eighth scanning control shift register unit.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel.
  • FIG1 is a schematic diagram of some structures of pixel circuits provided by embodiments of the present disclosure.
  • FIG2 is a schematic diagram of some other structures of the pixel circuit provided by the embodiment of the present disclosure.
  • FIG3 is a schematic diagram of some other structures of pixel circuits provided by embodiments of the present disclosure.
  • FIG4a is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG4b is another signal timing diagram provided by an embodiment of the present disclosure.
  • FIG5 is a flow chart of a driving method provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of some other structures of the pixel circuit provided by the embodiment of the present disclosure.
  • FIG7 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of some other structures of pixel circuits provided by embodiments of the present disclosure.
  • FIG9 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG10a is a schematic diagram of some other structures of the pixel circuit provided by the embodiment of the present disclosure.
  • FIG10b is a schematic diagram of some other structures of the pixel circuit provided by the embodiment of the present disclosure.
  • FIG11 is a schematic diagram of some structures of a display panel provided in an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure.
  • FIG13 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure.
  • FIG14 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of some further structures of the display panel provided in the embodiment of the present disclosure.
  • the display device may include a display panel.
  • the display panel may include a substrate.
  • the substrate may include a display area and a non-display area (i.e., an area in the substrate except for the area surrounded by the display area).
  • the display area may include a plurality of pixel units arranged in an array.
  • each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors.
  • the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display.
  • the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display.
  • the luminous color of the sub-pixel in the pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following is an example of a pixel unit including a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • each sub-pixel may include a pixel circuit
  • the pixel circuit may include a driving transistor M0 and a light-emitting device L to control the light-emitting device L to emit light, so that the display panel can realize the function of displaying a picture.
  • the threshold voltage Vth of the driving transistor M0 may drift, which affects the generated driving current and causes flickering problems when displaying high and low grayscales.
  • the embodiments of the present disclosure provide some pixel circuits, as shown in FIG1, which may include: a light-emitting device L, a driving transistor M0, a first control circuit 10, a second control circuit 20, and a third control circuit 30.
  • the driving transistor M0 is coupled to the light-emitting device L
  • the first control circuit 10 is coupled to the gate of the driving transistor M0
  • the second control circuit 20 is coupled to the first setting electrode of the driving transistor M0
  • the third control circuit 30 is coupled to the driving transistor M0.
  • the driving transistor M0 is configured to generate a working current for driving the light-emitting device L according to the data voltage.
  • the first control circuit 10 is configured to reduce the gate leakage of the driving transistor M0 based on the signal of the leakage adjustment signal terminal VS.
  • the second control circuit 20 is configured to initialize the first setting electrode of the driving transistor M0 before driving the light-emitting device L to emit light.
  • the third control circuit 30 is configured to reset the gate of the driving transistor M0, control the data voltage to be input into the gate of the driving transistor M0, and control the driving transistor M0 to generate a working current to drive the light-emitting device L to emit light.
  • the pixel circuit provided in the embodiment of the present disclosure can control the data voltage input to the gate of the driving transistor M0 and control the driving transistor M0 to generate an operating current by setting a third control circuit 30, thereby driving the light-emitting device L to emit light.
  • a first control circuit 10 coupled to the gate of the driving transistor M0
  • the gate leakage of the driving transistor M0 can be reduced based on the signal of the leakage adjustment signal terminal VS, thereby improving the flicker problem during low grayscale display.
  • the first setting electrode of the driving transistor M0 can be initialized before driving the light-emitting device L to emit light, thereby improving the hysteresis effect of the driving transistor M0, thereby improving the flicker problem during high grayscale display.
  • the pixel circuit provided by the embodiment of the present disclosure can be applied to display panels driven by different refresh frequencies. Since the pixel circuit provided by the embodiment of the present disclosure can be compatible with improving the flicker problem when displaying high and low grayscales, when switching between different refresh frequencies, the flicker problem is improved, thereby improving the display effect of the product. In addition, in order to reduce power consumption, the pixel circuit provided by the embodiment of the present disclosure can be applied to the case of driving at a lower refresh frequency (for example, 1Hz, 30Hz, etc.). In addition, in order to improve the display effect, the pixel circuit provided by the embodiment of the present disclosure can be applied to the case of driving at a higher refresh frequency (for example, 60Hz, 90Hz, 120Hz, 240Hz, etc.).
  • the first setting electrode may be the first electrode of the driving transistor M0 .
  • the second control circuit 20 is coupled to the first electrode of the driving transistor M0 , and the second control circuit 20 is further configured to initialize the first electrode of the driving transistor M0 after inputting the data voltage.
  • the second control circuit 20 is further configured to provide the signal of the first initialization signal terminal VINIT1 to the first setting electrode in response to the signal of the first control signal terminal CS1.
  • the first setting electrode may be the first electrode of the driving transistor M0
  • the second control circuit 20 is configured to provide the signal of the first initialization signal terminal VINIT1 to the first electrode of the driving transistor M0 after the data voltage is input in response to the signal of the first control signal terminal CS1.
  • the third control circuit 30 may include:
  • the data writing circuit 31 is configured to input the data voltage of the data signal terminal DA into the first electrode of the driving transistor M0 in response to the signal of the second control signal terminal CS2;
  • the reset circuit 32 is configured to input the signal of the second initialization signal terminal VINIT2 to the second setting electrode of the driving transistor M0 in response to the signal of the third control signal terminal CS3;
  • the initialization circuit 33 is configured to input the signal of the third initialization signal terminal VINIT3 to the first electrode of the light emitting device L in response to the signal of the first control signal terminal CS1;
  • the threshold compensation circuit 34 is configured to connect the gate of the driving transistor M0 to its second electrode in response to the signal of the fourth control signal terminal CS4, and stabilize the voltage difference between the first power supply terminal VDD and the gate of the driving transistor M0;
  • the light emitting control circuit 35 is configured to connect the first electrode of the driving transistor M0 to the first power supply terminal VDD and the second electrode of the driving transistor M0 to the first electrode of the light emitting device L in response to the signal of the light emitting control signal terminal EM, so as to control the operating current generated by the driving transistor M0 to be input into the light emitting device L.
  • the second setting electrode may be set as the gate of the driving transistor M0 .
  • the first electrode of the light emitting device L may be coupled to the light emitting control circuit 35.
  • the second electrode of the light emitting device L may be coupled to the second power supply terminal VSSVSS.
  • the first electrode of the light emitting device L may be its anode, and the second electrode may be its cathode.
  • the light emitting device L may be an electroluminescent diode.
  • the light emitting device L may include: at least one of a micro light emitting diode (Micro Light Emitting Diode, Micro LED), an organic electroluminescent diode (Organic Light Emitting Diode, OLED) and a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED).
  • a micro light emitting diode Micro Light Emitting Diode, Micro LED
  • an organic electroluminescent diode Organic Light Emitting Diode, OLED
  • a quantum dot light emitting diode Quantantum Dot Light Emitting Diodes, QLED.
  • the specific structure of the light emitting device L can be designed and determined according to the actual application environment, which is not limited here.
  • the first power supply terminal VDD can be configured to load a constant first power supply voltage, and the first power supply voltage is generally a positive value.
  • the second power supply terminal VSS can load a constant second power supply voltage, and the second power supply voltage can generally be a ground voltage or a negative value.
  • the specific values of the first power supply voltage and the second power supply voltage can be designed and determined according to the actual application environment, and are not limited here.
  • the driving transistor M0 can be set as a P-type transistor; wherein the first electrode of the driving transistor M0 can be its source, the second electrode of the driving transistor M0 can be its drain, and when the driving transistor M0 is in a saturated state, the current flows from the source of the driving transistor M0 to its drain.
  • the driving transistor M0 can also be set as an N-type transistor, which is not limited here.
  • the first control circuit 10 includes: a first transistor M1 and a second transistor M2.
  • the gate of the first transistor M1 is coupled to the gate of the driving transistor M0, the first electrode of the first transistor M1 is floating, and the second electrode of the first transistor M1 is coupled to the leakage adjustment signal terminal VS.
  • the gate of the second transistor M2 is coupled to the gate of the driving transistor M0, the first electrode of the second transistor M2 is floating, and the second electrode of the second transistor M2 is coupled to the leakage adjustment signal terminal VS.
  • vs represents the signal of the leakage adjustment signal terminal VS.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS is the first voltage Vvs1
  • the voltage of the signal vs of the leakage adjustment signal terminal VS is the second voltage Vvs2.
  • the second voltage Vvs2 can be made equal to the first voltage Vvs1. In this way, the voltage of the signal vs of the leakage adjustment signal terminal VS can be a fixed voltage in one display frame.
  • the first voltage Vvs1 may be made the same, so that the first voltage Vvs1 does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 can be made greater than the third voltage Vvs3.
  • the third voltage Vvs3 is Vda-Vth
  • Vda represents the data voltage
  • Vth represents the threshold voltage of the driving transistor.
  • Vda-Vth is approximately 0-1V
  • the second voltage Vvs2 can be set to 2V.
  • Vda can be a data voltage corresponding to a larger grayscale or a maximum grayscale.
  • the second voltage Vvs2 can be made the same, so that the second voltage Vvs2 does not need to be adjusted frequently, thereby reducing power consumption.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS can be made a fixed voltage, so that the voltage of the signal vs of the leakage adjustment signal terminal VS does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 can also be increased as the third voltage Vvs3 increases, so that the second voltage Vvs2 can be adjusted according to the third voltage Vvs3 to further reduce leakage.
  • the voltage of the signal vs at the leakage adjustment signal terminal VS can be an alternating voltage to further reduce leakage.
  • vs represents the signal of the leakage adjustment signal terminal VS.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS is the first voltage Vvs1
  • the voltage of the signal vs of the leakage adjustment signal terminal VS is the second voltage Vvs2.
  • the second voltage Vvs2 can be made greater than the first voltage Vvs1. In this way, the voltage of the signal vs of the leakage adjustment signal terminal VS can be an alternating voltage in one display frame.
  • the first voltage Vvs1 may be made the same, so that the first voltage Vvs1 does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 can be made greater than the third voltage Vvs3.
  • the third voltage Vvs3 is Vda-Vth
  • Vda represents the data voltage
  • Vth represents the threshold voltage of the driving transistor.
  • Vda-Vth is approximately 0-1V
  • the second voltage Vvs2 can be set to 2V.
  • Vda can be a data voltage corresponding to a larger grayscale or a maximum grayscale.
  • the second voltage Vvs2 may be made the same, so that the second voltage Vvs2 does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 may also be increased as the third voltage Vvs3 increases, so that the second voltage Vvs2 may be adjusted according to the third voltage Vvs3 to further reduce leakage.
  • the first transistor M1 and the second transistor M2 may be configured as P-type transistors.
  • the first transistor and the second transistor may also be configured as N-type transistors, which is not limited here.
  • the second control circuit 20 includes: a third transistor M3 .
  • the gate of the third transistor M3 is coupled to the first control signal terminal CS1
  • the first electrode of the third transistor M3 is coupled to the first initialization signal terminal VINIT1
  • the second electrode of the third transistor M3 is coupled to the first setting electrode.
  • the third transistor M3 is turned on under the control of the effective level of the first control signal of the first control signal terminal CS1, and is turned off under the control of the ineffective level of the first control signal.
  • the third transistor M3 can be set as a P-type transistor, then the effective level of the first control signal can be a low level, and the ineffective level of the first control signal can be a high level.
  • the third transistor M3 can also be set as an N-type transistor, then the effective level of the first control signal can be a high level, and the ineffective level of the first control signal can be a low level.
  • the signal at the first initialization signal terminal can be set to a high level.
  • the driving transistor can be turned on based on the voltage of its gate and the first electrode, thereby initializing not only the first electrode of the driving transistor but also the second electrode of the driving transistor, further improving the hysteresis effect of the driving transistor M0, thereby improving the flicker problem during high grayscale display.
  • the first initialization signal terminal and the first power terminal are the same signal terminal, which can reduce the number of signal terminals.
  • the first initialization signal terminal and the first power terminal can be independent signal terminals, so that the signal loaded on the first initialization signal terminal is not affected by the first power terminal.
  • the signal at the first initialization signal terminal may also be set to a low level. In this way, after the signal at the first initialization signal terminal is input to the first electrode of the driving transistor, the first electrode of the driving transistor is initialized to improve the hysteresis effect of the driving transistor M0, thereby improving the flicker problem during high grayscale display.
  • the first initialization signal terminal and the second power terminal are the same signal terminal, which can reduce the number of signal terminals.
  • the first initialization signal terminal and the second power terminal can be independent signal terminals, so that the signal loaded on the first initialization signal terminal is not affected by the second power terminal.
  • the data writing circuit 31 includes a fourth transistor M4, a gate of the fourth transistor M4 is coupled to the second control signal terminal CS2, a first electrode of the fourth transistor M4 is coupled to the data signal terminal DA, and a second electrode of the fourth transistor M4 is coupled to the first electrode of the driving transistor M0.
  • the fourth transistor M4 is turned on under the control of the effective level of the second control signal of the second control signal terminal CS2, and is turned off under the control of the ineffective level of the second control signal.
  • the fourth transistor M4 can be set as a P-type transistor, then the effective level of the second control signal can be a low level, and the ineffective level of the second control signal can be a high level.
  • the fourth transistor M4 can also be set as an N-type transistor, then the effective level of the second control signal can be a high level, and the ineffective level of the second control signal can be a low level.
  • the reset circuit 32 includes a fifth transistor M5, the gate of the fifth transistor M5 is coupled to the third control signal terminal CS3, the first electrode of the fifth transistor M5 is coupled to the second initialization signal terminal VINIT2, and the second electrode of the fifth transistor M5 is coupled to the second setting electrode of the driving transistor M0.
  • the fifth transistor M5 is turned on under the control of the effective level of the third control signal of the third control signal terminal CS3, and is turned off under the control of the ineffective level of the third control signal.
  • the fifth transistor M5 can be set as a P-type transistor, then the effective level of the third control signal can be a low level, and the ineffective level of the third control signal can be a high level.
  • the fifth transistor M5 can also be set as an N-type transistor, then the effective level of the third control signal can be a high level, and the ineffective level of the third control signal can be a low level.
  • the initialization circuit 33 includes a sixth transistor M6, the gate of the sixth transistor M6 is coupled to the first control signal terminal CS1, the first electrode of the sixth transistor M6 is coupled to the third initialization signal terminal VINIT3, and the second electrode of the sixth transistor M6 is coupled to the first electrode of the light-emitting device L.
  • the sixth transistor M6 is turned on under the control of the effective level of the first control signal of the first control signal terminal CS1, and is turned off under the control of the ineffective level of the first control signal.
  • the sixth transistor M6 can be set as a P-type transistor, then the effective level of the first control signal can be a low level, and the ineffective level of the first control signal can be a high level.
  • the sixth transistor M6 can also be set as an N-type transistor, then the effective level of the first control signal can be a high level, and the ineffective level of the first control signal can be a low level.
  • the threshold compensation circuit 34 includes a seventh transistor M7 and a storage capacitor CST, the gate of the seventh transistor M7 is coupled to the fourth control signal terminal CS4, the first electrode of the seventh transistor M7 is coupled to the gate of the driving transistor M0, the second electrode of the seventh transistor M7 is coupled to the second electrode of the driving transistor M0, the first electrode of the storage capacitor CST is coupled to the first power supply terminal VDD, and the second electrode of the storage capacitor CST is coupled to the gate of the driving transistor M0.
  • the seventh transistor M7 is turned on under the control of the effective level of the fourth control signal of the fourth control signal terminal CS4, and is turned off under the control of the ineffective level of the fourth control signal.
  • the seventh transistor M7 can be set as a P-type transistor, then the effective level of the fourth control signal can be a low level, and the ineffective level of the fourth control signal can be a high level.
  • the seventh transistor M7 can also be set as an N-type transistor, then the effective level of the fourth control signal can be a high level, and the ineffective level of the fourth control signal can be a low level.
  • the light-emitting control circuit 35 includes an eighth transistor M8 and a ninth transistor M9, the gate of the eighth transistor M8 is coupled to the light-emitting control signal terminal EM, the first electrode of the eighth transistor M8 is coupled to the first power supply terminal VDD, the second electrode of the eighth transistor M8 is coupled to the first electrode of the driving transistor M0, the gate of the ninth transistor M9 is coupled to the light-emitting control signal terminal EM, the first electrode of the ninth transistor M9 is coupled to the second electrode of the driving transistor M0, and the second electrode of the ninth transistor M9 is coupled to the first electrode of the light-emitting device L.
  • the eighth transistor M8 is turned on under the control of the effective level of the light emitting control signal of the light emitting control signal terminal EM, and is turned off under the control of the invalid level of the light emitting control signal.
  • the eighth transistor M8 can be set as a P-type transistor, then the effective level of the light emitting control signal can be a low level, and the invalid level of the light emitting control signal can be a high level.
  • the eighth transistor M8 can also be set as an N-type transistor, then the effective level of the light emitting control signal can be a high level, and the invalid level of the light emitting control signal can be a low level.
  • the ninth transistor M9 is turned on under the control of the effective level of the light emitting control signal of the light emitting control signal terminal EM, and is turned off under the control of the invalid level of the light emitting control signal.
  • the ninth transistor M9 can be set as a P-type transistor, then the effective level of the light emitting control signal can be a low level, and the invalid level of the light emitting control signal can be a high level.
  • the ninth transistor M9 can also be set as an N-type transistor, then the effective level of the light emitting control signal can be a high level, and the invalid level of the light emitting control signal can be a low level.
  • the second initialization signal terminal VINIT2 and the third initialization signal terminal VINIT3 can be the same signal terminal.
  • the second initialization signal terminal VINIT2 and the third initialization signal terminal VINIT3 can also be independent signal terminals, so that the second initialization signal terminal VINIT2 and the third initialization signal terminal VINIT3 can be loaded with the same or different voltages.
  • the second initialization signal terminal VINIT2 and the first initialization signal terminal VINIT1 can be the same signal terminal.
  • the second initialization signal terminal VINIT2 and the first initialization signal terminal VINIT1 can also be independent signal terminals, so that the second initialization signal terminal VINIT2 and the first initialization signal terminal VINIT1 can be loaded with the same or different voltages.
  • the second control signal terminal CS2 and the fourth control signal terminal CS4 may be independent signal terminals, and different signals may be loaded to the second control signal terminal CS2 and the fourth control signal terminal CS4.
  • the first electrode of the transistor can be used as its source and the second electrode as its drain according to the type of transistor and the signal of its gate; or, conversely, the first electrode of the transistor can be used as its drain and the second electrode can be used as its source.
  • This can be designed and determined according to the actual application environment, and no specific distinction is made here.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG3 is shown in FIG4a.
  • the effective level of the first control signal terminal CS1 is later than the effective level of the second control signal terminal CS2.
  • the turn-on time of the third transistor M3 can be made later than the turn-on time of the fourth transistor M4, or it can be said that the turn-on time of the fourth transistor M4 is earlier than the turn-on time of the third transistor M3.
  • the driving method of the pixel circuit may include the following steps:
  • the third control circuit resets the gate of the driving transistor
  • the third control circuit controls the data voltage to be input into the gate of the driving transistor
  • the first control circuit reduces the gate leakage of the driving transistor based on the signal at the leakage adjustment signal terminal; the third control circuit controls the driving transistor to generate the working current to drive the light-emitting device to emit light.
  • the reset phase includes the reset circuit 32 responding to the signal of the third control signal terminal CS3 and inputting the signal of the second initialization signal terminal VINIT2 into the second setting electrode of the driving transistor M0.
  • the second setting electrode is the gate of the driving transistor M0.
  • the reset stage may further include: the threshold compensation circuit 34 connects the gate of the driving transistor M0 to the second electrode thereof in response to the signal of the fourth control signal terminal CS4.
  • the initialization stage further includes: the initialization circuit 33 inputs the signal of the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L in response to the signal of the first control signal terminal CS1.
  • the data writing stage includes: the data writing circuit 31 responds to the signal of the second control signal terminal CS2 to input the data voltage of the data signal terminal DA into the first electrode of the driving transistor M0; the threshold compensation circuit 34 responds to the signal of the second control signal terminal CS2 to turn on the gate of the driving transistor M0 and its second electrode.
  • the light-emitting stage includes: the light-emitting control circuit 35 responds to the signal of the light-emitting control signal terminal EM, connects the first electrode of the driving transistor M0 with the first power supply terminal VDD, and connects the second electrode of the driving transistor M0 with the first electrode of the light-emitting device L, and controls the working current generated by the driving transistor M0 to be input into the light-emitting device L.
  • the structure of the pixel circuit shown in FIG3 is taken as an example, and the working process of the pixel circuit provided by the embodiment of the present disclosure in a display frame is described in combination with the signal timing diagrams shown in FIG4a and FIG4b.
  • the reset phase T1 the data writing phase T2
  • the initialization phase T3 the light-emitting phase T4 in the signal timing diagram shown in FIG4a are mainly selected.
  • em represents the light-emitting control signal loaded to the light-emitting control signal terminal EM
  • vc1 represents the first control signal of the first control signal terminal CS1
  • vc2 represents the second control signal of the second control signal terminal CS2
  • vc3 represents the third control signal of the third control signal terminal CS3
  • vc4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the fifth transistor M5 is turned on under the control of the low level of the third control signal cs3, the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1, the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2, the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4, and the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the gate of the driving transistor M0, and resets the gate of the driving transistor M0.
  • the fifth transistor M5 is turned on under the control of the low level of the third control signal cs3, the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1, the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2, the seventh transistor M7 is turned on under the control of the low level of the fourth control signal cs4, and the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the gate of the driving transistor M0, and initializes the gate of the driving transistor M0.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the gate of the driving transistor M0, and resets the gate of the driving transistor M0.
  • the turned-on seventh transistor M7 conducts the gate of the driving transistor M0 with its second pole, and also provides the signal of the second initialization signal terminal VINIT2 to the second pole of the driving transistor M0, and resets the second pole of the driving transistor M0.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1
  • the fourth transistor M4 is turned on under the control of the low level of the second control signal cs2
  • the seventh transistor M7 is turned on under the control of the low level of the fourth control signal cs4
  • the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fourth transistor M4 inputs the data voltage Vda of the data signal terminal DA to the first electrode of the driving transistor M0.
  • the turned-on seventh transistor M7 turns on the gate of the driving transistor M0 and its second electrode, so that the driving transistor M0 forms a diode connection mode, and the gate of the driving transistor M0 can be charged by the data voltage Vda, so that the voltage of the gate of the driving transistor M0 becomes Vda-Vth.
  • Vth represents the threshold voltage of the driving transistor M0.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned on under the control of the low level of the first control signal cs1
  • the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2
  • the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4
  • the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on third transistor M3 provides the signal of the first initialization signal terminal VINIT1 to the first electrode of the driving transistor M0, and initializes the first electrode of the driving transistor M0.
  • the turned-on sixth transistor M6 provides the signal of the third initialization signal terminal VINIT3 to the first electrode of the light emitting device L, and initializes the first electrode of the light emitting device L.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1
  • the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2
  • the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4
  • the eighth transistor M8 and the ninth transistor M9 are turned on under the control of the low level of the light-emitting control signal em.
  • the turned-on eighth transistor M8 conducts the first power supply terminal VDD with the first electrode of the driving transistor M0, so that the voltage of the first electrode of the driving transistor M0 is the first power supply voltage Vdd.
  • the gate leakage of the driving transistor M0 can be reduced based on the signal of the leakage adjustment signal terminal VS, thereby improving the flicker problem during low grayscale display.
  • the first electrode of the driving transistor M0 can be initialized after the data voltage is input and before the light-emitting device L is driven to emit light, thereby improving the hysteresis effect of the driving transistor M0, thereby improving the flicker problem during high grayscale display. Therefore, the pixel circuit provided in the embodiment of the present disclosure can be compatible with improving the flicker problem during high and low grayscale display.
  • the above-mentioned pixel circuit provided in the embodiment of the present disclosure has a buffer stage T5 between the data writing stage T2 and the initialization stage T3, and a buffer stage T6 between the initialization stage T3 and the light-emitting stage T4.
  • the buffer stages T5 and T6 By setting the buffer stages T5 and T6, the signal in the pixel circuit can be stabilized before entering the next stage, thereby further improving the stability of the pixel circuit.
  • inventions of the present invention provide other schematic diagrams of pixel circuits, as shown in Figure 6, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the second setting electrode can also be set to the second electrode of the driving transistor M0.
  • the reset circuit 32 is configured to input the signal of the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0 in response to the signal of the third control signal terminal CS3.
  • the second electrode of the fifth transistor M5 is coupled to the second electrode of the driving transistor M0.
  • the first control signal terminal CS1, the second control signal terminal CS2, the third control signal terminal CS3 and the fourth control signal terminal CS4 are independent signal terminals to load different signals respectively.
  • the first setting electrode may be the first electrode of the driving transistor M0.
  • the second control circuit 20 is coupled to the first electrode of the driving transistor M0, and the second control circuit 20 is further configured to initialize the first electrode of the driving transistor M0 after inputting the data voltage.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG6 may be as shown in FIG4a and FIG4b.
  • the driving process of the pixel circuit provided by the embodiment of the present disclosure is as follows:
  • the fifth transistor M5 is turned on under the control of the low level of the third control signal cs3, the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1, the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2, the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4, and the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0, and resets the second electrode of the driving transistor M0.
  • the fifth transistor M5 is turned on under the control of the low level of the third control signal cs3, the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1, the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2, the seventh transistor M7 is turned on under the control of the low level of the fourth control signal cs4, and the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the gate of the driving transistor M0, and initializes the gate of the driving transistor M0.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0, and resets the second electrode of the driving transistor M0.
  • the turned-on seventh transistor M7 conducts the gate of the driving transistor M0 with its second electrode, and also provides the signal of the second initialization signal terminal VINIT2 to the gate of the driving transistor M0, and resets the gate of the driving transistor M0.
  • the working process in the data writing stage T2, the initialization stage T3 and the light emitting stage T4 can refer to the above description and will not be elaborated here.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG6 may also be shown in FIG7.
  • the working process of the pixel circuit provided by the embodiment of the present disclosure within a display frame is described.
  • the reset phase T1 the data writing phase T2
  • the initialization phase T3 the initialization phase T3 and the light-emitting phase T4 in the signal timing diagram shown in FIG7 are mainly selected.
  • em represents the light-emitting control signal loaded to the light-emitting control signal terminal EM
  • vc1 represents the first control signal of the first control signal terminal CS1
  • vc2 represents the second control signal of the second control signal terminal CS2
  • vc3 represents the third control signal of the third control signal terminal CS3
  • vc4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the fifth transistor M5 is turned on under the control of the low level of the third control signal cs3, the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1, the fourth transistor M4 is turned off under the control of the high level of the second control signal cs2, the seventh transistor M7 is turned on under the control of the low level of the fourth control signal cs4, and the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal.
  • the turned-on fifth transistor M5 provides the signal of the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0, and resets the second electrode of the driving transistor M0.
  • the turned-on seventh transistor M7 turns on the gate of the driving transistor M0 and its second electrode, and resets the gate of the driving transistor M0.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1
  • the fourth transistor M4 is turned on under the control of the low level of the second control signal cs2
  • the seventh transistor M7 is turned on under the control of the low level of the fourth control signal cs4
  • the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal.
  • the turned-on fourth transistor M4 inputs the data voltage Vda of the data signal terminal DA to the first electrode of the driving transistor M0.
  • the turned-on seventh transistor M7 turns on the gate of the driving transistor M0 and its second electrode, so that the driving transistor M0 forms a diode connection mode, and the gate of the driving transistor M0 can be charged by the data voltage Vda, so that the voltage of the gate of the driving transistor M0 becomes Vda-Vth.
  • Vth represents the threshold voltage of the driving transistor M0.
  • the working process in the initialization stage T3 can refer to the above description and will not be elaborated here.
  • the working process in the light-emitting stage T4 can refer to the above description and will not be elaborated here.
  • inventions of the present invention provide some further structural schematic diagrams of pixel circuits, as shown in Figure 8, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the second control signal terminal CS2 and the fourth control signal terminal CS4 are the same signal terminal to reduce the number of signal terminals and the number of wirings.
  • the gate of the fourth transistor M4 and the gate of the seventh transistor M7 are both coupled to the second control signal terminal CS2.
  • the second initialization signal terminal VINIT2 and the third initialization signal terminal VINIT3 are the same signal terminal to reduce the number of signal terminals and the number of wirings.
  • the second electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6 are both coupled to the third initialization signal terminal VINIT3.
  • the first setting electrode may be the first electrode of the driving transistor M0.
  • the second control circuit 20 is coupled to the first electrode of the driving transistor M0, and the second control circuit 20 is further configured to initialize the first electrode of the driving transistor M0 after inputting the data voltage.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG8 is shown in FIG9.
  • the working process of the pixel circuit provided by the embodiment of the present disclosure within a display frame is described in combination with the signal timing diagram shown in FIG9.
  • the reset phase T1 the data writing phase T2
  • the initialization phase T3 the initialization phase T3 and the light-emitting phase T4 in the signal timing diagram shown in FIG9 are mainly selected.
  • em represents the light-emitting control signal loaded to the light-emitting control signal terminal EM
  • vc1 represents the first control signal of the first control signal terminal CS1
  • vc2 represents the second control signal of the second control signal terminal CS2
  • vc3 represents the third control signal of the third control signal terminal CS3.
  • the fifth transistor M5 is turned on under the control of the low level of the third control signal cs3, the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1, the fourth transistor M4 and the seventh transistor M7 are turned off under the control of the high level of the second control signal cs2, and the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 provides the signal of the third initialization signal terminal VINIT3 to the gate of the driving transistor M0, and resets the gate of the driving transistor M0.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1
  • the fourth transistor M4 and the seventh transistor M7 are turned on under the control of the low level of the second control signal cs2
  • the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fourth transistor M4 inputs the data voltage Vda of the data signal terminal DA to the first electrode of the driving transistor M0.
  • the turned-on seventh transistor M7 turns on the gate of the driving transistor M0 and its second electrode, so that the driving transistor M0 forms a diode connection mode, and the gate of the driving transistor M0 can be charged by the data voltage Vda, so that the voltage of the gate of the driving transistor M0 becomes Vda-Vth.
  • Vth represents the threshold voltage of the driving transistor M0.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned on under the control of the low level of the first control signal cs1
  • the fourth transistor M4 and the seventh transistor M7 are turned off under the control of the high level of the second control signal cs2
  • the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on third transistor M3 provides the signal of the first initialization signal terminal VINIT1 to the first electrode of the driving transistor M0, and initializes the first electrode of the driving transistor M0.
  • the turned-on sixth transistor M6 provides the signal of the third initialization signal terminal VINIT3 to the first electrode of the light emitting device L, and initializes the first electrode of the light emitting device L.
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned off under the control of the high level of the first control signal cs1
  • the fourth transistor M4 and the seventh transistor M7 are turned off under the control of the high level of the second control signal cs2
  • the eighth transistor M8 and the ninth transistor M9 are turned on under the control of the low level of the light-emitting control signal em.
  • the turned-on eighth transistor M8 conducts the first power supply terminal VDD with the first electrode of the driving transistor M0, so that the voltage of the first electrode of the driving transistor M0 is the first power supply voltage Vdd.
  • the gate leakage of the driving transistor M0 can be reduced based on the signal of the leakage adjustment signal terminal VS, thereby improving the flicker problem during low grayscale display.
  • the first electrode of the driving transistor M0 can be initialized after the data voltage is input and before the light-emitting device L is driven to emit light, thereby improving the hysteresis effect of the driving transistor M0, thereby improving the flicker problem during high grayscale display. Therefore, the pixel circuit provided in the embodiment of the present disclosure can be compatible with improving the flicker problem during high and low grayscale display.
  • the pixel circuit provided in the embodiment of the present disclosure has a buffer stage T65 between the initialization stage T3 and the light emitting stage T4.
  • the buffer stage T5 By setting the buffer stage T5, the signal in the pixel circuit can be stabilized before entering the next stage, further improving the stability of the pixel circuit.
  • the present invention provides some further schematic diagrams of the structure of the pixel circuit, as shown in Fig. 10a, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the second control signal terminal CS2 and the fourth control signal terminal CS4 are the same signal terminal to reduce the number of signal terminals and the number of wirings.
  • the gate of the fourth transistor M4 and the gate of the seventh transistor M7 are both coupled to the second control signal terminal CS2.
  • the first setting electrode may be the second electrode of the driving transistor M0 .
  • the second control circuit 20 is coupled to the first electrode of the driving transistor M0 , and the second control circuit 20 is further configured to initialize the second electrode of the driving transistor M0 after inputting the data voltage.
  • the second initialization signal terminal VINIT2 and the third initialization signal terminal VINIT3 are the same signal terminal to reduce the number of signal terminals and the number of wirings.
  • the second electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6 are both coupled to the third initialization signal terminal VINIT3.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG10a may be shown in FIG9.
  • the driving process of the pixel circuit provided by the embodiment of the present disclosure is as follows:
  • the fifth transistor M5 is turned off under the control of the high level of the third control signal cs3
  • the third transistor M3 and the sixth transistor M6 are turned on under the control of the low level of the first control signal cs1
  • the fourth transistor M4 and the seventh transistor M7 are turned off under the control of the high level of the second control signal cs2
  • the eighth transistor M8 and the ninth transistor M9 are turned off under the control of the high level of the light emitting control signal em.
  • the turned-on third transistor M3 provides the signal of the first initialization signal terminal VINIT1 to the second electrode of the driving transistor M0, and initializes the second electrode of the driving transistor M0.
  • the turned-on sixth transistor M6 provides the signal of the third initialization signal terminal VINIT3 to the first electrode of the light emitting device L, and initializes the first electrode of the light emitting device L.
  • the working process in the light-emitting stage T4 can refer to the above description and will not be elaborated here.
  • the present invention provides some further schematic diagrams of the structure of the pixel circuit, as shown in Fig. 10b, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the first control circuit 10 may also include: a voltage stabilizing capacitor CFT, wherein a first electrode of the voltage stabilizing capacitor CFT is coupled to the gate of the driving transistor M0, and a second electrode of the voltage stabilizing capacitor CFT is coupled to the leakage adjustment signal terminal VS.
  • a voltage stabilizing capacitor CFT wherein a first electrode of the voltage stabilizing capacitor CFT is coupled to the gate of the driving transistor M0, and a second electrode of the voltage stabilizing capacitor CFT is coupled to the leakage adjustment signal terminal VS.
  • the implementation of the signal at the leakage adjustment signal terminal VS may be set with reference to the above description, which will not be elaborated herein.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 10ba may be shown in Figure 9.
  • the driving process of the pixel circuit provided by the embodiment of the present disclosure may refer to the above description, which will not be repeated here.
  • Each sub-pixel in the display panel provided by the embodiment of the present disclosure may include any of the above-mentioned pixel circuits provided by the embodiment of the present disclosure.
  • the display panel may also include multiple control signal lines and a drive control circuit. At least one of the multiple control signal lines is coupled to the pixel circuits in a row of sub-pixels, and the drive control circuit is coupled to the multiple control signal lines respectively.
  • the plurality of control signal lines include a plurality of light-emitting control signal lines, a plurality of first scanning signal lines, a plurality of second scanning control signal lines, and a plurality of third scanning control signal lines; wherein a row of sub-pixels corresponds to a light-emitting control signal line, a row of sub-pixels corresponds to two first scanning signal lines, and a row of sub-pixels corresponds to a second scanning control signal line and a third scanning control signal line.
  • each light-emitting control signal line is coupled to a light-emitting control signal terminal EM of a pixel circuit in a corresponding row of sub-pixels.
  • the first first scanning signal line of the two first scanning signal lines is coupled to a third control signal terminal CS3 of a pixel circuit in a corresponding row of sub-pixels, and the second first scanning signal line is coupled to a fourth control signal terminal CS4 of a pixel circuit in a corresponding row of sub-pixels.
  • Each second scanning control signal line is coupled to a second control signal terminal CS2 of a pixel circuit in a corresponding row of sub-pixels
  • each third scanning control signal line is coupled to a first control signal terminal CS1 of a pixel circuit in a corresponding row of sub-pixels.
  • the driving control circuit includes: a light-emitting scanning circuit SRE, a first scanning control circuit SRG1, a second scanning control circuit SRG2 and a third scanning control circuit SRG3.
  • the light-emitting scanning circuit SRE includes a plurality of light-emitting scanning shift register units arranged in sequence; wherein a light-emitting control signal line coupled to a row of sub-pixels is coupled to a light-emitting scanning shift register unit.
  • the first scanning control circuit SRG1 includes a plurality of first scanning control shift register units arranged in sequence; wherein, in every two adjacent rows of sub-pixels, the first first scanning control signal line coupled to the next row of sub-pixels and the second first scanning control signal line coupled to the previous row of sub-pixels are coupled to the same first scanning control shift register unit.
  • the second scan control circuit SRG2 includes a plurality of second scan control shift register units arranged in sequence; wherein a second scan control signal line coupled to a row of sub-pixels is coupled to a corresponding second scan control shift register unit.
  • the third scan control circuit SRG3 includes a plurality of third scan control shift register units arranged in sequence; wherein a third scan control signal line coupled to a row of sub-pixels is coupled to a corresponding third scan control shift register unit.
  • a light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE two adjacent first scanning control shift register units SRGA1(N-1) to SRGA1(N) in the first scanning control circuit SRG1, a second scanning control shift register unit SRGA2(N) in the second scanning control circuit SRG2, and a third scanning control shift register unit SRGA3(N) in the third scanning control circuit SRG3 are illustrated.
  • the Nth light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE is coupled to the light-emitting control signal line EML(N) corresponding to the Nth row of sub-pixels.
  • the N-1th first scanning control shift register unit SRGA1(N-1) in the first scanning control circuit SRG1 is coupled to the second first scanning control signal line GA1LB(N) corresponding to the Nth row of sub-pixels, and the Nth first scanning control shift register unit SRGA1(N) is coupled to the first first scanning control signal line GA1LA(N) corresponding to the Nth row of sub-pixels.
  • the Nth second scan control shift register unit SRGA2(N) in the second scan control circuit SRG2 is coupled to the second scan control signal line GA2L(N) corresponding to the Nth row of sub-pixels.
  • the Nth third scan control shift register unit SRGA3(N) in the third scan control circuit SRG3 is coupled to the third scan control signal line GA3L(N) corresponding to the Nth row of sub-pixels.
  • inventions of the present invention provide some further structural schematic diagrams of pixel circuits, as shown in Figure 12, which are modified from the implementation methods in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.
  • the plurality of control signal lines include a plurality of light-emitting control signal lines, a plurality of first scanning signal lines, a plurality of fourth scanning control signal lines, and a plurality of fifth scanning control signal lines; wherein a row of sub-pixels corresponds to a light-emitting control signal line, a row of sub-pixels corresponds to two first scanning signal lines, and a row of sub-pixels corresponds to a fourth scanning control signal line and a fifth scanning control signal line.
  • each light-emitting control signal line is coupled to a light-emitting control signal terminal EM of a pixel circuit in a corresponding row of sub-pixels.
  • the first first scanning signal line of the two first scanning signal lines is coupled to a third control signal terminal CS3 of a pixel circuit in a corresponding row of sub-pixels, and the second first scanning signal line is coupled to a fourth control signal terminal CS4 of a pixel circuit in a corresponding row of sub-pixels.
  • Each fourth scanning control signal line is coupled to a second control signal terminal CS2 of a pixel circuit in a corresponding row of sub-pixels, and each fifth scanning control signal line is coupled to a first control signal terminal CS1 of a pixel circuit in a corresponding row of sub-pixels.
  • the driving control circuit includes: a light-emitting scanning circuit SRE, a first scanning control circuit SRG1 and a fourth scanning control circuit SRG4.
  • the light-emitting scanning circuit SRE includes a plurality of light-emitting scanning shift register units arranged in sequence; wherein a light-emitting control signal line coupled to a row of sub-pixels is coupled to a light-emitting scanning shift register unit.
  • the first scanning control circuit SRG1 includes a plurality of first scanning control shift register units arranged in sequence; wherein, in every two adjacent rows of sub-pixels, the first first scanning control signal line coupled to the next row of sub-pixels and the second first scanning control signal line coupled to the previous row of sub-pixels are coupled to the same first scanning control shift register unit.
  • the fourth scan control circuit SRG4 includes a plurality of fourth scan control shift register units arranged in sequence; wherein, in every three adjacent rows of sub-pixels, the fifth scan control signal line coupled to the third row of sub-pixels and the fourth scan control signal line coupled to the first row of sub-pixels are coupled correspondingly to the same fourth scan control shift register unit.
  • a light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE two adjacent first scanning control shift register units SRGA1(N-1) to SRGA1(N) in the first scanning control circuit SRG1, and three adjacent fourth scanning control shift register units SRGA4(N-2) to SRGA4(N) in the fourth scanning control circuit SRG4 are illustrated.
  • the Nth light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE is coupled to the light-emitting control signal line EML(N) corresponding to the Nth row of sub-pixels.
  • the N-1th first scanning control shift register unit SRGA1(N-1) in the first scanning control circuit SRG1 is coupled to the second first scanning control signal line CS3L(N) corresponding to the Nth row of sub-pixels, and the Nth first scanning control shift register unit SRGA1(N) is coupled to the first first scanning control signal line CS4L(N) corresponding to the Nth row of sub-pixels.
  • the N-2th fourth scanning control shift register unit SRGA4(N-2) in the fourth scanning control circuit SRG4 is coupled to the fourth scanning control signal line GA4L(N) corresponding to the Nth row of sub-pixels, and the Nth fourth scanning control shift register unit SRGA4(N) is coupled to the fifth scanning control signal line GA5L(N) corresponding to the Nth row of sub-pixels.
  • inventions of the present invention provide some further structural schematic diagrams of pixel circuits, as shown in Figure 13, which are modified from the implementation methods in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.
  • the multiple control signal lines include multiple light-emitting control signal lines, multiple sixth scanning control signal lines, multiple seventh scanning control signal lines, and multiple eighth scanning control signal lines; wherein, a row of sub-pixels corresponds to a light-emitting control signal line, and a row of sub-pixels corresponds to a sixth scanning control signal line, a seventh scanning control signal line, and an eighth scanning control signal line.
  • each light-emitting control signal line is coupled to the light-emitting control signal terminal EM of the pixel circuit in the corresponding row of sub-pixels.
  • Each sixth scanning control signal line is coupled to the third control signal terminal CS3 of the pixel circuit in the corresponding row of sub-pixels, each seventh scanning control signal line is coupled to the second control signal terminal CS2 of the pixel circuit in the corresponding row of sub-pixels, and each eighth scanning control signal line is coupled to the first control signal terminal CS1 of the pixel circuit in the corresponding row of sub-pixels.
  • the driving control circuit includes: a light-emitting scanning circuit SRE, the light-emitting scanning circuit SRE includes a plurality of light-emitting scanning shift register units arranged in sequence; wherein, a light-emitting control signal line coupled to a row of sub-pixels is coupled to a corresponding light-emitting scanning shift register unit.
  • the drive control circuit includes: a fifth scanning control circuit SRG5 and a sixth scanning control circuit SRG6.
  • the fifth scanning control circuit SRG5 includes a plurality of fifth scanning control shift register units arranged in sequence; wherein, in each two adjacent rows of sub-pixels, the sixth scanning control signal line coupled to the next row of sub-pixels and the seventh scanning control signal line coupled to the previous row of sub-pixels are coupled to the same fifth scanning control shift register unit.
  • the sixth scanning control circuit SRG6 includes a plurality of sixth scanning control shift register units arranged in sequence; wherein, the eighth scanning control signal line coupled to a row of sub-pixels is coupled to a sixth scanning control shift register unit.
  • a light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE, a sixth scanning control shift register unit SRGA6(N) in the sixth scanning control circuit SRG6, and two adjacent fifth scanning control shift register units SRGA5(N-1) to SRGA5(N) in the fifth scanning control circuit SRG5 are illustrated.
  • the Nth light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE is coupled to the light-emitting control signal line EML(N) corresponding to the Nth row of sub-pixels.
  • the Nth sixth scanning control shift register unit SRGA6(N) in the sixth scanning control circuit SRG6 is coupled to the eighth scanning control signal line CS8L(N) corresponding to the Nth row of sub-pixels.
  • the N-1th fifth scanning control shift register unit SRGA5(N-1) in the fifth scanning control circuit SRG5 is coupled to the sixth scanning control signal line GA6L(N) corresponding to the Nth row of sub-pixels, and the Nth fifth scanning control shift register unit SRGA5(N) is coupled to the seventh scanning control signal line GA7L(N) corresponding to the Nth row of sub-pixels.
  • inventions of the present invention provide some further structural schematic diagrams of pixel circuits, as shown in Figure 14, which are modified from the implementation methods in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.
  • the multiple control signal lines include multiple light-emitting control signal lines, multiple ninth scanning control signal lines, multiple tenth scanning control signal lines, and multiple eleventh scanning control signal lines; wherein, one row of sub-pixels corresponds to one ninth scanning control signal line, one tenth scanning control signal line, and one eleventh scanning control signal line.
  • each light-emitting control signal line is coupled to the light-emitting control signal terminal EM of the pixel circuit in the corresponding row of sub-pixels.
  • Each ninth scanning control signal line is coupled to the third control signal terminal CS3 of the pixel circuit in the corresponding row of sub-pixels, each tenth scanning control signal line is coupled to the second control signal terminal CS2 of the pixel circuit in the corresponding row of sub-pixels, and each eleventh scanning control signal line is coupled to the first control signal terminal CS1 of the pixel circuit in the corresponding row of sub-pixels.
  • the driving control circuit includes: a light-emitting scanning circuit SRE, the light-emitting scanning circuit SRE includes a plurality of light-emitting scanning shift register units arranged in sequence; wherein, a light-emitting control signal line coupled to a row of sub-pixels is coupled to a corresponding light-emitting scanning shift register unit.
  • the driving control circuit includes: a seventh scanning control circuit SRG7, the seventh scanning control circuit SRG7 includes a plurality of seventh scanning control shift register units arranged in sequence; wherein, in every two adjacent rows of sub-pixels, the ninth scanning control signal line coupled to the next row of sub-pixels and the tenth scanning control signal line coupled to the previous row of sub-pixels are coupled to the same seventh scanning control shift register unit, and the tenth scanning control signal line coupled to the next row of sub-pixels and the eleventh scanning control signal line coupled to the previous row of sub-pixels are coupled to the same seventh scanning control shift register unit.
  • a light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE and two adjacent seventh scanning control shift register units SRGA7(N-2) to SRGA7(N) in the seventh scanning control circuit SRG7 are illustrated.
  • the Nth light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE is coupled to the light-emitting control signal line EML(N) corresponding to the Nth row of sub-pixels.
  • the N-2th seventh scanning control shift register unit SRGA7(N-2) in the seventh scanning control circuit SRG7 is coupled to the ninth scanning control signal line GA9L(N) corresponding to the Nth row of sub-pixels
  • the N-1th seventh scanning control shift register unit SRGA7(N-1) is coupled to the tenth scanning control signal line GA10L(N) corresponding to the Nth row of sub-pixels
  • the Nth seventh scanning control shift register unit SRGA7(N) is coupled to the eleventh scanning control signal line GA11L(N) corresponding to the Nth row of sub-pixels.
  • inventions of the present invention provide some further structural schematic diagrams of pixel circuits, as shown in Figure 15, which are modified from the implementation methods in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.
  • the plurality of control signal lines include a plurality of light-emitting control signal lines, a plurality of sixth scanning control signal lines, a plurality of seventh scanning control signal lines, a plurality of eighth scanning control signal lines, and a plurality of twelfth scanning control signal lines; wherein, one row of sub-pixels corresponds to one light-emitting control signal line, one row of sub-pixels corresponds to one sixth scanning control signal line, one seventh scanning control signal line, and one eighth scanning control signal line, and one row of sub-pixels corresponds to one twelfth scanning control signal line.
  • each light-emitting control signal line is coupled to the light-emitting control signal terminal EM of the pixel circuit in the corresponding row of sub-pixels.
  • Each sixth scanning control signal line is coupled to the third control signal terminal CS3 of the pixel circuit in the corresponding row of sub-pixels, each seventh scanning control signal line is coupled to the second control signal terminal CS2 of the pixel circuit in the corresponding row of sub-pixels, and each eighth scanning control signal line is coupled to the first control signal terminal CS1 of the pixel circuit in the corresponding row of sub-pixels.
  • Each twelfth scanning control signal line is coupled to the fourth control signal terminal CS4 of the pixel circuit in the corresponding row of sub-pixels.
  • the drive control circuit includes: a fifth scanning control circuit SRG5 and a sixth scanning control circuit SRG6.
  • the fifth scanning control circuit SRG5 includes a plurality of fifth scanning control shift register units arranged in sequence; wherein, in each two adjacent rows of sub-pixels, the sixth scanning control signal line coupled to the next row of sub-pixels and the seventh scanning control signal line coupled to the previous row of sub-pixels are coupled to the same fifth scanning control shift register unit.
  • the sixth scanning control circuit SRG6 includes a plurality of sixth scanning control shift register units arranged in sequence; wherein, the eighth scanning control signal line coupled to a row of sub-pixels is coupled to a sixth scanning control shift register unit.
  • the driving control circuit includes: an eighth scanning control circuit SRG8, the eighth scanning control circuit SRG8 includes a plurality of eighth scanning control shift register units arranged in sequence; wherein, the twelfth scanning control signal line coupled to a row of sub-pixels is coupled to a corresponding eighth scanning control shift register unit.
  • a light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE a sixth scanning control shift register unit SRGA6(N) in the sixth scanning control circuit SRG6, two adjacent fifth scanning control shift register units SRGA5(N-1) to SRGA5(N) in the fifth scanning control circuit SRG5, and an eighth scanning control shift register unit SRGA8(N) in the eighth scanning control circuit SRG8 are illustrated, wherein the Nth light-emitting scanning shift register unit SREM(N) in the light-emitting scanning circuit SRE is coupled to the light-emitting control signal line EML(N) corresponding to the Nth row of sub-pixels.
  • the Nth sixth scanning control shift register unit SRGA6(N) in the sixth scanning control circuit SRG6 is coupled to the eighth scanning control signal line CS8L(N) corresponding to the Nth row of sub-pixels.
  • the N-1th fifth scanning control shift register unit SRGA5(N-1) in the fifth scanning control circuit SRG5 is coupled to the sixth scanning control signal line GA6L(N) corresponding to the N-th row of sub-pixels, and the N-th fifth scanning control shift register unit SRGA5(N) is coupled to the seventh scanning control signal line GA7L(N) corresponding to the N-th row of sub-pixels.
  • the N-th eighth scanning control shift register unit SRGA8(N) in the eighth scanning control circuit SRG8 is coupled to the twelfth scanning control signal line CS12L(N) corresponding to the N-th row of sub-pixels.
  • the embodiment of the present invention further provides a display device, including the display panel provided by the embodiment of the present invention.
  • the principle of solving the problem by the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device should be understood by ordinary technicians in the field, and will not be elaborated here, nor should they be used as limitations to the present disclosure.

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Abstract

一种像素电路、驱动方法、显示面板及显示装置，其中，像素电路包括：发光器件（L）；驱动晶体管（M0），与发光器件（L）耦接，被配置为根据数据电压产生驱动发光器件（L）的工作电流；第一控制电路（10），与驱动晶体管（M0）的栅极耦接，被配置为基于漏电调节信号端（VS）的信号，降低驱动晶体管（M0）的栅极漏电；第二控制电路（20），与驱动晶体管（M0）的第一设定极耦接，被配置为在驱动发光器件（L）发光之前，对驱动晶体管（M0）的第一设定极进行初始化；其中，第一设定极为驱动晶体管（M0）的第一极和/或第二极；第三控制电路（30），与驱动晶体管（M0）耦接，被配置为对驱动晶体管（M0）的栅极进行复位，控制数据电压输入驱动晶体管（M0）的栅极以及控制驱动晶体管（M0）产生工作电流，驱动发光器件（L）发光。

Description

像素电路、驱动方法、显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及像素电路、驱动方法、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。一般电致发光显示装置中采用像素电路来驱动电致发光二极管发光。
发明内容
本公开实施例提供的像素电路，包括：
发光器件；
驱动晶体管，与所述发光器件耦接，被配置为根据数据电压产生驱动所述发光器件的工作电流；
第一控制电路，与所述驱动晶体管的栅极耦接，被配置为基于漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；
第二控制电路，与所述驱动晶体管的第一设定极耦接，被配置为在驱动所述发光器件发光之前，对所述驱动晶体管的第一设定极进行初始化；其中，所述第一设定极为所述驱动晶体管的第一极和/或第二极；
第三控制电路，与所述驱动晶体管耦接，被配置为对所述驱动晶体管的栅极进行复位，控制所述数据电压输入所述驱动晶体管的栅极以及控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
在一些可能的实施方式中，所述第一控制电路包括：第一晶体管和第二 晶体管；
所述第一晶体管的栅极与所述驱动晶体管的栅极耦接，所述第一晶体管的第一极浮接，所述第一晶体管的第二极与所述漏电调节信号端耦接；
所述第二晶体管的栅极与所述驱动晶体管的栅极耦接，所述第二晶体管的第一极浮接，所述第二晶体管的第二极与所述漏电调节信号端耦接。
在一些可能的实施方式中，述第一控制电路包括：稳压电容；
所述稳压电容的第一电极与所述驱动晶体管的栅极耦接，所述稳压电容的第二电极与所述漏电调节信号端耦接。
在一些可能的实施方式中，在同一个显示帧中，在对所述驱动晶体管的栅极进行复位时，所述漏电调节信号端的信号的电压为第一电压，在所述数据电压输入所述驱动晶体管的栅极时，所述漏电调节信号端的信号的电压为第二电压；
所述第二电压不小于所述第一电压。
在一些可能的实施方式中，在不同显示帧中，所述第一电压相同。
在一些可能的实施方式中，在不同显示帧中，所述第二电压大于第三电压；
所述第三电压为Vda-Vth；Vda代表所述数据电压，Vth代表所述驱动晶体管的阈值电压。
在一些可能的实施方式中，在不同显示帧中，所述第二电压相同；
或者，在不同显示帧中，所述第二电压随着所述第三电压的增加而增加。
在一些可能的实施方式中，所述第二控制电路进一步被配置为响应于第一控制信号端的信号，在所述输入数据电压之后将第一初始化信号端的信号提供给所述第一设定极。
在一些可能的实施方式中，所述第一初始化信号端为高电平或低电平。
在一些可能的实施方式中，在所述第一初始化信号端为高电平时，所述第一初始化信号端与第一电源端为同一信号端。
在一些可能的实施方式中，所述第二控制电路包括：第三晶体管；
所述第三晶体管的栅极与所述第一控制信号端耦接，所述第三晶体管的第一极与所述第一初始化信号端耦接，所述第三晶体管的第二极与所述第一设定极耦接。
在一些可能的实施方式中，所述第三控制电路包括：
数据写入电路，被配置为响应于第二控制信号端的信号，将数据信号端的数据电压输入所述驱动晶体管的第一极；
复位电路，被配置为响应于第三控制信号端的信号，将第二初始化信号端的信号输入所述驱动晶体管的第二设定极；所述第二设定极为所述驱动晶体管的栅极或第二极；
初始化电路，被配置为响应于第一控制信号端的信号，将第三初始化信号端的信号输入所述发光器件的第一电极；
阈值补偿电路，被配置为响应于第四控制信号端的信号，将所述驱动晶体管的栅极与其第二极导通；
发光控制电路，被配置为响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件的第一电极导通，控制所述驱动晶体管产生的工作电流输入所述发光器件。
在一些可能的实施方式中，所述数据写入电路包括第四晶体管，所述第四晶体管的栅极与所述第二控制信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述复位电路包括第五晶体管，所述第五晶体管的栅极与所述第三控制信号端耦接，所述第五晶体管的第一极与所述第二初始化信号端耦接，所述第五晶体管的第二极与所述驱动晶体管的第二设定极耦接；
所述初始化电路包括第六晶体管，所述第六晶体管的栅极与所述第一控制信号端耦接，所述第六晶体管的第一极与所述第三初始化信号端耦接，所述第六晶体管的第二极与所述发光器件的第一电极耦接；
所述阈值补偿电路包括第七晶体管和存储电容，所述第七晶体管的栅极与所述第四控制信号端耦接，所述第七晶体管的第一极与所述驱动晶体管的栅极耦接，所述第七晶体管的第二极与所述驱动晶体管的第二极耦接，所述存储电容的第一电极与所述第一电源端耦接，所述存储电容的第二电极与所述驱动晶体管的栅极耦接；
所述发光控制电路包括第八晶体管和第九晶体管，所述第八晶体管的栅极与所述发光控制信号端耦接，所述第八晶体管的第一极与所述第一电源端耦接，所述第八晶体管的第二极与所述驱动晶体管的第一极耦接，所述第九晶体管的栅极与所述发光控制信号端耦接，所述第九晶体管的第一极与所述驱动晶体管的第二极耦接，所述第九晶体管的第二极与所述发光器件的第一电极耦接。
在一些可能的实施方式中，所述第二控制信号端与所述第四控制信号端为同一信号端或相互独立的信号端。
在一些可能的实施方式中，在同一显示帧中，所述第一控制信号端的有效电平晚于所述第二控制信号端的有效电平。
本公开实施例还提供了用于上述的像素电路的驱动方法，包括：
复位阶段，第三控制电路对所述驱动晶体管的栅极进行复位；
数据写入阶段，第三控制电路控制数据电压输入所述驱动晶体管的栅极；
初始化阶段，第二控制电路对所述驱动晶体管的第一设定极进行初始化；
发光阶段，第一控制电路基于漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；第三控制电路控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
在一些可能的实施方式中，所述复位阶段包括：复位电路响应于第三控制信号端的信号，将第二初始化信号端的信号输入所述驱动晶体管的第二设定极；
所述初始化阶段还包括：初始化电路响应于第一控制信号端的信号，将所述第三初始化信号端的信号输入所述发光器件的第一电极。
在一些可能的实施方式中，所述数据写入阶段包括：数据写入电路响应于第二控制信号端的信号，将数据信号端的数据电压输入所述驱动晶体管的第一极；阈值补偿电路响应于第二控制信号端的信号，将所述驱动晶体管的栅极与其第二极导通；
所述发光阶段包括：发光控制电路响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件的第一电极导通，控制所述驱动晶体管产生的工作电流输入所述发光器件。
本公开实施例还提供了显示面板，包括：
多个子像素，所述多个子像素中的每一个所述子像素包括上述的像素电路；
多条控制信号线，所述多条控制信号线中的至少一条控制信号线与一行子像素中的像素电路耦接；
驱动控制电路，所述驱动控制电路分别与所述多条控制信号线耦接。
在一些可能的实施方式中，所述多条控制信号线包括多条发光控制信号线；其中，一行子像素与一条发光控制信号线对应，且每一条所述发光控制信号线与对应行子像素中的像素电路的发光控制信号端耦接；
所述驱动控制电路包括：发光扫描电路，所述发光扫描电路包括依次设置的多个发光扫描移位寄存器单元；其中，一行子像素耦接的所述发光控制信号线与一个所述发光扫描移位寄存器单元对应耦接。
在一些可能的实施方式中，所述多条控制信号线包括多条第一扫描信号线；其中，一行子像素与两条第一扫描信号线对应，且所述两条第一扫描信号线中的第一条第一扫描信号线与对应行子像素中的像素电路的第三控制信号端耦接，第二条第一扫描信号线与对应行子像素中的像素电路的第四控制信号端耦接；
所述驱动控制电路包括：第一扫描控制电路，所述第一扫描控制电路包括依次设置的多个第一扫描控制移位寄存器单元；其中，每相邻两行子像素 中，下一行子像素耦接的第一条第一扫描控制信号线和上一行子像素耦接的第二条第一扫描控制信号线与同一个所述第一扫描控制移位寄存器单元对应耦接。
在一些可能的实施方式中，所述多条控制信号线还包括多条第二扫描控制信号线和多条第三扫描控制信号线；一行子像素与一条第二扫描控制信号线和一条第三扫描控制信号线对应，每一条所述第二扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第三扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
所述驱动控制电路包括：第二扫描控制电路和第三扫描控制电路；
所述第二扫描控制电路包括依次设置的多个第二扫描控制移位寄存器单元；其中，一行子像素耦接的所述第二扫描控制信号线与一个所述第二扫描控制移位寄存器单元对应耦接；
所述第三扫描控制电路包括依次设置的多个第三扫描控制移位寄存器单元；其中，一行子像素耦接的所述第三扫描控制信号线与一个所述第三扫描控制移位寄存器单元对应耦接。
在一些可能的实施方式中，所述多条控制信号线还包括多条第四扫描控制信号线和多条第五扫描控制信号线；一行子像素与一条第四扫描控制信号线和一条第五扫描控制信号线对应，每一条所述第四扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第五扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
所述驱动控制电路包括：第四扫描控制电路，所述第四扫描控制电路包括依次设置的多个第四扫描控制移位寄存器单元；其中，每相邻三行子像素中，第三行子像素耦接的第五扫描控制信号线和第一行子像素耦接的第四扫描控制信号线与同一个所述第四扫描控制移位寄存器单元对应耦接。
在一些可能的实施方式中，所述多条控制信号线还包括多条第六扫描控制信号线、多条第七扫描控制信号线以及多条第八扫描控制信号线；一行子像素与一条第六扫描控制信号线、一条第七扫描控制信号线以及一条第八扫 描控制信号线对应，每一条所述第六扫描控制信号线与对应行子像素中的像素电路的第三控制信号端耦接，每一条所述第七扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第八扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
所述驱动控制电路包括：第五扫描控制电路和第六扫描控制电路；
所述第五扫描控制电路包括依次设置的多个第五扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第六扫描控制信号线和上一行子像素耦接的第七扫描控制信号线与同一个所述第五扫描控制移位寄存器单元对应耦接；
所述第六扫描控制电路包括依次设置的多个第六扫描控制移位寄存器单元；其中，一行子像素耦接的所述第八扫描控制信号线与一个所述第六扫描控制移位寄存器单元对应耦接。
在一些可能的实施方式中，所述多条控制信号线还包括多条第九扫描控制信号线、多条第十扫描控制信号线以及多条第十一扫描控制信号线；一行子像素与一条第九扫描控制信号线、一条第十扫描控制信号线以及一条第十一扫描控制信号线对应，每一条所述第九扫描控制信号线与对应行子像素中的像素电路的第三控制信号端耦接，每一条所述第十扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第十一扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
所述驱动控制电路包括：第七扫描控制电路，所述第七扫描控制电路包括依次设置的多个第七扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第九扫描控制信号线和上一行子像素耦接的第十扫描控制信号线与同一个所述第七扫描控制移位寄存器单元对应耦接，且下一行子像素耦接的第十扫描控制信号线和上一行子像素耦接的第十一扫描控制信号线与同一个所述第七扫描控制移位寄存器单元对应耦接。
在一些可能的实施方式中，所述多条控制信号线还包括多条第十二扫描控制信号线；一行子像素与一条第十二扫描控制信号线对应，每一条所述第 十二扫描控制信号线与对应行子像素中的像素电路的第四控制信号端耦接；
所述驱动控制电路包括：第八扫描控制电路，所述第八扫描控制电路包括依次设置的多个第八扫描控制移位寄存器单元；其中，一行子像素耦接的所述第十二扫描控制信号线与一个所述第八扫描控制移位寄存器单元对应耦接。
本公开实施例还提供了显示装置，包括上述的显示面板。
附图说明
图1为本公开实施例提供的像素电路的一些结构示意图；
图2为本公开实施例提供的像素电路的又一些结构示意图；
图3为本公开实施例提供的像素电路的又一些结构示意图；
图4a为本公开实施例提供的一些信号时序图；
图4b为本公开实施例提供的另一些信号时序图；
图5为本公开实施例提供的驱动方法的流程图；
图6为本公开实施例提供的像素电路的又一些结构示意图；
图7为本公开实施例提供的又一些信号时序图；
图8为本公开实施例提供的像素电路的又一些结构示意图；
图9为本公开实施例提供的又一些信号时序图；
图10a为本公开实施例提供的像素电路的又一些结构示意图；
图10b为本公开实施例提供的像素电路的又一些结构示意图；
图11为本公开实施例提供的显示面板的一些结构示意图；
图12为本公开实施例提供的显示面板的又一些结构示意图；
图13为本公开实施例提供的显示面板的又一些结构示意图；
图14为本公开实施例提供的显示面板的又一些结构示意图；
图15为本公开实施例提供的显示面板的又一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的耦接，而是可以包括电性的耦接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本发明内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在本公开一些实施例中，本公开实施例提供的显示装置可以包括显示面板。显示面板可以包括衬底基板。其中，衬底基板可以包括显示区域和非显示区域(即衬底基板中除显示区域包围区域之外的区域)。其中，显示区域可以包括多个阵列排布的像素单元。示例性地，每个像素单元包括同一种颜色的子像素或多种不同颜色的子像素。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。下面以像素单元包括红色子像素，绿色子像素以及蓝 色子像素为例进行说明。
在本公开一些实施例中，每一个子像素中可以包括像素电路，像素电路可以包括驱动晶体管M0和发光器件L，以控制发光器件L发光，从而使显示面板实现画面显示的功能。但是由于工艺、老化等原因会造成驱动晶体管M0的阈值电压Vth漂移，对产生的驱动电流造成影响，并且在高低灰阶显示时造成闪烁(Flicker)的问题。
本公开实施例提供了一些像素电路，如图1所示，可以包括：发光器件L、驱动晶体管M0、第一控制电路10、第二控制电路20以及第三控制电路30。其中，驱动晶体管M0与发光器件L耦接，第一控制电路10与驱动晶体管M0的栅极耦接，第二控制电路20与驱动晶体管M0的第一设定极耦接，第三控制电路30与驱动晶体管M0耦接。并且，驱动晶体管M0被配置为根据数据电压产生驱动发光器件L的工作电流。第一控制电路10被配置为基于漏电调节信号端VS的信号，降低驱动晶体管M0的栅极漏电。第二控制电路20被配置为在驱动发光器件L发光之前，对驱动晶体管M0的第一设定极进行初始化。第三控制电路30被配置为对驱动晶体管M0的栅极进行复位，控制数据电压输入驱动晶体管M0的栅极以及控制驱动晶体管M0产生工作电流，驱动发光器件L发光。
本公开实施例提供的像素电路，通过设置第三控制电路30，可以控制数据电压输入驱动晶体管M0的栅极以及控制驱动晶体管M0产生工作电流，驱动发光器件L发光。通过设置与驱动晶体管M0的栅极耦接的第一控制电路10，可以基于漏电调节信号端VS的信号，降低驱动晶体管M0的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。以及通过设置第二控制电路20，可以在驱动发光器件L发光之前，对驱动晶体管M0的第一设定极进行初始化，改善驱动晶体管M0的迟滞效应，从而实现改善高灰阶显示时的闪烁(Flicker)问题。
本公开实施例提供的像素电路可以应用于不同刷新频率驱动的显示面板中。由于本公开实施例提供的像素电路可以兼容改善高低灰阶显示时的闪烁 (Flicker)问题，在不同刷新频率切换时，改善出现的闪烁等的问题，提高产品的显示效果。并且，为了降低功耗，本公开实施例提供的像素电路可以应用于较低刷新频率(例如，1Hz、30Hz等)驱动的情况下。以及，为了提高显示效果，本公开实施例提供的像素电路可以应用于较高刷新频率(例如，60Hz、90Hz、120Hz、240Hz等)驱动的情况下。
在本公开一些实施例中，如图1所示，第一设定极可以为驱动晶体管M0的第一极。则第二控制电路20与驱动晶体管M0的第一极耦接，且第二控制电路20进一步被配置为在输入数据电压之后，对驱动晶体管M0的第一极进行初始化。
示例性地，如图2所示，第二控制电路20进一步被配置为响应于第一控制信号端CS1的信号，将第一初始化信号端VINIT1的信号提供给第一设定极。例如，第一设定极可以为驱动晶体管M0的第一极，则第二控制电路20被配置为响应于第一控制信号端CS1的信号，在输入数据电压之后将第一初始化信号端VINIT1的信号提供给驱动晶体管M0的第一极。
在本公开一些实施例中，如图2所示，第三控制电路30可以包括：
数据写入电路31，被配置为响应于第二控制信号端CS2的信号，将数据信号端DA的数据电压输入驱动晶体管M0的第一极；
复位电路32，被配置为响应于第三控制信号端CS3的信号，将第二初始化信号端VINIT2的信号输入驱动晶体管M0的第二设定极；
初始化电路33，被配置为响应于第一控制信号端CS1的信号，将第三初始化信号端VINIT3的信号输入发光器件L的第一电极；
阈值补偿电路34，被配置为响应于第四控制信号端CS4的信号，将驱动晶体管M0的栅极与其第二极导通，以及稳定第一电源端VDD和驱动晶体管M0的栅极之间的电压差稳定；
发光控制电路35，被配置为响应于发光控制信号端EM的信号，将驱动晶体管M0的第一极与第一电源端VDD导通，以及将驱动晶体管M0的第二极与发光器件L的第一电极导通，控制驱动晶体管M0产生的工作电流输入 发光器件L。
示例性地，第二设定极可以设置为驱动晶体管M0的栅极。
下面结合具体实施例，对本发明进行详细说明。需要说明的是，本实施例中是为了更好的解释本发明，但不限制本发明。
在本公开一些实施例中，如图3所示，发光器件L的第一电极可以与发光控制电路35耦接。发光器件L的第二电极可以与第二电源端VSSVSS耦接。并且，发光器件L的第一电极可以为其阳极，第二电极为其阴极。示例性地，发光器件L可以为电致发光二极管。例如，发光器件L可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。在实际应用中，可以根据实际应用环境来设计确定发光器件L的具体结构，在此不作限定。
在本公开一些实施例中，第一电源端VDD可以被配置为加载恒定的第一电源电压，并且第一电源电压一般为正值。以及，第二电源端VSS可以加载恒定的第二电源电压，并且第二电源电压一般可以为接地电压或为负值。在实际应用中，第一电源电压和第二电源电压的具体数值可以根据实际应用环境来设计确定，在此不作限定。
在本公开一些实施例中，如图1至图3所示，驱动晶体管M0可以设置为P型晶体管；其中，驱动晶体管M0的第一极可以为其源极，驱动晶体管M0的第二极可以为其漏极，并且该驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的源极流向其漏极。当然，驱动晶体管M0也可以设置为N型晶体管，在此不作限定。
在本公开一些实施例中，如图3所示，第一控制电路10包括：第一晶体管M1和第二晶体管M2。其中，第一晶体管M1的栅极与驱动晶体管M0的栅极耦接，第一晶体管M1的第一极浮接，第一晶体管M1的第二极与漏电调节信号端VS耦接。第二晶体管M2的栅极与驱动晶体管M0的栅极耦接，第二晶体管M2的第一极浮接，第二晶体管M2的第二极与漏电调节信号端VS 耦接。这样通过设置第一晶体管M1和第二晶体管M2，并使第一晶体管M1和第二晶体管M2均与漏电调节信号端VS连接，在漏电调节信号端VS加载电压VS时，可以改善驱动晶体管M0的栅极的漏电。
在一些示例中，如图4a所示，vs代表漏电调节信号端VS的信号。示例性地，在同一个显示帧中，在对驱动晶体管M0的栅极进行复位时，漏电调节信号端VS的信号vs的电压为第一电压Vvs1，在数据电压输入驱动晶体管M0的栅极时，漏电调节信号端VS的信号vs的电压为第二电压Vvs2。可以使第二电压Vvs2等于第一电压Vvs1。这样可以使漏电调节信号端VS的信号vs的电压在一个显示帧中是固定电压。
示例性地，在不同显示帧中，可以使第一电压Vvs1相同，从而可以不用频繁的调整第一电压Vvs1，降低功耗。
示例性地，在不同显示帧中，可以使第二电压Vvs2大于第三电压Vvs3。其中，第三电压Vvs3为Vda-Vth，Vda代表所数据电压，Vth代表驱动晶体管的阈值电压。例如，Vda-Vth大约为0～1V，则第二电压Vvs2可以设置为2V。可选地，Vda可为较大灰阶或最大灰阶对应的数据电压。
示例性地，在不同显示帧中，可以使第二电压Vvs2相同，从而可以不用频繁的调整第二电压Vvs2，降低功耗。基于此，在不同显示帧中，可以使漏电调节信号端VS的信号vs的电压为固定电压，从而可以不用频繁的调整漏电调节信号端VS的信号vs的电压，降低功耗。
示例性地，在不同显示帧中，也可以使第二电压Vvs2随着第三电压Vvs3的增加而增加，从而可以随着第三电压Vvs3来调整第二电压Vvs2，进一步降低漏电。基于此，在不同显示帧中，可以使漏电调节信号端VS的信号vs的电压为交变电压，进一步降低漏电。
在又一些示例中，如图4b所示，vs代表漏电调节信号端VS的信号。示例性地，在同一个显示帧中，在对驱动晶体管M0的栅极进行复位时，漏电调节信号端VS的信号vs的电压为第一电压Vvs1，在数据电压输入驱动晶体管M0的栅极时，漏电调节信号端VS的信号vs的电压为第二电压Vvs2。可以 使第二电压Vvs2大于第一电压Vvs1。这样可以使漏电调节信号端VS的信号vs的电压在一个显示帧中是交变电压。
示例性地，在不同显示帧中，可以使第一电压Vvs1相同，从而可以不用频繁的调整第一电压Vvs1，降低功耗。
示例性地，在不同显示帧中，可以使第二电压Vvs2大于第三电压Vvs3。其中，第三电压Vvs3为Vda-Vth，Vda代表所数据电压，Vth代表驱动晶体管的阈值电压。例如，Vda-Vth大约为0～1V，则第二电压Vvs2可以设置为2V。可选地，Vda可为较大灰阶或最大灰阶对应的数据电压。
示例性，在不同显示帧中，可以使第二电压Vvs2相同，从而可以不用频繁的调整第二电压Vvs2，降低功耗。
示例性地，在不同显示帧中，也可以使第二电压Vvs2随着第三电压Vvs3的增加而增加，从而可以随着第三电压Vvs3来调整第二电压Vvs2，进一步降低漏电。
示例性地，第一晶体管M1和第二晶体管M2可以设置为P型晶体管。当然，在实际应用中，第一晶体管和第二晶体管也可以设置为N型晶体管，在此不作限定。
在本公开一些实施例中，如图3所示，第二控制电路20包括：第三晶体管M3。其中，第三晶体管M3的栅极与第一控制信号端CS1耦接，第三晶体管M3的第一极与第一初始化信号端VINIT1耦接，第三晶体管M3的第二极与第一设定极耦接。
示例性地，第三晶体管M3在第一控制信号端CS1的第一控制信号的有效电平的控制下导通，在第一控制信号的无效电平的控制下截止。可选地，第三晶体管M3可以设置为P型晶体管，则第一控制信号的有效电平可以为低电平，第一控制信号的无效电平可以为高电平。或者，第三晶体管M3也可以设置为N型晶体管，则第一控制信号的有效电平可以为高电平，第一控制信号的无效电平可以为低电平。
在一些示例中，第一初始化信号端的信号可以设置为高电平。这样在将 第一初始化信号端的信号输入到驱动晶体管的第一极后，可以使驱动晶体管基于其栅极和第一极的电压导通，从而不仅对驱动晶体管的第一极进行初始化，还会对驱动晶体管的第二极进行初始化，进一步改善驱动晶体管M0的迟滞效应，从而实现改善高灰阶显示时的闪烁(Flicker)问题。
可选地，第一初始化信号端与第一电源端为同一信号端，这样可以降低信号端的数量。当然，第一初始化信号端与第一电源端可以为相互独立的信号端，从而可以对第一初始化信号端加载的信号不受第一电源端影响。
在另一些示例中，第一初始化信号端的信号也可以设置为低电平。这样在将第一初始化信号端的信号输入到驱动晶体管的第一极后，对驱动晶体管的第一极进行初始化，以改善驱动晶体管M0的迟滞效应，从而实现改善高灰阶显示时的闪烁(Flicker)问题。
可选地，第一初始化信号端与第二电源端为同一信号端，这样可以降低信号端的数量。当然，第一初始化信号端与第二电源端可以为相互独立的信号端，从而可以对第一初始化信号端加载的信号不受第二电源端影响。
在本公开一些实施例中，如图3所示，数据写入电路31包括第四晶体管M4，第四晶体管M4的栅极与第二控制信号端CS2耦接，第四晶体管M4的第一极与数据信号端DA耦接，第四晶体管M4的第二极与驱动晶体管M0的第一极耦接。
示例性地，第四晶体管M4在第二控制信号端CS2的第二控制信号的有效电平的控制下导通，在第二控制信号的无效电平的控制下截止。可选地，第四晶体管M4可以设置为P型晶体管，则第二控制信号的有效电平可以为低电平，第二控制信号的无效电平可以为高电平。或者，第四晶体管M4也可以设置为N型晶体管，则第二控制信号的有效电平可以为高电平，第二控制信号的无效电平可以为低电平。
在本公开一些实施例中，如图3所示，复位电路32包括第五晶体管M5，第五晶体管M5的栅极与第三控制信号端CS3耦接，第五晶体管M5的第一极与第二初始化信号端VINIT2耦接，第五晶体管M5的第二极与驱动晶体管 M0的第二设定极耦接。
示例性地，第五晶体管M5在第三控制信号端CS3的第三控制信号的有效电平的控制下导通，在第三控制信号的无效电平的控制下截止。可选地，第五晶体管M5可以设置为P型晶体管，则第三控制信号的有效电平可以为低电平，第三控制信号的无效电平可以为高电平。或者，第五晶体管M5也可以设置为N型晶体管，则第三控制信号的有效电平可以为高电平，第三控制信号的无效电平可以为低电平。
在本公开一些实施例中，如图3所示，初始化电路33包括第六晶体管M6，第六晶体管M6的栅极与第一控制信号端CS1耦接，第六晶体管M6的第一极与第三初始化信号端VINIT3耦接，第六晶体管M6的第二极与发光器件L的第一电极耦接。
示例性地，第六晶体管M6在第一控制信号端CS1的第一控制信号的有效电平的控制下导通，在第一控制信号的无效电平的控制下截止。可选地，第六晶体管M6可以设置为P型晶体管，则第一控制信号的有效电平可以为低电平，第一控制信号的无效电平可以为高电平。或者，第六晶体管M6也可以设置为N型晶体管，则第一控制信号的有效电平可以为高电平，第一控制信号的无效电平可以为低电平。
在本公开一些实施例中，如图3所示，阈值补偿电路34包括第七晶体管M7和存储电容CST，第七晶体管M7的栅极与第四控制信号端CS4耦接，第七晶体管M7的第一极与驱动晶体管M0的栅极耦接，第七晶体管M7的第二极与驱动晶体管M0的第二极耦接，存储电容CST的第一电极与第一电源端VDD耦接，存储电容CST的第二电极与驱动晶体管M0的栅极耦接。
示例性地，第七晶体管M7在第四控制信号端CS4的第四控制信号的有效电平的控制下导通，在第四控制信号的无效电平的控制下截止。可选地，第七晶体管M7可以设置为P型晶体管，则第四控制信号的有效电平可以为低电平，第四控制信号的无效电平可以为高电平。或者，第七晶体管M7也可以设置为N型晶体管，则第四控制信号的有效电平可以为高电平，第四控制 信号的无效电平可以为低电平。
在本公开一些实施例中，如图3所示，发光控制电路35包括第八晶体管M8和第九晶体管M9，第八晶体管M8的栅极与发光控制信号端EM耦接，第八晶体管M8的第一极与第一电源端VDD耦接，第八晶体管M8的第二极与驱动晶体管M0的第一极耦接，第九晶体管M9的栅极与发光控制信号端EM耦接，第九晶体管M9的第一极与驱动晶体管M0的第二极耦接，第九晶体管M9的第二极与发光器件L的第一电极耦接。
示例性地，第八晶体管M8在发光控制信号端EM的发光控制信号的有效电平的控制下导通，在发光控制信号的无效电平的控制下截止。可选地，第八晶体管M8可以设置为P型晶体管，则发光控制信号的有效电平可以为低电平，发光控制信号的无效电平可以为高电平。或者，第八晶体管M8也可以设置为N型晶体管，则发光控制信号的有效电平可以为高电平，发光控制信号的无效电平可以为低电平。
示例性地，第九晶体管M9在发光控制信号端EM的发光控制信号的有效电平的控制下导通，在发光控制信号的无效电平的控制下截止。可选地，第九晶体管M9可以设置为P型晶体管，则发光控制信号的有效电平可以为低电平，发光控制信号的无效电平可以为高电平。或者，第九晶体管M9也可以设置为N型晶体管，则发光控制信号的有效电平可以为高电平，发光控制信号的无效电平可以为低电平。
示例性地，可以使第二初始化信号端VINIT2与第三初始化信号端VINIT3为同一信号端。当然，也可以使第二初始化信号端VINIT2与第三初始化信号端VINIT3为相互独立的信号端，这样可以使第二初始化信号端VINIT2与第三初始化信号端VINIT3分别加载相同或不同的电压。
示例性地，可以使第二初始化信号端VINIT2与第一初始化信号端VINIT1为同一信号端。当然，也可以使第二初始化信号端VINIT2与第一初始化信号端VINIT1为相互独立的信号端，这样可以使第二初始化信号端VINIT2与第一初始化信号端VINIT1分别加载相同或不同的电压。
示例性地，可以使第二控制信号端CS2与第四控制信号端CS4为相互独立的信号端，则可以对第二控制信号端CS2与第四控制信号端CS4加载不同的信号。
在具体实施中，可以根据晶体管的类型以及其栅极的信号，将晶体管的第一极作为其源极，第二极作为其漏极；或者，反之，将晶体管的第一极作为其漏极，第二极作为其源极，这可以根据实际应用环境来设计确定，具体在此不做具体区分。
以上仅是举例说明本公开实施例提供的像素电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，具体在此不作限定。
下面以上述各晶体管为P型为例进行说明。示例性地，图3所示的像素电路对应的信号时序图，如图4a所示。在同一显示帧中，第一控制信号端CS1的有效电平晚于第二控制信号端CS2的有效电平。这样在同一显示帧中，可以使第三晶体管M3的导通时刻晚于第四晶体管M4的导通时刻，也可以说第四晶体管M4的导通时刻早于第三晶体管M3的导通时刻。
如图5所示，本公开实施例提供的像素电路的驱动方法，可以包括如下步骤：
S100、复位阶段，第三控制电路对所述驱动晶体管的栅极进行复位；
S200、数据写入阶段，第三控制电路控制数据电压输入驱动晶体管的栅极；
S300、初始化阶段，第二控制电路对驱动晶体管的第一设定极进行初始化；
S400、发光阶段，第一控制电路基于漏电调节信号端的信号，降低驱动晶体管的栅极漏电；第三控制电路控制驱动晶体管产生所述工作电流，驱动发光器件发光。
示例性地，复位阶段包括，复位电路32响应于第三控制信号端CS3的信 号，将第二初始化信号端VINIT2的信号输入驱动晶体管M0的第二设定极。示例性地，第二设定极为驱动晶体管M0的栅极。
可选地，复位阶段还可以包括：阈值补偿电路34响应于第四控制信号端CS4的信号，将驱动晶体管M0的栅极与其第二极导通。
示例性地，初始化阶段还包括：初始化电路33响应于第一控制信号端CS1的信号，将第二初始化信号端VINIT2的信号输入发光器件L的第一电极。
示例性地，数据写入阶段包括：数据写入电路31响应于第二控制信号端CS2的信号，将数据信号端DA的数据电压输入驱动晶体管M0的第一极；阈值补偿电路34响应于第二控制信号端CS2的信号，将驱动晶体管M0的栅极与其第二极导通。
示例性地，发光阶段包括：发光控制电路35响应于发光控制信号端EM的信号，将驱动晶体管M0的第一极与第一电源端VDD导通，以及将驱动晶体管M0的第二极与发光器件L的第一电极导通，控制驱动晶体管M0产生的工作电流输入发光器件L。
在一些示例中，下面以图3所示的像素电路的结构为例，结合图4a与图4b所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，主要选取图4a所示的信号时序图中的复位阶段T1、数据写入阶段T2、初始化阶段T3以及发光阶段T4。其中，em代表加载到发光控制信号端EM的发光控制信号，vc1代表第一控制信号端CS1的第一控制信号，vc2代表第二控制信号端CS2的第二控制信号，vc3代表第三控制信号端CS3的第三控制信号，vc4代表第四控制信号端CS4的第四控制信号。
在复位阶段T1中，首先，第五晶体管M5在第三控制信号cs3的低电平的控制下导通，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的栅极， 对驱动晶体管M0的栅极进行复位。
之后，第五晶体管M5在第三控制信号cs3的低电平的控制下导通，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的低电平的控制下导通，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行复位。并且，导通的第七晶体管M7将驱动晶体管M0的栅极与其第二极导通，将第二初始化信号端VINIT2的信号也提供给驱动晶体管M0的第二极，对驱动晶体管M0的第二极进行复位。
在数据写入阶段T2，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的低电平的控制下导通，第七晶体管M7在第四控制信号cs4的低电平的控制下导通，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第四晶体管M4将数据信号端DA的数据电压Vda输入到驱动晶体管M0的第一极。导通的第七晶体管M7将驱动晶体管M0的栅极与其第二极导通，使驱动晶体管M0形成二极管连接方式，则可以通过数据电压Vda对驱动晶体管M0的栅极进行充电，使驱动晶体管M0的栅极的电压变为Vda-Vth。其中，Vth代表驱动晶体管M0的阈值电压。
在初始化阶段T3，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的低电平的控制下导通，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第三晶体管 M3将第一初始化信号端VINIT1的信号提供给驱动晶体管M0的第一极，对驱动晶体管M0的第一极进行初始化。导通的第六晶体管M6将第三初始化信号端VINIT3的信号提供给发光器件L的第一电极，对发光器件L的第一电极进行初始化。
在发光阶段T4，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的低电平的控制下导通。导通的第八晶体管M8将第一电源端VDD与驱动晶体管M0的第一极导通，以使驱动晶体管M0的第一极的电压为第一电源电压Vdd。驱动晶体管M0的栅极的电压为Vda-Vth，则驱动晶体管M0产生驱动发光器件L发光的工作电流为Ids＝K[Vdd-(Vda-Vth)-Vth] 2＝K[Vdd-Vda] 2。因此，驱动发光器件L发光的工作电流与驱动晶体管M0的阈值电压Vth无关。并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管M0的栅极漏电，可以进一步保持驱动晶体管M0的栅极电压的稳定。
综上，通过第一晶体管M1和第二晶体管M2，可以基于漏电调节信号端VS的信号，降低驱动晶体管M0的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。以及通过第三晶体管M3，可以在输入数据电压之后且在驱动发光器件L发光之前，对驱动晶体管M0的第一极进行初始化，改善驱动晶体管M0的迟滞效应，从而实现改善高灰阶显示时的闪烁(Flicker)问题。因此，本公开实施例提供的像素电路可以兼容改善高低灰阶显示时的闪烁(Flicker)问题。
并且，本公开实施例提供的上述像素电路，在数据写入阶段T2和初始化阶段T3之间具有缓冲阶段T5，以及在初始化阶段T3和发光阶段T4之间具有缓冲阶段T6，通过设置缓冲阶段T5和T6，可以使像素电路中的信号稳定后再进入下一个阶段，进一步提高像素电路的稳定性。
本发明实施例提供了像素电路的另一些结构示意图，如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开另一些实施例中，如图6所示，第二设定极也可以设置为驱动晶体管M0的第二极。则，复位电路32被配置为响应于第三控制信号端CS3的信号，将第二初始化信号端VINIT2的信号输入驱动晶体管M0的第二极。并且，第五晶体管M5的第二极与驱动晶体管M0的第二极耦接。
在本公开一些实施例中，第一控制信号端CS1、第二控制信号端CS2、第三控制信号端CS3以及第四控制信号端CS4为相互独立的信号端，以分别加载不同的信号。
在本公开一些实施例中，如图6所示，第一设定极可以为驱动晶体管M0的第一极。则第二控制电路20与驱动晶体管M0的第一极耦接，且第二控制电路20进一步被配置为在输入数据电压之后，对驱动晶体管M0的第一极进行初始化。
在一些示例中，图6所示的像素电路对应的信号时序图，可以如图4a和图4b所示。本公开实施例提供的像素电路的驱动过程如下：
在复位阶段T1中，首先，第五晶体管M5在第三控制信号cs3的低电平的控制下导通，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的第二极，对驱动晶体管M0的第二极进行复位。
之后，第五晶体管M5在第三控制信号cs3的低电平的控制下导通，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的低电平的控制下导通，第八晶体管M8和第九晶体管M9 在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的第二极，对驱动晶体管M0的第二极进行复位。并且，导通的第七晶体管M7将驱动晶体管M0的栅极与其第二极导通，将第二初始化信号端VINIT2的信号也提供给驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行复位。
在数据写入阶段T2、初始化阶段T3以及发光阶段T4中的工作过程，可以参照上述描述，在此不作赘述。
在另一些示例中，图6所示的像素电路对应的信号时序图，也可以如图7所示。下面以图6所示的像素电路的结构为例，结合图7所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，主要选取图7所示的信号时序图中的复位阶段T1、数据写入阶段T2、初始化阶段T3以及发光阶段T4。其中，em代表加载到发光控制信号端EM的发光控制信号，vc1代表第一控制信号端CS1的第一控制信号，vc2代表第二控制信号端CS2的第二控制信号，vc3代表第三控制信号端CS3的第三控制信号，vc4代表第四控制信号端CS4的第四控制信号。
在复位阶段T1中，首先，第五晶体管M5在第三控制信号cs3的低电平的控制下导通，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4在第二控制信号cs2的高电平的控制下截止，第七晶体管M7在第四控制信号cs4的低电平的控制下导通，第八晶体管M8和第九晶体管M9在发光控制信号的高电平的控制下截止。导通的第五晶体管M5将第二初始化信号端VINIT2的信号提供给驱动晶体管M0的第二极，对驱动晶体管M0的第二极进行复位。导通的第七晶体管M7将驱动晶体管M0的栅极与其第二极导通，对驱动晶体管M0的栅极进行复位。
在数据写入阶段T2，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的 控制下截止，第四晶体管M4在第二控制信号cs2的低电平的控制下导通，第七晶体管M7在第四控制信号cs4的低电平的控制下导通，第八晶体管M8和第九晶体管M9在发光控制信号的高电平的控制下截止。导通的第四晶体管M4将数据信号端DA的数据电压Vda输入到驱动晶体管M0的第一极。导通的第七晶体管M7将驱动晶体管M0的栅极与其第二极导通，使驱动晶体管M0形成二极管连接方式，则可以通过数据电压Vda对驱动晶体管M0的栅极进行充电，使驱动晶体管M0的栅极的电压变为Vda-Vth。其中，Vth代表驱动晶体管M0的阈值电压。
在初始化阶段T3中的工作过程，可以参照上述描述，在此不作赘述。
在发光阶段T4中的工作过程，可以参照上述描述，在此不作赘述。
本发明实施例提供了像素电路的又一些结构示意图，如图8所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开又一些实施例中，第二控制信号端CS2与第四控制信号端CS4为同一信号端，以降低信号端的数量，降低走线的数量。示例性地，如图8所示，第四晶体管M4的栅极和第七晶体管M7的栅极均与第二控制信号端CS2耦接。
在本公开又一些实施例中，第二初始化信号端VINIT2与第三初始化信号端VINIT3为同一信号端，以降低信号端的数量，降低走线的数量。示例性地，如图8所示，第五晶体管M5的第二极和第六晶体管M6的第二极均与第三初始化信号端VINIT3耦接。
在本公开一些实施例中，如图8所示，第一设定极可以为驱动晶体管M0的第一极。则第二控制电路20与驱动晶体管M0的第一极耦接，且第二控制电路20进一步被配置为在输入数据电压之后，对驱动晶体管M0的第一极进行初始化。
图8所示的像素电路对应的信号时序图，如图9所示。下面以图8所示的像素电路的结构为例，结合图9所示的信号时序图，对本公开实施例提供 的像素电路在一个显示帧内的工作过程作以描述。其中，主要选取图9所示的信号时序图中的复位阶段T1、数据写入阶段T2、初始化阶段T3以及发光阶段T4。其中，em代表加载到发光控制信号端EM的发光控制信号，vc1代表第一控制信号端CS1的第一控制信号，vc2代表第二控制信号端CS2的第二控制信号，vc3代表第三控制信号端CS3的第三控制信号。
在复位阶段T1中，第五晶体管M5在第三控制信号cs3的低电平的控制下导通，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4和第七晶体管M7在第二控制信号cs2的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第三初始化信号端VINIT3的信号提供给驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行复位。
在数据写入阶段T2，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4和第七晶体管M7在第二控制信号cs2的低电平的控制下导通，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第四晶体管M4将数据信号端DA的数据电压Vda输入到驱动晶体管M0的第一极。导通的第七晶体管M7将驱动晶体管M0的栅极与其第二极导通，使驱动晶体管M0形成二极管连接方式，则可以通过数据电压Vda对驱动晶体管M0的栅极进行充电，使驱动晶体管M0的栅极的电压变为Vda-Vth。其中，Vth代表驱动晶体管M0的阈值电压。
在初始化阶段T3，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的低电平的控制下导通，第四晶体管M4和第七晶体管M7在第二控制信号cs2的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第三晶体管M3将第一初始化信号端VINIT1的信号提供给驱动晶体管M0的第一极，对驱动晶体管M0的第一极进行初始化。导通的第六晶体管M6将第三初始化信号端VINIT3的信号提供给发光器件L的第 一电极，对发光器件L的第一电极进行初始化。
在发光阶段T4，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的高电平的控制下截止，第四晶体管M4和第七晶体管M7在第二控制信号cs2的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的低电平的控制下导通。导通的第八晶体管M8将第一电源端VDD与驱动晶体管M0的第一极导通，以使驱动晶体管M0的第一极的电压为第一电源电压Vdd。驱动晶体管M0的栅极的电压为Vda-Vth，则驱动晶体管M0产生驱动发光器件L发光的工作电流为Ids＝K[Vdd-(Vda-Vth)-Vth] 2＝K[Vdd-Vda] 2。因此，驱动发光器件L发光的工作电流与驱动晶体管M0的阈值电压Vth无关。并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管M0的栅极漏电，可以进一步保持驱动晶体管M0的栅极电压的稳定。
综上，通过第一晶体管M1和第二晶体管M2，可以基于漏电调节信号端VS的信号，降低驱动晶体管M0的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。以及通过第三晶体管M3，可以在输入数据电压之后且在驱动发光器件L发光之前，对驱动晶体管M0的第一极进行初始化，改善驱动晶体管M0的迟滞效应，从而实现改善高灰阶显示时的闪烁(Flicker)问题。因此，本公开实施例提供的像素电路可以兼容改善高低灰阶显示时的闪烁(Flicker)问题。
并且，本公开实施例提供的上述像素电路，在初始化阶段T3和发光阶段T4之间具有缓冲阶段T65，通过设置缓冲阶段T5，可以使像素电路中的信号稳定后再进入下一个阶段，进一步提高像素电路的稳定性。
本发明实施例提供了像素电路的又一些结构示意图，如图10a所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开又一些实施例中，第二控制信号端CS2与第四控制信号端CS4为同一信号端，以降低信号端的数量，降低走线的数量。示例性地，如图10a 所示，第四晶体管M4的栅极和第七晶体管M7的栅极均与第二控制信号端CS2耦接。
在本公开一些实施例中，如图10a所示，第一设定极可以为驱动晶体管M0的第二极。则第二控制电路20与驱动晶体管M0的第一极耦接，且第二控制电路20进一步被配置为在输入数据电压之后，对驱动晶体管M0的第二极进行初始化。
在本公开又一些实施例中，第二初始化信号端VINIT2与第三初始化信号端VINIT3为同一信号端，以降低信号端的数量，降低走线的数量。示例性地，如图10a所示，第五晶体管M5的第二极和第六晶体管M6的第二极均与第三初始化信号端VINIT3耦接。
图10a所示的像素电路对应的信号时序图，可以如图9所示。本公开实施例提供的像素电路的驱动过程如下：
在复位阶段T1中的工作过程，可以参照上述描述，在此不作赘述。
在数据写入阶段T2中的工作过程，可以参照上述描述，在此不作赘述。
在初始化阶段T3，第五晶体管M5在第三控制信号cs3的高电平的控制下截止，第三晶体管M3和第六晶体管M6在第一控制信号cs1的低电平的控制下导通，第四晶体管M4和第七晶体管M7在第二控制信号cs2的高电平的控制下截止，第八晶体管M8和第九晶体管M9在发光控制信号em的高电平的控制下截止。导通的第三晶体管M3将第一初始化信号端VINIT1的信号提供给驱动晶体管M0的第二极，对驱动晶体管M0的第二极进行初始化。导通的第六晶体管M6将第三初始化信号端VINIT3的信号提供给发光器件L的第一电极，对发光器件L的第一电极进行初始化。
在发光阶段T4中的工作过程，可以参照上述描述，在此不作赘述。
本发明实施例提供了像素电路的又一些结构示意图，如图10b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开又一些实施例中，如图10b所示，第一控制电路10也可以包括： 稳压电容CFT，其中，稳压电容CFT的第一电极与驱动晶体管M0的栅极耦接，稳压电容CFT的第二电极与漏电调节信号端VS耦接。这样，通过稳压电容CFT，可以基于漏电调节信号端VS的信号，降低驱动晶体管M0的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。
示例性地，漏电调节信号端VS的信号的实施方式可以参照上述描述进行设置，在此不作赘述。
图10ba所示的像素电路对应的信号时序图，可以如图9所示。并且，本公开实施例提供的像素电路的驱动过程，可以参照上述描述，在此不作赘述。
本公开实施例提供的显示面板中的每一个子像素可以包括本公开实施例提供的上述任一像素电路。并且，显示面板还可以包括多条控制信号线和驱动控制电路。其中，多条控制信号线中的至少一条控制信号线与一行子像素中的像素电路耦接，以及，驱动控制电路分别与多条控制信号线耦接。
在本公开一些实施例中，在显示面板采用如图3所示的像素电路时，如图11所示，多条控制信号线包括多条发光控制信号线、多条第一扫描信号线、多条第二扫描控制信号线以及多条第三扫描控制信号线；其中，一行子像素与一条发光控制信号线对应，一行子像素与两条第一扫描信号线对应，一行子像素与一条第二扫描控制信号线和一条第三扫描控制信号线对应。并且，每一条发光控制信号线与对应行子像素中的像素电路的发光控制信号端EM耦接。两条第一扫描信号线中的第一条第一扫描信号线与对应行子像素中的像素电路的第三控制信号端CS3耦接，第二条第一扫描信号线与对应行子像素中的像素电路的第四控制信号端CS4耦接。每一条第二扫描控制信号线与对应行子像素中的像素电路的第二控制信号端CS2耦接，每一条第三扫描控制信号线与对应行子像素中的像素电路的第一控制信号端CS1耦接。
示例性地，如图11所示，驱动控制电路包括：发光扫描电路SRE、第一扫描控制电路SRG1、第二扫描控制电路SRG2以及第三扫描控制电路SRG3。其中，发光扫描电路SRE包括依次设置的多个发光扫描移位寄存器单元；其中，一行子像素耦接的发光控制信号线与一个发光扫描移位寄存器单元对应 耦接。
示例性地，如图11所示，第一扫描控制电路SRG1包括依次设置的多个第一扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第一条第一扫描控制信号线和上一行子像素耦接的第二条第一扫描控制信号线与同一个第一扫描控制移位寄存器单元对应耦接。
示例性地，如图11所示，第二扫描控制电路SRG2包括依次设置的多个第二扫描控制移位寄存器单元；其中，一行子像素耦接的第二扫描控制信号线与一个第二扫描控制移位寄存器单元对应耦接。
示例性地，如图11所示，第三扫描控制电路SRG3包括依次设置的多个第三扫描控制移位寄存器单元；其中，一行子像素耦接的第三扫描控制信号线与一个第三扫描控制移位寄存器单元对应耦接。
示例性地，如图11所示，示意出了发光扫描电路SRE中的一个发光扫描移位寄存器单元SREM(N)，第一扫描控制电路SRG1中的相邻两个第一扫描控制移位寄存器单元SRGA1(N-1)～SRGA1(N)，第二扫描控制电路SRG2中的一个第二扫描控制移位寄存器单元SRGA2(N)，第三扫描控制电路SRG3中的一个第三扫描控制移位寄存器单元SRGA3(N)。其中，发光扫描电路SRE中的第N个发光扫描移位寄存器单元SREM(N)与第N行子像素对应的发光控制信号线EML(N)耦接。第一扫描控制电路SRG1中的第N-1个第一扫描控制移位寄存器单元SRGA1(N-1)与第N行子像素对应的第二条第一扫描控制信号线GA1LB(N)耦接，第N个第一扫描控制移位寄存器单元SRGA1(N)与第N行子像素对应的第一条第一扫描控制信号线GA1LA(N)耦接。第二扫描控制电路SRG2中的第N个第二扫描控制移位寄存器单元SRGA2(N)与第N行子像素对应的第二扫描控制信号线GA2L(N)耦接。第三扫描控制电路SRG3中的第N个第三扫描控制移位寄存器单元SRGA3(N)与第N行子像素对应的第三扫描控制信号线GA3L(N)耦接。
本发明实施例提供了像素电路的又一些结构示意图，如图12所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例 的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，在显示面板采用如图3所示的像素电路时，如图12所示，多条控制信号线包括多条发光控制信号线、多条第一扫描信号线、多条第四扫描控制信号线以及多条第五扫描控制信号线；其中，一行子像素与一条发光控制信号线对应，一行子像素与两条第一扫描信号线对应，一行子像素与一条第四扫描控制信号线和一条第五扫描控制信号线对应。并且，每一条发光控制信号线与对应行子像素中的像素电路的发光控制信号端EM耦接。两条第一扫描信号线中的第一条第一扫描信号线与对应行子像素中的像素电路的第三控制信号端CS3耦接，第二条第一扫描信号线与对应行子像素中的像素电路的第四控制信号端CS4耦接。每一条第四扫描控制信号线与对应行子像素中的像素电路的第二控制信号端CS2耦接，每一条第五扫描控制信号线与对应行子像素中的像素电路的第一控制信号端CS1耦接。
示例性地，如图12所示，驱动控制电路包括：发光扫描电路SRE、第一扫描控制电路SRG1以及第四扫描控制电路SRG4。其中，发光扫描电路SRE包括依次设置的多个发光扫描移位寄存器单元；其中，一行子像素耦接的发光控制信号线与一个发光扫描移位寄存器单元对应耦接。
示例性地，如图12所示，第一扫描控制电路SRG1包括依次设置的多个第一扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第一条第一扫描控制信号线和上一行子像素耦接的第二条第一扫描控制信号线与同一个第一扫描控制移位寄存器单元对应耦接。
示例性地，如图12所示，第四扫描控制电路SRG4包括依次设置的多个第四扫描控制移位寄存器单元；其中，每相邻三行子像素中，第三行子像素耦接的第五扫描控制信号线和第一行子像素耦接的第四扫描控制信号线与同一个第四扫描控制移位寄存器单元对应耦接。
示例性地，如图12所示，示意出了发光扫描电路SRE中的一个发光扫描移位寄存器单元SREM(N)，第一扫描控制电路SRG1中的相邻两个第一扫描控制移位寄存器单元SRGA1(N-1)～SRGA1(N)，第四扫描控制电路SRG4中 的相邻三个第四扫描控制移位寄存器单元SRGA4(N-2)～SRGA4(N)。其中，发光扫描电路SRE中的第N个发光扫描移位寄存器单元SREM(N)与第N行子像素对应的发光控制信号线EML(N)耦接。第一扫描控制电路SRG1中的第N-1个第一扫描控制移位寄存器单元SRGA1(N-1)与第N行子像素对应的第二条第一扫描控制信号线CS3L(N)耦接，第N个第一扫描控制移位寄存器单元SRGA1(N)与第N行子像素对应的第一条第一扫描控制信号线CS4L(N)耦接。第四扫描控制电路SRG4中的第N-2个第四扫描控制移位寄存器单元SRGA4(N-2)与第N行子像素对应的第四扫描控制信号线GA4L(N)耦接，第N个第四扫描控制移位寄存器单元SRGA4(N)与第N行子像素对应的第五扫描控制信号线GA5L(N)耦接。
本发明实施例提供了像素电路的又一些结构示意图，如图13所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，在显示面板采用如图6和图8所示的像素电路时，如图13所示，多条控制信号线包括多条发光控制信号线、多条第六扫描控制信号线、多条第七扫描控制信号线以及多条第八扫描控制信号线；其中，一行子像素与一条发光控制信号线对应，一行子像素与一条第六扫描控制信号线、一条第七扫描控制信号线以及一条第八扫描控制信号线对应。并且，每一条发光控制信号线与对应行子像素中的像素电路的发光控制信号端EM耦接。每一条第六扫描控制信号线与对应行子像素中的像素电路的第三控制信号端CS3耦接，每一条第七扫描控制信号线与对应行子像素中的像素电路的第二控制信号端CS2耦接，每一条第八扫描控制信号线与对应行子像素中的像素电路的第一控制信号端CS1耦接。
示例性地，如图13所示，驱动控制电路包括：发光扫描电路SRE，发光扫描电路SRE包括依次设置的多个发光扫描移位寄存器单元；其中，一行子像素耦接的发光控制信号线与一个发光扫描移位寄存器单元对应耦接。
示例性地，如图13所示，驱动控制电路包括：第五扫描控制电路SRG5 和第六扫描控制电路SRG6。第五扫描控制电路SRG5包括依次设置的多个第五扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第六扫描控制信号线和上一行子像素耦接的第七扫描控制信号线与同一个第五扫描控制移位寄存器单元对应耦接。第六扫描控制电路SRG6包括依次设置的多个第六扫描控制移位寄存器单元；其中，一行子像素耦接的第八扫描控制信号线与一个第六扫描控制移位寄存器单元对应耦接。
示例性地，如图13所示，示意出了发光扫描电路SRE中的一个发光扫描移位寄存器单元SREM(N)，第六扫描控制电路SRG6中的一个第六扫描控制移位寄存器单元SRGA6(N)，第五扫描控制电路SRG5中的相邻两个第五扫描控制移位寄存器单元SRGA5(N-1)～SRGA5(N)。其中，发光扫描电路SRE中的第N个发光扫描移位寄存器单元SREM(N)与第N行子像素对应的发光控制信号线EML(N)耦接。第六扫描控制电路SRG6中的第N个第六扫描控制移位寄存器单元SRGA6(N)与第N行子像素对应的第八扫描控制信号线CS8L(N)耦接。第五扫描控制电路SRG5中的第N-1个第五扫描控制移位寄存器单元SRGA5(N-1)与第N行子像素对应的第六扫描控制信号线GA6L(N)耦接，第N个第五扫描控制移位寄存器单元SRGA5(N)与第N行子像素对应的第七扫描控制信号线GA7L(N)耦接。
本发明实施例提供了像素电路的又一些结构示意图，如图14所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，在显示面板采用如图6和图8所示的像素电路时，如图14所示，多条控制信号线包括多条发光控制信号线、多条第九扫描控制信号线、多条第十扫描控制信号线以及多条第十一扫描控制信号线；其中，一行子像素与一条第九扫描控制信号线、一条第十扫描控制信号线以及一条第十一扫描控制信号线对应。并且，每一条发光控制信号线与对应行子像素中的像素电路的发光控制信号端EM耦接。每一条第九扫描控制信号线与对应行子像素中的像素电路的第三控制信号端CS3耦接，每一条第十扫描 控制信号线与对应行子像素中的像素电路的第二控制信号端CS2耦接，每一条第十一扫描控制信号线与对应行子像素中的像素电路的第一控制信号端CS1耦接。
示例性地，如图14所示，驱动控制电路包括：发光扫描电路SRE，发光扫描电路SRE包括依次设置的多个发光扫描移位寄存器单元；其中，一行子像素耦接的发光控制信号线与一个发光扫描移位寄存器单元对应耦接。
示例性地，如图14所示，驱动控制电路包括：第七扫描控制电路SRG7，第七扫描控制电路SRG7包括依次设置的多个第七扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第九扫描控制信号线和上一行子像素耦接的第十扫描控制信号线与同一个第七扫描控制移位寄存器单元对应耦接，且下一行子像素耦接的第十扫描控制信号线和上一行子像素耦接的第十一扫描控制信号线与同一个第七扫描控制移位寄存器单元对应耦接。
示例性地，如图14所示，示意出了发光扫描电路SRE中的一个发光扫描移位寄存器单元SREM(N)，第七扫描控制电路SRG7中的相邻两个第七扫描控制移位寄存器单元SRGA7(N-2)～SRGA7(N)。其中，发光扫描电路SRE中的第N个发光扫描移位寄存器单元SREM(N)与第N行子像素对应的发光控制信号线EML(N)耦接。第七扫描控制电路SRG7中的第N-2个第七扫描控制移位寄存器单元SRGA7(N-2)与第N行子像素对应的第九扫描控制信号线GA9L(N)耦接，第N-1个第七扫描控制移位寄存器单元SRGA7(N-1)与第N行子像素对应的第十扫描控制信号线GA10L(N)耦接，第N个第七扫描控制移位寄存器单元SRGA7(N)与第N行子像素对应的第十一扫描控制信号线GA11L(N)耦接。
本发明实施例提供了像素电路的又一些结构示意图，如图15所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，在显示面板采用如图6所示的像素电路时，如图15所示，多条控制信号线包括多条发光控制信号线、多条第六扫描控制信 号线、多条第七扫描控制信号线、多条第八扫描控制信号线以及多条第十二扫描控制信号线；其中，一行子像素与一条发光控制信号线对应，一行子像素与一条第六扫描控制信号线、一条第七扫描控制信号线以及一条第八扫描控制信号线对应，一行子像素与一条第十二扫描控制信号线对应。并且，每一条发光控制信号线与对应行子像素中的像素电路的发光控制信号端EM耦接。每一条第六扫描控制信号线与对应行子像素中的像素电路的第三控制信号端CS3耦接，每一条第七扫描控制信号线与对应行子像素中的像素电路的第二控制信号端CS2耦接，每一条第八扫描控制信号线与对应行子像素中的像素电路的第一控制信号端CS1耦接。每一条第十二扫描控制信号线与对应行子像素中的像素电路的第四控制信号端CS4耦接。
示例性地，如图15所示，驱动控制电路包括：第五扫描控制电路SRG5和第六扫描控制电路SRG6。第五扫描控制电路SRG5包括依次设置的多个第五扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第六扫描控制信号线和上一行子像素耦接的第七扫描控制信号线与同一个第五扫描控制移位寄存器单元对应耦接。第六扫描控制电路SRG6包括依次设置的多个第六扫描控制移位寄存器单元；其中，一行子像素耦接的第八扫描控制信号线与一个第六扫描控制移位寄存器单元对应耦接。
示例性地，如图15所示，驱动控制电路包括：第八扫描控制电路SRG8，第八扫描控制电路SRG8包括依次设置的多个第八扫描控制移位寄存器单元；其中，一行子像素耦接的第十二扫描控制信号线与一个第八扫描控制移位寄存器单元对应耦接。
示例性地，如图15所示，示意出了发光扫描电路SRE中的一个发光扫描移位寄存器单元SREM(N)，第六扫描控制电路SRG6中的一个第六扫描控制移位寄存器单元SRGA6(N)，第五扫描控制电路SRG5中的相邻两个第五扫描控制移位寄存器单元SRGA5(N-1)～SRGA5(N)，第八扫描控制电路SRG8中的一个第八扫描控制移位寄存器单元SRGA8(N)，其中，发光扫描电路SRE中的第N个发光扫描移位寄存器单元SREM(N)与第N行子像素对应的发光控 制信号线EML(N)耦接。第六扫描控制电路SRG6中的第N个第六扫描控制移位寄存器单元SRGA6(N)与第N行子像素对应的第八扫描控制信号线CS8L(N)耦接。第五扫描控制电路SRG5中的第N-1个第五扫描控制移位寄存器单元SRGA5(N-1)与第N行子像素对应的第六扫描控制信号线GA6L(N)耦接，第N个第五扫描控制移位寄存器单元SRGA5(N)与第N行子像素对应的第七扫描控制信号线GA7L(N)耦接。第八扫描控制电路SRG8中的第N个第八扫描控制移位寄存器单元SRGA8(N)与第N行子像素对应的第十二扫描控制信号线CS12L(N)耦接。
本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
需要说明的是，在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (27)

  1. 一种像素电路，包括：
    发光器件；
    驱动晶体管，与所述发光器件耦接，被配置为根据数据电压产生驱动所述发光器件的工作电流；
    第一控制电路，与所述驱动晶体管的栅极耦接，被配置为基于漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；
    第二控制电路，与所述驱动晶体管的第一设定极耦接，被配置为在驱动所述发光器件发光之前，对所述驱动晶体管的第一设定极进行初始化；其中，所述第一设定极为所述驱动晶体管的第一极和/或第二极；
    第三控制电路，与所述驱动晶体管耦接，被配置为对所述驱动晶体管的栅极进行复位，控制所述数据电压输入所述驱动晶体管的栅极以及控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
  2. 如权利要求1所述的像素电路，其中，所述第一控制电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的栅极与所述驱动晶体管的栅极耦接，所述第一晶体管的第一极浮接，所述第一晶体管的第二极与所述漏电调节信号端耦接；
    所述第二晶体管的栅极与所述驱动晶体管的栅极耦接，所述第二晶体管的第一极浮接，所述第二晶体管的第二极与所述漏电调节信号端耦接。
  3. 如权利要求1所述的像素电路，其中，所述第一控制电路包括：稳压电容；
    所述稳压电容的第一电极与所述驱动晶体管的栅极耦接，所述稳压电容的第二电极与所述漏电调节信号端耦接。
  4. 如权利要求1-3任一项所述的像素电路，其中，在同一个显示帧中，在对所述驱动晶体管的栅极进行复位时，所述漏电调节信号端的信号的电压为第一电压，在所述数据电压输入所述驱动晶体管的栅极时，所述漏电调节 信号端的信号的电压为第二电压；
    所述第二电压不小于所述第一电压。
  5. 如权利要求4所述的像素电路，其中，在不同显示帧中，所述第一电压相同。
  6. 如权利要求4或5所述的像素电路，其中，在不同显示帧中，所述第二电压大于第三电压；
    所述第三电压为Vda-Vth；Vda代表所述数据电压，Vth代表所述驱动晶体管的阈值电压。
  7. 如权利要求6所述的像素电路，其中，在不同显示帧中，所述第二电压相同；
    或者，在不同显示帧中，所述第二电压随着所述第三电压的增加而增加。
  8. 如权利要求1-7任一项所述的像素电路，其中，所述第二控制电路进一步被配置为响应于第一控制信号端的信号，在所述输入数据电压之后将第一初始化信号端的信号提供给所述第一设定极。
  9. 如权利要求8所述的像素电路，其中，所述第一初始化信号端为高电平或低电平。
  10. 如权利要求8所述的像素电路，其中，在所述第一初始化信号端为高电平时，所述第一初始化信号端与第一电源端为同一信号端。
  11. 如权利要求8-10任一项所述的像素电路，其中，所述第二控制电路包括：第三晶体管；
    所述第三晶体管的栅极与所述第一控制信号端耦接，所述第三晶体管的第一极与所述第一初始化信号端耦接，所述第三晶体管的第二极与所述第一设定极耦接。
  12. 如权利要求1-11任一项所述的像素电路，其中，所述第三控制电路包括：
    数据写入电路，被配置为响应于第二控制信号端的信号，将数据信号端的数据电压输入所述驱动晶体管的第一极；
    复位电路，被配置为响应于第三控制信号端的信号，将第二初始化信号端的信号输入所述驱动晶体管的第二设定极；所述第二设定极为所述驱动晶体管的栅极或第二极；
    初始化电路，被配置为响应于第一控制信号端的信号，将第三初始化信号端的信号输入所述发光器件的第一电极；
    阈值补偿电路，被配置为响应于第四控制信号端的信号，将所述驱动晶体管的栅极与其第二极导通；
    发光控制电路，被配置为响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件的第一电极导通，控制所述驱动晶体管产生的工作电流输入所述发光器件。
  13. 如权利要求12所述的像素电路，其中，所述数据写入电路包括第四晶体管，所述第四晶体管的栅极与所述第二控制信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述复位电路包括第五晶体管，所述第五晶体管的栅极与所述第三控制信号端耦接，所述第五晶体管的第一极与所述第二初始化信号端耦接，所述第五晶体管的第二极与所述驱动晶体管的第二设定极耦接；
    所述初始化电路包括第六晶体管，所述第六晶体管的栅极与所述第一控制信号端耦接，所述第六晶体管的第一极与所述第三初始化信号端耦接，所述第六晶体管的第二极与所述发光器件的第一电极耦接；
    所述阈值补偿电路包括第七晶体管和存储电容，所述第七晶体管的栅极与所述第四控制信号端耦接，所述第七晶体管的第一极与所述驱动晶体管的栅极耦接，所述第七晶体管的第二极与所述驱动晶体管的第二极耦接，所述存储电容的第一电极与所述第一电源端耦接，所述存储电容的第二电极与所述驱动晶体管的栅极耦接；
    所述发光控制电路包括第八晶体管和第九晶体管，所述第八晶体管的栅 极与所述发光控制信号端耦接，所述第八晶体管的第一极与所述第一电源端耦接，所述第八晶体管的第二极与所述驱动晶体管的第一极耦接，所述第九晶体管的栅极与所述发光控制信号端耦接，所述第九晶体管的第一极与所述驱动晶体管的第二极耦接，所述第九晶体管的第二极与所述发光器件的第一电极耦接。
  14. 如权利要求12或13所述的像素电路，其中，所述第二控制信号端与所述第四控制信号端为同一信号端或相互独立的信号端。
  15. 如权利要求12-14任一项所述的像素电路，其中，在同一显示帧中，所述第一控制信号端的有效电平晚于所述第二控制信号端的有效电平。
  16. 一种用于如权利要求1-15任一项所述的像素电路的驱动方法，包括：
    复位阶段，第三控制电路对所述驱动晶体管的栅极进行复位；
    数据写入阶段，第三控制电路控制数据电压输入所述驱动晶体管的栅极；
    初始化阶段，第二控制电路对所述驱动晶体管的第一设定极进行初始化；
    发光阶段，第一控制电路基于漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；第三控制电路控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
  17. 如权利要求16所述的驱动方法，其中，所述复位阶段包括：复位电路响应于第三控制信号端的信号，将第二初始化信号端的信号输入所述驱动晶体管的第二设定极；
    所述初始化阶段还包括：初始化电路响应于第一控制信号端的信号，将所述第三初始化信号端的信号输入所述发光器件的第一电极。
  18. 如权利要求16或17所述的驱动方法，其中，所述数据写入阶段包括：数据写入电路响应于第二控制信号端的信号，将数据信号端的数据电压输入所述驱动晶体管的第一极；阈值补偿电路响应于第二控制信号端的信号，将所述驱动晶体管的栅极与其第二极导通；
    所述发光阶段包括：发光控制电路响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极 与所述发光器件的第一电极导通，控制所述驱动晶体管产生的工作电流输入所述发光器件。
  19. 一种显示面板，包括：
    多个子像素，所述多个子像素中的每一个所述子像素包括如权利要求1-15任一项所述的像素电路；
    多条控制信号线，所述多条控制信号线中的至少一条控制信号线与一行子像素中的像素电路耦接；
    驱动控制电路，所述驱动控制电路分别与所述多条控制信号线耦接。
  20. 如权利要求19所述的显示面板，其中，所述多条控制信号线包括多条发光控制信号线；其中，一行子像素与一条发光控制信号线对应，且每一条所述发光控制信号线与对应行子像素中的像素电路的发光控制信号端耦接；
    所述驱动控制电路包括：发光扫描电路，所述发光扫描电路包括依次设置的多个发光扫描移位寄存器单元；其中，一行子像素耦接的所述发光控制信号线与一个所述发光扫描移位寄存器单元对应耦接。
  21. 如权利要求20所述的显示面板，其中，所述多条控制信号线包括多条第一扫描信号线；其中，一行子像素与两条第一扫描信号线对应，且所述两条第一扫描信号线中的第一条第一扫描信号线与对应行子像素中的像素电路的第三控制信号端耦接，第二条第一扫描信号线与对应行子像素中的像素电路的第四控制信号端耦接；
    所述驱动控制电路包括：第一扫描控制电路，所述第一扫描控制电路包括依次设置的多个第一扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第一条第一扫描控制信号线和上一行子像素耦接的第二条第一扫描控制信号线与同一个所述第一扫描控制移位寄存器单元对应耦接。
  22. 如权利要求21所述的显示面板，其中，所述多条控制信号线还包括多条第二扫描控制信号线和多条第三扫描控制信号线；一行子像素与一条第二扫描控制信号线和一条第三扫描控制信号线对应，每一条所述第二扫描控 制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第三扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
    所述驱动控制电路包括：第二扫描控制电路和第三扫描控制电路；
    所述第二扫描控制电路包括依次设置的多个第二扫描控制移位寄存器单元；其中，一行子像素耦接的所述第二扫描控制信号线与一个所述第二扫描控制移位寄存器单元对应耦接；
    所述第三扫描控制电路包括依次设置的多个第三扫描控制移位寄存器单元；其中，一行子像素耦接的所述第三扫描控制信号线与一个所述第三扫描控制移位寄存器单元对应耦接。
  23. 如权利要求21所述的显示面板，其中，所述多条控制信号线还包括多条第四扫描控制信号线和多条第五扫描控制信号线；一行子像素与一条第四扫描控制信号线和一条第五扫描控制信号线对应，每一条所述第四扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第五扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
    所述驱动控制电路包括：第四扫描控制电路，所述第四扫描控制电路包括依次设置的多个第四扫描控制移位寄存器单元；其中，每相邻三行子像素中，第三行子像素耦接的第五扫描控制信号线和第一行子像素耦接的第四扫描控制信号线与同一个所述第四扫描控制移位寄存器单元对应耦接。
  24. 如权利要求20所述的显示面板，其中，所述多条控制信号线还包括多条第六扫描控制信号线、多条第七扫描控制信号线以及多条第八扫描控制信号线；一行子像素与一条第六扫描控制信号线、一条第七扫描控制信号线以及一条第八扫描控制信号线对应，每一条所述第六扫描控制信号线与对应行子像素中的像素电路的第三控制信号端耦接，每一条所述第七扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第八扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
    所述驱动控制电路包括：第五扫描控制电路和第六扫描控制电路；
    所述第五扫描控制电路包括依次设置的多个第五扫描控制移位寄存器单 元；其中，每相邻两行子像素中，下一行子像素耦接的第六扫描控制信号线和上一行子像素耦接的第七扫描控制信号线与同一个所述第五扫描控制移位寄存器单元对应耦接；
    所述第六扫描控制电路包括依次设置的多个第六扫描控制移位寄存器单元；其中，一行子像素耦接的所述第八扫描控制信号线与一个所述第六扫描控制移位寄存器单元对应耦接。
  25. 如权利要求20所述的显示面板，其中，所述多条控制信号线还包括多条第九扫描控制信号线、多条第十扫描控制信号线以及多条第十一扫描控制信号线；一行子像素与一条第九扫描控制信号线、一条第十扫描控制信号线以及一条第十一扫描控制信号线对应，每一条所述第九扫描控制信号线与对应行子像素中的像素电路的第三控制信号端耦接，每一条所述第十扫描控制信号线与对应行子像素中的像素电路的第二控制信号端耦接，每一条所述第十一扫描控制信号线与对应行子像素中的像素电路的第一控制信号端耦接；
    所述驱动控制电路包括：第七扫描控制电路，所述第七扫描控制电路包括依次设置的多个第七扫描控制移位寄存器单元；其中，每相邻两行子像素中，下一行子像素耦接的第九扫描控制信号线和上一行子像素耦接的第十扫描控制信号线与同一个所述第七扫描控制移位寄存器单元对应耦接，且下一行子像素耦接的第十扫描控制信号线和上一行子像素耦接的第十一扫描控制信号线与同一个所述第七扫描控制移位寄存器单元对应耦接。
  26. 如权利要求24或25所述的显示面板，其中，所述多条控制信号线还包括多条第十二扫描控制信号线；一行子像素与一条第十二扫描控制信号线对应，每一条所述第十二扫描控制信号线与对应行子像素中的像素电路的第四控制信号端耦接；
    所述驱动控制电路包括：第八扫描控制电路，所述第八扫描控制电路包括依次设置的多个第八扫描控制移位寄存器单元；其中，一行子像素耦接的所述第十二扫描控制信号线与一个所述第八扫描控制移位寄存器单元对应耦接。
  27. 一种显示装置，包括如权利要求19-26任一项所述的显示面板。
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