WO2024060366A1 - 显示面板 - Google Patents

显示面板 Download PDF

Info

Publication number
WO2024060366A1
WO2024060366A1 PCT/CN2022/130324 CN2022130324W WO2024060366A1 WO 2024060366 A1 WO2024060366 A1 WO 2024060366A1 CN 2022130324 W CN2022130324 W CN 2022130324W WO 2024060366 A1 WO2024060366 A1 WO 2024060366A1
Authority
WO
WIPO (PCT)
Prior art keywords
ohmic contact
boss
contact structure
substrate
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/130324
Other languages
English (en)
French (fr)
Inventor
李治福
刘广辉
艾飞
宋德伟
李壮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US17/925,002 priority Critical patent/US20250072093A1/en
Publication of WO2024060366A1 publication Critical patent/WO2024060366A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel.
  • Integrating pixel driving circuits, gate driving circuits, source driving circuits, timing controllers and other circuits on a glass substrate can greatly improve the integration of display panels, reduce dependence on integrated circuit chips, and reduce costs.
  • Achieving SOG requires increasing the integration level, maximum operating frequency, and current density of thin film transistors in existing display panels, which all require thin film transistors to have shorter channel lengths, higher mobility, and smaller volumes.
  • the existing display panel has the problem that the existing process cannot reduce the channel length and volume of the thin film transistor. Therefore, it is necessary to provide a display panel to improve this defect.
  • Embodiments of the present application provide a display panel that can use existing processes to reduce the channel length of thin film transistors and the volume of thin film transistors, increase the on-state current of thin film transistors, and improve the integration of thin film transistors in the display panel.
  • An embodiment of the present application provides a display panel, including:
  • a first ohmic contact structure is provided on the substrate
  • a first boss disposed on a side of the first ohmic contact structure away from the substrate, the first boss having at least one side wall;
  • a second ohmic contact structure is provided on a side of the first boss away from the first ohmic contact structure
  • a semiconductor structure is provided at least on the sidewall and is in contact with the first ohmic contact structure and the second ohmic contact structure respectively;
  • a gate electrode is disposed on a side of the semiconductor structure facing away from the substrate.
  • the first ohmic contact structure has a first sidewall adjacent to the sidewall, and the semiconductor structure is in contact with the first sidewall.
  • the first ohmic contact structure includes:
  • the body part is disposed between the first boss and the substrate;
  • the protruding part is connected to the body part, the orthographic projection of the protruding part on the substrate does not overlap with the orthographic projection of the first boss on the substrate, and the semiconductor structure and the protruding part are The surface of the side of the outlet facing away from the substrate is in contact.
  • the length of the protrusion is between 0.5 microns and 3 microns.
  • the first part is provided on the substrate and/or the first ohmic contact structure
  • a second part is provided on the side wall and connected to the first part
  • the third part is disposed on a side of the second ohmic contact structure away from the first boss, and is connected to the second part.
  • an angle between the side wall and the plane where the substrate is located is between 45 degrees and 90 degrees.
  • the first boss has two oppositely disposed side walls, and the semiconductor structure and the gate located on a side of the semiconductor structure away from the substrate are disposed on both side walls;
  • the semiconductor structures on both sidewalls are in contact with the first ohmic contact structure and the second ohmic contact structure.
  • the semiconductor structure is continuously provided on the two side walls of the first boss and the second ohmic contact structure.
  • an orthographic projection of the gate on the substrate covers an orthographic projection of the semiconductor structure on the substrate.
  • the display panel includes:
  • a third ohmic contact structure is provided on the substrate.
  • a fourth ohmic contact structure is disposed on a side of the second boss away from the first ohmic contact structure.
  • the semiconductor structure is at least disposed on a side wall of the second boss and is respectively connected with the first ohmic contact structure.
  • the third ohmic contact structure is in contact with the fourth ohmic contact structure;
  • the display panel further includes a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected to the first ohmic contact structure and the third ohmic contact structure, the source electrode The other one of the drain electrode and the drain electrode is electrically connected to the second ohmic contact structure and the fourth ohmic contact structure.
  • the semiconductor structure is continuously provided on the first boss, the second boss, and the area between the first boss and the second boss.
  • the orthographic projection of the gate on the substrate covers the orthographic projection of the semiconductor structure on the substrate.
  • the display panel further includes a gate insulating layer and an interlayer dielectric layer, the gate insulating layer is at least disposed between the gate and the semiconductor structure and covers the second ohmic contact structure and the first ohmic contact structure, and the interlayer dielectric layer is disposed on a side of the gate insulating layer away from the substrate and covers the gate;
  • the display panel also includes a source and a drain, and the source and the drain are both arranged on the side of the interlayer dielectric layer away from the substrate, one of the source and the drain passes through the interlayer dielectric layer and the gate insulating layer to contact the first ohmic contact structure, and the other of the source and the drain passes through the interlayer dielectric layer and the gate insulating layer to contact the second ohmic contact structure.
  • the display panel further includes a light-shielding structure disposed on a side of the first ohmic contact structure close to the substrate, and the semiconductor structure includes a light-shielding structure connected to the first ohmic contact structure. Between the contact structure and the second ohmic contact structure;
  • the orthographic projection of the light-shielding structure on the substrate covers the orthographic projection of the channel portion on the substrate.
  • the length of the channel portion along the extending direction of the side wall is between 0.01 micron and 1 micron.
  • the thickness of the first boss in the thickness direction of the display panel is between 0.0071 micron and 1 micron.
  • the first boss has a single-layer or multi-layer structure.
  • the material of the first boss includes one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.
  • the material of the first boss includes acrylic resin, epoxy resin, phenolic resin, polyamide-based resin, polyimide-based resin, unsaturated polyester resin, polyacrylate, poly One or a combination of carbonates, polyimides, and polystyrenes.
  • the side wall is a flat surface or an arc surface.
  • the embodiments of the present application provide a display panel, which includes a substrate and a first ohmic contact structure, a second ohmic contact structure, a semiconductor structure and a gate stacked on the substrate, the first boss having at least one side wall, and by disposing the semiconductor structure on the side wall of the first boss and respectively contacting the first ohmic contact structure and the second ohmic contact structure, the channel length of the thin film transistor can be shortened by utilizing existing processes, and the volume of the thin film transistor can be reduced, thereby improving the integration of the thin film transistor in the display panel.
  • Figure 1 is a schematic plan view of a first thin film transistor provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional view along the B-B direction of the first thin film transistor provided by an embodiment of the present application;
  • Figure 3 is a schematic cross-sectional view along the A-A direction of the first thin film transistor provided by the embodiment of the present application;
  • Figure 4 is a schematic plan view of a second thin film transistor provided by an embodiment of the present application.
  • Figure 5 is a schematic cross-sectional view along the B-B direction of the second thin film transistor provided by the embodiment of the present application;
  • Figure 6 is a schematic cross-sectional view along the A-A direction of the second thin film transistor provided by the embodiment of the present application;
  • Figure 7 is a schematic plan view of a third thin film transistor provided by an embodiment of the present application.
  • Figure 8 is a schematic cross-sectional view along the B-B direction of the third thin film transistor provided by the embodiment of the present application.
  • Figure 9 is a schematic cross-sectional view along the A-A direction of the third thin film transistor provided by the embodiment of the present application.
  • FIG10 is a schematic plan view of a fourth thin film transistor provided in an embodiment of the present application.
  • Figure 11 is a schematic cross-sectional view along the B-B direction of the fourth thin film transistor provided by the embodiment of the present application.
  • Figure 12 is a schematic cross-sectional view along the A-A direction of the fourth thin film transistor provided by the embodiment of the present application.
  • 13a to 13g are schematic flow diagrams of a method for manufacturing a display panel according to an embodiment of the present application.
  • Embodiments of the present application provide a display panel that can use existing processes to reduce the channel length of the thin film transistor and the volume of the thin film transistor, increase the on-state current of the thin film transistor, and improve the integration of the thin film transistor in the display panel.
  • the display panel includes a substrate 10 and a plurality of thin film transistors 20 disposed on the substrate 10 .
  • the thin film transistor 20 can be applied in at least one circuit module such as a pixel driving circuit, a gate driving circuit, a source driving circuit, and a timing controller of the display panel.
  • being disposed on the substrate 10 may refer to being in direct contact with the substrate 10 or indirect contact with the substrate 10 .
  • Figure 1 is a schematic plan view of the first thin film transistor provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional view along the B-B direction of the first thin film transistor provided by an embodiment of the present application.
  • Figure 3 This is a schematic cross-sectional view of the first thin film transistor along the A-A direction provided in the embodiment of the present application.
  • the display panel may also include a buffer layer 11.
  • the buffer layer 11 is disposed on the side of the substrate 10 close to the thin film transistor 20. On the surface, the thin film transistor 20 is disposed on the buffer layer 11 .
  • the display panel includes a first ohmic contact structure 21 , a first boss 23 , a second ohmic contact structure 22 , a semiconductor structure 24 and a gate electrode 25 .
  • the first ohmic contact structure 21 is disposed on the substrate 10 .
  • the first ohmic contact structure 21 may be disposed on a side surface of the buffer layer 11 facing away from the substrate 10 .
  • the first ohmic contact structure 21 is made of N-type heavily doped amorphous silicon material, and the first ohmic contact structure 21 may be doped with elemental impurities such as phosphorus or arsenic.
  • the first boss 23 is disposed on a side of the first ohmic contact structure 21 away from the substrate 10 .
  • the material of the first boss 23 may be a single-layer or multi-layer structure formed of inorganic insulating material or organic insulating material.
  • the first boss 23 may be a stacked structure formed by stacking multiple layers of the same material in sequence, or may be formed by stacking at least two different materials. The laminated structure formed.
  • the material of the first boss 23 can be commonly used inorganic insulating materials such as silicon nitride, silicon oxide or silicon oxynitride.
  • the material of the first boss 23 can also be acrylic resin, epoxy resin, Any one or two or more of phenolic resin, polyamide-based resin, polyimide-based resin, unsaturated polyester resin, polyacrylate, polycarbonate, polyimide, polystyrene Combined materials.
  • the second ohmic contact structure 22 is disposed on a side of the first boss 23 away from the first ohmic contact structure 21 .
  • the material of the second ohmic contact structure 22 is N-type heavily doped amorphous silicon material, and the second ohmic contact structure 22 may be doped with elemental impurities such as phosphorus or arsenic.
  • first boss 23 has at least one side wall 230
  • the semiconductor structure 24 is at least disposed on the side wall 230 and is in contact with the first ohmic contact structure 21 and the second ohmic contact structure 21 respectively.
  • Structure 22 contacts.
  • the first boss 23 may have a first surface 231 and a second surface 232 arranged oppositely.
  • the first surface 231 and the second surface 232 may be arranged parallel to each other.
  • the first surface 231 and the second surface 232 may be arranged parallel to each other.
  • the second surface 232 may be disposed on a side of the first surface 231 away from the substrate 10 .
  • the first surface 231 may be in direct contact with a surface of the first ohmic contact structure 21 facing away from the substrate 10
  • the second ohmic contact structure 22 may be disposed on a side of the second surface 232 facing away from the substrate 10 , and may be in direct contact with the second surface 232 .
  • the side wall 230 is disposed between the first surface 231 and the second surface 232 and is connected to the first surface 231 and the second surface 232 respectively.
  • the side wall 230 is arranged in an inclined state and forms a certain angle with the first surface 231 and the second surface 232 .
  • the semiconductor structure 24 is disposed along the sidewall 230 and extends to contact the first ohmic contact structure 21 and the second ohmic contact structure 22 respectively.
  • the semiconductor structure 24 is made of undoped polysilicon material.
  • the channel portion 240 in the semiconductor structure 24 that is opposite to the sidewall 230 can be used as a channel of the thin film transistor 20 .
  • the channel The length L of the portion 240 along the extending direction of the sidewall 230 is the channel length of the thin film transistor.
  • the gate 25 is disposed on a side of the semiconductor structure 24 away from the substrate 10 .
  • the display panel further includes a gate insulating layer 13 , which is disposed on a side of the semiconductor structure 24 away from the substrate 10 and continuously covers the semiconductor structure. 24.
  • a part of the gate insulating layer 13 is laid flat on the buffer layer 11 and the horizontally arranged semiconductor structure 24, and a part of the gate insulating layer 13 is laid along the The portion of the semiconductor structure 24 extending on the sidewall 230 is also in an inclined state, and the other portion of the gate insulating layer 13 extends to a portion of the second ohmic contact structure 22 away from the first boss. 23 and covers the semiconductor structure 24 located above the second surface 232 of the first boss 23 .
  • a part of the gate electrode 25 is laid flat on the horizontally arranged gate insulating layer 13 , and a part of the gate electrode 25 is placed on the gate insulating layer 13 in an inclined state, and is also in an inclined state. , another part of the gate electrode 25 extends to a side surface of the gate insulating layer 13 away from the second ohmic contact structure 22 .
  • the orthographic projection of the gate 25 on the sidewall 230 can cover the orthographic projection of the channel portion 240 on the sidewall 230 , thus ensuring the control of the channel portion 240 by the gate 25 .
  • the first ohmic contact structure 21 has a first sidewall 210 adjacent to the sidewall 230 , and the semiconductor structure 24 is in contact with the first sidewall 210 .
  • a side surface of the first ohmic contact structure 21 close to the first boss 23 completely overlaps with the first surface 231 of the first boss 23 .
  • the first ohmic contact structure 21 has an inclined first side wall 210 at one end close to the semiconductor structure 24, and the first side wall 210 is adjacent to the side wall 230 of the first boss 23, The semiconductor structure 24 is in contact with the first sidewall 210 .
  • first side wall 210 and the side wall 230 are both flat surfaces, and the first side wall 210 and the side wall 230 of the first boss 23 are in contact with the substrate.
  • the included angle between the planes 10 may be the same, that is, the first side wall 210 and the side wall 230 are on the same inclined plane.
  • the side wall 230 may also be an arc surface, a non-planar surface with a plurality of protrusions or depressions, or other special-shaped surfaces, and the arc surface may be recessed into the first boss 23 .
  • the arc surface can also be an outwardly protruding arc surface, and there is no restriction here.
  • the semiconductor structure 24 is configured to extend along the sidewall 230 to a side surface of the second ohmic contact structure 22 away from the first boss 23 .
  • a side surface of the second ohmic contact structure 22 close to the first boss 23 completely overlaps with the second surface 232 of the first boss 23 .
  • the second ohmic contact structure 22 has an inclined second side wall 220 at one end close to the semiconductor structure 24, and the second side wall 220 is adjacent to the side wall 230 of the first boss 23,
  • the semiconductor structure 24 may be in contact with the second sidewall 220 and extend along the second sidewall 220 to a side surface of the second ohmic contact structure 22 away from the first boss 23 .
  • the semiconductor structure 24 may have a first part 241 , a second part 242 and a third part 243 , and the first part 241 may be disposed on the substrate 10 and/or the first ohmic On the contact structure 21 , the second portion 242 can be disposed on the side wall 230 , and the third portion 243 can be disposed on a side of the second ohmic contact structure 22 away from the first boss 23 On the surface.
  • the first portion 241 can be laid flat on a side surface of the buffer layer 11 away from the substrate 10 .
  • the first portion 241 It can be directly laid flat on the substrate 10 .
  • the second portion 242 is not only disposed on the side wall 230 , but also can be disposed on the first side wall 210 and the second side wall 220 to connect with the first ohmic contact structure 21 and the second side wall 220 respectively.
  • the third portion 243 can be laid flat on a side surface of the second ohmic contact structure 22 away from the first boss 23 .
  • the semiconductor structure 24 by extending the distribution range of the semiconductor structure 24 in the B-B direction, it extends to the buffer layer 11 on the side of the first ohmic contact structure 21 and the side of the second ohmic contact structure 22 away from the substrate 10 On the surface, it is easier to implement on the existing process and can reduce the accuracy requirements for the exposure machine.
  • the semiconductor structure 24 may only have the second portion 242 , that is, the semiconductor structure 24 may only be disposed on the first sidewall 210 , the sidewall 230 , and the second sidewall 220 .
  • the first part 241 and the third part 243 may be arranged parallel to each other and form a certain angle with the second part 242 .
  • the amorphous silicon in the semiconductor structure 24 is annealed by excimer laser
  • a seed crystal may be formed at the corner of the first part 241 and the second part 242 , and the seed crystal may be formed along the side wall of the first boss 23 230 growth, by controlling the length of the sidewall 230 between 0.01 micron and 1 micron, the channel length L of the thin film transistor can be controlled between 0.01 micron and 1 micron, so that the semiconductor structure 24 can be Only one crystal grain exists in the channel portion 240 .
  • the entire active layer is on the same plane. Due to the limitations of exposure and etching processes, the channel length is generally more than 2 microns, and there are many grain boundaries in the channel, so the mobility of the thin film transistor is relatively low. Low.
  • the existing process can be used to shorten the channel length of the thin film transistor to Between 0.01 micron and 1 micron, and the channel is composed of a single crystal grain, without grain boundaries, which can greatly increase the mobility of the thin film transistor while reducing the size of the thin film transistor.
  • angle ⁇ between the side wall 230 and the plane of the substrate 10 is between 45 degrees and 90 degrees.
  • the angle ⁇ between the side wall 230 and the plane where the substrate 10 is located can be 45 degrees, 60 degrees, 75 degrees, 80 degrees or 90 degrees, etc., so that the side wall 230 of the first boss 23 can form a corner with the plane where the substrate 10 or the buffer layer 11 is located, and ensure that during the ELA process, a seed crystal growing along the side wall 230 can be formed at the corner between the first part 241 and the second part 242.
  • a thickness H of the first boss 23 in the thickness direction of the display panel is between 0.0071 micrometers and 1 micrometer.
  • the channel length L of the thin film transistor 20 is equal to the length of the sidewall 230 of the first boss 23 , and the channel length L of the thin film transistor 20 depends on the first boss 23
  • the channel length L of the thin film transistor can be made to be between 0.01 micron and 1 micron, thereby ensuring that only one crystal grain exists in the channel of the thin film transistor.
  • the display panel further includes an interlayer dielectric layer 14 , a source electrode 26 and a drain electrode 27 .
  • the interlayer dielectric layer 14 is disposed on a side of the gate insulating layer 13 away from the substrate 10 and covers the gate 25 .
  • the source electrode 26 and the drain electrode 27 are both disposed on a side of the interlayer dielectric layer 14 away from the substrate 10 , and one of the source electrode 26 and the drain electrode 27 is electrically connected to the The first ohmic contact structure 21, the other one of the source electrode 26 and the drain electrode 27 is electrically connected to the second ohmic contact structure 22.
  • the thin film transistor 20 can be made of, but is not limited to, the source electrode 26 , the drain electrode 27, the first ohmic contact structure 21, the second ohmic contact structure 22, the semiconductor structure 24 and the gate electrode 25 are composed.
  • the first ohmic contact structure 21 includes a body part 211 and an overlapping part 213 .
  • the body part 211 is provided between the first boss 23 and the substrate 10 .
  • the portion 213 is connected to the main body portion 211 , and the orthographic projection of the overlapping portion 213 on the substrate 10 does not overlap with the orthographic projection of the first boss 23 on the substrate 10 .
  • the overlapping portion 213 and the body portion 211 are part of the first ohmic contact structure 21 .
  • the overlapping portion 213 can be regarded as the body portion 211 in the first ohmic contact structure 21 .
  • the drain electrode 27 passes through the interlayer dielectric layer 14 and the gate insulating layer 13 and the overlapping portion 213
  • the source electrode 26 passes through the interlayer dielectric layer 14 and the gate insulating layer 13 and contacts the surface of the second ohmic contact structure 22 away from the substrate 10 . Surface contact on one side.
  • FIG. 4 is a plan schematic diagram of the second thin film transistor provided in the embodiment of the present application
  • FIG. 5 is a cross-sectional schematic diagram of the second thin film transistor provided in the embodiment of the present application along the B-B direction
  • FIG. 6 is a cross-sectional schematic diagram of the second thin film transistor provided in the embodiment of the present application along the A-A direction.
  • the structure of the second display panel shown in FIG. 4 to 6 is substantially the same as the structure of the first display panel shown in FIG.
  • the first ohmic contact structure 21 includes a main body portion 211 and a protruding portion 212, the main body portion 211 is arranged between the first boss 23 and the substrate 10, the protruding portion 212 is connected to the main body portion 211, and the orthographic projection of the protruding portion 212 on the substrate 10 does not overlap with the orthographic projection of the first boss 23 on the substrate 10.
  • the protruding portion 212 and the body portion 211 are part of the first ohmic contact structure 21 , and the protruding portion 212 can be regarded as a component of the first ohmic contact structure 21 .
  • One end of the body portion 211 extends beyond a portion of the edge of the first boss 23 , and the semiconductor structure 24 is in contact with a surface of the protruding portion 212 away from the substrate 10 .
  • the semiconductor structure 24 is in contact with the first sidewall 210 of the first ohmic contact structure 21 , and the contact area is relatively small.
  • the semiconductor structure 24 is in contact with the first sidewall 210 of the first ohmic contact structure 21 .
  • the first ohmic contact structure 21 is in contact with the surface of the side of the protruding portion 212 beyond the edge of the first boss 23 away from the substrate 10 , and the contact area is relatively large. In this way, by increasing the size of the semiconductor structure 24 and the The contact area of the first ohmic contact structure 21 reduces the risk of poor contact between the semiconductor structure 24 and the first ohmic contact structure 21 .
  • the first portion 241 of the semiconductor structure 24 may be disposed on the substrate 10 and the first ohmic contact structure 21 .
  • being disposed on the substrate 10 may refer to direct contact with the substrate 10 , or may refer to indirect contact with the substrate 10 .
  • the first portion 241 of the semiconductor structure 24 is disposed on a side of the buffer layer 11 facing away from the substrate 10 and a side of the protruding portion 212 facing away from the substrate 10 .
  • the semiconductor structure 24 can be in contact with the side surface of the protruding portion 212 away from the substrate 10 and the first side wall 210 of the protruding portion 212 at the same time, which can further increase the The contact area between the semiconductor structure 24 and the first ohmic contact structure 21 is increased.
  • the first portion 241 of the semiconductor structure 24 may also be disposed only on a side surface of the protruding portion 212 of the first ohmic contact structure 21 facing away from the substrate 10 , so that The contact area with the first ohmic contact structure 21 can also be increased.
  • the length L1 of the protruding portion 212 is between 0.5 microns and 3 microns.
  • the length L1 of the protruding portion 212 may be 0.5 micrometer, 0.8 micrometer, 1 micrometer, 1.5 micrometer, 2 micrometer, 2.5 micrometer, or 3 micrometer. This ensures that a corner can be formed between the protruding portion 212 and the side wall 230 of the first boss 23 , and enables the semiconductor structure 24 to form an edge along all directions at the corner of the protruding portion 212 and the side wall 230 .
  • the seed crystal grown on the sidewall 230 ensures that there is only one crystal grain in the channel of the thin film transistor.
  • FIG. 7 is a schematic plan view of the third thin film transistor provided by an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of the third thin film transistor provided by an embodiment of the present application along the B-B direction.
  • FIG. 9 A schematic cross-sectional view of the third thin film transistor along the A-A direction provided in the embodiment of the present application, the structure of the third display panel shown in Figures 7 to 9 and the structure of the second display panel shown in Figures 4 to 6 Roughly the same, the difference is that the first boss 23 has two opposite side walls 230 , the semiconductor structure 24 is disposed on both side walls 230 , and the semiconductor structure 24 is located on the two side walls 230 .
  • the gate electrode 25 is on the side facing away from the substrate 10 .
  • the first boss 23 includes two opposite side walls 230a and 230b.
  • the semiconductor structure 24 is disposed on both the side wall 230a and the side wall 230b.
  • the semiconductor structures 24 on 230b are all in contact with the first ohmic contact structure 21 and the second ohmic contact structure 22 .
  • the gate 25 is provided on the side of the semiconductor structure 24 on the side wall 230a that is away from the substrate 10.
  • the side of the semiconductor structure 24 on the side wall 230b that is away from the substrate 10 is also provided with a gate electrode.
  • the gate 25 can control the semiconductor structures 24 on the sidewalls 230a and 230b respectively through the two gates on both sides of the first boss 23. This is equivalent to dividing the semiconductor structures on both sides of the first boss 23. 24 channels are connected in parallel to increase the equivalent channel width of the thin film transistor, thereby increasing the on-state current of the thin film transistor.
  • the charging time of the pixel capacitor can be reduced, which is beneficial to improving the refresh rate of the display panel.
  • the semiconductor structure 24 is continuously disposed on the two sidewalls 230 of the first boss 23 and the second ohmic contact structure 22 .
  • the semiconductor structure 24 is configured from one side of the first boss 23 , through the sidewall 230 a and the side of the second ohmic contact structure 22 away from the first boss in sequence.
  • One side surface of the platform 23 extends to the side wall 230b on the other side of the first boss 23 .
  • the gate 25 is on the semiconductor structure 24 on the two sidewalls 230 of the first boss 23 and on a side of the second ohmic contact structure 22 away from the substrate 10 .
  • the semiconductor structures 24 are arranged continuously on the side.
  • the gate 25 is configured from one side of the first boss 23 to passing through the sidewall 230 a and the second ohmic contact structure 22 away from the third side.
  • One side surface of a boss 23 extends to the side wall 230b on the other side of the first boss 23, and the orthographic projection of the gate 25 on the substrate 10 can cover the semiconductor structure. 24 on the substrate 10. From the perspective of the thin film transistor array, by connecting the gate electrodes 25 on opposite sides of the first boss 23 together, an uninterrupted scanning line can be used to simultaneously control the gate electrodes located on the opposite sides of each first boss 23. gate, thereby simplifying the patterning complexity of the gate metal layer.
  • the semiconductor structures 24 located on both sides of the first boss 23 may also be disconnected from each other on a side surface of the second ohmic contact structure 22 away from the first boss 23 .
  • the gates 25 located on both sides of the first boss 23 may also be disconnected from each other and spaced apart on a side surface of the second ohmic contact structure 22 away from the first boss 23 .
  • FIG. 10 is a schematic plan view of the fourth thin film transistor provided by an embodiment of the present application
  • FIG. 11 is a schematic diagram of the fourth thin film transistor provided by an embodiment of the present application along B-B.
  • 12 is a schematic cross-sectional view along the A-A direction of the fourth thin film transistor provided by the embodiment of the present application.
  • the structure of the fourth display panel shown in Figures 10 to 12 is the same as that shown in Figures 7 to 9
  • the structure of the third display panel is roughly the same. The difference is that the display panel also includes a second boss 28, a third ohmic contact structure 29 and two fourth ohmic contact structures 30.
  • the third ohmic contact structure 29 is provided on the substrate 10
  • the second boss 28 is provided on a side of the third ohmic contact structure 29 away from the substrate 10
  • the fourth ohmic contact structure 30 is provided on the second The side of the boss 28 facing away from the third ohmic contact structure 29 .
  • the third ohmic contact structure 29 and the first ohmic contact structure 21 are arranged in the same layer, and both are arranged on the side surface of the buffer layer 11 away from the substrate 10 .
  • the second boss 28 is disposed on a side of the third ohmic contact structure 29 away from the substrate 10
  • the fourth ohmic contact structure 30 is disposed on a side of the second boss 28 away from the third ohmic contact.
  • the structure of the second boss 28 may refer to the structure of the first boss 23 in the above embodiment, and the structure of the semiconductor structure on the boss 28 may also refer to the first boss 23 in the above embodiment.
  • the structure of the corresponding semiconductor structure 24 on the stage 23 will not be described again here.
  • the structure of the second boss 28 may be the same as that of the first boss 23, with two inclined side walls disposed oppositely, and the semiconductor structure 24 may be disposed at least on the first boss 23. on the side wall of the second boss 28 and in contact with the third ohmic contact structure 29 and the fourth ohmic contact structure 30 respectively.
  • the gate 25 is also provided on the side of the semiconductor structure 24 away from the substrate 10 .
  • One of the source electrode 26 and the drain electrode 27 is electrically connected to the first ohmic contact structure 21 and the third ohmic contact structure 29
  • the other one of the source electrode 26 and the drain electrode 27 is electrically connected to the first ohmic contact structure 21 and the third ohmic contact structure 29
  • One is electrically connected to the second ohmic contact structure 22 and the fourth ohmic contact structure 30 .
  • the thin film transistor may have a first boss 23 and a second boss 28 at the same time, and the source 26 is connected with the first ohmic contact structure 21 and the third ohmic contact structure 29 connection, the drain electrode 27 is connected to the second ohmic contact structure 22 and the fourth ohmic contact structure 30, and the first ohmic contact structure 21 and the third ohmic contact structure 29 are connected in parallel through the source electrode 26.
  • the drain electrode 27 connects the second ohmic contact structure 22 and the fourth ohmic contact structure 30 in parallel, which can further increase the equivalent channel width of the thin film transistor based on the embodiment shown in FIGS. 7 to 9 .
  • the thin film transistor may also include three or more bosses and corresponding ohmic contact structures on both sides of the boss. By connecting the channels corresponding to multiple bosses in parallel, the film can be further enlarged. The equivalent channel width of transistor 20. The number of bosses in the thin film transistor and corresponding ohmic contact structures on both sides of the boss can be selected according to actual needs, and there is no limit here.
  • the semiconductor structure 24 is on the first boss 23 and the second boss 28 and the area between the first boss 23 and the second boss 28 Continuous setting.
  • the semiconductor structure 24 passes from the side of the first boss 23 away from the second boss 28 , through the first boss 23 and the first boss 28 .
  • the area between the platform 23 and the second boss 28 extends to a side of the second boss 28 away from the first boss 23 .
  • the gate 25 is on the semiconductor structure 24 corresponding to the first boss 23 and the second boss 28, and between the first boss 23 and the second boss 28.
  • the semiconductor structures 24 are continuously arranged.
  • the gate 25 passes from the side of the first boss 23 away from the second boss 28 , passes through the first boss 23 , and the first boss 23 .
  • the area between the platform 23 and the second boss 28 extends to the side of the second boss 28 away from the first boss 23 , and the orthographic projection of the grid 25 on the substrate 10
  • the orthographic projection of the semiconductor structure 24 on the substrate 10 may be covered. From the perspective of the thin film transistor array, by connecting the gate electrodes 25 on the first boss 23 and the second boss 28 together, an uninterrupted scan line can be used to simultaneously control the first boss 23 and the second boss 28 .
  • the gate electrode 25 is on the two bosses 28, thereby simplifying the patterning complexity of the gate metal layer.
  • the semiconductor structure 24 in the area between the first boss 23 and the second boss 28 can also be disconnected from each other and arranged at intervals.
  • the gate electrodes 25 can also be disconnected from each other and arranged at intervals in the area between the first boss 23 and the second boss 28 .
  • the display panel further includes a gate insulating layer 13 and an interlayer dielectric layer 14.
  • the gate insulating layer 13 is disposed on a side of the semiconductor structure 24 away from the substrate 10 and covers the semiconductor.
  • structure 24 , the second ohmic contact structure 22 , the first boss 23 and the first ohmic contact structure 21 , the gate 25 is disposed on a side of the gate insulating layer 13 away from the substrate 10 .
  • the interlayer dielectric layer 14 is disposed on a side of the gate insulating layer 13 away from the substrate 10 and covers the gate electrode 25 .
  • the source electrode 26 and the drain electrode 27 are both disposed on a side of the interlayer dielectric layer 14 away from the substrate 10 , and one of the source electrode 26 and the drain electrode 27 passes through the
  • the interlayer dielectric layer 14 and the gate insulating layer 13 are in contact with the first ohmic contact structure 21 , and the other one of the source electrode 26 and the drain electrode 27 passes through the interlayer dielectric layer 14 and the first ohmic contact structure 21 .
  • the gate insulating layer 13 is in contact with the second ohmic contact structure 22 .
  • the display panel further includes a light-shielding structure 12 disposed on a side of the first ohmic contact structure 21 close to the substrate 10 , and the semiconductor
  • the structure 24 includes a channel portion 240 disposed opposite the side wall 230 .
  • the orthographic projection of the light-shielding structure 12 on the substrate 10 covers the orthographic projection of the channel portion 240 on the substrate 10 .
  • the light-shielding structure 12 blocks the channel portion 240 to prevent light from passing through the substrate 10 .
  • Side illumination is directed to the channel portion 240 , thereby preventing light from affecting the electrical performance of the thin film transistor 20 .
  • a corresponding light-shielding structure is provided below each of the channel portions 240 . 12.
  • the embodiment of the present application also provides a method for manufacturing the display panel, as shown in conjunction with Figures 13a to 13g.
  • Figures 13a to 13g illustrate the production of the display panel provided in the embodiments of the present application.
  • the manufacturing method of the display panel includes:
  • Step S1 Form the light-shielding structure 12 on the substrate 10;
  • Step S2 Form a buffer layer 11 on the substrate 10, and sequentially form a first ohmic contact layer, an insulating layer, and a second ohmic contact layer on the buffer layer 11.
  • the insulating layer and the second ohmic contact layer are etched to form the first ohmic contact structure 21 , the first boss 23 and the second ohmic contact structure 22 .
  • the material of the buffer layer 11 may include but is not limited to any one or a combination of silicon nitride, silicon oxide, or silicon oxynitride.
  • step S20 as shown in FIG. 13b, the first ohmic contact structure 21 is disposed on the buffer layer 11, and the first boss 23 is disposed on a side of the first ohmic contact structure 21 away from the buffer layer 11.
  • the second ohmic contact structure 22 is disposed on a side of the first boss 23 away from the first ohmic contact structure 21 .
  • the first boss 23 has a side wall 230 , and an angle ⁇ between the side wall 230 and a plane where the substrate 10 is located is between 45 degrees and 90 degrees.
  • the first ohmic contact structure 21 has a first side wall 210 which is adjacent to the side wall 230 .
  • the second ohmic contact structure 22 has a second side wall 220 .
  • the side wall 220 is adjacent to the side wall 230 .
  • the angle between the first side wall 210 and the second side wall 220 and the plane of the substrate may be the same as the angle between the side wall 230 and the substrate 10 .
  • the angle ⁇ between the planes is equal, that is, the first side wall 210 , the side wall 230 and the second side wall 220 are on the same inclined plane.
  • the first ohmic contact layer and the second ohmic contact layer are both made of N-type heavily doped amorphous silicon material.
  • the layers can be doped with impurity elements such as phosphorus or arsenic.
  • the insulating layer may be made of commonly used inorganic insulating materials such as silicon nitride, silicon oxide or silicon oxynitride.
  • step S20 chemical vapor deposition (chemical vapor deposition) can be used to The first ohmic contact layer, the insulating layer, and the second ohmic contact layer are sequentially deposited using a vapor deposition (CVD) method.
  • CVD vapor deposition
  • Step S3 Etch the first ohmic contact structure 21, the first boss 23 and the second ohmic contact structure 22, so that the second ohmic contact structure 22 and the first boss 23 are etched. Partially etched, the first ohmic contact structure 21 is not etched.
  • Step S4 Form an amorphous silicon layer on the buffer layer 11.
  • the amorphous silicon layer covers the first ohmic contact structure 21, the first boss 23 and the second ohmic contact structure 22. ; Perform a crystallization process on the amorphous silicon layer, and then pattern it to form a semiconductor structure 24;
  • the amorphous silicon layer can be crystallized through an excimer laser annealing process, so that the amorphous silicon in the amorphous silicon layer can be converted into a polycrystalline silicon structure, and then the polycrystalline silicon structure can be etched. , forming the semiconductor structure 24.
  • the first ohmic contact structure 21 and the second ohmic contact structure 22 can still maintain the amorphous silicon structure.
  • the amorphous silicon layer may form a seed crystal at the corner of the buffer layer 11 and the side wall 230 of the first boss 23 . Crystals can grow along the direction of the sidewall 230. By controlling the length of the sidewall 230 between 0.01 micron and 1 micron, only one crystal grain can exist in the semiconductor structure 24 on the sidewall 230. .
  • Step S5 Form a gate insulating layer 13 on the semiconductor structure 24.
  • the gate insulating layer 13 covers the semiconductor structure 24, the first ohmic contact structure 21, the first boss 23 and the the second ohmic contact structure 22; forming a gate electrode 25 on the gate insulating layer 13;
  • Step S6 Form an interlayer dielectric layer 14 on the gate insulating layer 13, and the interlayer dielectric layer 14 covers the gate electrode 25; form a first via hole OH1 and a first via hole OH1 on the interlayer dielectric layer 14.
  • Step S7 Form a source electrode 26 and a drain electrode 27 on the interlayer dielectric layer 14.
  • the drain electrode 27 passes through the first via hole OH1 and contacts the first ohmic contact structure 21.
  • 26 passes through the second via hole OH2 and contacts the second ohmic contact structure 22 .
  • the manufacturing method of the display panel provided by the embodiment of the present application only takes the structure of the first display panel shown in Figures 1 to 3 as an example.
  • the manufacturing method of the display panel in other embodiments can refer to Figure 13a
  • the manufacturing method of the display panel shown in Figure 13b will not be described in detail here.
  • Embodiments of the present application provide a display panel, which includes a substrate and a first ohmic contact structure, a first boss, and a second ohmic contact structure that are stacked on the substrate.
  • a semiconductor structure and a gate electrode, the first boss has at least one sidewall, by disposing the semiconductor structure on the sidewall of the first boss and being connected to the first ohmic contact structure and the gate electrode respectively.
  • the second ohmic contact structure contact can use existing processes to shorten the length of the channel in the semiconductor structure and reduce the volume of the thin film transistor, thereby improving the integration of the thin film transistor in the display panel.

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本申请提供一种显示面板，该显示面板包括基板和层叠设置于基板上的第一欧姆接触结构、第一凸台、第二欧姆接触结构、半导体结构和栅极，第一凸台具有至少一个侧壁，通过将半导体结构设置于第一凸台的侧壁上，可以利用现有的工艺缩短沟道的长度，并减小薄膜晶体管的体积，从而可以提高显示面板内的薄膜晶体管的集成度。

Description

显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
将像素驱动电路、栅极驱动电路、源极驱动电路、时序控制器等电路集成在玻璃基板上（system on glass，SOG），可以极大提高显示面板的集成度，降低对于集成电路芯片的依赖性，可以降低成本。
 技术问题
实现SOG需要提高现有显示面板中的薄膜晶体管的集成度、最大工作频率和电流密度，这些都要求薄膜晶体管具有更短的沟道长度、更高的迁移率和更小的体积。
综上所述，现有显示面板存在现有的工艺无法减小薄膜晶体管的沟道长度和体积的问题。故，有必要提供一种显示面板来改善这一缺陷。
 技术解决方案
本申请实施例提供一种显示面板，可以利用现有的工艺减小薄膜晶体管的沟道长度和薄膜晶体管的体积，增大薄膜晶体管的开态电流，提高显示面板内薄膜晶体管的集成度。
本申请实施例提供一种显示面板，包括：
基板；
第一欧姆接触结构，设置于所述基板上；
第一凸台，设置于所述第一欧姆接触结构的背离所述基板的一侧，所述第一凸台具有至少一个侧壁；
第二欧姆接触结构，设置于所述第一凸台的背离所述第一欧姆接触结构的一侧；
半导体结构，至少设置于所述侧壁上，并且分别与所述第一欧姆接触结构和所述第二欧姆接触结构接触；以及
栅极，设置于所述半导体结构的背离所述基板的一侧。
根据本申请一实施例，所述第一欧姆接触结构具有邻接于所述侧壁的第一侧壁，所述半导体结构与所述第一侧壁接触。
根据本申请一实施例，所述第一欧姆接触结构包括：
本体部，设置于所述第一凸台与所述基板之间；以及
凸出部，与所述本体部连接，所述凸出部在所述基板上的正投影与所述第一凸台在所述基板上的正投影不重叠，所述半导体结构与所述凸出部的背离所述基板的一侧表面接触。
根据本申请一实施例，所述凸出部的长度介于0.5微米至3微米之间。
根据本申请一实施例，包括：
第一部，设置于所述基板和/或所述第一欧姆接触结构上；
第二部，设置于所述侧壁上，且与所述第一部连接；以及
第三部，设置于所述第二欧姆接触结构的背离所述第一凸台的一侧，且与所述第二部连接。
根据本申请一实施例，所述侧壁与所述基板所在平面之间的夹角介于45度至90度之间。
根据本申请一实施例，所述第一凸台具有两个相对设置的所述侧壁，两个所述侧壁上均设置有所述半导体结构、以及位于所述半导体结构的背离所述基板一侧的所述栅极；
其中，两个所述侧壁上的所述半导体结构均与所述第一欧姆接触结构和所述第二欧姆接触结构接触。
根据本申请一实施例，所述半导体结构在所述第一凸台的两个所述侧壁、以及所述第二欧姆接触结构上连续设置。
根据本申请一实施例，所述栅极在所述基板上的正投影覆盖所述半导体结构在所述基板上的正投影。
根据本申请一实施例，所述显示面板包括：
第三欧姆接触结构，设置于所述基板上；
第二凸台，设置于所述第三欧姆接触结构的背离所述基板的一侧；以及
第四欧姆接触结构，设置于所述第二凸台的背离所述第一欧姆接触结构的一侧，所述半导体结构至少设置于所述第二凸台的侧壁上，且分别与所述第三欧姆接触结构和所述第四欧姆接触结构接触；
其中，所述显示面板还包括源极和漏极，所述源极和所述漏极的其中之一电连接于所述第一欧姆接触结构和所述第三欧姆接触结构，所述源极和所述漏极的其中另一电连接于所述第二欧姆接触结构和所述第四欧姆接触结构。
根据本申请一实施例，所述半导体结构在所述第一凸台和所述第二凸台上、以及所述第一凸台与所述第二凸台之间的区域连续设置。
根据本申请一实施例，所述栅极在所述基板上的正投影覆盖所述半导体结构在所述基板上的正投影。
根据本申请一实施例，所述显示面板还包括栅极绝缘层和层间介质层，所述栅极绝缘层至少设置于所述栅极与所述半导体结构之间，并且覆盖所述第二欧姆接触结构和所述第一欧姆接触结构，所述层间介质层设置于所述栅极绝缘层的背离所述基板的一侧，并且覆盖所述栅极；
其中，所述显示面板还包括源极和漏极，所述源极和所述漏极均设置于所述层间介质层的背离所述基板的一侧，所述源极和所述漏极的其中之一穿过所述层间介质层和所述栅极绝缘层与所述第一欧姆接触结构接触，所述源极和所述漏极的其中另一穿过所述层间介质层和所述栅极绝缘层与所述第二欧姆接触结构接触。
根据本申请一实施例，所述显示面板还包括遮光结构，所述遮光结构设置于所述第一欧姆接触结构的靠近所述基板的一侧，所述半导体结构包括连接于所述第一欧姆接触结构与第二欧姆接触结构之间；
其中，所述遮光结构在所述基板上的正投影覆盖所述沟道部在所述基板上的正投影。
根据本申请一实施例，所述沟道部沿所述侧壁延伸方向上的长度介于0.01微米至1微米之间。
根据本申请一实施例，所述第一凸台在所述显示面板的厚度方向上的厚度介于0.0071微米至1微米之间。
根据本申请一实施例，所述第一凸台为单层或者多层结构。
根据本申请一实施例，所述第一凸台的材料包括氮化硅、氧化硅、氮氧化硅中的一种或者多种的组合。
根据本申请一实施例，所述第一凸台的材料包括丙烯酸基树脂、环氧树脂、酚醛树脂、聚酰胺基树脂、聚酰亚胺基树脂、不饱和聚酯树脂、聚丙烯酸酯、聚碳酸酯类、聚酰亚胺、聚苯乙烯类中的一种或者多种的组合。
根据本申请一实施例，所述侧壁为平面或者弧面。
 有益效果
本揭示实施例的有益效果：本申请实施例提供一种显示面板，所述显示面板包括基板和层叠设置于所述基板上的第一欧姆接触结构、第二欧姆接触结构、半导体结构和栅极，所述第一凸台具有至少一个侧壁，通过将所述半导体结构设置于所述第一凸台的所述侧壁上，并且分别与所述第一欧姆接触结构和所述第二欧姆接触结构接触，可以利用现有的工艺缩短薄膜晶体管的沟道长度，并减小薄膜晶体管的体积，从而可以提高显示面板内的薄膜晶体管的集成度。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的第一种薄膜晶体管的平面示意图；
图2为本申请实施例提供的第一种薄膜晶体管沿B-B方向的截面示意图；
图3为本申请实施例提供的第一种薄膜晶体管沿A-A方向的截面示意图；
图4为本申请实施例提供的第二种薄膜晶体管的平面示意图；
图5为本申请实施例提供的第二种薄膜晶体管沿B-B方向的截面示意图；
图6为本申请实施例提供的第二种薄膜晶体管沿A-A方向的截面示意图；
图7为本申请实施例提供的第三种薄膜晶体管的平面示意图；
图8为本申请实施例提供的第三种薄膜晶体管沿B-B方向的截面示意图；
图9为本申请实施例提供的第三种薄膜晶体管沿A-A方向的截面示意图；
图10为本申请实施例提供的第四种薄膜晶体管的平面示意图；
图11为本申请实施例提供的第四种薄膜晶体管沿B-B方向的截面示意图；
图12为本申请实施例提供的第四种薄膜晶体管沿A-A方向的截面示意图；
图13a至图13g为本申请实施例提供的显示面板的制作方法的流程示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种显示面板，可以利用现有的工艺减小薄膜晶体管的沟道长度和薄膜晶体管的体积，增大薄膜晶体管的开态电流，提高显示面板内薄膜晶体管的集成度。
所述显示面板包括基板10和设置于所述基板10上的多个薄膜晶体管20。所述薄膜晶体管20可以应用于所述显示面板的像素驱动电路、栅极驱动电路、源极驱动电路、时序控制器等至少一个电路模块中。
需要说明的是，设置于所述基板10上可以指的是与所述基板10直接接触，也可以指的是与所述基板10间接接触。
结合图1和图3所述，图1为本申请实施例提供的第一种薄膜晶体管的平面示意图，图2为本申请实施例提供的第一种薄膜晶体管沿B-B方向的截面示意图，图3为本申请实施例提供的第一种薄膜晶体管沿A-A方向的截面示意图，所述显示面板还可以包括缓冲层11，所述缓冲层11设置于所述基板10靠近所述薄膜晶体管20一侧的表面上，所述薄膜晶体管20设置于所述缓冲层11上。
进一步的，所述显示面板包括第一欧姆接触结构21、第一凸台23、第二欧姆接触结构22、半导体结构24和栅极25。
所述第一欧姆接触结构21设置于所述基板10上。例如，所述第一欧姆接触结构21可以设置于所述缓冲层11的背离所述基板10的一侧表面上。
所述第一欧姆接触结构21的材料为N型重掺杂非晶硅材料，所述第一欧姆接触结构21内可以掺杂有磷或砷等元素杂质。
所述第一凸台23设置于所述第一欧姆接触结构21的背离所述基板10的一侧。
所述第一凸台23的材料可以为无机绝缘材料或者有机绝缘材料所形成的单层或者多层结构。当所述第一凸台23为多层结构时，所述第一凸台23可以是由多层相同的材料依次叠加所形成的叠层结构，也可以是由至少两种不同的材料叠加所形成的叠层结构。
例如，所述第一凸台23的材料可以为氮化硅、氧化硅或者氮氧化硅等常用的无机绝缘材料，所述第一凸台23的材料也可以为丙烯酸基树脂、环氧树脂、酚醛树脂、聚酰胺基树脂、聚酰亚胺基树脂、不饱和聚酯树脂、聚丙烯酸酯、聚碳酸酯类、聚酰亚胺、聚苯乙烯类中的任意一种或者两种及以上的组合材料。
所述第二欧姆接触结构22设置于所述第一凸台23的背离所述第一欧姆接触结构21的一侧。
所述第二欧姆接触结构22的材料为N型重掺杂非晶硅材料，所述第二欧姆接触结构22内可以掺杂有磷或砷等元素杂质。
进一步的，所述第一凸台23具有至少一个侧壁230，所述半导体结构24至少设置于所述侧壁230上，并且分别与所述第一欧姆接触结构21和所述第二欧姆接触结构22接触。
在其中一个实施例中，所述第一凸台23可以具有相对设置的第一表面231和第二表面232，所述第一表面231可以与所述第二表面232相互平行设置，所述第二表面232可以设置于所述第一表面231的背离所述基板10的一侧。
所述第一表面231可以与所述第一欧姆接触结构21的背离所述基板10的一侧表面直接接触，所述第二欧姆接触结构22可以设置于所述第二表面232背离所述基板10的一侧上，并且可以与所述第二表面232直接接触。
所述侧壁230设置于所述第一表面231和所述第二表面232之间，并且分别连接于所述第一表面231和所述第二表面232。所述侧壁230呈倾斜状态设置，并且与所述第一表面231和所述第二表面232之间形成一定的夹角。
所述半导体结构24沿所述侧壁230设置，并且延伸至分别与所述第一欧姆接触结构21和所述第二欧姆接触结构22接触。
所述半导体结构24的材料为非掺杂的多晶硅材料，所述半导体结构24中与所述侧壁230正对设置的沟道部240可以作为所述薄膜晶体管20的沟道，所述沟道部240沿所述侧壁230延伸方向的长度L即为所述薄膜晶体管的沟道长度。
所述栅极25设置于所述半导体结构24的背离所述基板10的一侧。
如图2所示，所述显示面板还包括栅极绝缘层13，所述栅极绝缘层13设置于所述半导体结构24的背离所述基板10的一侧，并且连续地覆盖所述半导体结构24、所述第二欧姆接触结构22、所述第一凸台23、所述第一欧姆接触结构21以及所述缓冲层11。
在所述第一凸台23处，所述栅极绝缘层13的一部分平铺设置于所述缓冲层11以及水平设置的所述半导体结构24上，所述栅极绝缘层13的一部分沿所述半导体结构24在所述侧壁230上的部分延伸设置，并且同样呈倾斜状态，所述栅极绝缘层13的另一部分延伸至所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上，并且覆盖位于所述第一凸台23的第二表面232上方的所述半导体结构24。
所述栅极25的一部分平铺设置于水平设置的所述栅极绝缘层13上，所述栅极25的一部分设置于呈倾斜状态的所述栅极绝缘层13上，并且同样呈倾斜状态，所述栅极25的另一部分延伸至所述栅极绝缘层13的背离所述第二欧姆接触结构22的一侧表面上。
所述栅极25在所述侧壁230上的正投影可以覆盖所述沟道部240在所述侧壁230上的正投影，如此可以保证栅极25对于沟道部240的控制。
在其中一个实施例中，所述第一欧姆接触结构21具有邻接于所述侧壁230的第一侧壁210，所述半导体结构24与所述第一侧壁210接触。
如图2所示，所述第一欧姆接触结构21靠近所述第一凸台23的一侧表面与所述第一凸台23的所述第一表面231完全重叠。所述第一欧姆接触结构21靠近所述半导体结构24的一端具有一个倾斜设置的第一侧壁210，所述第一侧壁210邻接于所述第一凸台23的所述侧壁230，所述半导体结构24与所述第一侧壁210接触。
在其中一个实施例中，所述第一侧壁210和所述侧壁230均为平整表面，所述第一侧壁210和所述第一凸台23的所述侧壁230与所述基板10所在平面之间的夹角可以相同，即所述第一侧壁210与所述侧壁230处于同一倾斜设置的平面上。
在其中一个实施例中，所述侧壁230也可以为弧面、具有多个凸起或凹陷的不平面表面或者其他异形表面，所述弧面可以是向所述第一凸台23内凹陷的弧面，也可以是向外突出的弧面，此处不做限制。
进一步的，所述半导体结构24配置成沿所述侧壁230延伸至所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上。
如图2所示，所述第二欧姆接触结构22靠近所述第一凸台23的一侧表面与所述第一凸台23的所述第二表面232完全重叠。所述第二欧姆接触结构22靠近所述半导体结构24的一端具有一个倾斜设置的第二侧壁220，所述第二侧壁220邻接于所述第一凸台23的所述侧壁230，所述半导体结构24可以与所述第二侧壁220接触，并且沿所述第二侧壁220延伸至所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上。
在其中一个实施例中，所述半导体结构24可以具有第一部241、第二部242和第三部243，所述第一部241可以设置于所述基板10和/或所述第一欧姆接触结构21上，所述第二部242可以设置于所述侧壁230上，所述第三部243可以设置于所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上。
如图2所示，所述第一部241可以平铺设置于所述缓冲层11的背离所述基板10的一侧表面上，当没有设置所述缓冲层11时，所述第一部241可以直接平铺设置于所述基板10上。所述第二部242不仅设置于所述侧壁230上，还可以设置于所述第一侧壁210以及所述第二侧壁220上，以分别与所述第一欧姆接触结构21和所述第二欧姆接触结构22接触，所述第三部243可以平铺设置于所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上。
需要说明的是，通过延长半导体结构24在B-B方向上的分布范围，使其延伸至第一欧姆接触结构21一侧的缓冲层11上、以及第二欧姆接触结构22的背离基板10的一侧表面上，在现有工艺上更易于实现，可以降低对于曝光机的精度要求。
在其中一个实施例中，所述半导体结构24可以仅具有第二部242，即所述半导体结构24可以仅设置于所述第一侧壁210、所述侧壁230以及所述第二侧壁220上。
所述第一部241与所述第三部243可以相互平行设置，并且与所述第二部242之间形成一定的夹角。
在对所述半导体结构24中的非晶硅通过准分子激光退火（excimer laser annealing, ELA）工艺进行结晶处理时，在所述第一部241与所述第二部242的拐角处可以形成籽晶，籽晶可以沿着所述第一凸台23的所述侧壁230生长，通过将所述侧壁230的长度控制在0.01微米至1微米之间，使得薄膜晶体管的沟道长度L可以控制在0.01微米至1微米之间，如此可以使所述半导体结构24的沟道部240内只存在有一个晶粒。
相较于现有低温多晶硅薄膜晶体管中整个有源层在同一平面，受曝光、刻蚀工艺限制，沟道长度一般在2微米以上，且沟道内存在较多晶界，薄膜晶体管的迁移率较低。本申请实施例，通过将薄膜晶体管的沟道（即半导体结构24的沟道部240）形成在第一凸台23的侧壁230上，可以利用现有工艺将薄膜晶体管的沟道长度缩短为0.01微米至1微米之间，且沟道由单颗晶粒构成，不存在晶界，从而可以在减小薄膜晶体管尺寸的同时，大幅提升薄膜晶体管的迁移率。
进一步的，所述侧壁230与所述基板10所在平面之间的夹角θ介于45度至90度之间。
例如，所述侧壁230与所述基板10所在平面之间的夹角θ可以为45度、60度、75度、80度或者90度等，如此可以使第一凸台23的侧壁230与基板10或者缓冲层11所在的平面能够形成拐角，并确保在ELA的过程中，第一部241与第二部242的拐角处能够形成沿所述侧壁230生长的籽晶。
进一步的，所述第一凸台23在所述显示面板的厚度方向上的厚度H介于0.0071微米至1微米之间。
需要说明的是，所述薄膜晶体管20的沟道长度L与所述第一凸台23的侧壁230的长度相等，所述薄膜晶体管20的沟道长度L取决于所述第一凸台23沿所述显示面板的厚度方向上的厚度H以及所述侧壁230与所述基板10所在平面之间的夹角θ，即L=H/sinθ。通过将所述第一凸台23的厚度H限制在0.0071微米至1微米之间，并将所述侧壁230与所述基板10所在平面之间的夹角θ限制在45度至90度之间，可以使得所述薄膜晶体管的沟道长度L介于0.01微米至1微米之间，从而可以确保所述薄膜晶体管的沟道内仅存在有一颗晶粒。
进一步的，所述显示面板还包括层间介质层14、源极26和漏极27，所述层间介质层14设置于所述栅极绝缘层13的背离所述基板10的一侧，并且覆盖所述栅极25。
所述源极26和所述漏极27均设置于所述层间介质层14的背离所述基板10的一侧，所述源极26和所述漏极27的其中之一电连接于所述第一欧姆接触结构21，所述源极26和所述漏极27的其中另一电连接于所述第二欧姆接触结构22，所述薄膜晶体管20可以由但不限于所述源极26、所述漏极27、第一欧姆接触结构21、第二欧姆接触结构22、半导体结构24以及栅极25构成。
如图3所示，所述第一欧姆接触结构21包括本体部211和搭接部213，所述本体部211设置于所述第一凸台23与所述基板10之间，所述搭接部213连接于本体部211，所述搭接部213在所述基板10上的正投影与所述第一凸台23在所述基板10上的正投影不重叠。
所述搭接部213和所述本体部211属于所述第一欧姆接触结构21的其中一部分，可以将所述搭接部213视为所述第一欧姆接触结构21中由所述本体部211沿A-A方向延伸出并且超出所述第一凸台23的一侧边缘的一部分，所述漏极27穿过所述层间介质层14和所述栅极绝缘层13与所述搭接部213的背离所述基板10的一侧表面接触，所述源极26穿过所述层间介质层14和所述栅极绝缘层13与所述第二欧姆接触结构22的背离所述基板10的一侧表面接触。
结合图4至图6所示，图4为本申请实施例提供的第二种薄膜晶体管的平面示意图，图5为本申请实施例提供的第二种薄膜晶体管沿B-B方向的截面示意图，图6为本申请实施例提供的第二种薄膜晶体管沿A-A方向的截面示意图，图4至图6所示的第二种显示面板的结构与图1至图3所示的第一种显示面板的结构大致相同，区别在于：所述第一欧姆接触结构21包括本体部211和凸出部212，所述本体部211设置于所述第一凸台23与所述基板10之间，所述凸出部212与所述本体部211连接，所述凸出部212在所述基板10上的正投影与所述第一凸台23在所述基板10上的正投影不重叠。
需要说明的是，所述凸出部212与所述本体部211属于所述第一欧姆接触结构21的其中一部分，可以将所述凸出部212视为所述第一欧姆接触结构21中由所述本体部211的一端延伸并超出所述第一凸台23的边缘的一部分，所述半导体结构24与所述凸出部212的背离所述基板10的一侧表面接触。
在图2所示的实施例中，半导体结构24与所述第一欧姆接触结构21的第一侧壁210接触，接触面积相对较小，在图4所示的实施例中，半导体结构24与所述第一欧姆接触结构21超出所述第一凸台23边缘的凸出部212的背离所述基板10的一侧表面接触，接触面积相对较大，如此通过增大半导体结构24与所述第一欧姆接触结构21的接触面积，降低半导体结构24与所述第一欧姆接触结构21接触不良的风险。
在其中一个实施例中，所述半导体结构24的第一部241可以设置于基板10和所述第一欧姆接触结构21上。
需要说明的是，设置于所述基板10上可以指的是与所述基板10直接接触，也可以指的是与所述基板10间接接触。
如图2所示，所述半导体结构24的第一部241设置于所述缓冲层11的背离所述基板10的一侧表面上、以及所述凸出部212的背离所述基板10的一侧表面上，所述半导体结构24可以同时与所述凸出部212的背离所述基板10的一侧表面、以及所述凸出部212的所述第一侧壁210接触，如此可以进一步增大所述半导体结构24与所述第一欧姆接触结构21的接触面积。
在其中一个实施例中，所述半导体结构24的第一部241也可以仅设置于所述第一欧姆接触结构21的所述凸出部212的背离所述基板10的一侧表面上，如此同样可以增大与所述第一欧姆接触结构21的接触面积。
进一步的，所述凸出部212的长度L1介于0.5微米至3微米之间。例如，所述凸出部212的长度L1可以为0.5微米、0.8微米、1微米、1.5微米、2微米、2.5微米或者3微米等。如此可以确保凸出部212与第一凸台23的侧壁230之间能够形成拐角，并使所述半导体结构24在所述凸出部212与所述侧壁230的拐角处能够形成沿所述侧壁230生长的籽晶，以此确保薄膜晶体管的沟道内仅存在有一颗晶粒。
结合图7至图9所示，图7为本申请实施例提供的第三种薄膜晶体管的平面示意图，图8为本申请实施例提供的第三种薄膜晶体管沿B-B方向的截面示意图，图9为本申请实施例提供的第三种薄膜晶体管沿A-A方向的截面示意图，图7至图9所示的第三种显示面板的结构与图4至图6所示的第二种显示面板的结构大致相同，区别在于：所述第一凸台23具有相对设置的两个所述侧壁230，两个所述侧壁230上均设置有所述半导体结构24、以及位于所述半导体结构24的背离所述基板10一侧的所述栅极25。
如图8所述，所述第一凸台23包括相对设置的两个所述侧壁230a、230b，侧壁230a和侧壁230b上均设置有所述半导体结构24，侧壁230a和侧壁230b上的所述半导体结构24均与所述第一欧姆接触结构21以及所述第二欧姆接触结构22接触。
所述侧壁230a上的半导体结构24的背离所述基板10的一侧设置有所述栅极25，所述侧壁230b上的半导体结构24的背离所述基板10的一侧也设置有所述栅极25，通过第一凸台23两侧的两部分栅极可以分别对侧壁230a和侧壁230b上的半导体结构24进行控制，如此相当于将第一凸台23两侧的半导体结构24的沟道并联，以此增大薄膜晶体管的等效沟道宽度，从而可以增大薄膜晶体管的开态电流。对于液晶显示面板的像素驱动电路而言，可以减少像素电容的充电时间，有利于提高显示面板的刷新率。
在其中一个实施例中，所述半导体结构24在所述第一凸台23的两个侧壁230、以及所述第二欧姆接触结构22上连续设置。
结合图7至图8所示，所述半导体结构24配置成由第一凸台23的一侧，依次经过所述侧壁230a、以及所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面，延伸至所述第一凸台23的另一侧的所述侧壁230b上。
进一步的，所述栅极25在所述第一凸台23的两个所述侧壁230上的所述半导体结构24上、以及所述第二欧姆接触结构22的背离所述基板10的一侧的所述半导体结构24上连续设置。
结合图7至图8所示，所述栅极25配置成由所述第一凸台23的一侧，依次经过所述侧壁230a、以及所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面，延伸至所述第一凸台23的另一侧的所述侧壁230b上，所述栅极25在所述基板10上的正投影可以覆盖所述半导体结构24在所述基板10上的正投影。从薄膜晶体管阵列的角度看，通过将第一凸台23相对两侧的栅极25连在一起，可以利用一条不断开的扫描线同时控制位于各个所述第一凸台23的相对两侧的栅极，从而可以简化栅极金属层的图案化复杂程度。
在其中一个实施例中，位于所述第一凸台23两侧的所述半导体结构24在所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上也可以相互断开并间隔设置。位于所述第一凸台23两侧的所述栅极25在所述第二欧姆接触结构22的背离所述第一凸台23的一侧表面上也可以相互断开并间隔设置。
在其中一个实施例中，结合图10至图12所示，图10为本申请实施例提供的第四种薄膜晶体管的平面示意图，图11为本申请实施例提供的第四种薄膜晶体管沿B-B方向的截面示意图，图12为本申请实施例提供的第四种薄膜晶体管沿A-A方向的截面示意图，图10至图12所示的第四种显示面板的结构与图7至图9所示的第三种显示面板的结构大致相同，区别在于：所述显示面板还包括第二凸台28、第三欧姆接触结构29和两个所述第四欧姆接触结构30，所述第三欧姆接触结构29设置于所述基板10上，所述第二凸台28设置于所述第三欧姆接触结构29的背离所述基板10的一侧，所述第四欧姆接触结构30设置于所述第二凸台28的背离所述第三欧姆接触结构29的一侧。
如图11所示，所述第三欧姆接触结构29与所述第一欧姆接触结构21同层设置，且均设置于所述缓冲层11的背离所述基板10的一侧表面上，所述第二凸台28设置于所述第三欧姆接触结构29的背离所述基板10的一侧，所述第四欧姆接触结构30设置于所述第二凸台28的背离所述第三欧姆接触结构29的一侧。
所述第二凸台28的结构可以参照上述实施例中所述第一凸台23的结构，所述凸台28上的所述半导体结构的结构同样可以参照上述实施例中所述第一凸台23上对应的所述半导体结构24的结构，此处不做赘述。
在其中一个实施例中，所述第二凸台28的结构可以与所述第一凸台23的结构相同，具有相对设置的两个倾斜的侧壁，所述半导体结构24可以至少设置于所述第二凸台28的侧壁上，并且分别与所述第三欧姆接触结构29和所述第四欧姆接触结构30接触。在所述第二凸台28处，所述半导体结构24的背离所述基板10一侧同样设置有所述栅极25。
所述源极26和所述漏极27的其中之一电连接于所述第一欧姆接触结构21和所述第三欧姆接触结构29，所述源极26和所述漏极27的其中另一电连接于所述第二欧姆接触结构22和所述第四欧姆接触结构30。
例如，在同一所述薄膜晶体管内，所述薄膜晶体管可以同时具有第一凸台23和第二凸台28，所述源极26与第一欧姆接触结构21和所述第三欧姆接触结构29连接，所述漏极27与第二欧姆接触结构22和所述第四欧姆接触结构30连接，通过源极26将所述第一欧姆接触结构21和所述第三欧姆接触结构29并联，通过漏极27将第二欧姆接触结构22和所述第四欧姆接触结构30并联，可以在图7至图9所示实施例的基础上，进一步增大薄膜晶体管的等效沟道宽度。
在其他一些实施例中，所述薄膜晶体管也可以包括3个及以上的凸台以及凸台上下两侧对应的欧姆接触结构，通过将多个凸台对应的沟道并联，可以进一步增大薄膜晶体管20的等效沟道宽度。所述薄膜晶体管内的凸台以及凸台上下两侧对应的欧姆接触结构的数量可以根据实际需求进行选择，此处不做限制。
在其中一个实施例中，所述半导体结构24在所述第一凸台23和所述第二凸台28上、以及所述第一凸台23与所述第二凸台28之间的区域连续设置。
结合图10至图11所示，所述半导体结构24由所述第一凸台23的背离所述第二凸台28的一侧，经过所述第一凸台23、以及所述第一凸台23与所述第二凸台28之间的区域延伸至所述第二凸台28的背离所述第一凸台23的一侧。
进一步的，所述栅极25在第一凸台23和所述第二凸台28对应的所述半导体结构24上、以及所述第一凸台23与所述第二凸台28之间的所述半导体结构24上连续设置。
结合图10至图11所示，所述栅极25由所述第一凸台23的背离所述第二凸台28的一侧，经过所述第一凸台23、以及所述第一凸台23与所述第二凸台28之间的区域延伸至所述第二凸台28的背离所述第一凸台23的一侧，所述栅极25在所述基板10上的正投影可以覆盖所述半导体结构24在所述基板10上的正投影。从薄膜晶体管阵列的角度看，通过将第一凸台23和第二凸台28上的栅极25连接在一起，可以利用一条不断开的扫描线同时控制位于所述第一凸台23和第二凸台28上的栅极25，从而可以简化栅极金属层的图案化复杂程度。
在其中一个实施例中，所述半导体结构24在第一凸台23与第二凸台28之间的区域也可以相互断开并间隔设置。所述栅极25在第一凸台23与第二凸台28之间的区域也可以相互断开并间隔设置。
进一步的，所述显示面板还包括栅极绝缘层13和层间介质层14，所述栅极绝缘层13设置于所述半导体结构24的背离所述基板10的一侧，并且覆盖所述半导体结构24、第二欧姆接触结构22、所述第一凸台23以及所述第一欧姆接触结构21，所述栅极25设置于所述栅极绝缘层13的背离所述基板10的一侧。
所述层间介质层14设置于所述栅极绝缘层13的背离所述基板10的一侧，并且覆盖所述栅极25。
所述源极26和所述27漏极均设置于所述层间介质层14的背离所述基板10的一侧，所述源极26和所述漏极27的其中之一穿过所述层间介质层14和所述栅极绝缘层13与所述第一欧姆接触结构21接触，所述源极26和所述漏极27的其中另一穿过所述层间介质层14和所述栅极绝缘层13与所述第二欧姆接触结构22接触。
在其中一个实施例中，如图2所示，所述显示面板还包括遮光结构12，所述遮光结构12设置于所述第一欧姆接触结构21靠近所述基板10的一侧，所述半导体结构24包括与所述侧壁230正对设置的沟道部240。
所述遮光结构12在所述基板10上的正投影覆盖所述沟道部240在所述基板10上的正投影，利用遮光结构12对沟道部240的遮挡，可以防止光线通过基板10一侧照射至所述沟道部240，从而可以避免光线影响薄膜晶体管20的电学性能。
在其中一个实施例中，结合图8和11所示，当所述薄膜晶体管具有两个及以上的沟道部240时，每个所述沟道部240下方均设置有对应的所述遮光结构12。
依据本申请上述实施例提供的显示面板，本申请实施例还提供一种显示面板的制作方法，结合图13a至图13g所示，图13a至图13g为本申请实施例提供的显示面板的制作方法的流程示意图，所述显示面板的制作方法包括：
步骤S1：在基板10上形成遮光结构12；
步骤S2：在所述基板10上形成缓冲层11，在所述缓冲层11上依次形成第一欧姆接触层、绝缘层、以及第二欧姆接触层，对所述第一欧姆接触层、所述绝缘层以及所述第二欧姆接触层进行蚀刻，形成第一欧姆接触结构21、第一凸台23以及第二欧姆接触结构22。
所述步骤S20中，所述缓冲层11的材料可以包括但不限于氮化硅、氧化硅或者氮氧化硅中的任意一种或者多种的组合材料。
所述步骤S20中，如图13b所示，所述第一欧姆接触结构21设置于所述缓冲层11上，所述第一凸台23设置于所述第一欧姆接触结构21的背离所述缓冲层11的一侧，所述第二欧姆接触结构22设置于所述第一凸台23的背离所述第一欧姆接触结构21的一侧。
所述第一凸台23具有一侧壁230，所述侧壁230与所述基板10所在平面之间的夹角θ介于45度至90度之间。
所述第一欧姆接触结构21具有第一侧壁210，所述第一侧壁210邻接于与所述侧壁230，所述第二欧姆接触结构22具有第二侧壁220，所述第二侧壁220邻接于所述侧壁230，所述第一侧壁210以及所述第二侧壁220与所述基板所在平面之间的夹角可以与所述侧壁230与所述基板10所在平面之间的夹角θ相等，即所述第一侧壁210与所述侧壁230以及所述第二侧壁220处于同一倾斜平面上。
在本申请实施例中，所述第一欧姆接触层和所述第二欧姆接触层的材料均为N型重掺杂非晶硅材料，所述第一欧姆接触层和所述第二欧姆接触层中均可以掺杂有磷或砷等杂质元素。
所述绝缘层的材料可以为氮化硅、氧化硅或者氮氧化硅等常用的无机绝缘材料。
在所述步骤S20中，可以通过化学气相沉积（chemical vapor deposition, CVD）的方式依次沉积形成所述第一欧姆接触层、绝缘层、以及第二欧姆接触层。
步骤S3：对所述第一欧姆接触结构21、所述第一凸台23以及所述第二欧姆接触结构22进行蚀刻，使所述第二欧姆接触结构22和所述第一凸台23被部分蚀刻，所述第一欧姆接触结构21不被蚀刻。
如图13c所示，通过对所述第二欧姆接触结构22和所述第一凸台23进行部分蚀刻，使所述第一欧姆接触结构21的部分未被所述第一凸台23和所述第二欧姆接触结构22覆盖。
步骤S4：在所述缓冲层11上形成一层非晶硅层，所述非晶硅层覆盖所述第一欧姆接触结构21、所述第一凸台23以及所述第二欧姆接触结构22；对所述非晶硅层进行结晶处理，然后通过图案化，形成半导体结构24；
所述步骤S4中，可以通过准分子激光退火工艺对所述非晶硅层进行结晶处理，使所述非晶硅层内的非晶硅可以转变为多晶硅结构，再对所述多晶硅结构进行蚀刻，形成所述半导体结构24。
由于准分子激光退火工艺的能量有限，且全部被所述非晶硅层所吸收，在对所述非晶硅层进行结晶处理时，所述第一欧姆接触结构21和所述第二欧姆接触结构22仍然可以保持非晶硅结构。
在对所述非晶硅层进行结晶处理的过程中，所述非晶硅层在所述缓冲层11与所述第一凸台23的侧壁230的拐角处可以形成籽晶，所述籽晶可以沿所述侧壁230的方向生长，通过将所述侧壁230的长度控制在0.01微米至1微米之间，可以使所述侧壁230上的半导体结构24内只存在有一个晶粒。
步骤S5：在所述半导体结构24上形成栅极绝缘层13，所述栅极绝缘层13覆盖所述半导体结构24、所述第一欧姆接触结构21、所述第一凸台23以及所述第二欧姆接触结构22；在所述栅极绝缘层13上形成栅极25；
步骤S6：在所述栅极绝缘层13上形成层间介质层14，所述层间介质层14覆盖所述栅极25；在所述层间介质层14上形成第一过孔OH1和第二过孔OH2，所述第一过孔OH1暴露出所述第一欧姆接触结构21，所述第二过孔OH2暴露出所述第二欧姆接触结构22；
步骤S7：在所述层间介质层14上形成源极26和漏极27，所述漏极27穿过所述第一过孔OH1与所述第一欧姆接触结构21接触，所述源极26穿过所述第二过孔OH2与所述第二欧姆接触结构22接触。
需要说明的是，本申请实施例提供的显示面板的制作方法仅以图1至图3所示的第一种显示面板的结构为例，其他实施例中的显示面板的制作方法可以参考图13a至图13b所示的显示面板的制作方法，此处不做赘述。
本申请实施例的有益效果：本申请实施例提供一种显示面板，所述显示面板包括基板和层叠设置于所述基板上的第一欧姆接触结构、第一凸台、第二欧姆接触结构、半导体结构和栅极，所述第一凸台具有至少一个侧壁，通过将所述半导体结构设置于所述第一凸台的所述侧壁上，并且分别与所述第一欧姆接触结构和所述第二欧姆接触结构接触，可以利用现有的工艺缩短半导体结构内的沟道的长度，并减小薄膜晶体管的体积，从而可以提高显示面板内的薄膜晶体管的集成度。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种显示面板，包括：
    基板；
    第一欧姆接触结构，设置于所述基板上；
    第一凸台，设置于所述第一欧姆接触结构的背离所述基板的一侧，所述第一凸台具有至少一个侧壁；
    第二欧姆接触结构，设置于所述第一凸台的背离所述第一欧姆接触结构的一侧；
    半导体结构，至少设置于所述侧壁上，并且分别与所述第一欧姆接触结构和所述第二欧姆接触结构接触；以及
    栅极，设置于所述半导体结构的背离所述基板的一侧。
  2. 如权利要求1所述的显示面板，其中，所述第一欧姆接触结构具有邻接于所述侧壁的第一侧壁，所述半导体结构与所述第一侧壁接触。
  3. 如权利要求1所述的显示面板，其中，所述第一欧姆接触结构包括：
    本体部，设置于所述第一凸台与所述基板之间；以及
    凸出部，与所述本体部连接，所述凸出部在所述基板上的正投影与所述第一凸台在所述基板上的正投影不重叠，所述半导体结构与所述凸出部的背离所述基板的一侧表面接触。
  4. 如权利要求3所述的显示面板，其中，所述凸出部的长度介于0.5微米至3微米之间。
  5. 如权利要求1所述的显示面板，其中，所述半导体结构包括：
    第一部，设置于所述基板和/或所述第一欧姆接触结构上；
    第二部，设置于所述侧壁上，且与所述第一部连接；以及
    第三部，设置于所述第二欧姆接触结构的背离所述第一凸台的一侧，且与所述第二部连接。
  6. 如权利要求1所述的显示面板，其中，所述侧壁与所述基板所在平面之间的夹角介于45度至90度之间。
  7. 如权利要求1所述的显示面板，其中，所述第一凸台具有两个相对设置的所述侧壁，两个所述侧壁上均设置有所述半导体结构、以及位于所述半导体结构的背离所述基板一侧的所述栅极；
    其中，两个所述侧壁上的所述半导体结构均与所述第一欧姆接触结构和所述第二欧姆接触结构接触。
  8. 如权利要求7所述的显示面板，其中，所述半导体结构在所述第一凸台的两个所述侧壁、以及所述第二欧姆接触结构上连续设置。
  9. 如权利要求8所述的显示面板，其中，所述栅极在所述基板上的正投影覆盖所述半导体结构在所述基板上的正投影。
  10. 如权利要求1所述的显示面板，其中，所述显示面板包括：
    第三欧姆接触结构，设置于所述基板上；
    第二凸台，设置于所述第三欧姆接触结构的背离所述基板的一侧；以及
    第四欧姆接触结构，设置于所述第二凸台的背离所述第一欧姆接触结构的一侧，所述半导体结构至少设置于所述第二凸台的侧壁上，且分别与所述第三欧姆接触结构和所述第四欧姆接触结构接触；
    其中，所述显示面板还包括源极和漏极，所述源极和所述漏极的其中之一电连接于所述第一欧姆接触结构和所述第三欧姆接触结构，所述源极和所述漏极的其中另一电连接于所述第二欧姆接触结构和所述第四欧姆接触结构。
  11. 如权利要求10所述的显示面板，其中，所述半导体结构在所述第一凸台和所述第二凸台上、以及所述第一凸台与所述第二凸台之间的区域连续设置。
  12. 如权利要求11所述的显示面板，其中，所述栅极在所述基板上的正投影覆盖所述半导体结构在所述基板上的正投影。
  13. 如权利要求1所述的显示面板，其中，所述显示面板还包括栅极绝缘层和层间介质层，所述栅极绝缘层至少设置于所述栅极与所述半导体结构之间，并且覆盖所述第二欧姆接触结构和所述第一欧姆接触结构，所述层间介质层设置于所述栅极绝缘层的背离所述基板的一侧，并且覆盖所述栅极；
    其中，所述显示面板还包括源极和漏极，所述源极和所述漏极均设置于所述层间介质层的背离所述基板的一侧，所述源极和所述漏极的其中之一穿过所述层间介质层和所述栅极绝缘层与所述第一欧姆接触结构接触，所述源极和所述漏极的其中另一穿过所述层间介质层和所述栅极绝缘层与所述第二欧姆接触结构接触。
  14. 如权利要求1所述的显示面板，其中，所述显示面板还包括遮光结构，所述遮光结构设置于所述第一欧姆接触结构的靠近所述基板的一侧，所述半导体结构包括连接于所述第一欧姆接触结构与第二欧姆接触结构之间的沟道部；
    其中，所述遮光结构在所述基板上的正投影覆盖所述沟道部在所述基板上的正投影。
  15. 如权利要求14所述的显示面板，其中，所述沟道部沿所述侧壁延伸方向上的长度介于0.01微米至1微米之间。
  16. 如权利要求1所述的显示面板，其中，所述第一凸台在所述显示面板的厚度方向上的厚度介于0.0071微米至1微米之间。
  17. 如权利要求1所述的显示面板，其中，所述第一凸台为单层或者多层结构。
  18. 如权利要求1所述的显示面板，其中，所述第一凸台的材料包括氮化硅、氧化硅、氮氧化硅中的一种或者多种的组合。
  19. 如权利要求1所述的显示面板，其中，所述第一凸台的材料包括丙烯酸基树脂、环氧树脂、酚醛树脂、聚酰胺基树脂、聚酰亚胺基树脂、不饱和聚酯树脂、聚丙烯酸酯、聚碳酸酯类、聚酰亚胺、聚苯乙烯类中的一种或者多种的组合。
  20. 如权利要求1所述的显示面板，其中，所述侧壁为平面或者弧面。
PCT/CN2022/130324 2022-09-23 2022-11-07 显示面板 Ceased WO2024060366A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/925,002 US20250072093A1 (en) 2022-09-23 2022-11-07 Display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211167619.2 2022-09-23
CN202211167619.2A CN115458588B (zh) 2022-09-23 2022-09-23 显示面板

Publications (1)

Publication Number Publication Date
WO2024060366A1 true WO2024060366A1 (zh) 2024-03-28

Family

ID=84306575

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/130324 Ceased WO2024060366A1 (zh) 2022-09-23 2022-11-07 显示面板

Country Status (3)

Country Link
US (1) US20250072093A1 (zh)
CN (1) CN115458588B (zh)
WO (1) WO2024060366A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118658862A (zh) * 2023-09-18 2024-09-17 昆山国显光电有限公司 半导体器件、显示面板及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0280370A2 (en) * 1987-02-27 1988-08-31 Philips Electronics Uk Limited Thin film transistors, display devices incorporting such transistors, and methods for their fabrication
CN103730508A (zh) * 2012-10-16 2014-04-16 瀚宇彩晶股份有限公司 显示面板的垂直式薄膜晶体管结构及其制作方法
CN106898654A (zh) * 2017-03-07 2017-06-27 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN107221501A (zh) * 2017-05-26 2017-09-29 京东方科技集团股份有限公司 垂直型薄膜晶体管及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100289654B1 (ko) * 1998-06-30 2001-05-02 박종섭 버티컬구조의박막트랜지스터를구비한액정표시소자및그의제조방법
KR101703511B1 (ko) * 2008-06-27 2017-02-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터
KR101484966B1 (ko) * 2008-07-07 2015-01-21 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
US11417689B2 (en) * 2020-07-16 2022-08-16 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel
CN111785759B (zh) * 2020-07-17 2025-04-29 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN114122015B (zh) * 2021-11-15 2023-08-22 武汉华星光电半导体显示技术有限公司 阵列基板及其制造方法、显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0280370A2 (en) * 1987-02-27 1988-08-31 Philips Electronics Uk Limited Thin film transistors, display devices incorporting such transistors, and methods for their fabrication
CN103730508A (zh) * 2012-10-16 2014-04-16 瀚宇彩晶股份有限公司 显示面板的垂直式薄膜晶体管结构及其制作方法
CN106898654A (zh) * 2017-03-07 2017-06-27 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN107221501A (zh) * 2017-05-26 2017-09-29 京东方科技集团股份有限公司 垂直型薄膜晶体管及其制备方法

Also Published As

Publication number Publication date
US20250072093A1 (en) 2025-02-27
CN115458588B (zh) 2026-01-23
CN115458588A (zh) 2022-12-09

Similar Documents

Publication Publication Date Title
US7294537B2 (en) Method of fabricating thin film transistor with multiple gates using super grain silicon crystallization
CN115602690B (zh) 显示面板
JP4263609B2 (ja) 多結晶シリコン用マスク及びこれを利用した薄膜トランジスタの製造方法
WO2024119795A1 (zh) 显示面板及显示装置
WO2024060514A1 (zh) 显示面板
JP2003092262A (ja) 多結晶化用マスク及びこれを利用した多結晶薄膜トランジスタの製造方法
WO2024103787A1 (zh) 显示面板及显示设备
CN114156285A (zh) 阵列基板及其制备方法、显示面板
CN100456497C (zh) 薄膜半导体器件
WO2024060366A1 (zh) 显示面板
CN100397660C (zh) 利用多晶硅的薄膜晶体管制造方法
CN114373771B (zh) 阵列基板、制作方法及显示装置
CN114628409A (zh) 一种显示基板及其制备方法、显示面板
US5181088A (en) Vertical field effect transistor with an extended polysilicon channel region
WO2019134380A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
WO2024159598A1 (zh) 阵列基板及显示面板
CN115985916B (zh) 薄膜晶体管基板及电子器件
JP2003282881A (ja) 薄膜トランジスタおよびその製造方法ならびに液晶表示装置
US20140124786A1 (en) Thin film transistor array panel and manufacturing method thereof
WO2019085009A1 (zh) 低温多晶硅薄膜及晶体管的制造方法
WO2019085013A1 (zh) 低温多晶硅薄膜及晶体管的制造方法
KR100870017B1 (ko) 박막 트랜지스터 기판의 제조 방법
US20060151790A1 (en) Thin film transistor
US20240222446A1 (en) Thin film transistor and electronic device
WO2025050511A1 (zh) 薄膜晶体管和电子器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22959368

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 17925002

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22959368

Country of ref document: EP

Kind code of ref document: A1