WO2024060363A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024060363A1
WO2024060363A1 PCT/CN2022/129830 CN2022129830W WO2024060363A1 WO 2024060363 A1 WO2024060363 A1 WO 2024060363A1 CN 2022129830 W CN2022129830 W CN 2022129830W WO 2024060363 A1 WO2024060363 A1 WO 2024060363A1
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WO
WIPO (PCT)
Prior art keywords
channel
display panel
sub
pixels
touch
Prior art date
Application number
PCT/CN2022/129830
Other languages
English (en)
French (fr)
Inventor
刘立旺
尹伟红
王超
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/998,977 priority Critical patent/US20240272734A1/en
Publication of WO2024060363A1 publication Critical patent/WO2024060363A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display device.
  • Narrow-border displays have the advantages of simplicity, beauty, and high screen-to-body ratio, and are gradually becoming a major development trend for high-end displays.
  • the development of narrow-border technology has reached a bottleneck, and it has become particularly difficult to further reduce the border of the display panel and improve product specifications.
  • the frame area of the display panel needs to be laid with gate drive circuits, driver chips, flexible printed circuit boards, Demux (demuxer) circuits, power supply wiring, touch circuit wiring, etc., so that the frame of the display panel It is difficult to reduce the size, which is not conducive to achieving narrow borders.
  • the present application provides a display panel and a display device to solve the technical problem in the prior art that the frame of the display panel is difficult to reduce and is not conducive to narrowing the frame.
  • This application provides a display panel, which includes:
  • a first demultiplexer comprises at least one first control unit and at least one first channel line, the extension direction of the first channel line is the same as the extension direction of the data line; each of the first channel lines is connected to at least two of the data lines; each of the first control units comprises a plurality of first switch elements; among the at least two data lines sharing the same first channel line, at least one of the data lines is connected to the first channel line through M first switch elements connected in parallel, M ⁇ 2;
  • the display panel has a display area
  • the first control unit is optionally disposed in the display area.
  • the first demultiplexer also includes at least two control lines. , at least two of the control lines are arranged at intervals along the extension direction of the data line, at least two of the control lines transmit different control signals, and the M first switching elements connected to the same data line The control terminals are all connected to the same control line.
  • the first demultiplexer further includes a plurality of control lines, and the plurality of control lines are arranged at intervals along the extension direction of the data line;
  • the M control lines transmit the same control signal; the M first switching elements connected to the same data line are respectively connected to the M control lines transmitting the same control signal.
  • the display panel further includes a plurality of sub-pixels arranged in an array, a plurality of the first switching elements are arranged in different sub-pixels, and each row of the One of the control lines is provided in the sub-pixel.
  • the data voltage polarity of the data line connected to the same first channel line is the same.
  • the display panel further includes at least one pixel area, and along the first direction, the pixel area includes 2N columns of sub-pixels, the pixel area is provided with two first channel wirings, and each column of the sub-pixels is correspondingly provided with one data line, where N is an integer greater than or equal to 2;
  • the data voltage polarities of two adjacent first channel lines are opposite.
  • the first first channel line is connected to the odd-numbered first channel line respectively.
  • the data lines are connected; the second first channel wiring is connected to the even-numbered data lines respectively.
  • the display panel further includes multiple columns of sub-pixels, the data voltages of two adjacent columns of sub-pixels have opposite polarities, and the data voltages of two adjacent first channel lines have opposite polarities.
  • the voltage polarity is opposite;
  • At least one auxiliary channel wire is provided between two adjacent first channel wires, and the first switching element connected to the auxiliary channel wire is arranged adjacent to the auxiliary channel wire. in the sub-pixel.
  • the display panel further includes at least one pixel area, the pixel area includes six columns of the sub-pixels, and the pixel area is provided with four of the first channel lines, Each column of said sub-pixels is provided with one said data line;
  • the first first channel line is connected to the first data line and the third data line respectively;
  • the second The first channel trace is connected to the second data line,
  • the third first channel trace is connected to the fourth data line and the sixth data line respectively, and
  • the fourth data line is connected to the fourth data line.
  • One channel wire is connected to the fifth data line, and the second first channel wire and the fourth first channel wire are both the auxiliary channel wires.
  • the first first channel trace is connected in parallel with the fourth first channel trace, and the second first channel trace is connected with the third first channel trace.
  • the first channel wiring is connected in parallel.
  • the display panel further includes at least one pixel area.
  • the pixel area includes N columns of the sub-pixels, and the pixel area is provided with a strip of For the first channel wiring, N is an integer greater than or equal to 2;
  • the first channel wiring is connected to the data line corresponding to the sub-pixel in each column.
  • the display panel further includes a plurality of pixel areas, each of which includes at least two columns of adjacent sub-pixels and is connected to the same first channel line.
  • a plurality of sub-pixels some of the sub-pixels are located in one of the pixel areas, and another part of the sub-pixels are located in another of the pixel areas.
  • the display panel further includes a plurality of touch traces; the plurality of touch traces are arranged at intervals along the first direction;
  • the display panel further includes a second demultiplexer, the second demultiplexer includes a plurality of second control units and a plurality of second channel lines, and the plurality of second channel lines are along the The first direction is arranged at intervals; each of the second channel traces is connected to at least two of the touch traces; each of the second control units includes a plurality of second switch elements; in sharing the same Among the at least two touch traces of the second channel trace, at least one of the touch traces is connected to one of the second channel traces through the corresponding at least one second switch element; The second control unit is arranged in the display area.
  • the display area includes a first display area and a second display area
  • the first demultiplexer is disposed on the second display area.
  • display area, the second demultiplexer is arranged in the first display area and the second display area, in the second display area, the first switching element is arranged in the odd-numbered row sub-pixel and In one of the even-numbered row sub-pixels, the second switching element is provided in the other one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels.
  • the display panel further includes multiple columns of sub-pixels, and each column of sub-pixels is provided with one of the data lines;
  • the first channel trace, the touch trace and the second channel trace are respectively arranged adjacent to different data lines.
  • the display panel further includes a plurality of touch electrodes arranged in an array, and each of the touch electrodes is connected to and/or corresponds to at least one of the touch traces.
  • Each touch electrode is provided with two second channel traces.
  • two second channel traces are provided corresponding to each touch electrode, and in the second display area, corresponding to each touch electrode Each of the touch electrodes is provided with four second channel traces.
  • the display panel further includes a plurality of touch electrodes arranged in an array, each of the touch electrodes is connected to at least one of the touch traces, and the touch electrodes are arranged in an array.
  • the control electrode is reused as a common electrode;
  • the display panel further includes a plurality of third channel traces; the plurality of third channel traces are arranged at intervals along the first direction, and each of the third channel traces is connected to the corresponding touch screen. control wiring connections.
  • the display panel further includes a third demultiplexer, and the third demultiplexer includes a plurality of third control units; each of the third channel lines Connected to at least two of the touch traces; each third control unit includes a plurality of third switching elements; in at least two of the touch traces sharing the same third channel trace , at least one of the touch traces is connected to a third channel trace through a corresponding at least one of the third switch element.
  • each touch electrode along the extension direction of the data line, each touch electrode includes a first part and a second part connected, and the second demultiplexer corresponds to the The second part is configured, and the third demultiplexer is configured corresponding to the first part.
  • the present application also provides a display device, including a display panel and a driver chip.
  • the display panel is the display panel described in any one of the above, and the driver chip is wired to the first channel.
  • This application provides a display panel and a display device.
  • a first demultiplexer in the display panel
  • embodiments of the present application can use a smaller number of first channel traces to provide corresponding data signals to a larger number of data lines, thereby reducing the number of driver chips. ,reduce manufacturing cost.
  • the embodiment of the present application can reduce the frame size of the display panel, which facilitates narrowing the frame.
  • the size of each first switching element is very small.
  • the resistance of the first switching element is related to the size of the device. If the size of the first switching element is small and the resistance is large, it may easily lead to poor data signal transmission.
  • at least one data line is connected to the first channel wiring through M first switching elements connected in parallel, which can improve the signal transmission yield.
  • Figure 1 is a first structural schematic diagram of a display panel provided by this application.
  • Figure 2 is a first plan view of the display panel provided by this application.
  • FIG. 3 is a second structural schematic diagram of the display panel provided by this application.
  • Figure 4 is a second plan view of the display panel provided by the present application.
  • FIG. 5 is a third structural schematic diagram of the display panel provided by this application.
  • Figure 6 is a third plan view of the display panel provided by this application.
  • Figure 7 is a schematic structural diagram of the touch electrode, the second demultiplexer and the third demultiplexer provided by this application;
  • Figure 8 is a fourth plan view of the display panel provided by the present application.
  • Figure 9 is a fifth plan view of the display panel provided by this application.
  • Figure 10 is a schematic structural diagram of a display device provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • the terms “connected” and “connected” should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or a connection through The intermediate medium is indirectly connected, which can be the internal connection between two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • This application provides a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a first structural schematic diagram of a display panel provided by this application.
  • the display panel 100 includes a plurality of data lines D and a first demultiplexer 10 .
  • the first demultiplexer 10 includes at least one first control unit 11 and at least one first channel wire S.
  • the extending direction of the first channel trace S is the same as the extending direction of the data line D.
  • Each first channel trace S is connected to at least two data lines D.
  • Each first control unit 11 includes a plurality of first switching elements T1. Among at least two data lines D sharing the same first channel line S, at least one data line D is connected to the first channel line S through M parallel-connected first switching elements T1, where M is greater than or equal to 2. integer.
  • the display panel 100 has a display area AA.
  • the first control unit 11 is provided in the display area AA.
  • the display panel 100 further includes a plurality of scan lines G (such as G1/G2/G3/G4/G5/G6, etc.).
  • the plurality of scan lines G are arranged at intervals along the extension direction of the data lines D.
  • the plurality of scan lines G and the plurality of data lines D intersect to define a plurality of sub-pixels 20.
  • the plurality of sub-pixels 20 are arranged in an array.
  • Each sub-pixel 20 is connected to a corresponding data line D and a corresponding scan line G. Since the same first channel wiring S is connected to a plurality of data lines D, the sub-pixels 20 of the corresponding rows can be controlled to open through the plurality of scan lines G to avoid data signal transmission errors.
  • the sub-pixels 20 presented in the display screen may be red sub-pixels, green sub-pixels, blue sub-pixels, white sub-pixels, yellow sub-pixels, etc., which are not specifically limited in this application.
  • the display panel 100 provided by this application can adopt standard RGB pixel arrangement architecture, RGB PenTile pixel arrangement architecture, RGB Delta pixel arrangement architecture, RGBW pixel arrangement architecture, etc.
  • RGB PenTile pixel arrangement architecture RGB PenTile pixel arrangement architecture
  • RGB Delta pixel arrangement architecture RGBW pixel arrangement architecture
  • RGBW pixel arrangement architecture etc.
  • the red sub-pixels, green sub-pixels and blue sub-pixels can be arranged and combined in RGB, RBG, BGR, BRG, GRB, GBR, etc. Any kind of repeating arrangement.
  • Each column of sub-pixels 20 has the same color.
  • the present application is not limited to this, and may be specifically set according to the display requirements of the display panel 100 .
  • the first demultiplexer 10 in the first aspect, by arranging the first demultiplexer 10 in the display panel 100, a smaller number of first channel traces S can be used to provide corresponding data to a larger number of data lines D. signals, thereby reducing the number of driver chips and reducing production costs.
  • Demux circuits are usually set up in the border area, and their height can reach hundreds or even thousands of microns, which becomes a major difficulty in achieving narrow borders on displays.
  • the frame size of the display panel 100 can be reduced, which facilitates narrowing the frame.
  • the size of the first switching element T1 is very small in order not to affect the aperture ratio of the sub-pixels 20 . It can be understood that the resistance size of the first switching element T1 is related to the size of the device. The size of the first switching element T1 is very small, which may easily lead to poor data signal transmission.
  • at least one data line D is connected to the first channel line S through M parallel-connected first switching elements T1, which can improve the transmission yield of data signals.
  • the first demultiplexer 10 further includes at least two control lines Mux. At least two control lines Mux are arranged at intervals along the extension direction of the data line D. Each control line Mux is used to transmit corresponding control signals. The control end of each first switching element T1 is connected to the corresponding control line Mux. The control line Mux is used to control the first switching element T1 to turn on or off.
  • control line Mux can be set on the same layer as the scan line G. On the one hand, it is conducive to reducing the film structure of the display panel 100 and making the display panel 100 thinner and lighter; on the other hand, in the process of manufacturing the scan line G, the control line Mux can be formed simultaneously, thereby saving the manufacturing process and improving production efficiency. .
  • the control line Mux and the scanning line G may also be formed of different conductive layers.
  • the input electrode of the first switch element T1 is connected to the corresponding first channel wiring S.
  • the output electrode of the first switch element T1 is connected to the corresponding data line D.
  • the first switch element T1 can be a thin film transistor.
  • the control end of the first switch element T1 is the gate of the thin film transistor.
  • the input electrode of the first switch element T1 is one of the source and drain of the thin film transistor.
  • the output electrode of the first switch element T1 is the other of the source and drain of the thin film transistor.
  • the control line Mux controls the opening or closing of the first switch element T1 connected thereto, so that the first channel wiring S can transmit the data signal to the corresponding data line D respectively.
  • the first switching element T1 is a thin film transistor
  • the size of the first switching element T1 is small, the channel width-to-length ratio W/L of the first switching element T1 is difficult to meet the preset requirements, resulting in poor data signal transmission. Therefore, in the embodiment of the present application, at least one data line D is connected to the first channel line S through at least two parallel-connected first switching elements T1. The resistance of multiple parallel-connected first switching elements T1 is reduced, which can improve the data signal. transmission yield.
  • the number of control lines Mux is related to the number of data lines D connected to each first channel line S1.
  • Each first channel trace S1 can be connected to 2 data lines D; each first channel trace S1 can also be connected to 3 data lines D; each first channel trace S1 can also be connected to 4 data lines D connection, this application will not detail them one by one here.
  • control line Mux includes a first control line Mux1, a second control line Mux2 and a third control line Mux3.
  • first control line Mux1 a first control line Mux1
  • second control line Mux2 a second control line Mux2
  • third control line Mux3 a third control line Mux3.
  • the M control lines Mux transmit the same control signal.
  • M first switching elements T1 connected to the same data line D are connected in one-to-one correspondence with M control lines Mux transmitting the same control signal. That is, at least one of the first control line Mux1, the second control line Mux2, and the third control line Mux3 may be provided as M lines.
  • the first control line Mux1, the second control line Mux2, and the third control line Mux3 are respectively set to two.
  • the two first control lines Mux1 can be connected in parallel to receive the same control signal; the two first control lines Mux1 can also be connected to the same control signal respectively.
  • the two second control lines Mux2 can be connected in parallel to receive the same control signal; the two second control lines Mux2 can also be connected to the same control signal respectively.
  • the two third control lines Mux3 can be connected in parallel to receive the same control signal; the two third control lines Mux3 can also be connected to the same control signal respectively.
  • the two first switching elements T1 connected to the first data line D1 or the fourth data line D4 are connected to the two first control lines Mux1 in a one-to-one correspondence.
  • the two first switching elements T1 connected to the second data line D2 or the fifth data line D5 are connected to the two second control lines Mux2 in one-to-one correspondence.
  • the two first switching elements T1 connected to the third data line D3 or the sixth data line D6 are connected to the two third control lines Mux3 in one-to-one correspondence.
  • the plurality of control lines Mux may be repeatedly arranged in units of the first control line Mux1, the second control line Mux2, and the third control line Mux3.
  • the embodiment of the present application can realize the parallel connection of multiple first switching elements T1 connected to the same data line D, improve the conductivity of the multiple first switching elements T1 and avoid poor data signal transmission.
  • first switching elements T1 there may be 3, 4 or more first switching elements T1 connected to the same data line D.
  • 3, 4 or more first control lines Mux1 (second control line Mux2 or third control line Mux3) can be set, which will not be described again here.
  • the first demultiplexer 10 may also include at least two control lines Mux, and the at least two control lines Mux transmit different control signals.
  • the control terminals of the plurality of first switching elements T1 connected to the same data line D are connected to the same control line Mux.
  • the embodiment of the present application can reduce the number of control lines Mux. Some of the first switch elements T1 can be connected to the corresponding control lines Mux by changing the line, which will not be described in detail here.
  • a plurality of first switch elements T1 are disposed in different sub-pixels 20. At most one control line Mux is disposed in each row of sub-pixels 20.
  • the display panel 100 has certain specifications for the pixel aperture ratio.
  • multiple first switching elements T1 are respectively arranged in different sub-pixels 20, and only one control line Mux is arranged in the corresponding row of sub-pixels 20, which can reduce the impact on the pixel aperture ratio and improve the display panel 100 display uniformity.
  • the data voltage polarity of the data line D connected to the same first channel line S is the same.
  • the data voltage polarity of the data line D connected to the same first channel line S can also be different.
  • connection method between each data line D and the first channel trace S by adjusting the connection method between each sub-pixel 20 and the data line D, different driving methods can be implemented, such as dot inversion, Column reversal, frame reversal, row reversal, etc.
  • the display panel 100 further includes at least one pixel area 201 .
  • the pixel area 201 includes 2N columns of sub-pixels 20 .
  • Each pixel area 201 is provided with two first channel traces S.
  • Each column of sub-pixels 20 is provided with one data line D.
  • N is an integer greater than or equal to 2.
  • the data voltage polarities of two adjacent first channel wirings S are opposite.
  • the first first channel wiring S1 is connected to the odd-numbered data lines D.
  • the second first channel wiring S2 is connected to the even-numbered data lines D.
  • the polarity of the sub-pixels 20 in each column can be the same, and the polarities of two adjacent sub-pixels 20 in each row of sub-pixels 20 are opposite. That is to say, embodiments of the present application can implement column inversion driving methods and improve display problems such as screen crosstalk.
  • each first channel line S transmits corresponding data signals to three data lines D respectively.
  • the second first channel trace S2 is arranged adjacent to the fourth data line D4.
  • the second first channel trace S2 is arranged on the left side of the fourth data line D4.
  • the first first channel line S1 is connected to the first data line D1, the fifth data line D5 and the third data line D3 respectively.
  • the second first channel line S2 is connected to the fourth data line D4, the second data line D2 and the sixth data line D6 respectively.
  • the first first channel trace S1 transmits a positive polarity data signal; the second first channel trace S2 transmits a negative polarity data signal. Therefore, along the first direction sex.
  • each pixel area 201 may include at least two columns of adjacent sub-pixels 20 .
  • each pixel area 201 may include three columns of RGB sub-pixels 20.
  • some of the sub-pixels 20 are located in one pixel area 201, and the other part of the sub-pixels 20 are located in another pixel area 201.
  • the data voltage polarity required by each sub-pixel 20 located in different pixel areas 201 can be achieved.
  • Figure 2 is a first plan view of the display panel provided by the present application.
  • first first channel trace S1 is set on the left side of the first data line D1
  • second first channel trace S2 is set to the left of the fourth data line D4
  • multiple line changes are required to realize the second first channel trace S2 and the second data line D2.
  • Connection. The design of multiple line changes results in a certain loss of pixel aperture ratio.
  • Figure 3 is a second structural schematic diagram of the display panel provided by this application
  • Figure 4 is a second plan schematic diagram of the display panel provided by this application.
  • the difference from the display panel 100 shown in FIGS. 1 and 2 is that in the embodiment of the present application, at least one auxiliary channel trace S is provided between two adjacent first channel traces S, and is connected with the auxiliary channel trace S.
  • the line-connected first switching element T1 is provided in the sub-pixel 20 adjacent to the auxiliary channel line.
  • the data voltage polarity of the latter first channel trace S is the same as the data voltage polarity of the auxiliary channel trace.
  • an auxiliary channel wire is added between two adjacent first channel wires S.
  • column reversal can be achieved; at the same time, the auxiliary channel wires connected to the auxiliary channel wires
  • the first switching element T1 is disposed in the sub-pixel 20 adjacent to the auxiliary channel line.
  • the auxiliary channel line can be connected to the corresponding sub-pixel 20 and the data line D without changing the lines.
  • each pixel area 201 includes six columns of sub-pixels 20 .
  • Each pixel area 201 is provided with four first channel traces S.
  • Each column of sub-pixels 20 is provided with one data line D.
  • the first first channel line S1 is connected to the first data line D1 and the third data line D3 respectively.
  • the second first channel trace S2 is connected to the second data line D2.
  • the third first channel trace S3 is connected to the fourth data line D4 and the sixth data line D6 respectively.
  • the fourth first channel trace S4 is connected to the fifth data line D5.
  • the second first channel trace S2 and the fourth first channel trace S4 are both auxiliary channel traces.
  • the first first channel trace S1 and the fourth first channel trace S4 have the same data voltage polarity.
  • the second first channel trace S2 and the third first channel trace S3 have the same data voltage polarity.
  • the data voltage polarities of the first first channel trace S1 and the second first channel trace S2 are opposite.
  • first first channel wire S1 and the fourth first channel wire S4 are connected in parallel; the second first channel wire S2 and the third first channel wire S3 are connected in parallel. in parallel.
  • first first channel line S1 and the fourth first channel line S4 are the same, and they are respectively connected with the first channel line S1 and the fourth first channel line S4,
  • the three data lines D connected to S4 respectively realize the transmission of data signals through different first switching elements T1. Therefore, the first first channel line S1 and the fourth first channel line S4 can be designed in parallel to further reduce the number of The number of traces S in one channel reduces the number of driver chips.
  • designing the second first channel trace S2 and the third first channel trace S3 in parallel can also reduce the number of driver chips and reduce production costs.
  • FIG. 5 is a third plan view of the display panel provided by the present application.
  • the difference from the display panel 100 shown in FIG. 1 and FIG. 2 is that in the embodiment of the present application, along the first direction X, the pixel area 201 includes N columns of sub-pixels 20 .
  • Each pixel area 201 is provided with a first channel trace S.
  • N is an integer greater than or equal to 2.
  • the first channel line S is connected to the data line D corresponding to each column of sub-pixels 20 respectively.
  • the first first channel line S1 is connected to the first data line D1, the second data line D2, and the third data line D3 respectively.
  • the second first channel trace S2 is connected to the fourth data line D4, the fifth data line D5 and the sixth data line D6 respectively.
  • multiple first channel traces S can transmit data signals with the same polarity. At the same time, there are very few line-changing designs in the display area AA, further improving the pixel aperture ratio.
  • FIG. 6 is a third plan view of the display panel provided by the present application
  • FIG. 7 is a touch electrode and a second demultiplexer provided by the present application. Structural diagram of three multiplexers.
  • the difference from the display panel 100 shown in FIG. 1 and FIG. 2 is that in the embodiment of the present application, the display panel 100 further includes a plurality of touch traces RX.
  • the plurality of touch traces RX are arranged at intervals along the first direction X.
  • the display panel 100 further includes a second demultiplexer 40 .
  • the second demultiplexer 40 includes a plurality of second control units 41 and a plurality of second channel lines TPS.
  • the second channel traces TPS are arranged at intervals along the first direction X.
  • Each second channel trace TPS is connected to at least two touch traces RX.
  • Each second control unit 41 includes a plurality of second switching elements T2. Among the plurality of touch traces RX sharing the same second channel trace TPS, at least one touch trace RX is connected to a second channel trace TPS through a corresponding at least one second switch element T2.
  • the frame size of the display panel 100 can be further reduced, which facilitates narrowing the frame.
  • the first channel trace S and the second channel trace TPS may be provided in different columns of sub-pixels 20.
  • the display panel 100 further includes a plurality of touch electrodes 30 .
  • Each touch electrode 30 can be designed corresponding to multiple sub-pixels 20 .
  • each touch electrode 30 can be arranged corresponding to 40 rows and 40 columns of sub-pixels 20, which is not specifically limited in this application.
  • FIG. 6 only shows part of the structure of the touch electrode 30, but it cannot be understood as limiting the present application.
  • Each touch electrode 30 is connected to at least one touch trace RX. It can be understood that due to the large area of the touch electrode 30, in order to improve the distribution uniformity of the touch signal, multiple touch traces RX can be set to be connected to the same touch electrode 30 to transmit the touch signal to the touch signal. at different positions of the electrode 30 .
  • At least one second channel trace TPS is provided corresponding to each touch electrode 30 .
  • multiple second channel traces TPS can be provided to provide touch signals for multiple touch traces RX.
  • the multiple second channel traces TPS can be connected in parallel to further reduce the number of channels of the driver chip.
  • each touch electrode 30 is connected to three touch traces RX.
  • the second touch trace RX2 is connected to the first second channel trace TPS1 through the second switching element T2;
  • the two second channel lines are connected by TPS2.
  • the second demultiplexer 40 also includes a plurality of control signal lines TPMux.
  • a plurality of control signal lines TPMux are arranged at intervals along the extension direction of the data line D.
  • at least one touch trace RX can be connected to a second channel trace TPS through a plurality of parallel second switch elements T2 to improve the transmission yield of touch signals.
  • the first control signal line TPMux1 is set to two, and each touch trace RX is connected to the same second channel trace TPS through two second switching elements T2.
  • the two second switching elements T2 are respectively connected to the two first control signal lines TPMux1, thereby realizing the parallel connection of the two second switching elements T2.
  • the second demultiplexer 40 includes two control signal lines TPMux that receive different control signals.
  • the first control signal line TPMux1 is used to control the first second channel line TPS1 and the second second channel line TPS2 to touch.
  • the control signal is transmitted to the upper touch electrode 30.
  • the second control signal line TPMux2 is used to control the first second channel line TPS1 and the second second channel line TPS2 to transmit the touch signal to the touch electrode 30 below. That is, the same second channel wire TPS is connected to at least two touch wires RX, thereby controlling at least two upper and lower touch electrodes 30 so that the touch electrodes 30 in odd-numbered rows and even-numbered rows do not work at the same time.
  • the first channel trace S, the touch trace RX, and the second channel trace TPS can be respectively disposed adjacent to different data lines D.
  • the display panel 100 further includes a plurality of third channel traces VS.
  • a plurality of third channel traces VS are arranged at intervals along the first direction X.
  • Each third channel trace VS is connected to a corresponding touch electrode 30 . Only one third channel trace VS is shown in FIG. 6 , but this cannot be understood as limiting the present application.
  • the first channel wiring S, the second channel wiring TPS and the third channel wiring VS may be disposed adjacent to different data lines D, respectively.
  • the touch electrode 30 can be reused as a common electrode.
  • each third channel trace VS transmits a common voltage to the corresponding touch electrode 30 .
  • each third channel trace VS transmits a touch signal to the corresponding touch electrode 30 . Since the touch electrode 30 has a large area, using the third channel wiring VS to transmit the touch signal to the corresponding touch electrode 30 can enhance the intensity of the touch signal and improve the distribution uniformity of the touch signal.
  • the display panel 100 further includes a third demultiplexer 50 .
  • the third demultiplexer 50 includes a plurality of third control units 51 .
  • Each third channel trace VS is connected to at least two touch traces RX.
  • Each third control unit 51 includes a plurality of third switching elements T3.
  • at least one touch trace RX is connected to a third channel trace VS through a corresponding at least one third switching element T3.
  • the frame size of the display panel 100 can be further reduced, which is conducive to achieving a narrow frame.
  • at least one touch line RX can be arranged to be connected to the third channel line VS through multiple parallel third switch elements T3, which can improve the transmission yield of the touch signal.
  • the structure and connection method of the second switching element T2 and the third switching element T3 can be referred to the first switching element T1 in the above embodiment, and will not be described again here.
  • the third demultiplexer 50 also includes a plurality of control lines VMux.
  • a plurality of control traces VMux are arranged at intervals along the extension direction of the data line D. Only one control line VMux is shown in FIG. 6 , but this cannot be understood as limiting the present application.
  • At least one touch trace RX can be connected to the third channel trace VS through a plurality of parallel third switching elements T3 to improve the transmission yield of touch signals.
  • the first control trace VMux1 is set to two, and each touch trace RX is connected to the same third channel trace VS through two third switching elements T3.
  • the two third switching elements T3 are respectively connected to the two first control lines VMux1, thereby realizing the parallel connection of the two third switching elements T3.
  • the third demultiplexer 50 includes two control lines VMux that are connected to different control signals.
  • the first control line VMux1 is used to control the third channel line VS to transmit the touch signal to the upper touch electrode 30 .
  • the second control line VMux2 is used to control the third channel line VS to transmit the touch signal to the touch electrode 30 below.
  • each touch electrode 30 includes a first portion 31 and a second portion 32 connected to each other along the extension direction of the data line D.
  • the second demultiplexer 40 is disposed corresponding to the second portion 32
  • the third demultiplexer 50 is disposed corresponding to the first portion 31 .
  • the second demultiplexer 40 and the third demultiplexer 50 are arranged in different areas, which can ensure the display uniformity of the display panel 100 .
  • the display area AA includes a first display area AA1 and a second display area AA2 .
  • the first demultiplexer 10 is provided in the second display area AA2.
  • the second demultiplexer 40 is provided in the first display area AA1 and the second display area AA2.
  • the first switching element T1 is provided in one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels.
  • the second switching element T2 is provided in the other one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels.
  • the third demultiplexer 50 may be disposed in the first display area AA1 and the second display area AA2.
  • the first switching element T1 and the third switching element T3 are also provided in different rows of sub-pixels 20 .
  • the first demultiplexer 10 and the second demultiplexer are distributed in different areas of the display panel 100 .
  • the second demultiplexer 40 and the third demultiplexer 50 are provided.
  • the application is not limited to this.
  • the first demultiplexer 10 , the second demultiplexer 40 and the third demultiplexer 50 can be evenly arranged in the display area AA, thereby improving the display uniformity of the display panel 100 .
  • two second channel traces TPS are provided corresponding to each touch electrode 30; in the second display area AA2, as shown in FIG. As shown in 6 , four second channel traces TPS are provided corresponding to each touch electrode 30 .
  • one third channel trace VS is provided corresponding to each touch electrode 30, and in the second display area AA2, two third channel traces are provided corresponding to each touch electrode 30. VS.
  • the first demultiplexer 10 , the second demultiplexer 40 and the third demultiplexer 50 are simultaneously provided in the second display area AA2 , and the first demultiplexer 10 occupies a part of the wiring space. . Therefore, in the second display area AA2, the second switching element T2 and the third switch T3 can only be disposed in one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels to interleave with the first switching element T1 layout. Therefore, in order to improve the transmission yield of touch signals, in the embodiment of the present application, four second channel traces TPS and two third channel traces VS are provided corresponding to each touch electrode 30 in the second display area AA2.
  • this application also provides a display device.
  • the display device includes a display panel.
  • the display panel is the display panel 100 described in any of the above embodiments, which will not be described again here.
  • the display device may be a smart phone, a tablet computer, an e-book reader, a smart watch, a camera, a game console, etc., which is not limited in this application.
  • the display device 1000 includes a display panel 100 and a driver chip 200.
  • the driver chip 200 is connected to a plurality of first channel traces S.
  • the driver chip 200 may be a source driver chip.
  • the driver chip 200 is used to provide data signals to a plurality of first channel lines S, and then drive each sub-pixel to perform picture display.
  • the second channel trace TPS and the third channel trace VS can also be connected to the driver chip 200 .
  • the driver chip 200 is also used to provide touch signals and common voltages, which improves the integration level of the driver chip 200 and reduces the number of driver chips 200 .
  • the display device 1000 in the embodiment of the present application includes a display panel 100.
  • the display panel 100 includes a plurality of data lines and a first demultiplexer.
  • a plurality of data lines are arranged at intervals along the first direction;
  • the first demultiplexer includes at least one first control unit and at least one first channel line, and the extension direction of the first channel line is the same as the extension direction of the data line;
  • Each first channel line is connected to at least two data lines;
  • each first control unit includes a plurality of first switching elements; among the at least two data lines sharing the same first channel line, at least one data line M parallel-connected first switch elements are connected to the first channel wiring, M ⁇ 2; wherein, the display panel has a display area, and the first control unit is arranged in the display area.
  • the first demultiplexer is integrated into the display area, which can reduce the frame size of the display panel 100 and facilitate the narrowing of the frame of the display device 1000 .

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Abstract

一种显示面板（100）及显示装置（1000），显示面板（100）包括多条数据线（D）以及第一多路分配器（10）；第一多路分配器（10）中，每条第一通道走线（S）与至少两条数据线（D）连接；每一第一控制单元（11）包括多个第一开关元件（T1）；至少一数据线（D）通过M个并联的第一开关元件（T1）与第一通道走线（S）连接，M≥2；其中，显示面板（100）具有显示区（AA），第一控制单元（11）设置在显示区（AA）内。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
窄边框显示屏具有简洁、美观、屏占比高等优点，逐渐成为高端显示屏的一大发展趋势。目前而言，窄边框技术的发展已接近瓶颈，进一步降低显示面板的边框、提高产品规格变得尤为困难。
现有技术中，显示面板的边框区需要布设栅极驱动电路、驱动芯片、柔性印刷电路板、Demux（多路分配器）电路、电源走线、触控电路走线等，使得显示面板的边框很难再缩小，不利于实现窄边框化。
 技术问题
本申请提供一种显示面板及显示装置，以解决现有技术中显示面板的边框难以减小，不利于实现窄边框化的技术问题。
 技术解决方案
本申请提供一种显示面板，其包括：
多条数据线，多条所述数据线沿第一方向间隔排布；
第一多路分配器，所述第一多路分配器包括至少一第一控制单元和至少一条第一通道走线，所述第一通道走线的延伸方向与所述数据线的延伸方向相同；每条所述第一通道走线与至少两条所述数据线连接；每一所述第一控制单元包括多个第一开关元件；在共用同一条所述第一通道走线的至少两条所述数据线中，至少一所述数据线通过M个并联的所述第一开关元件与所述第一通道走线连接，M≥2；
其中，所述显示面板具有显示区，所述第一控制单元设置在所述显示区内可选的，在本申请一些实施例中，所述第一多路分配器还包括至少两条控制线，至少两条所述控制线沿所述数据线的延伸方向间隔排布，至少两条所述控制线传输不同的控制信号，与同一条所述数据线连接的M个所述第一开关元件的控制端均连接于同一条所述控制线。
可选的，在本申请一些实施例中，所述第一多路分配器还包括多条控制线，多条所述控制线沿所述数据线的延伸方向间隔排布；
其中，M条所述控制线传输同一控制信号；与同一条所述数据线连接的M个所述第一开关元件分别与传输同一控制信号的M条所述控制线连接。
可选的，在本申请一些实施例中，所述显示面板还包括多个呈阵列排布的子像素，多个所述第一开关元件设置在不同的所述子像素中，每行所述子像素中设有一条所述控制线。
可选的，在本申请一些实施例中，与同一条所述第一通道走线连接的所述数据线的数据电压极性相同。
可选的，在本申请一些实施例中，所述显示面板还包括至少一像素区，沿所述第一方向，所述像素区包括2N列子像素，所述像素区设有两条所述第一通道走线，每列所述子像素对应设有一条所述数据线，N为大于或等于2的整数；
其中，相邻两条所述第一通道走线的数据电压极性相反，在所述像素区中，沿所述第一方向，第一条所述第一通道走线分别与第奇数条所述数据线连接；第二条所述第一通道走线分别与第偶数条所述数据线连接。
可选的，在本申请一些实施例中，所述显示面板还包括多列子像素，相邻两列所述子像素的数据电压极性相反，相邻两条所述第一通道走线的数据电压极性相反；
其中，相邻两条所述第一通道走线之间设有至少一条辅助通道走线，与所述辅助通道走线连接的所述第一开关元件设置在与所述辅助通道走线邻近的所述子像素中。
可选的，在本申请一些实施例中，所述显示面板还包括至少一像素区，所述像素区包括六列所述子像素，所述像素区设有四条所述第一通道走线，每列所述子像素对应设有一条所述数据线；
其中，在所述像素区中，沿所述第一方向，第一条所述第一通道走线分别与第一条所述数据线以及第三条所述数据线连接；第二条所述第一通道走线与第二条所述数据线连接，第三条所述第一通道走线分别与第四条所述数据线以及第六条所述数据线连接，第四条所述第一通道走线与第五条所述数据线连接，第二条所述第一通道走线和第四条所述第一通道走线均为所述辅助通道走线。
可选的，在本申请一些实施例中，第一条所述第一通道走线与第四条所述第一通道走线并联，第二条所述第一通道走线与第三条所述第一通道走线并联。
可选的，在本申请一些实施例中，所述显示面板还包括至少一像素区，沿所述第一方向，所述像素区包括N列所述子像素，所述像素区设有一条所述第一通道走线，N为大于或等于2的整数；
其中，在所述像素区中，所述第一通道走线分别与每列所述子像素对应的所述数据线连接。
可选的，在本申请一些实施例中，所述显示面板还包括多个像素区，每一所述像素区包括至少两列相邻的子像素，与同一条所述第一通道走线连接的多个所述子像素中，部分所述子像素位于一所述像素区中，另一部分所述子像素位于另一所述像素区中。
可选的，在本申请一些实施例中，所述显示面板还包括多条触控走线；多条所述触控走线沿所述第一方向间隔排布；
其中，所述显示面板还包括第二多路分配器，所述第二多路分配器包括多个第二控制单元和多条第二通道走线，多条所述第二通道走线沿所述第一方向间隔排布；每条所述第二通道走线与至少两条所述触控走线连接；每一所述第二控制单元包括多个第二开关元件；在共用同一条所述第二通道走线的至少两条所述触控走线中，至少一所述触控走线通过相应的至少一所述第二开关元件与一所述第二通道走线连接；所述第二控制单元设置在所述显示区内。
可选的，在本申请一些实施例中，沿所述数据线的延伸方向，所述显示区包括第一显示区和第二显示区，所述第一多路分配器设置在所述第二显示区，所述第二多路分配器设置在所述第一显示区以及所述第二显示区，在所述第二显示区中，所述第一开关元件设置在第奇数行子像素和第偶数行子像素中的一者中，所述第二开关元件设置在所述第奇数行子像素和所述第偶数行子像素中的另一者中。
可选的，在本申请一些实施例中，所述显示面板还包括多列子像素，每列所述子像素对应设有一条所述数据线；
沿所述第一方向，所述第一通道走线、所述触控走线以及所述第二通道走线分别邻近不同的所述数据线设置。
可选的，在本申请一些实施例中，所述显示面板还包括多个呈阵列排布的触控电极，每一所述触控电极与至少一条所述触控走线连接和/或对应每个所述触控电极设有两条所述第二通道走线。
可选的，在本申请一些实施例中，在所述第一显示区，对应每个所述触控电极设有两条所述第二通道走线，在所述第二显示区，对应每个所述触控电极设有四条所述第二通道走线。
可选的，在本申请一些实施例中，所述显示面板还包括多个呈阵列排布的触控电极，每一所述触控电极与至少一条所述触控走线连接，所述触控电极复用为公共电极；
其中，所述显示面板还包括多条第三通道走线；多条所述第三通道走线沿所述第一方向间隔排布，每条所述第三通道走线与相应的所述触控走线连接。
可选的，在本申请一些实施例中，所述显示面板还包括第三多路分配器，所述第三多路分配器包括多个第三控制单元；每条所述第三通道走线与至少两条所述触控走线连接；每一所述第三控制单元包括多个第三开关元件；在共用同一条所述第三通道走线的至少两条所述触控走线中，至少一所述触控走线通过相应的至少一所述第三开关元件与一所述第三通道走线连接。
可选的，在本申请一些实施例中，沿所述数据线的延伸方向，每一所述触控电极包括相连接的第一部分和第二部分，所述第二多路分配器对应所述第二部分设置，所述第三多路分配器对应所述第一部分设置。
相应的，本申请还提供一种显示装置，包括显示面板和驱动芯片，所述显示面板为上述任一项所述的显示面板，所述驱动芯片与所述第一通道走线连接。
 有益效果
本申请提供一种显示面板及显示装置。一方面，本申请实施例通过在显示面板中设置第一多路分配器，可以使用较少数量的第一通道走线向较多数量的数据线提供相应的数据信号，从而减少驱动芯片的数量，降低生产成本。第二方面，本申请实施例通过将第一多路分配器设置在显示区，可以减小显示面板的边框尺寸，利于实现窄边框化。第三方面，由于显示区内设有多个子像素，当将第一开关元件集成在显示区时，为了不影响子像素的开口率，每个第一开关元件的尺寸很小。可以理解的是，第一开关元件的电阻大小与器件尺寸有关，第一开关元件的尺寸小，电阻大，易导致数据信号传输不良。本申请实施例设置至少一数据线通过M个并联的第一开关元件与第一通道走线连接，可以提高信号传输良率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的显示面板的第一结构示意图；
图2是本申请提供的显示面板的第一平面示意图；
图3是本申请提供的显示面板的第二结构示意图；
图4是本申请提供的显示面板的第二平面示意图；
图5是本申请提供的显示面板的第三结构示意图；
图6是本申请提供的显示面板的第三平面示意图；
图7是本申请提供的触控电极与第二多路分配器以及第三多路分配器的结构示意图；
图8是本申请提供的显示面板的第四平面示意图；
图9是本申请提供的显示面板的第五平面示意图；
图10是本申请提供的显示装置的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。此外，需要说明的是，除非另有明确的规定和限定，术语“相连”、“连接”应做广义理解，例如，可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本申请提供一种显示面板及显示装置，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的显示面板的第一结构示意图。在本申请实施例中，显示面板100包括多条数据线D和第一多路分配器10。
其中，多条数据线D沿第一方向X间隔排布。第一多路分配器10包括至少一第一控制单元11和至少一条第一通道走线S。第一通道走线S的延伸方向与数据线D的延伸方向相同。每条第一通道走线S与至少两条数据线D连接。每一第一控制单元11包括多个第一开关元件T1。在共用同一条第一通道走线S的至少两条数据线D中，至少一数据线D通过M个并联的第一开关元件T1与第一通道走线S连接，M为大于或者等于2的整数。显示面板100具有显示区AA。第一控制单元11设置在显示区AA内。
在本申请实施例中，显示面板100还包括多条扫描线G（比如G1/G2/G3/G4/G5/G6等）。多条扫描线G沿数据线D的延伸方向间隔排布。多条扫描线G和多条数据线D交叉限定出多个子像素20。多个子像素20呈阵列排布。每一子像素20与相应的数据线D以及相应的扫描线G连接。由于同一条第一通道走线S与多条数据线D连接，通过多条扫描线G可以控制相应行的子像素20打开，避免数据信号传输错误。
其中，显示画面中呈现的子像素20可以是红色子像素、绿色子像素、蓝色子像素、白色子像素、黄色子像素等，本申请对此不作具体限定。本申请提供的显示面板100可以采用标准RGB像素排列架构、RGB PenTile像素排列架构、RGB Delta像素排列架构、RGBW像素排列架构等。当显示面板100采用标准RGB像素排列架构时，在同一行子像素20中，红色子像素、绿色子像素以及蓝色子像素可以以RGB、RBG、BGR、BRG、GRB、GBR等排列组合中的任一种重复排列。每一列子像素20的颜色相同。当然，本申请并不限于此，具体可根据显示面板100的显示需求进行设置。
在本申请实施例中，第一方面，通过在显示面板100中设置第一多路分配器10，可以使用较少数量的第一通道走线S向较多数量的数据线D提供相应的数据信号，从而减少驱动芯片的数量，降低生产成本。第二方面，Demux电路通常设置在边框区，其高度可达数百甚至上千微米，成为实现显示屏窄边框的一大困难。本申请实施例通过将第一多路分配器10设置在显示区AA，可以减小显示面板100的边框尺寸，利于实现窄边框化。第三方面，由于显示区AA内设有多个子像素20，当将第一开关元件T1集成在显示区AA时，为了不影响子像素20的开口率，第一开关元件T1的尺寸很小。可以理解的是，第一开关元件T1的电阻大小与器件尺寸有关，第一开关元件T1的尺寸很小，易导致数据信号传输不良。本申请实施例设置至少一数据线D通过M个并联的第一开关元件T1与第一通道走线S连接，可以提高数据信号的传输良率。
在本申请实施例中，第一多路分配器10还包括至少两条控制线Mux。至少两条控制线Mux沿数据线D的延伸方向间隔排布。每条控制线Mux均用于传输相应的控制信号。每一第一开关元件T1的控制端与相应的控制线Mux连接。控制线Mux用于控制第一开关元件T1打开或关闭。
其中，控制线Mux可以与扫描线G同层设置。一方面，有利于减少显示面板100的膜层结构，实现显示面板100的轻薄化；另一方面，在制作扫描线G的工艺中，可以同步形成控制线Mux，从而节省制作工艺，提高生产效率。当然，控制线Mux也可以与扫描线G由不同导电层形成。
其中，第一开关元件T1的输入极与相应的第一通道走线S连接。第一开关元件T1的输出极与相应的数据线D连接。其中，第一开关元件T1可以是薄膜晶体管。第一开关元件T1的控制端为薄膜晶体管的栅极。第一开关元件T1的输入极为薄膜晶体管的源极和漏极中的一者。第一开关元件T1的输出极为薄膜晶体管的源极和漏极中的另一者。控制线Mux控制与其相连的第一开关元件T1的打开或关闭，使得第一通道走线S可以将数据信号分别传输至相应的数据线D。
相应的，当第一开关元件T1为薄膜晶体管时，薄膜晶体管的沟道宽长比W/L越大，相同条件下电阻越小。但是，当第一开关元件T1的尺寸较小时，第一开关元件T1的沟道宽长比W/L很难达到预设要求，导致数据信号传输不良。因此，本申请实施例设置至少一数据线D通过至少两个并联的第一开关元件T1与第一通道走线S连接，多个并联的第一开关元件T1的电阻减小，可以提高数据信号的传输良率。
在本申请实施例中，控制线Mux的数量与与每条第一通道走线S1连接的数据线D的数量有关。每条第一通道走线S1可以与2条数据线D连接；每条第一通道走线S1也可以与3条数据线D连接；每条第一通道走线S1还可以与4条数据线D连接，本申请在此不一一详述。
需要说明的是，本申请以下各实施例均以每条第一通道走线S1与3条数据线D连接为例进行说明。相应的，控制线Mux包括第一控制线Mux1、第二控制线Mux2以及第三控制线Mux3。但不能理解为对本申请的限定。
在本申请一些实施例中，M条控制线Mux传输同一控制信号。与同一条数据线D连接的M个第一开关元件T1与传输同一控制信号的M条控制线Mux一一对应连接。也即，第一控制线Mux1、第二控制线Mux2以及第三控制线Mux3中的至少一者可以设置为M条。
具体的，请继续参阅图1，在本申请实施例中，第一控制线Mux1、第二控制线Mux2以及第三控制线Mux3分别设置为两条。两条第一控制线Mux1可以并联，以接入同一控制信号；两条第一控制线Mux1也可以分别接入同一控制信号。两条第二控制线Mux2可以并联，以接入同一控制信号；两条第二控制线Mux2也可以分别接入同一控制信号。两条第三控制线Mux3可以并联，以接入同一控制信号；两条第三控制线Mux3也可以分别接入同一控制信号。
其中，与第一条数据线D1或第四条数据线D4连接的两个第一开关元件T1与两条第一控制线Mux1一一对应连接。与第二条数据线D2或第五条数据线D5连接的两个第一开关元件T1与两条第二控制线Mux2一一对应连接。与第三条数据线D3或第六条数据线D6连接的两个第一开关元件T1与两条第三控制线Mux3一一对应连接。
其中，沿数据线D的延伸方向，多条控制线Mux可以以第一控制线Mux1、第二控制线Mux2以及第三控制线Mux3为单位重复排列。
由此，本申请实施例可以实现与同一条数据线D连接的多个第一开关元件T1的并联，提高多个第一开关元件T1的导电率，避免数据信号传输不良。
需要说明的是，在本申请一些实施例中，与同一条数据线D连接的第一开关元件T1还可以为3个、4个或者更多个。对应的，可以设置3条、4条或者更多条第一控制线Mux1（第二控制线Mux2或第三控制线Mux3），在此不再赘述。
当然，在本申请一些实施例中，第一多路分配器10还可以包括至少两条控制线Mux，至少两条控制线Mux传输不同的控制信号。与同一条数据线D连接的多个第一开关元件T1的控制端连接于同一条控制线Mux。
本申请实施例可以减少控制线Mux的数量。其中一些第一开关元件T1可以通过换线方式与相应的控制线Mux连接，在此不再详述。
进一步的，在本申请一些实施例中，多个第一开关元件T1设置在不同的子像素20中。每行子像素20中至多设有一条控制线Mux。
可以理解的是，显示面板100对像素开口率具有一定的规格要求。本申请实施例将多个第一开关元件T1分别设置在不同的子像素20中，以及在相应行子像素20中仅设置一条控制线Mux，可以降低对像素开口率的影响，提高显示面板100的显示均一性。
在本申请实施例中，与同一条第一通道走线S连接的数据线D的数据电压极性相同。当然，在一些实施例中，若在驱动芯片内对数据电压的极性进行调整变换，也可以使得与同一条第一通道走线S连接的数据线D的数据电压极性不同。
在本申请实施例中，通过调整各数据线D与第一通道走线S的连接方式，或者调整各子像素20与数据线D的连接方式，可以实现不同的驱动方式，比如点反转、列反转、帧反转、行反转等。
请继续参阅图1，在本申请实施例中，显示面板100还包括至少一像素区201。沿第一方向X，像素区201包括2N列子像素20。每一像素区201设有两条第一通道走线S。每列子像素20对应设有一条数据线D。其中N为大于或等于2的整数。
其中，相邻两条第一通道走线S的数据电压极性相反。在每一像素区201中，沿第一方向X，第一条第一通道走线S1分别与第奇数条数据线D连接。第二条第一通道走线S2分别与第偶数条数据线D连接。
通过上述连接方式，可实现每一列子像素20的极性相同，每一行子像素20中的相邻两个子像素20的极性相反。也即，本申请实施例可实现列反转的驱动方式，改善画面串扰等显示问题。
进一步的，本申请实施例以N为3，像素区201包括6列子像素20为例进行说明。也即，每条第一通道走线S分别向3条数据线D传输相应的数据信号。
具体的，在每一像素区201中，沿第一方向X，第一条第一通道走线S1邻近第一条数据线D1设置，比如第一条第一通道走线S1设置在第一条数据线D1的左侧；第二条第一通道走线S2邻近第四条数据线D4设置，比如第二条第一通道走线S2设置在第四条数据线D4的左侧。第一条第一通道走线S1分别与第一条数据线D1、第五条数据线D5以及第三条数据线D3连接。第二条第一通道走线S2分别与第四条数据线D4、第二条数据线D2以及第六条数据线D6连接。
其中，第一条第一通道走线S1传输正极性的数据信号；第二条第一通道走线S2传输负极性的数据信号。因此，沿第一方向X，第一列子像素20、第三列子像素20以及第五列子像素20均为正极性；第二列子像素20、第四列子像素20以及第六列子像素20均为负极性。
在本申请实施例中，每一像素区201可以包括至少两列相邻的子像素20。比如，每一像素区201可以包括RGB三列子像素20。与同一条第一通道走线S连接的多个子像素20中，部分子像素20位于一像素区201中，另一部分子像素20位于另一像素区201中。通过在面内设计换线连接，可以实现位于不同像素区201的各子像素20所需要的数据电压极性。
进一步的，请参阅图1和图2，图2是本申请提供的显示面板的第一平面示意图。如图2所示，由于第一条第一通道走线S1设置在第一条数据线D1的左侧，为避免不同信号线之间发生短路，需要通过多次换线设计才能实现第一条第一通道走线S1与第五条数据线D5之间的连接。同理，由于第二条第一通道走线S2设置在第四条数据线D4的左侧，需要通过多次换线设计才能实现第二条第一通道走线S2与第二条数据线D2的连接。多次换线设计导致像素开口率有一定的损失。
对此，请参阅图3和图4，图3是本申请提供的显示面板的第二结构示意图；图4是本申请提供的显示面板的第二平面示意图。与图1和图2所示的显示面板100的不同之处在于，在本申请实施例中，相邻两条第一通道走线S之间设有至少一条辅助通道走线，与辅助通道走线连接的第一开关元件T1设置在与辅助通道走线邻近的子像素20中。
其中，沿第一方向X，在相邻的两条第一通道走线S和一条辅助通道走线中，前一条第一通道走线S的数据电压极性与辅助通道走线的数据电压极性相反。后一条第一通道走线S的数据电压极性与辅助通道走线的数据电压极性相同。
本申请实施例在相邻两条第一通道走线S之间增设辅助通道走线，通过控制辅助通道走线的电压极性，可以实现列反转；同时，将与辅助通道走线连接的第一开关元件T1设置在与辅助通道走线邻近的子像素20中，在不换线的情况下，可以实现辅助通道走线与相应子像素20以及数据线D的连接。
进一步的，在一具体实施例中，每一像素区201包括六列子像素20。每一像素区201设有四条第一通道走线S。每列子像素20对应设有一条数据线D。
其中，在每一像素区201中，沿第一方向X，第一条第一通道走线S1分别与第一条数据线D1和第三条数据线D3连接。第二条第一通道走线S2与第二条数据线D2连接。第三条第一通道走线S3分别与第四条数据线D4和第六条数据线D6连接。第四条第一通道走线S4与第五条数据线D5连接。
其中，第二条第一通道走线S2和第四条第一通道走线S4均为辅助通道走线。第一条第一通道走线S1与第四条第一通道走线S4的数据电压极性相同。第二条第一通道走线S2与第三条第一通道走线S3的数据电压极性相同。第一条第一通道走线S1与第二条第一通道走线S2的的数据电压极性相反。
由此，在实现列反转的驱动方式的同时，可以减少显示区AA内的换线，从而增大像素开口率，改善画面显示效果。
进一步的，在本申请实施例中，第一条第一通道走线S1与第四条第一通道走线S4并联；第二条第一通道走线S2与第三条第一通道走线S3并联。
可以理解的是，由于第一条第一通道走线S1与第四条第一通道走线S4的数据电压极性相同，且分别与第一通道走线S1以及第四条第一通道走线S4连接的三条数据线D分别通过不同的第一开关元件T1实现数据信号的传输，因此可以将第一条第一通道走线S1与第四条第一通道走线S4并联设计，进一步减少第一通道走线S的数量，从而减少驱动芯片的数量。同理，将第二条第一通道走线S2与第三条第一通道走线S3并联设计，也可以减少驱动芯片的数量，降低生产成本。
在本申请一些实施例中，请参阅图5，图5是本申请提供的显示面板的第三平面示意图。与图1和图2所示的显示面板100的不同之处在于，在本申请实施例中，沿第一方向X，像素区201包括N列子像素20。每一像素区201设有一条第一通道走线S。N为大于或等于2的整数。其中，在每一像素区201中，第一通道走线S分别与每列子像素20对应的数据线D连接。
如图5所示，本申请实施例以N=3为例进行说明，但不能理解为对本申请的限定。具体的，沿第一方向X，第一条第一通道走线S1分别与第一条数据线D1、第二条数据线D2以及第三条数据线D3连接。第二条第一通道走线S2分别与第四条数据线D4、第五条数据线D5以及第六条数据线D6连接。
在本申请实施例中，多条第一通道走线S可以传输极性相同的数据信号。同时显示区AA内的换线设计很少，进一步提高了像素开口率。
在本申请一些实施例中，请参阅图6和图7，图6是本申请提供的显示面板的第三平面示意图；图7是本申请提供的触控电极与第二多路分配器以及第三多路分配器的结构示意图。与图1以及图2所示的显示面板100的不同之处在于，在本申请实施例中，显示面板100还包括多条触控走线RX。多条触控走线RX沿第一方向X间隔排布。
其中，显示面板100还包括第二多路分配器40。第二多路分配器40包括多个第二控制单元41和多条第二通道走线TPS。第二通道走线TPS沿第一方X间隔排布。每条第二通道走线TPS与至少两条触控走线RX连接。每一第二控制单元41包括多个第二开关元件T2。在共用同一条第二通道走线TPS的多条触控走线RX中，至少一触控走线RX通过相应的至少一第二开关元件T2与一第二通道走线TPS连接。
本申请通过将第二多路分配器40设置在显示区AA内，可以进一步减小显示面板100的边框尺寸，利于实现窄边框化。
需要说明的是，为了提高显示面板100的显示均一性，第一通道走线S和第二通道走线TPS可以设置在不同列子像素20中。
在本申请实施例中，显示面板100还包括多个触控电极30。每个触控电极30可对应多个子像素20设计。比如，每个触控电极30可对应40行40列子像素20设置，本申请对此不作具体限定。图6仅示出触控电极30的部分结构，但不能理解为对本申请的限定。
其中，每一触控电极30与至少一条触控走线RX连接。可以理解的是，由于触控电极30的面积较大，为了提高触控信号的分布均匀性，可以设置多条触控走线RX与同一触控电极30连接，以传输触控信号至触控电极30的不同位置处。
其中，对应每个触控电极30设有至少一条第二通道走线TPS。同理，由于触控电极30的面积较大，通过设置多条第二通道走线TPS，可以为多条触控走线RX提供触控信号。当对应每列触控电极30设置多条第二通道走线TPS时，多条第二通道走线TPS可以并联在一起，进一步减少驱动芯片的通道数量。
如图6所示，本申请实施例以每一触控电极30与3条触控走线RX连接为例进行说明。其中，沿第一方向X，第二条触控走线RX2通过第二开关元件T2与第一条第二通道走线TPS1连接；第二条触控走线RX2通过第二开关元件T2与第二条第二通道走线TPS2连接。
其中，第二多路分配器40还包括多条控制信号线TPMux。多条控制信号线TPMux沿数据线D的延伸方向间隔设置。同理，本申请实施例可以设置至少一触控走线RX通过多个并联的第二开关元件T2与一第二通道走线TPS连接，以提高触控信号的传输良率。比如，如图6所示，第一条控制信号线TPMux1设置为两条，每条触控走线RX通过两个第二开关元件T2与同一条第二通道走线TPS连接。两个第二开关元件T2分别与两条第一条控制信号线TPMux1对应连接，从而实现两个第二开关元件T2的并联。
如图7所示，第二多路分配器40包括两条接入不同控制信号的控制信号线TPMux。沿数据线D的延伸方向，在相邻两个触控电极30中，第一条控制信号线TPMux1用于控制第一条第二通道走线TPS1以及第二条第二通道走线TPS2将触控信号传输至上方的触控电极30。第二条控制信号线TPMux2用于控制第一条第二通道走线TPS1以及第二条第二通道走线TPS2将触控信号传输至下方的触控电极30。也即，同一条第二通道走线TPS与至少两条触控走线RX连接，进而控制至少上下两个触控电极30，使得奇数行和偶数行的触控电极30不同时工作。
为了提高显示面板100的显示均一性，第一通道走线S、触控走线RX以及第二通道走线TPS可以分别邻近不同的数据线D设置。
在本申请实施例中，显示面板100还包括多条第三通道走线VS。多条第三通道走线VS沿第一方向X间隔排布。每条第三通道走线VS与相应的触控电极30连接。图6中仅示出的1条第三通道走线VS，但不能理解为对本申请的限定。
需要说明的是，为了提高显示面板100的显示均一性，第一通道走线S、第二通道走线TPS以及第三通道走线VS可以分别邻近不同的数据线D设置。
在本申请一些实施例中，触控电极30可以复用为公共电极。在显示阶段，每条第三通道走线VS传输公共电压至相应的触控电极30。在触控阶段，每条第三通道走线VS传输触控信号至相应的触控电极30。由于触控电极30的面积较大，利用第三通道走线VS传输触控信号至相应的触控电极30，可以增强触控信号的强度，提高触控信号的分布均匀性。
在本申请一些实施例中，显示面板100还包括第三多路分配器50。第三多路分配器50包括多个第三控制单元51。每条第三通道走线VS与至少两条触控走线RX连接。每一第三控制单元51包括多个第三开关元件T3。在共用同一条第三通道走线VS的多条触控走线RX中，至少一触控走线RX通过相应的至少一第三开关元件T3与一第三通道走线VS连接。
本申请通过将第三多路分配器50设置在显示区AA内，可以进一步减小显示面板100的边框尺寸，利于实现窄边框化。同理，本申请实施例可以设置至少一触控走线RX通过多个并联的第三开关元件T3与第三通道走线VS连接，可以提高触控信号传输良率。
需要说明的是，第二开关元件T2以及第三开关元件T3的结构以及连接方式可参阅上述实施例中的第一开关元件T1，在此不再赘述。
其中，第三多路分配器50还包括多条控制走线VMux。多条控制走线VMux沿数据线D的延伸方向间隔设置。图6中仅示出了一条控制走线VMux，但不能理解为对本申请的限定。
同理，本申请实施例可以设置至少一触控走线RX通过多个并联的第三开关元件T3与第三通道走线VS连接，以提高触控信号的传输良率。比如，如图6所示，第一条控制走线VMux1设置为两条，每条触控走线RX通过两个第三开关元件T3与同一条第三通道走线VS连接。两个第三开关元件T3分别与两条第一条控制走线VMux1对应连接，从而实现两个第三开关元件T3的并联。
具体的，如图6和图7所示，第三多路分配器50包括两条接入不同控制信号的控制走线VMux。沿数据线D的延伸方向，在相邻两个触控电极30中，第一条控制走线VMux1用于控制第三通道走线VS将触控信号传输至第上方的触控电极30。第二条控制走线VMux2用于控制第三通道走线VS将触控信号传输至下方的触控电极30。
进一步的，在本申请一些实施例中，如图7所示，沿数据线D的延伸方向，每一触控电极30包括相连接的第一部分31和第二部分32。第二多路分配器40对应第二部分32设置，第三多路分配器50对应第一部分31设置。
可以理解的是，本申请实施例将第二多路分配器40和第三多路分配器50分区域设置，可以保证显示面板100的显示均一性。
在本申请一些实施例中，请同时参阅图1、图6以及图8，沿数据线D的延伸方向，显示区AA包括第一显示区AA1和第二显示区AA2。第一多路分配器10设置在第二显示区AA2。第二多路分配器40设置在第一显示区AA1和第二显示区AA2中。在第二显示区AA2中，第一开关元件T1设置在第奇数行子像素和第偶数行子像素中的一者中。第二开关元件T2设置在第奇数行子像素和第偶数行子像素中的另一者中。
进一步的，第三多路分配器50可以设置在第一显示区AA1和第二显示区AA2中。第一开关元件T1和第三开关元件T3也设置在不同行子像素20中。
比如，以分辨率为1920×720的显示面板100为例，在显示面板100的下方240行（占据6个触控电极30的高度）中，第一多路分配器10、第二多路分配器40以及第三多路分配器50分布在显示面板100的不同区域。在显示面板100上方的480行（占据12个触控电极30的高度）中，仅设置第二多路分配器40和第三多路分配器50。当然，本申请并不限于此。
由此，可以将第一多路分配器10、第二多路分配器40以及第三多路分配器50均匀设置在显示区AA中，提高显示面板100的显示均一性。
此外，在本申请一些实施例中，在第一显示区AA1，如图9所示，对应每个触控电极30设有两条第二通道走线TPS；在第二显示区AA2，如图6所示，对应每个触控电极30设有四条第二通道走线TPS。
进一步的，在第一显示区AA1，对应每个触控电极30设有一条第三通道走线VS，在第二显示区AA2，对应每个触控电极30设有两条第三通道走线VS。
可以理解的是，第二显示区AA2中同时设有第一多路分配器10、第二多路分配器40以及第三多路分配器50，第一多路分配器10占用了一部分布线空间。由此，在第二显示区AA2中，第二开关元件T2和第三开关T3只能设置在第奇数行子像素和第偶数行子像素中的一者中，以与第一开关元件T1交错布置。因此，为了提高触控信号的传输良率，本申请实施例在第二显示区AA2中，对应每个触控电极30设置四条第二通道走线TPS和两条第三通道走线VS。
相应的，本申请还提供一种显示装置。显示装置包括显示面板。显示面板为上述任一实施例所述的显示面板100，在此不再赘述。
此外，显示装置可以是智能手机、平板电脑、电子书阅读器、智能手表、摄像机、游戏机等，本申请对此不作限定。
具体的，请参阅图10，图10是本申请提供的显示装置的一种结构示意图。在本申请实施例中，显示装置1000包括显示面板100和驱动芯片200。驱动芯片200与多条第一通道走线S连接。
其中，驱动芯片200可以是源极驱动芯片。驱动芯片200用于提供数据信号至多条第一通道走线S，进而驱动各子像素进行画面显示。
在本申请实施例中，第二通道走线TPS以及第三通道走线VS也可以与驱动芯片200连接。驱动芯片200还用于提供触控信号以及公共电压，提高了驱动芯片200的集成度，减少了驱动芯片200的数量。
本申请实施例中的显示装置1000包括显示面板100，显示面板100包括多条数据线以及第一多路分配器。多条数据线沿第一方向间隔排布；第一多路分配器包括至少一第一控制单元和至少一条第一通道走线，第一通道走线的延伸方向与数据线的延伸方向相同；每条第一通道走线与至少两条数据线连接；每一第一控制单元包括多个第一开关元件；在共用同一条第一通道走线的至少两条数据线中，至少一数据线通过M个并联的第一开关元件与第一通道走线连接，M≥2；其中，显示面板具有显示区，第一控制单元设置在显示区内。本申请实施例将第一多路分配器集成于显示区，可以减小显示面板100的边框尺寸，利于实现显示装置1000的窄边框化。
以上对本申请实施例提供的显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其包括：
    多条数据线，多条所述数据线沿第一方向间隔排布；
    第一多路分配器，所述第一多路分配器包括至少一第一控制单元和至少一条第一通道走线，所述第一通道走线的延伸方向与所述数据线的延伸方向相同；每条所述第一通道走线与至少两条所述数据线连接；每一所述第一控制单元包括多个第一开关元件；在共用同一条所述第一通道走线的至少两条所述数据线中，至少一所述数据线通过M个并联的所述第一开关元件与所述第一通道走线连接，M≥2；
    其中，所述显示面板具有显示区，所述第一控制单元设置在所述显示区内。
  2. 根据权利要求1所述的显示面板，其中，所述第一多路分配器还包括至少两条控制线，至少两条所述控制线沿所述数据线的延伸方向间隔排布，至少两条所述控制线传输不同的控制信号，与同一条所述数据线连接的M个所述第一开关元件均连接于同一条所述控制线。
  3. 根据权利要求1所述的显示面板，其中，所述第一多路分配器还包括至少两条控制线，至少两条所述控制线沿所述数据线的延伸方向间隔排布；
    其中，M条所述控制线传输同一控制信号；与同一条所述数据线连接的M个所述第一开关元件与传输同一所述控制信号的M条所述控制线一一对应连接。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括多个呈阵列排布的子像素，多个所述第一开关元件设置在不同的所述子像素中，每行所述子像素中至多设有一条所述控制线。
  5. 根据权利要求1所述的显示面板，其中，与同一条所述第一通道走线连接的所述数据线的数据电压极性相同。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括至少一像素区，沿所述第一方向，所述像素区包括2N列子像素，所述像素区设有两条所述第一通道走线，每列所述子像素对应设有一条所述数据线，N为大于或等于2的整数；
    其中，相邻两条所述第一通道走线的数据电压极性相反，在所述像素区中，沿所述第一方向，第一条所述第一通道走线分别与第奇数条所述数据线连接；第二条所述第一通道走线分别与第偶数条所述数据线连接。
  7. 根据权利要求5所述的显示面板，其中，所述显示面板还包括多列子像素，相邻两列所述子像素的数据电压极性相反，相邻两条所述第一通道走线的数据电压极性相反；
    其中，相邻两条所述第一通道走线之间设有至少一条辅助通道走线，与所述辅助通道走线连接的所述第一开关元件设置在与所述辅助通道走线邻近的所述子像素中。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板还包括至少一像素区，所述像素区包括六列子像素，所述像素区设有四条所述第一通道走线，每列所述子像素对应设有一条所述数据线；
    其中，在所述像素区中，沿所述第一方向，第一条所述第一通道走线分别与第一条所述数据线以及第三条所述数据线连接；第二条所述第一通道走线与第二条所述数据线连接，第三条所述第一通道走线分别与第四条所述数据线以及第六条所述数据线连接，第四条所述第一通道走线与第五条所述数据线连接；第二条所述第一通道走线和第四条所述第一通道走线均为所述辅助通道走线。
  9. 根据权利要求8所述的显示面板，其中，第一条所述第一通道走线与第四条所述第一通道走线并联，第二条所述第一通道走线与第三条所述第一通道走线并联。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括至少一像素区，沿所述第一方向，所述像素区包括N列所述子像素，所述像素区设有一条所述第一通道走线，N为大于或等于2的整数；
    其中，在所述像素区中，所述第一通道走线分别与每列所述子像素对应的所述数据线连接。
  11. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个像素区，每一所述像素区包括至少两列相邻的子像素，与同一条所述第一通道走线连接的多个所述子像素中，部分所述子像素位于一所述像素区中，另一部分所述子像素位于另一所述像素区中。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多条触控走线；多条所述触控走线沿所述第一方向间隔排布；
    其中，所述显示面板还包括第二多路分配器，所述第二多路分配器包括多个第二控制单元和多条第二通道走线，多条所述第二通道走线沿所述第一方向间隔排布；每条所述第二通道走线与至少两条所述触控走线连接；每一所述第二控制单元包括多个第二开关元件；在共用同一条所述第二通道走线的至少两条所述触控走线中，至少一所述触控走线通过相应的至少一所述第二开关元件与一所述第二通道走线连接；所述第二控制单元设置在所述显示区内。
  13. 根据权利要求12所述的显示面板，其中，沿所述数据线的延伸方向，所述显示区包括第一显示区和第二显示区，所述第一多路分配器设置在所述第二显示区，所述第二多路分配器设置在所述第一显示区以及所述第二显示区，在所述第二显示区中，所述第一开关元件设置在第奇数行子像素和第偶数行子像素中的一者中，所述第二开关元件设置在所述第奇数行子像素和所述第偶数行子像素中的另一者中。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板还包括多列子像素，每列所述子像素对应设有一条所述数据线；
    沿所述第一方向，所述第一通道走线、所述触控走线以及所述第二通道走线分别邻近不同的所述数据线设置。
  15. 根据权利要求13所述的显示面板，其中，所述显示面板还包括多个呈阵列排布的触控电极，每一所述触控电极与至少一条所述触控走线连接和/或对应每个所述触控电极设有至少一条所述第二通道走线。
  16. 根据权利要求15所述的显示面板，其中，在所述第一显示区，对应每个所述触控电极设有两条所述第二通道走线，在所述第二显示区，对应每个所述触控电极设有四条所述第二通道走线。
  17. 根据权利要求12所述的显示面板，其中，所述显示面板还包括多个呈阵列排布的触控电极，每一所述触控电极与至少一条所述触控走线连接，所述触控电极复用为公共电极；
    其中，所述显示面板还包括多条第三通道走线；多条所述第三通道走线沿所述第一方向间隔排布，每条所述第三通道走线与相应的一所述触控走线连接。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括第三多路分配器，所述第三多路分配器包括多个第三控制单元；每条所述第三通道走线与至少两条所述触控走线连接；每一所述第三控制单元包括多个第三开关元件；在共用同一条所述第三通道走线的至少两条所述触控走线中，至少一所述触控走线通过相应的至少一所述第三开关元件与一所述第三通道走线连接；所述第三控制单元设置在所述显示区内。
  19. 根据权利要求18所述的显示面板，其中，沿所述数据线的延伸方向，每一所述触控电极包括相连接的第一部分和第二部分，所述第二多路分配器对应所述第二部分设置，所述第三多路分配器对应所述第一部分设置。
  20. 一种显示装置，包括显示面板和驱动芯片，所述显示面板为权利要求1所述的显示面板，所述驱动芯片与所述第一通道走线连接。
PCT/CN2022/129830 2022-09-21 2022-11-04 显示面板及显示装置 WO2024060363A1 (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105549792A (zh) * 2016-02-05 2016-05-04 上海天马微电子有限公司 阵列基板以及显示面板
CN107039467A (zh) * 2017-05-15 2017-08-11 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN109887458A (zh) * 2019-03-26 2019-06-14 厦门天马微电子有限公司 显示面板和显示装置
CN111752413A (zh) * 2020-06-22 2020-10-09 Oppo广东移动通信有限公司 触控显示面板及其驱动方法、显示装置
CN113282187A (zh) * 2020-02-20 2021-08-20 上海中航光电子有限公司 显示面板和显示装置
CN114115606A (zh) * 2021-11-30 2022-03-01 武汉华星光电半导体显示技术有限公司 触控显示面板及显示装置
CN114637147A (zh) * 2022-03-30 2022-06-17 广州华星光电半导体显示技术有限公司 显示面板及显示装置
US20220208124A1 (en) * 2020-12-24 2022-06-30 Lg Display Co., Ltd. Display device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105549792A (zh) * 2016-02-05 2016-05-04 上海天马微电子有限公司 阵列基板以及显示面板
CN107039467A (zh) * 2017-05-15 2017-08-11 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN109887458A (zh) * 2019-03-26 2019-06-14 厦门天马微电子有限公司 显示面板和显示装置
CN113282187A (zh) * 2020-02-20 2021-08-20 上海中航光电子有限公司 显示面板和显示装置
CN111752413A (zh) * 2020-06-22 2020-10-09 Oppo广东移动通信有限公司 触控显示面板及其驱动方法、显示装置
US20220208124A1 (en) * 2020-12-24 2022-06-30 Lg Display Co., Ltd. Display device
CN114115606A (zh) * 2021-11-30 2022-03-01 武汉华星光电半导体显示技术有限公司 触控显示面板及显示装置
CN114637147A (zh) * 2022-03-30 2022-06-17 广州华星光电半导体显示技术有限公司 显示面板及显示装置

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