WO2019223663A1 - 像素排布结构、其驱动方法、显示面板及显示装置 - Google Patents

像素排布结构、其驱动方法、显示面板及显示装置 Download PDF

Info

Publication number
WO2019223663A1
WO2019223663A1 PCT/CN2019/087671 CN2019087671W WO2019223663A1 WO 2019223663 A1 WO2019223663 A1 WO 2019223663A1 CN 2019087671 W CN2019087671 W CN 2019087671W WO 2019223663 A1 WO2019223663 A1 WO 2019223663A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
polarity
pixel
sub
selectors
Prior art date
Application number
PCT/CN2019/087671
Other languages
English (en)
French (fr)
Inventor
马明超
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/649,643 priority Critical patent/US10991327B2/en
Publication of WO2019223663A1 publication Critical patent/WO2019223663A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel arrangement structure, a method for driving the pixel arrangement structure, a display panel, and a display device.
  • Thin film transistor liquid crystal displays are widely used in mobile products such as mobile phones and tablet computers.
  • TFT-LCD Thin film transistor liquid crystal displays
  • RGBW Red Green Blue White
  • a pixel arrangement structure including: a plurality of pixel repeating units arranged in a matrix in a row direction and a column direction, each of the plurality of pixel repeating units being included in a column
  • the second pixel unit includes a third sub-pixel, a fourth sub-pixel, a first sub-pixel, and a second sub-pixel arranged in order in a row direction; and a plurality of data lines extending in a column direction.
  • the first sub-pixel in rows 4m + 1 and 4n + 1, the third sub-pixel in rows 4m + 2 and 4n + 1, the third sub-pixel in rows 4m + 3 and 4n + 2 are connected to the 4n + 1th data line of the plurality of data lines.
  • Three sub-pixels, and the first sub-pixel in the 4m + 4th row and the 4n + 3th column are connected to the 4n + 2th data line of the plurality of data lines.
  • the third sub-pixel in rows 4m + 1 and 4n + 3, the first sub-pixel in rows 4m + 2 and 4n + 3, the third sub-pixel in rows 4m + 3 and 4n + 4 Four sub-pixels, and the second sub-pixel in the 4m + 4th row and the 4n + 4th column are connected to the 4n + 3th data line of the plurality of data lines.
  • One sub-pixel, and the third sub-pixel in the 4m + 4th row and the 4n + 5th column are connected to the 4n + 4th data line of the plurality of data lines.
  • m and n are integers greater than or equal to zero.
  • the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are selected from a red subpixel, a green subpixel, a blue subpixel, and a white subpixel. Each sub-pixel in the pixel is different.
  • a method for driving a pixel arrangement structure as described above includes applying a corresponding data voltage to the data line in one frame period so that any two pixel repeating units adjacent in a row direction have opposite data voltage polarity patterns.
  • the sub-pixels in the 4i + 1th row and the 8j + 1th to 8j + 4th columns have data voltages with the following polarities: first polarity, second polarity, second polarity, and First polarity.
  • the sub-pixels in the 4i + 2 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities, respectively: first polarity, second polarity, second polarity, and first polarity.
  • the sub-pixels in the 4i + 3 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities: the second polarity, the first polarity, the second polarity, and the second polarity, respectively.
  • the sub-pixels in the 4i + 4th row and the 8j + 1th to 8j + 4th columns have data voltages of the following polarities: the second polarity, the first polarity, the second polarity, and the second polarity, respectively.
  • i and j are integers greater than or equal to 0, i ⁇ m, j ⁇ n / 2.
  • the sub-pixels in rows 4i + 1 and columns 8j + 1 to 8j + 4 have data voltages of the following polarities: first polarity, first polarity, second polarity, and First polarity.
  • the sub-pixels in the 4i + 2 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities, respectively: first polarity, first polarity, second polarity, and first polarity.
  • the sub-pixels in the 4i + 3 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities: the second polarity, the first polarity, the first polarity, and the second polarity, respectively.
  • the sub-pixels in the 4i + 4th row and the 8j + 1th to 8j + 4th columns have data voltages of the following polarities: the second polarity, the first polarity, the first polarity, and the second polarity, respectively.
  • i and j are integers greater than or equal to 0, i ⁇ m, j ⁇ n / 2.
  • the first polarity and the second polarity select different polarities from each of a positive polarity and a negative polarity.
  • a display panel including the pixel arrangement structure as described above.
  • the display panel further includes a plurality of data selectors located at the same end of the plurality of data lines and configured to transmit a data voltage to a corresponding one of the plurality of data lines.
  • the plurality of data selectors include a plurality of three-to-one data selectors, and each of the three-to-one data selectors includes a data input terminal and three data output terminals.
  • the three data output terminals of the 8k + 1th three-to-one data selector in the plurality of three-to-one data selectors are respectively connected to the 24k + 1 in the plurality of data lines. 24k + 4 and 24k + 6 data lines.
  • the three data output terminals of the 8k + 2 three-to-one data selector in the plurality of three-to-one data selectors are respectively connected to the 24k + 2 and 24k + 3 of the plurality of data lines. And 24k + 5 data lines.
  • the three data output terminals of the 8k + 3 three-to-one data selector in the plurality of three-to-one data selectors are respectively connected to the 24k + 7 and 24k + 9 of the plurality of data lines.
  • the three data output terminals of the 8k + 4 three-to-one data selector in the plurality of three-to-one data selectors are respectively connected to the 24k + 8 and 24k + 10 of the multiple data lines And 24k + 11 data lines.
  • the three data output terminals of the 8k + 5 three-to-one data selectors in the plurality of three-to-one data selectors are respectively connected to the 24k + 13 and 24k + 16 of the multiple data lines And 24k + 18 data lines.
  • the three data output terminals of the 8k + 6 three-to-one data selectors in the plurality of three-to-one data selectors are respectively connected to the 24k + 14 and 24k + 15 of the multiple data lines And 24k + 17 data lines.
  • the three data output terminals of the 8k + 7 three-select one-to-one data selector among the plurality of three-to-one data selectors are respectively connected to the 24k + 19 and 24k + 21 of the multiple data lines And 24k + 24 data lines.
  • the three data output terminals of the 8k + 8 three-to-one data selectors in the plurality of three-to-one data selectors are respectively connected to the 24k + 20 and 24k + 22 of the plurality of data lines And 24k + 23 data lines.
  • k is an integer greater than or equal to 0, and k ⁇ (n-5) / 6.
  • data input of the 8k + 1th, 8k + 3, 8k + 6, and 8k + 8 three-to-one data selectors in the plurality of three-to-one data selectors The terminal is configured to receive a data voltage of a first polarity in a frame period.
  • the data input ends of the 8k + 2, 8k + 4, 8k + 5, and 8k + 7 three-to-one data selectors of the three-to-one data selector are configured to The data voltage of the second polarity is received in the frame period.
  • the second polarity is opposite to the first polarity.
  • the plurality of data selectors include a plurality of four-to-one data selectors, and each of the four-to-one data selectors includes a data input terminal and four data output terminals.
  • the four data output terminals of the 2k + 1th four-to-one data selector in the plurality of four-to-one data selectors are respectively connected to the 8k + 1th in the plurality of data lines. 8k + 4, 8k + 6, and 8k + 7 data lines.
  • the four data output terminals of the 2k + 2 four-to-one data selector in the plurality of four-to-one data selectors are respectively connected to the 8k + 2 and 8k + 3 of the plurality of data lines. 8k + 5 and 8k + 8 data lines.
  • k is an integer greater than or equal to 0, and k ⁇ (n-1) / 2.
  • a data input terminal of a 2k + 1 quadruple-to-one data selector in the plurality of quad-to-one data selectors is configured to receive a data voltage of a first polarity in a frame period.
  • a data input terminal of a 2k + 2 four-to-one data selector in the plurality of four-to-one data selectors is configured to receive a data voltage of a second polarity in the frame period. The second polarity is opposite to the first polarity.
  • a display device including a display panel as described above.
  • FIG. 1 is a schematic plan view of a pixel arrangement structure in the related art
  • FIG. 2 is a schematic plan view of a pixel arrangement structure according to an embodiment of the present disclosure
  • FIG. 3 is an example polar pattern for the pixel arrangement structure of FIG. 2;
  • FIG. 4 is another example polar pattern for the pixel arrangement structure of FIG. 2;
  • FIG. 5 is a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic plan view of a display panel according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections Portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below can be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • Spatial relative terms such as “above” and the like may be used herein to describe the relationship between one element or feature and another element or features as illustrated in the figure for ease of description. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below other elements or features” or “below other elements or features” or “below other elements or features” would then be oriented as “under other elements or features" Over features.
  • the exemplary terms “below” and “below” can encompass both orientations above and below. Terms such as “before” or “before” and “after” or “following” may similarly be used, for example, to indicate the order in which light passes through an element.
  • the device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as being “between two layers”, it may be the only layer between the two layers, or one or more intervening layers may also be present.
  • Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the shapes of the illustrations should be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments of the present disclosure should not be interpreted as being limited to the specific shape of the regions illustrated herein, but should include shape deviations due to manufacturing, for example. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
  • FIG. 1 illustrates a pixel arrangement structure 100 in the related art.
  • the pixel arrangement structure 100 includes a plurality of sub-pixels (more specifically, pixel electrodes) arranged in rows and columns, and sub-pixels of different columns are connected to respective different data lines DL.
  • data voltages of the same polarity are applied to the same column of sub-pixels through a corresponding data line DL.
  • This can induce a coupling voltage of a single polarity on a common electrode (not shown), and obtain a polarity pattern as shown in FIG. 1.
  • display defects such as vertical lines (“mura") may occur.
  • FIG. 2 is a schematic plan view of a pixel arrangement structure 200 according to an embodiment of the present disclosure.
  • the pixel arrangement structure 200 includes a plurality of pixel repeating units 210 arranged in a matrix in a row direction D1 and a column direction D2.
  • Each pixel repeating unit 210 includes a first pixel unit 211 and a first pixel unit 212 arranged in a column direction D2.
  • the first pixel unit 211 includes a first sub-pixel 201, a second sub-pixel 202, a third sub-pixel 203, and a fourth sub-pixel 204 which are sequentially arranged along the row direction D1.
  • the second pixel unit 212 includes a third sub-pixel 203, a fourth sub-pixel 204, a first sub-pixel 201, and a second sub-pixel 202 that are sequentially arranged along the row direction D1.
  • the first, second, third, and fourth sub-pixels 201, 202, 203, and 204 are selected from different sub-pixels among red, green, blue, and white sub-pixels.
  • the first, second, third, and fourth sub-pixels 201, 202, 203, and 204 are respectively a red sub-pixel (R), a green sub-pixel (G), a blue sub-pixel (B), and a white sub-pixel ( W).
  • each column of sub-pixels in the pixel arrangement structure 200 is divided into a sub-pixel connected to a first subset of the first data line and a second subset connected to the second data line.
  • Sub-pixels of the first sub-set include 4k + 1 and 4k + 2 sub-pixels in the column of sub-pixels
  • sub-pixels of the second sub-set include 4k + 3 and 4k + 4th sub-pixel (k is an integer greater than or equal to 0).
  • the sub-pixels of the first subset of the sub-pixels in the k + 1th column and the sub-pixels of the second subset of the sub-pixels in the k + 2 column share the same data line.
  • the first subpixel in the 4m + 1 row and the 4n + 1 column, the third subpixel in the 4m + 2 row and the 4n + 1 column, the 4m + 3 row, and the 4n + 2 column are connected to the 4n + 1th data line (m and n are integers greater than or equal to 0).
  • the third sub-pixel in rows 4m + 1 and 4n + 3, the first sub-pixel in rows 4m + 2 and 4n + 3, the third sub-pixel in rows 4m + 3 and 4n + 4 Four sub-pixels, and the second sub-pixel in the 4m + 4th row and the 4n + 4th column are connected to the 4n + 3th data line.
  • the fourth subpixel in rows 4m + 1 and 4n + 4, the second subpixel in rows 4m + 2 and 4n + 4, the fourth subpixel in rows 4m + 3 and 4n + 5 One sub-pixel, and the third sub-pixel in the 4m + 4th row and the 4n + 5th column are connected to the 4n + 4th data line.
  • each sub-pixel shown in FIG. 2 is not intended to represent a complete sub-pixel structure, but may be considered as, for example, each pixel electrode.
  • each sub-pixel is shown as being directly connected to a corresponding one of the data lines, this is only schematic, because in reality each sub-pixel should be connected to a corresponding data line via a corresponding pixel transistor.
  • the sub-pixels of the second subset in the leftmost column of sub-pixels are shown as not connected to any data line, but the sub-pixels of this second subset are actually connected to an additional data line (not Shows).
  • connection between the sub-pixels and the data lines shown in FIG. 2 may be referred to as a so-called 2H Zigzag connection, where each data line is alternately connected to two adjacent columns of sub-pixels at intervals of two horizontal periods.
  • this allows a column of sub-pixels to have data voltage polarities that alternately change at intervals of two horizontal periods, thereby alleviating or eliminating display failure caused by the polar pattern of FIG. 1.
  • FIG. 3 illustrates an example polar pattern for the pixel arrangement structure 200 of FIG. 2.
  • corresponding data voltages are applied to the data lines DL1 to DL8 in one frame period so that any two pixel repeating units 210 adjacent in the row direction D1 have opposite data voltage polarity patterns.
  • the sub-pixels in the 4i + 1th row and the 8j + 1 to 8j + 4th columns (i and j are integers greater than or equal to 0, i ⁇ m, j ⁇ n / 2) have the following polarities, respectively Data voltage: first polarity, second polarity, second polarity, and first polarity.
  • the sub-pixels in the 4i + 2 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities, respectively: first polarity, second polarity, second polarity, and first polarity.
  • the sub-pixels in the 4i + 3 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities: the second polarity, the first polarity, the second polarity, and the second polarity, respectively.
  • the sub-pixels in the 4i + 4th row and the 8j + 1th to 8j + 4th columns have data voltages of the following polarities: the second polarity, the first polarity, the second polarity, and the second polarity, respectively.
  • the example polarity pattern shown in FIG. 3 can be implemented by applying data voltages of the following polarities to the data lines DL1 to DL8, respectively: positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and Negative polarity. It will be understood that in the so-called frame inversion mode, the positive polarity is switched to the negative polarity in the next frame period, and vice versa. In this example, the data voltage polarity of each column of sub-pixels (except the third and seventh columns) is alternately changed at intervals of two horizontal periods.
  • the polarity of the data voltages of every two sub-pixels adjacent in the row direction D1 is also opposite to each other as much as possible. This promotes the cancellation of the coupling voltage on the common electrode caused by the data voltage on different sub-pixels, thereby alleviating or eliminating display failure.
  • the first sub-pixel 201 as the red sub-pixel and the third sub-pixel 203 as the blue sub-pixel may be disposed in the third column (more generally, the 8j + 3 column) of the sub-pixels and In the seventh column (more generally, column 8j + 7), the human eye is less sensitive to red and blue than green and white. In this way, even if the columns of sub-pixels have data voltage polarities that do not change alternately, no perceptible display defects will be brought about.
  • FIG. 4 illustrates another example polar pattern for the pixel arrangement structure 200 of FIG. 2.
  • the illustrated polar pattern (which is different from the polar pattern of FIG. 3) is achieved by applying data voltages of the following polarities to the data lines DL1 to DL8, respectively: positive polarity, positive polarity, negative polarity, positive polarity Polarity, negative polarity, negative polarity, positive polarity, and negative polarity. It will be understood that in the so-called frame inversion mode, the positive polarity is switched to the negative polarity in the next frame period, and vice versa.
  • the sub-pixels in rows 4i + 1 and columns 8j + 1 to 8j + 4 have the following polarities, respectively Data voltage: first polarity, first polarity, second polarity, and first polarity.
  • the sub-pixels in the 4i + 2 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities, respectively: first polarity, first polarity, second polarity, and first polarity.
  • the sub-pixels in the 4i + 3 row and the 8j + 1 to 8j + 4 columns have data voltages of the following polarities: the second polarity, the first polarity, the first polarity, and the second polarity, respectively.
  • the sub-pixels in the 4i + 4th row and the 8j + 1th to 8j + 4th columns have data voltages of the following polarities: the second polarity, the first polarity, the first polarity, and the second polarity, respectively.
  • the data voltage polarity of each column of subpixels (except the second and sixth columns of subpixels) alternates at intervals of two horizontal periods.
  • the polarity of the data voltages of every two sub-pixels adjacent in the row direction D1 is also opposite to each other as much as possible. This promotes the cancellation of the coupling voltage on the common electrode caused by the data voltage on different sub-pixels, thereby alleviating or eliminating display failure.
  • the first sub-pixel 201 as the red sub-pixel and the third sub-pixel 203 as the blue sub-pixel may be provided in the second column (more generally, the 8j + 2 column) sub-pixel Neutralize the sixth column (more generally, 8j + 6th column) of the sub-pixels because the human eye is less sensitive to red and blue than green and white. In this way, even if the columns of sub-pixels have data voltage polarities that do not change alternately, no perceptible display defects will be brought about.
  • FIG. 5 is a schematic plan view of a display panel 500 according to an embodiment of the present disclosure.
  • the display panel 500 includes the pixel arrangement structure 200 as described above with respect to FIG. 2, and details thereof will not be repeated here.
  • the display panel 500 further includes a plurality of data lines DL extending in the column direction D2.
  • data lines DL extending in the column direction D2.
  • other known elements in the display panel 500 are not shown, such as a gate line extending in the row direction D1, a pixel transistor located at the intersection of the gate line and the data line, and an associated sub-pixel.
  • Various storage capacitors are not shown, such as a gate line extending in the row direction D1, a pixel transistor located at the intersection of the gate line and the data line, and an associated sub-pixel.
  • the display panel 500 also includes a plurality of data selectors, which are collectively indicated by the reference numeral 510. These data selectors 510 are located at the same end of the plurality of data lines DL and are configured to transmit data voltages to corresponding ones of the plurality of data lines DL.
  • Data selectors are known per se in the art and typically include a data input, a plurality of data outputs, and a plurality of switches that couple the data input to a corresponding data output of the plurality of data outputs.
  • the data selector may be controlled such that a plurality of switches are sequentially turned on to transmit the multiplexed data received at the data input terminal to the corresponding data output terminal. In this way, the number of source driver chips that supply data voltage to the display panel 500 can be reduced, which may be advantageous in some applications, for example, to reduce the occupied area of the frame of the display panel, or to reduce costs.
  • the connections between the plurality of data selectors 510 and the plurality of data lines DL are repeated at intervals of 24 data lines.
  • the 8k + 1th of the multiple three-to-one data selectors 510 (k is an integer greater than or equal to 0, k ⁇ (n-5) / 6)
  • the data output terminals SW1, SW2, and SW3 are respectively connected to the 24k + 1th, 24k + 4, and 24k + 6 data lines of the plurality of data lines DL.
  • the three data output terminals SW1, SW2 and SW3 of the 8k + 2 three-to-one data selector in the plurality of three-to-one data selectors 510 are respectively connected to the 24k + in the plurality of data lines DL 2, 24k + 3 and 24k + 5 data lines.
  • the three data output terminals SW1, SW2, and SW3 of the 8k + 3 three-to-one data selector in the plurality of three-to-one data selectors 510 are respectively connected to the 24k + th in the plurality of data lines DL 7, 24k + 9 and 24k + 12 data lines.
  • the three data output terminals SW1, SW2 and SW3 of the 8k + 4 three-to-one data selectors in the plurality of three-to-one data selectors 510 are respectively connected to the 24k + th in the plurality of data lines DL 8, 24k + 10 and 24k + 11 data lines.
  • the three data output terminals SW1, SW2, and SW3 of the 8k + 5th three-to-one data selector in the plurality of three-to-one data selectors 510 are respectively connected to the 24k + th in the plurality of data lines DL 13, 24k + 16 and 24k + 18 data lines.
  • the three data output terminals SW1, SW2 and SW3 of the 8k + 6 three-select one-data selectors in the plurality of three-select one-data selectors 510 are respectively connected to the 24k + one of the plurality of data lines DL 14, 24k + 15 and 24k + 17 data lines.
  • the three data output terminals SW1, SW2 and SW3 of the 8k + 7 three-to-one data selectors in the plurality of three-to-one data selectors 510 are respectively connected to the 24k + th in the plurality of data lines DL 19, 24k + 21 and 24k + 24 data lines.
  • the three data output terminals SW1, SW2, and SW3 of the 8k + 8 three-to-one data selectors in the plurality of three-to-one data selectors 510 are respectively connected to the 24k + th in the plurality of data lines DL 20, 24k + 22 and 24k + 23 data lines.
  • the data of the 8k + 1th, 8k + 3, 8k + 6, and 8k + 8 three-to-one data selectors in the plurality of three-to-one data selectors 510 The input terminal is configured to receive a data voltage of a first polarity (for example, a positive polarity) in one frame period, and the 8k + 2, 8k + 4 of the plurality of three-to-one data selectors 510
  • the data input terminals of the 8k + 5th and 8k + 7th three-out-one data selectors are configured to receive a data voltage of a second polarity (eg, negative polarity) during the frame period.
  • the second polarity is opposite to the first polarity. This can produce a data voltage polarity pattern as shown in FIG. 3.
  • FIG. 6 is a schematic plan view of a display panel 600 according to another embodiment of the present disclosure.
  • the display panel 600 includes the pixel arrangement structure 200 as described above with respect to FIG. 2, and details thereof will not be repeated here.
  • the display panel 600 further includes a plurality of data lines DL extending in the column direction D2. Similar to FIG. 5, for the convenience of illustration, other known elements in the display panel 600 are not shown, such as a gate line extending in the row direction D1, a pixel transistor located at the intersection of the gate line and the data line, and each other Each storage capacitor associated with a sub-pixel.
  • the display panel 600 further includes a plurality of data selectors, which are collectively indicated by the reference numeral 610.
  • the connections between the plurality of data selectors 610 and the plurality of data lines DL are repeated at intervals of eight data lines.
  • the 2k + 1th of the plurality of four-to-one data selectors 610 (k is an integer greater than or equal to 0, k ⁇ (n-1) / 2) four of the four-to-one data selectors
  • the data output terminals SW1, SW2, SW3, and SW4 are respectively connected to the 8k + 1th, 8k + 4, 8k + 6, and 8k + 7 data lines of the plurality of data lines DL, and all
  • the four data output terminals SW1, SW2, SW3, and SW4 of the 2k + 2 four-to-one data selector in the plurality of four-to-one data selectors 610 are respectively connected to the 8kth in the plurality of data lines DL. +2, 8k + 3, 8k + 5, and 8k + 8 data lines.
  • a data input terminal of a 2k + 1th one-out four-out data selector in the plurality of out-of-one data selectors 610 is configured to receive a first polarity (for example, (Positive polarity) data voltage
  • the data input terminal of the 2k + 2 four-to-one data selector in the plurality of four-to-one data selectors 610 is configured to receive the second polarity in the frame period (Eg, negative polarity) data voltage.
  • the second polarity is opposite to the first polarity. This can produce a data voltage polarity pattern as shown in FIG. 3.
  • FIG. 7 is a schematic block diagram of a display device 700 according to an embodiment of the present disclosure.
  • the display device 700 includes a display panel 710, a timing controller 720, a gate driver 730, a data driver 740, and a data selection circuit DSEL.
  • the display panel 710 is connected to a plurality of gate lines GL and a plurality of data lines DL.
  • the gate line GL extends in the row direction D1
  • the data line DL extends in the column direction D2 crossing (for example, substantially perpendicular) to the row direction D1.
  • the display panel 710 includes a plurality of sub-pixels SP arranged in a matrix form. Each of the sub-pixels SP is electrically connected to a corresponding one of the gate lines GL and a corresponding one of the data lines DL.
  • Each sub-pixel SP includes a pixel transistor tft (for example, a thin film transistor), a liquid crystal capacitor C LC, and a storage capacitor Cst.
  • the liquid crystal capacitor C LC and the storage capacitor Cst are electrically connected to the pixel transistor tft.
  • the liquid crystal capacitor C LC includes a first electrode connected to a pixel electrode and a second electrode connected to a common electrode.
  • the data voltage from the data line DL is applied to the first electrode of the liquid crystal capacitor C LC via the pixel transistor tft.
  • a common voltage is applied to the second electrode of the liquid crystal capacitor C LC .
  • the storage capacitor Cst includes a first electrode connected to the pixel electrode and a second electrode connected to the storage electrode.
  • the data voltage is applied to the first electrode of the storage capacitor Cst via the pixel transistor tft.
  • a storage voltage is applied to the second electrode of the storage capacitor Cst.
  • the storage voltage may be substantially equal to the common voltage.
  • the display panel 710 embodies the display panel 500 or 600 described above with reference to FIGS. 5 and 6.
  • Each pixel SP has a substantially rectangular shape.
  • each pixel SP has a relatively short side in the row direction D1 and a relatively long side in the column direction D2.
  • the relatively short side of each pixel SP is substantially parallel to the gate line GL.
  • the relatively long side of each pixel SP is substantially parallel to the data line DL.
  • the display panel 710 further includes a data selection circuit DSEL, which embodies the plurality of data selectors 510 or 610 described above with reference to FIGS. 5 and 6, and the details thereof will not be repeated here.
  • the timing controller 720 controls operations of the display panel 710, the gate driver 730, the data driver 740, and the data selection circuit DSEL.
  • the timing controller 720 receives input image data RGBD and an input control signal CONT from a system interface.
  • the input image data RGBD includes a plurality of input pixel data for a plurality of sub-pixels SP.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.
  • the timing controller 720 generates output image data RGBD ', a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 based on the input image data RGBD and the input control signal CONT.
  • the timing controller 720 may generate output image data RGBD 'based on the input image data RGBD.
  • the output image data RGBD ' may be image data generated by converting the original format of the input image data RGBD to fit the pixel arrangement structure of the display panel 710.
  • the output image data RGBD ' may include a plurality of output pixel data for a plurality of sub-pixels SP.
  • the timing controller 720 generates a first control signal CONT1 based on the input control signal CONT.
  • the first control signal CONT1 may include a vertical start signal, a gate clock signal, and the like.
  • the timing controller 720 generates a second control signal CONT2 based on the input control signal CONT.
  • the second control signal CONT2 may include a horizontal start signal, a data clock signal, a data load signal, a polarity control signal, and the like.
  • the timing controller 720 generates a third control signal CONT3 based on the input control signal CONT, which is supplied to the data selection circuit DSEL to control a plurality of switches in the data selection circuit DSEL to operate in synchronization with the gate driver 730 and the data driver 740.
  • the gate driver 730 receives a first control signal CONT1 from the timing controller 720, and generates a plurality of gate signals for driving the gate line GL based on the first control signal CONT1.
  • the gate driver 730 sequentially applies a plurality of gate signals to the gate lines GL.
  • the gate driver 730 is integrated in the display panel 710 as an array substrate row driving (GOA) circuit.
  • the gate driver 730 is connected to the display panel 710 through a tape carrier package (TCP).
  • the data driver 740 receives the second control signal CONT2 and the output image data RGBD 'from the timing controller 720, and generates a plurality of data voltages based on the second control signal CONT2 and the output image data RGBD'.
  • the data driver 740 operates in synchronization with the gate driver 730 to apply a plurality of data voltages to the data line DL.
  • the data driver 740 includes a shift register, a latch, a digital-to-analog converter, and a buffer.
  • the shift register outputs a latch pulse to the latch.
  • the latch temporarily stores the output image data RGBD 'and outputs the output image data RGBD' to a digital-to-analog converter.
  • the digital-to-analog converter generates an analog data voltage based on the output image data RGBD ', and outputs the analog data voltage to a buffer.
  • the buffer outputs the analog data voltage to the data line DL.
  • each data line DL carries the corresponding Multiple (three or four) data voltages.
  • the data selection circuit DSEL transmits a plurality of multiplexed data voltages to corresponding sub-pixels in the plurality of sub-pixels SP in each horizontal scanning period.
  • the display device 700 may be any product or component having a display function, and examples thereof include, but are not limited to, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device 700 provides the same advantages as the pixel arrangement structure embodiment described above, which will not be repeated here.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素排布结构（100），包括在行方向和列方向上呈矩阵排列的多个像素重复单元（210）。多个像素重复单元（210）中的每一个包括在列方向上依次排列的第一像素单元（211）和第二像素单元（212）。第一像素单元（211）包括在行方向上依次排列的第一子像素（201）、第二子像素（202）、第三子像素（203）和第四子像素（204）。第二像素单元（212）包括在行方向上依次排列的第三子像素（203）、第四子像素（204）、第一子像素（201）和第二子像素（202）。每列子像素被划分成连接到第一数据线的第一子集的子像素和连接到第二数据线的第二子集的子像素。

Description

像素排布结构、其驱动方法、显示面板及显示装置
相关申请的交叉引用
本申请要求2018年5月22日提交的中国专利申请No.201810494618.6的优先权，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素排布结构、驱动该像素排布结构的方法、显示面板及显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于移动产品如手机，平板电脑中。为了满足高亮度的需求，已经提出了各种各样的像素排布结构，其中一种是所谓的RGBW(红绿蓝白)。在这种像素排布结构中，当白色子像素被点亮时，显示器的亮度可显著提高。
发明内容
根据本公开的一些实施例，提供了一种像素排布结构，包括：多个像素重复单元，在行方向和列方向上呈矩阵排列，所述多个像素重复单元中的每一个包括在列方向上依次排列的第一像素单元和第二像素单元，所述第一像素单元包括在行方向上依次排列的第一子像素、第二子像素、第三子像素和第四子像素，所述第二像素单元包括在行方向上依次排列的第三子像素、第四子像素、第一子像素和第二子像素；以及多条数据线，沿列方向延伸。第4m+1行和第4n+1列中的第一子像素、第4m+2行和第4n+1列中的第三子像素、第4m+3行和第4n+2列中的第二子像素、以及第4m+4行和第4n+2列中的第四子像素连接到所述多条数据线中的第4n+1条数据线。第4m+1行和第4n+2列中的第二子像素、第4m+2行和第4n+2列中的第四子像素、第4m+3行和第4n+3列中的第三子像素、以及第4m+4行和第4n+3列中的第一子像素连接到所述多条数据线中的第4n+2条数据线。第4m+1行和第4n+3列中的第三子像素、第4m+2行和第4n+3列中的第一子像素、第4m+3行和第4n+4列中的第四子像素、以及第4m+4行和第4n+4列 中的第二子像素连接到所述多条数据线中的第4n+3条数据线。第4m+1行和第4n+4列中的第四子像素、第4m+2行和第4n+4列中的第二子像素、第4m+3行和第4n+5列中的第一子像素、以及第4m+4行和第4n+5列中的第三子像素连接到所述多条数据线中的第4n+4条数据线。m和n为大于或等于0的整数。
在一些实施例中，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素选自红色子像素、绿色子像素、蓝色子像素和白色子像素中各自不同的子像素。
根据本公开的一些实施例，提供了一种驱动如上所述的像素排布结构的方法。所述方法包括：在一帧周期中向所述数据线施加相应的数据电压，以使得在行方向上相邻的任意两个像素重复单元具有彼此相反的数据电压极性图案。
在一些实施例中，第4i+1行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第二极性、第二极性和第一极性。第4i+2行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第二极性、第二极性和第一极性。第4i+3行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第二极性和第二极性。第4i+4行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第二极性和第二极性。i和j为大于或等于0的整数，i≤m，j≤n/2。
在一些实施例中，第4i+1行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第一极性、第二极性和第一极性。第4i+2行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第一极性、第二极性和第一极性。第4i+3行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第一极性和第二极性。第4i+4行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第一极性和第二极性。i和j为大于或等于0的整数，i≤m，j≤n/2。
在一些实施例中，所述第一极性和所述第二极性选择正极性和负极性中各自不同的极性。
根据本公开的一些实施例，提供了一种显示面板，包括如上所述的像素排布结构。
在一些实施例中，所述显示面板还包括多个数据选择器，其位于所述多条数据线的同一端并且被配置成向所述多条数据线中的相应数据线传送数据电压。
在一些实施例中，所述多个数据选择器包括多个三选一数据选择器，每一所述三选一数据选择器包括一个数据输入端和三个数据输出端。
在一些实施例中，所述多个三选一数据选择器中的第8k+1个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+1条、第24k+4条和第24k+6条数据线。所述多个三选一数据选择器中的第8k+2个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+2条、第24k+3条和第24k+5条数据线。所述多个三选一数据选择器中的第8k+3个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+7条、第24k+9条和第24k+12条数据线。所述多个三选一数据选择器中的第8k+4个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+8条、第24k+10条和第24k+11条数据线。所述多个三选一数据选择器中的第8k+5个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+13条、第24k+16条和第24k+18条数据线。所述多个三选一数据选择器中的第8k+6个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+14条、第24k+15条和第24k+17条数据线。所述多个三选一数据选择器中的第8k+7个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+19条、第24k+21条和第24k+24条数据线。所述多个三选一数据选择器中的第8k+8个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+20条、第24k+22条和第24k+23条数据线。k为大于或等于0的整数，k≤(n-5)/6。
在一些实施例中，所述多个三选一数据选择器中的第8k+1个、第8k+3个、第8k+6个和第8k+8个三选一数据选择器的数据输入端被配置成在一帧周期中接收第一极性的数据电压。所述多个三选一数据选择器中的第8k+2个、第8k+4个、第8k+5个和第8k+7个三选一数据选择器的数据输入端被配置成在所述帧周期中接收第二极性的数据电压。所述第二极性与所述第一极性相反。
在一些实施例中，所述多个数据选择器包括多个四选一数据选择器，每一所述四选一数据选择器包括一个数据输入端和四个数据输出端。
在一些实施例中，所述多个四选一数据选择器中的第2k+1个四选一数据选择器的四个数据输出端分别连接到所述多条数据线中的第8k+1条、第8k+4条、第8k+6条和第8k+7条数据线。所述多个四选一数据选择器中的第2k+2个四选一数据选择器的四个数据输出端分别连接到所述多条数据线中的第8k+2条、第8k+3条、第8k+5条和第8k+8条数据线。k为大于或等于0的整数，k≤(n-1)/2。
在一些实施例中，所述多个四选一数据选择器中的第2k+1个四选一数据选择器的数据输入端被配置成在一帧周期中接收第一极性的数据电压。所述多个四选一数据选择器中的第2k+2个四选一数据选择器的数据输入端被配置成在所述帧周期中接收第二极性的数据电压。所述第二极性与所述第一极性相反。
根据本公开的一些实施例，提供了一种显示装置，包括如上所述的显示面板。
附图说明
图1为相关技术中像素排布结构的示意性平面图；
图2为根据本公开实施例的像素排布结构的示意性平面图；
图3为用于图2的像素排布结构的示例极性图案；
图4为用于图2的像素排布结构的另一示例极性图案；
图5为根据本公开实施例的显示面板的示意性平面图；
图6为根据本公开另一实施例的显示面板的示意性平面图；并且
图7为根据本公开实施例的显示装置的示意性框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层 或部分而不偏离本公开的教导。
诸如“行”、“列”、“在...下面”、“在...之下”、“较下”、“在...下方”、“在...之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”和“在...下方”可以涵盖在...之上和在...之下的取向两者。诸如“在...之前”或“在...前”和“在...之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存 在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
图1示出了相关技术中的一种像素排布结构100。
参考图1，像素排布结构100包括排布在行和列中的多个子像素(更具体地，像素电极)，并且不同列子像素连接到各自不同的数据线DL。在一帧画面被显示时，同一列子像素经由相应的一条数据线DL被施加相同极性的数据电压。这可以在公共电极(未示出)上感应出单一极性的耦合电压，得到如图1所示的极性图案。作为结果，若公共电极的RC loading较大或者感应出的耦合电压具有较大量值，有可能产生诸如竖线之类的显示不良(“mura”)。
图2为根据本公开实施例的像素排布结构200的示意性平面图。
参考图2，像素排布结构200包括在行方向D1和列方向D2上呈矩阵排列的多个像素重复单元210，每个像素重复单元210包括沿列方向D2排列的第一像素单元211和第二像素单元212。
第一像素单元211包括沿行方向D1依次排列的第一子像素201、第二子像素202、第三子像素203和第四子像素204。第二像素单元212包括沿行方向D1依次排列的第三子像素203、第四子像素204、第一子像素201和第二子像素202。
第一、第二、第三和第四子像素201、202、203和204选自红色子像素、绿色子像素、蓝色子像素和白色子像素中各自不同的子像素。 例如，第一、第二、第三和第四子像素201、202、203和204分别为红色子像素(R)、绿色子像素(G)、蓝色子像素(B)和白色子像素(W)。
与图1的像素排布结构100不同，像素排布结构200中的每列子像素被划分成连接到第一数据线的第一子集的子像素和连接到第二数据线的第二子集的子像素，其中第一子集的子像素包括该列子像素中的第4k+1个和4k+2个子像素，并且第二子集的子像素包括该列子像素中的第4k+3个和第4k+4个子像素(k为大于或等于0的整数)。而且，第k+1列子像素中的第一子集的子像素与第k+2列子像素中的第二子集的子像素共用相同的数据线。
具体地，第4m+1行和第4n+1列中的第一子像素、第4m+2行和第4n+1列中的第三子像素、第4m+3行和第4n+2列中的第二子像素、以及第4m+4行和第4n+2列中的第四子像素连接到第4n+1条数据线(m和n为大于或等于0的整数)。第4m+1行和第4n+2列中的第二子像素、第4m+2行和第4n+2列中的第四子像素、第4m+3行和第4n+3列中的第三子像素、以及第4m+4行和第4n+3列中的第一子像素连接到第4n+2条数据线。第4m+1行和第4n+3列中的第三子像素、第4m+2行和第4n+3列中的第一子像素、第4m+3行和第4n+4列中的第四子像素、以及第4m+4行和第4n+4列中的第二子像素连接到第4n+3条数据线。第4m+1行和第4n+4列中的第四子像素、第4m+2行和第4n+4列中的第二子像素、第4m+3行和第4n+5列中的第一子像素、以及第4m+4行和第4n+5列中的第三子像素连接到第4n+4条数据线。
将理解的是，图2中仅示意性地示出了像素排布结构200的局部区域，并且为了图示的方便，未示出其他已知的元件，诸如沿行方向D1延伸的栅线、位于栅线与数据线交叉处的像素晶体管、以及与相应子像素相关联的存储电容器。因此，图2中示出的各个子像素并不意图代表完整的子像素结构，而是可以被认为是例如各个像素电极。虽然每个子像素被示出为直接连接到对应的一条数据线，但是这只是示意性的，因为实际上每个子像素应当经由一个相应的像素晶体管连接到一条对应的数据线。另外，最左边的一列子像素中的第二子集的子像素被示出为未被连接到任何数据线，但是该第二子集的子像素实际上被连接到一条附加的数据线(未示出)。
图2中所示的子像素与数据线之间的连接可以被称为所谓2H Zigzag连接，其中每条数据线以两个水平周期为间隔，交错地连接到各自的相邻两列子像素。如后面将进一步描述的，这允许一列子像素具有以两个水平周期为间隔而交替变化的数据电压极性，从而缓解或消除图1的极性图案所导致的显示不良。
图3示出了用于图2的像素排布结构200的示例极性图案。
参考图3，在一帧周期中向数据线DL1至DL8施加相应的数据电压，以使得在行方向D1上相邻的任意两个像素重复单元210具有彼此相反的数据电压极性图案。
具体地，第4i+1行和第8j+1至第8j+4列(i和j为大于或等于0的整数，i≤m，j≤n/2)中的子像素分别具有以下极性的数据电压：第一极性、第二极性、第二极性和第一极性。第4i+2行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第二极性、第二极性和第一极性。第4i+3行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第二极性和第二极性。第4i+4行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第二极性和第二极性。
图3中所示的示例极性图案可以通过向数据线DL1至DL8分别施加以下极性的数据电压来实现：正极性、负极性、负极性、正极性、负极性、正极性、正极性和负极性。将理解的是，在所谓帧反转(frame inversion)的模式中，正极性在下一帧周期中被切换成负极性，并且反之亦然。在该示例中，每列子像素(除了第三列和第七列子像素之外)的数据电压极性以两个水平周期为间隔而交替变化。并且，在行方向D1上相邻的每两个子像素的数据电压极性也尽可能地彼此相反。这促进了由不同子像素上的数据电压所引起的公共电极上的耦合电压的抵消，从而缓解或消除显示不良。
在一些实施例中，可以将作为红色子像素的第一子像素201和作为蓝色子像素的第三子像素203设置于第三列(更一般地，第8j+3列)子像素中和第七列(更一般地，第8j+7列)子像素中，因为比起绿色和白色，人眼对于红色和蓝色更不敏感。这样，即使这些列子像素具有不交替变化的数据电压极性，也不会带来可察觉的显示不良。
图4示出了用于图2的像素排布结构200的另一示例极性图案。
参考图4，所示出的极性图案(其不同于图3的极性图案)通过向数据线DL1至DL8分别施加以下极性的数据电压来实现：正极性、正极性、负极性、正极性、负极性、负极性、正极性和负极性。将理解的是，在所谓帧反转(frame inversion)的模式中，正极性在下一帧周期中被切换成负极性，并且反之亦然。
更一般地，第4i+1行和第8j+1至第8j+4列(i和j为大于或等于0的整数，i≤m，j≤n/2)中的子像素分别具有以下极性的数据电压：第一极性、第一极性、第二极性和第一极性。第4i+2行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第一极性、第二极性和第一极性。第4i+3行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第一极性和第二极性。第4i+4行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第一极性和第二极性。
在图4的示例中，每列子像素(除了第二列和第六列子像素之外)的数据电压极性以两个水平周期为间隔而交替变化。并且，在行方向D1上相邻的每两个子像素的数据电压极性也尽可能地彼此相反。这促进了由不同子像素上的数据电压所引起的公共电极上的耦合电压的抵消，从而缓解或消除显示不良。
在可替换的实施例中，可以将作为红色子像素的第一子像素201和作为蓝色子像素的第三子像素203设置于第二列(更一般地，第8j+2列)子像素中和第六列(更一般地，第8j+6列)子像素中，因为比起绿色和白色，人眼对于红色和蓝色更不敏感。这样，即使这些列子像素具有不交替变化的数据电压极性，也不会带来可察觉的显示不良。
图5为根据本公开实施例的显示面板500的示意性平面图。
参考图5，显示面板500包括如上面关于图2描述的像素排布结构200，其细节在此不再重复。显示面板500还包括沿列方向D2延伸的多条数据线DL。为了图示的方便，未示出显示面板500中的其他已知的元件，诸如沿行方向D1延伸的栅线、位于栅线与数据线交叉处的像素晶体管、以及与各个子像素相关联的各个存储电容器。
显示面板500还包括多个数据选择器，它们集体地由参考标记510指示。这些数据选择器510位于所述多条数据线DL的同一端并且被配置成向所述多条数据线DL中的相应数据线传送数据电压。数据选择器 本身是本领域已知的，其典型地包括一个数据输入端、多个数据输出端以及将数据输入端耦合至多个数据输出端中的相应数据输出端的多个开关。数据选择器可被控制以使得多个开关被依次接通以将在数据输入端接收的被多路复用的数据传送至相应的数据输出端。这样，可以减少向显示面板500供应数据电压的源极驱动器芯片的数目，这在一些应用中可以是有利的，例如以减小显示面板的边框的占用面积，或者以降低成本。
在该实施例中，所述多个数据选择器510包括多个三选一数据选择器，每一所述三选一数据选择器包括一个数据输入端Sx(在图5的示例中，x＝1、2、3、4、5、6、7或8)、三个数据输出端、以及将数据输入端耦合至三个数据输出端中的相应数据输出端的三个开关SW1、SW2和SW3。
在该实施例中，所述多个数据选择器510与所述多条数据线DL之间的连接以24条数据线为间隔被重复。具体地，所述多个三选一数据选择器510中的第8k+1个(k为大于或等于0的整数，k≤(n-5)/6)三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+1条、第24k+4条和第24k+6条数据线。所述多个三选一数据选择器510中的第8k+2个三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+2条、第24k+3条和第24k+5条数据线。所述多个三选一数据选择器510中的第8k+3个三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+7条、第24k+9条和第24k+12条数据线。所述多个三选一数据选择器510中的第8k+4个三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+8条、第24k+10条和第24k+11条数据线。所述多个三选一数据选择器510中的第8k+5个三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+13条、第24k+16条和第24k+18条数据线。所述多个三选一数据选择器510中的第8k+6个三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+14条、第24k+15条和第24k+17条数据线。所述多个三选一数据选择器510中的第8k+7个三选一数据选择器的三个数据输出端SW1、 SW2和SW3分别连接到所述多条数据线DL中的第24k+19条、第24k+21条和第24k+24条数据线。所述多个三选一数据选择器510中的第8k+8个三选一数据选择器的三个数据输出端SW1、SW2和SW3分别连接到所述多条数据线DL中的第24k+20条、第24k+22条和第24k+23条数据线。
在该实施例中，所述多个三选一数据选择器510中的第8k+1个、第8k+3个、第8k+6个和第8k+8个三选一数据选择器的数据输入端被配置成在一帧周期中接收第一极性(例如，正极性)的数据电压，并且所述多个三选一数据选择器510中的第8k+2个、第8k+4个、第8k+5个和第8k+7个三选一数据选择器的数据输入端被配置成在所述帧周期中接收第二极性(例如，负极性)的数据电压。所述第二极性与所述第一极性相反。这可以产生如图3所示的数据电压极性图案。
图6为根据本公开另一实施例的显示面板600的示意性平面图。
参考图6，显示面板600包括如上面关于图2描述的像素排布结构200，其细节在此不再重复。显示面板600还包括沿列方向D2延伸的多条数据线DL。与图5类似，为了图示的方便，未示出显示面板600中的其他已知的元件，诸如沿行方向D1延伸的栅线、位于栅线与数据线交叉处的像素晶体管、以及与各个子像素相关联的各个存储电容器。
在该实施例中，显示面板600还包括多个数据选择器，它们集体地由参考标记610指示。
在该实施例中，所述多个数据选择器610包括多个四选一数据选择器，每一所述四选一数据选择器包括一个数据输入端Sx(在图6的示例中，x＝1或2)、四个数据输出端、以及将数据输入端耦合至四个数据输出端中的相应数据输出端的四个开关SW1、SW2、SW3和SW4。
在该实施例中，所述多个数据选择器610与所述多条数据线DL之间的连接以8条数据线为间隔被重复。具体地，所述多个四选一数据选择器610中的第2k+1个(k为大于或等于0的整数，k≤(n-1)/2)四选一数据选择器的四个数据输出端SW1、SW2、SW3和SW4分别连接到所述多条数据线DL中的第8k+1条、第8k+4条、第8k+6条和第8k+7条数据线，并且所述多个四选一数据选择器610中的第2k+2个四选一数据选择器的四个数据输出端SW1、SW2、SW3和SW4分别连接到所述多条数据线DL中的第8k+2条、第8k+3条、第8k+5条和第 8k+8条数据线。
在该实施例中，所述多个四选一数据选择器610中的第2k+1个四选一数据选择器的数据输入端被配置成在一帧周期中接收第一极性(例如，正极性)的数据电压，并且所述多个四选一数据选择器610中的第2k+2个四选一数据选择器的数据输入端被配置成在所述帧周期中接收第二极性(例如，负极性)的数据电压。所述第二极性与所述第一极性相反。这可以产生如图3所示的数据电压极性图案。
图7为根据本公开实施例的显示装置700的示意性框图。
参考图7，显示装置700包括显示面板710、时序控制器720、栅极驱动器730、数据驱动器740和数据选择电路DSEL。
显示面板710连接至多条栅线GL和多条数据线DL。栅线GL在行方向D1上延伸，并且数据线DL在与行方向D1交叉(例如，基本垂直)的列方向D2上延伸。
显示面板710包括以矩阵形式排列的多个子像素SP。子像素SP中的每一个电连接至栅线GL中的对应一条栅线和数据线DL中的对应一条数据线。每个子像素SP包括像素晶体管tft(例如，薄膜晶体管)、液晶电容器C LC和存储电容器Cst。液晶电容器C LC和存储电容器Cst电连接至像素晶体管tft。液晶电容器C LC包括连接至像素电极的第一电极和连接至公共电极的第二电极。来自数据线DL的数据电压经由像素晶体管tft被施加至液晶电容器C LC的第一电极。公共电压被施加至液晶电容器C LC的第二电极。存储电容器Cst包括连接至像素电极的第一电极和连接至存储电极的第二电极。数据电压经由像素晶体管tft被施加至存储电容器Cst的第一电极。存储电压被施加至存储电容器Cst的第二电极。存储电压可基本等于公共电压。
显示面板710体现上面关于图5和6描述的显示面板500或600。每个像素SP具有基本上矩形的形状。例如，每个像素SP在行方向D1具有相对短的边，而在列方向D2具有相对长的边。每个像素SP的相对短的边基本平行于栅线GL。每个像素SP的相对长的边基本平行于数据线DL。显示面板710还包括数据选择电路DSEL，其体现上面关于图5和6描述的多个数据选择器510或610，并且其详细在此不再重复。
时序控制器720控制显示面板710、栅极驱动器730、数据驱动器 740和数据选择电路DSEL的操作。时序控制器720从系统接口接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD包括用于多个子像素SP的多个输入像素数据。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器720基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1、第二控制信号CONT2和第三控制信号CONT3。例如，时序控制器720可基于输入图像数据RGBD生成输出图像数据RGBD’。在一些实施例中，输出图像数据RGBD’可以是通过转换输入图像数据RGBD的原始格式而生成的图像数据以适配显示面板710的像素排布结构。输出图像数据RGBD’可包括用于多个子像素SP的多个输出像素数据。时序控制器720基于输入控制信号CONT生成第一控制信号CONT1，所述第一控制信号CONT1可包括垂直启动信号、栅极时钟信号等。时序控制器720基于输入控制信号CONT生成第二控制信号CONT2，所述第二控制信号CONT2可包括水平启动信号、数据时钟信号、数据负载信号、极性控制信号等。时序控制器720基于输入控制信号CONT生成第三控制信号CONT3，其被供应给数据选择电路DSEL以控制数据选择电路DSEL中的多个开关与栅极驱动器730和数据驱动器740相同步地操作。
栅极驱动器730从时序控制器720接收第一控制信号CONT1，并且基于第一控制信号CONT1生成用于驱动栅线GL的多个栅极信号。栅极驱动器730顺序地将多个栅极信号施加至栅线GL。在一些示例性实施例中，栅极驱动器730被作为阵列基板行驱动(GOA)电路集成在显示面板710中。替换地，栅极驱动器730通过带式载体封装(Tape Carrier Package，TCP)连接至显示面板710。
数据驱动器740从时序控制器720接收第二控制信号CONT2和输出图像数据RGBD’，并且基于第二控制信号CONT2和输出图像数据RGBD’生成多个数据电压。数据驱动器740与栅极驱动器730相同步地操作以将多个数据电压施加至数据线DL。在一些示例性实施例中，数据驱动器740包括移位寄存器、锁存器、数模转换器和缓冲器。移位寄存器向锁存器输出锁存脉冲。锁存器暂时存储输出图像数据RGBD’，并且将输出图像数据RGBD’输出至数模转换器。数模转换器基于输出图像数据RGBD’生成模拟数据电压，并且将模拟数据电压输 出至缓冲器。缓冲器将模拟数据电压输出至数据线DL。
取决于数据选择电路DSEL的实现(例如，一组三选一数据选择器或四选一数据选择器)，在每个水平扫描周期中，各条数据线DL上承载被多路复用的相应多个(三个或四个)数据电压。响应于第三控制信号CONT3，数据选择电路DSEL在每个水平扫描周期中将被多路复用的多个数据电压传送至多个子像素SP中的对应子像素。
该显示装置700可以是任何具有显示功能的产品或部件，其示例包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等。该显示装置700提供了如上面关于像素排布结构实施例相同的优点，其在此不再赘述。
本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的范围。倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种像素排布结构，包括：
    多个像素重复单元，在行方向和列方向上呈矩阵排列，所述多个像素重复单元中的每一个包括在列方向上依次排列的第一像素单元和第二像素单元，所述第一像素单元包括在行方向上依次排列的第一子像素、第二子像素、第三子像素和第四子像素，所述第二像素单元包括在行方向上依次排列的第三子像素、第四子像素、第一子像素和第二子像素；以及
    多条数据线，沿列方向延伸，
    其中第4m+1行和第4n+1列中的第一子像素、第4m+2行和第4n+1列中的第三子像素、第4m+3行和第4n+2列中的第二子像素、以及第4m+4行和第4n+2列中的第四子像素连接到所述多条数据线中的第4n+1条数据线，
    其中第4m+1行和第4n+2列中的第二子像素、第4m+2行和第4n+2列中的第四子像素、第4m+3行和第4n+3列中的第三子像素、以及第4m+4行和第4n+3列中的第一子像素连接到所述多条数据线中的第4n+2条数据线，
    其中第4m+1行和第4n+3列中的第三子像素、第4m+2行和第4n+3列中的第一子像素、第4m+3行和第4n+4列中的第四子像素、以及第4m+4行和第4n+4列中的第二子像素连接到所述多条数据线中的第4n+3条数据线，
    其中第4m+1行和第4n+4列中的第四子像素、第4m+2行和第4n+4列中的第二子像素、第4m+3行和第4n+5列中的第一子像素、以及第4m+4行和第4n+5列中的第三子像素连接到所述多条数据线中的第4n+4条数据线，并且
    其中m和n为大于或等于0的整数。
  2. 如权利要求1所述的像素排布结构，其中所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素选自红色子像素、绿色子像素、蓝色子像素和白色子像素中各自不同的子像素。
  3. 一种驱动如权利要求1或2所述的像素排布结构的方法，包括：
    在一帧周期中向所述数据线施加相应的数据电压，以使得在行方 向上相邻的任意两个像素重复单元具有彼此相反的数据电压极性图案。
  4. 如权利要求3所述的方法，
    其中第4i+1行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第二极性、第二极性和第一极性，
    其中第4i+2行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第二极性、第二极性和第一极性，
    其中第4i+3行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第二极性和第二极性，
    其中第4i+4行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第二极性和第二极性，并且
    其中i和j为大于或等于0的整数，i≤m，j≤n/2。
  5. 如权利要求3所述的方法，
    其中第4i+1行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第一极性、第二极性和第一极性，
    其中第4i+2行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第一极性、第一极性、第二极性和第一极性，
    其中第4i+3行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第一极性和第二极性，
    其中第4i+4行和第8j+1至第8j+4列中的子像素分别具有以下极性的数据电压：第二极性、第一极性、第一极性和第二极性，并且
    其中i和j为大于或等于0的整数，i≤m，j≤n/2。
  6. 如权利要求4或5所述的方法，其中所述第一极性和所述第二极性选择正极性和负极性中各自不同的极性。
  7. 一种显示面板，包括如权利要求1或2所述的像素排布结构。
  8. 如权利要求7所述的显示面板，还包括多个数据选择器，位于所述多条数据线的同一端并且被配置成向所述多条数据线中的相应数据线传送数据电压。
  9. 如权利要求8所述的显示面板，其中所述多个数据选择器包括多个三选一数据选择器，每一所述三选一数据选择器包括一个数据输入端和三个数据输出端。
  10. 如权利要求9所述的显示面板，
    其中所述多个三选一数据选择器中的第8k+1个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+1条、第24k+4条和第24k+6条数据线，
    其中所述多个三选一数据选择器中的第8k+2个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+2条、第24k+3条和第24k+5条数据线，
    其中所述多个三选一数据选择器中的第8k+3个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+7条、第24k+9条和第24k+12条数据线，
    其中所述多个三选一数据选择器中的第8k+4个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+8条、第24k+10条和第24k+11条数据线，
    其中所述多个三选一数据选择器中的第8k+5个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+13条、第24k+16条和第24k+18条数据线，
    其中所述多个三选一数据选择器中的第8k+6个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+14条、第24k+15条和第24k+17条数据线，
    其中所述多个三选一数据选择器中的第8k+7个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+19条、第24k+21条和第24k+24条数据线，
    其中所述多个三选一数据选择器中的第8k+8个三选一数据选择器的三个数据输出端分别连接到所述多条数据线中的第24k+20条、第24k+22条和第24k+23条数据线，并且
    其中k为大于或等于0的整数，k≤(n-5)/6。
  11. 如权利要求10所述的显示面板，
    其中所述多个三选一数据选择器中的第8k+1个、第8k+3个、第8k+6个和第8k+8个三选一数据选择器的数据输入端被配置成在一帧周期中接收第一极性的数据电压，
    其中所述多个三选一数据选择器中的第8k+2个、第8k+4个、第8k+5个和第8k+7个三选一数据选择器的数据输入端被配置成在所述帧周期中接收第二极性的数据电压，并且
    其中所述第二极性与所述第一极性相反。
  12. 如权利要求8所述的显示面板，其中所述多个数据选择器包括多个四选一数据选择器，每一所述四选一数据选择器包括一个数据输入端和四个数据输出端。
  13. 如权利要求12所述的显示面板，
    其中所述多个四选一数据选择器中的第2k+1个四选一数据选择器的四个数据输出端分别连接到所述多条数据线中的第8k+1条、第8k+4条、第8k+6条和第8k+7条数据线，
    其中所述多个四选一数据选择器中的第2k+2个四选一数据选择器的四个数据输出端分别连接到所述多条数据线中的第8k+2条、第8k+3条、第8k+5条和第8k+8条数据线，并且
    其中k为大于或等于0的整数，k≤(n-1)/2。
  14. 如权利要求13所述的显示面板，
    其中所述多个四选一数据选择器中的第2k+1个四选一数据选择器的数据输入端被配置成在一帧周期中接收第一极性的数据电压，
    其中所述多个四选一数据选择器中的第2k+2个四选一数据选择器的数据输入端被配置成在所述帧周期中接收第二极性的数据电压，并且
    其中所述第二极性与所述第一极性相反。
  15. 一种显示装置，包括如权利要求7-14中任一项所述的显示面板。
PCT/CN2019/087671 2018-05-22 2019-05-21 像素排布结构、其驱动方法、显示面板及显示装置 WO2019223663A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/649,643 US10991327B2 (en) 2018-05-22 2019-05-21 Method of driving pixel arrangement structure and display panel and display apparatus associated therewith

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810494618.6 2018-05-22
CN201810494618.6A CN108761938B (zh) 2018-05-22 2018-05-22 像素排布结构、其驱动方法、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2019223663A1 true WO2019223663A1 (zh) 2019-11-28

Family

ID=64007860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/087671 WO2019223663A1 (zh) 2018-05-22 2019-05-21 像素排布结构、其驱动方法、显示面板及显示装置

Country Status (3)

Country Link
US (1) US10991327B2 (zh)
CN (1) CN108761938B (zh)
WO (1) WO2019223663A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108761938B (zh) 2018-05-22 2021-02-09 京东方科技集团股份有限公司 像素排布结构、其驱动方法、显示面板及显示装置
US11270658B2 (en) * 2019-06-28 2022-03-08 Ordos Yuansheng Optoelectronics Co., Ltd. Method of image display in display apparatus, data signal compensation apparatus for compensating data signals of display apparatus, and display apparatus
CN110441969A (zh) * 2019-08-20 2019-11-12 京东方科技集团股份有限公司 一种显示基板、其驱动方法及显示装置
CN110827740B (zh) * 2019-10-28 2021-03-23 Tcl华星光电技术有限公司 显示面板以及显示装置
CN111025710B (zh) * 2019-12-25 2021-10-15 华为技术有限公司 显示面板和显示装置
CN113571024B (zh) * 2021-07-28 2022-10-14 厦门天马微电子有限公司 一种显示面板、驱动方法以及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105139813A (zh) * 2014-06-02 2015-12-09 三星显示有限公司 显示设备及驱动该显示设备的方法
CN105182638A (zh) * 2015-08-28 2015-12-23 重庆京东方光电科技有限公司 阵列基板、显示装置及其驱动方法
CN105741799A (zh) * 2014-12-30 2016-07-06 三星显示有限公司 显示装置及其处理数据的方法
CN105892182A (zh) * 2016-06-07 2016-08-24 深圳市华星光电技术有限公司 像素结构及相应的液晶显示面板
US20180137829A1 (en) * 2015-06-22 2018-05-17 Samsung Display Co., Ltd. Liquid crystal display
CN108761938A (zh) * 2018-05-22 2018-11-06 京东方科技集团股份有限公司 像素排布结构、其驱动方法、显示面板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185326B (zh) * 2015-08-12 2017-10-17 深圳市华星光电技术有限公司 一种液晶显示面板及其驱动电路
US10490154B2 (en) * 2016-12-01 2019-11-26 Seiko Epson Corporation Electro-optical device and electronic device
US10504398B2 (en) * 2017-09-15 2019-12-10 Wuhan China Star Optoelectronics Technology Co., Ltd Driving method for display panel
CN107978287B (zh) * 2017-12-18 2019-07-12 惠科股份有限公司 显示面板的驱动方法及显示装置
CN108231031B (zh) * 2018-01-30 2020-06-05 厦门天马微电子有限公司 显示面板及其驱动方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105139813A (zh) * 2014-06-02 2015-12-09 三星显示有限公司 显示设备及驱动该显示设备的方法
CN105741799A (zh) * 2014-12-30 2016-07-06 三星显示有限公司 显示装置及其处理数据的方法
US20180137829A1 (en) * 2015-06-22 2018-05-17 Samsung Display Co., Ltd. Liquid crystal display
CN105182638A (zh) * 2015-08-28 2015-12-23 重庆京东方光电科技有限公司 阵列基板、显示装置及其驱动方法
CN105892182A (zh) * 2016-06-07 2016-08-24 深圳市华星光电技术有限公司 像素结构及相应的液晶显示面板
CN108761938A (zh) * 2018-05-22 2018-11-06 京东方科技集团股份有限公司 像素排布结构、其驱动方法、显示面板及显示装置

Also Published As

Publication number Publication date
CN108761938B (zh) 2021-02-09
CN108761938A (zh) 2018-11-06
US20200258460A1 (en) 2020-08-13
US10991327B2 (en) 2021-04-27

Similar Documents

Publication Publication Date Title
WO2019223663A1 (zh) 像素排布结构、其驱动方法、显示面板及显示装置
US9741299B2 (en) Display panel including a plurality of sub-pixel
KR100951350B1 (ko) 액정 표시 장치
CN105719606B (zh) 选择电路和具有选择电路的显示装置
WO2016188257A1 (zh) 阵列基板、显示面板和显示装置
KR101127593B1 (ko) 액정 표시 장치
KR101385225B1 (ko) 액정표시장치 및 그 구동방법
CN111522161B (zh) 一种阵列基板、显示面板、显示装置及驱动方法
WO2017015972A1 (zh) 一种液晶显示器
US8717271B2 (en) Liquid crystal display having an inverse polarity between a common voltage and a data signal
US10311821B2 (en) Data driver of liquid crystal display having two individually regulable gamma voltages
KR102169032B1 (ko) 표시장치
KR20190014361A (ko) 표시 패널
KR101307950B1 (ko) 액정 표시 장치 및 그의 구동 방법
JP2002297109A (ja) 液晶表示装置及びその駆動回路
KR101272177B1 (ko) 액정표시장치의 회전 구동방법
KR100909775B1 (ko) 액정표시장치
WO2020255536A1 (ja) 液晶表示装置
KR101447257B1 (ko) 액정 디스플레이 장치
KR101826352B1 (ko) 액정표시장치
KR20070109011A (ko) 액정패널, 액정표시장치 그의 구동방법
KR102290615B1 (ko) 액정표시장치
CN111210751B (zh) 一种显示驱动电路、显示屏及电子设备
US8411001B2 (en) Display device with floating bar
US20200402471A1 (en) Liquid crystal display

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19807032

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19807032

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 12.05.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19807032

Country of ref document: EP

Kind code of ref document: A1