WO2024060083A1 - 半导体器件及其制备方法、电子设备 - Google Patents

半导体器件及其制备方法、电子设备 Download PDF

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Publication number
WO2024060083A1
WO2024060083A1 PCT/CN2022/120296 CN2022120296W WO2024060083A1 WO 2024060083 A1 WO2024060083 A1 WO 2024060083A1 CN 2022120296 W CN2022120296 W CN 2022120296W WO 2024060083 A1 WO2024060083 A1 WO 2024060083A1
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layer
substrate
semiconductor device
gate cap
gate
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PCT/CN2022/120296
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English (en)
French (fr)
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段焕涛
倪茹雪
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华为技术有限公司
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Priority to PCT/CN2022/120296 priority Critical patent/WO2024060083A1/zh
Publication of WO2024060083A1 publication Critical patent/WO2024060083A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and its preparation method, and electronic equipment.
  • GaN power devices Due to the better switching characteristics, faster switching frequency, and lower losses of gallium nitride (GaN) materials, GaN power devices provide better switching performance and smaller size, and can be used to achieve smaller, lighter, and more reliable Efficient, more energy-saving power systems. GaN power devices are mainly used in fast chargers for smartphones and computers, and have good prospects in future applications such as electric vehicles, photovoltaic power generation, uninterruptible power supply (UPS), and data centers.
  • UPS uninterruptible power supply
  • High electron mobility transistor (HEMT) device is a semiconductor device that is widely used due to its advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability. Used as radio frequency devices or power devices.
  • GaN HEMT enhancement-mode devices mainly use cascode technology or p-GaN gate technology.
  • Cascode technology cascades the enhancement-type silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET) and the depletion-mode HEMT into an integral device, and realizes the enhancement-mode HEMT device by controlling the enhancement-mode MOSFET .
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the switching power consumption of the GaN HEMT enhancement-mode devices implemented by this technology is relatively large, and the additional MOSFET introduced will also increase the size of the system and increase packaging difficulty and cost.
  • p-GaN gate technology sets a p-GaN gate cap layer under the gate to raise the energy band at the channel position and deplete the 2DEG in the channel, thereby realizing enhanced HEMT devices.
  • the p-GaN gate cap layer needs to be etched. It is difficult to control conditions such as roughness, uniformity, and selectivity in the etching process, which easily results in etching. Problems of uneven corrosion and interface damage.
  • Embodiments of the present application provide a semiconductor device, a preparation method thereof, and electronic equipment, which are used to avoid uneven etching caused by etching the p-GaN gate cap layer while realizing an enhancement-mode high electron mobility transistor. and interface damage issues to improve the performance of semiconductor devices.
  • the present application provides a semiconductor device, which includes a substrate, a channel layer, a barrier layer, a gate cap layer, a gate electrode, a source electrode and a drain electrode.
  • the channel layer is located on one side of the substrate; the barrier layer is located on the side of the channel layer away from the substrate; the gate cap layer is located on the side of the barrier layer away from the substrate;
  • the gate cap layer includes free P-type impurities and a complex composed of P-type impurities and hydrogen impurities;
  • the gate cap layer includes a first part and a second part, and the second part is at least located on the first part Both sides; the complex concentration in the first part is less than the complex concentration in the second part, and the hydrogen impurities in the second part are evenly distributed.
  • the gate electrode, the source electrode and the drain electrode are located on a side of the gate cap layer away from the substrate.
  • the gate electrode is located on the first part, and the source electrode and the drain electrode are located on the second part.
  • the gate cap layer is located on the side of the barrier layer away from the channel layer.
  • the gate cap layer includes free P-type impurities and a complex formed by the combination of P-type impurities and hydrogen impurities.
  • the gate cap layer The concentration of the complex in the first part of the layer is less than the concentration of the complex in the second part of the gate cap layer, that is, there are more free P-type impurities in the first part than in the second part.
  • the hole concentration is greater than that in the second part.
  • the first part is in contact with the gate and the second part is in contact with the source and drain. In this way, when the voltage applied on the gate is zero, the two-dimensional electron gas in the channel layer below the gate can be depleted by the holes in the first part, and the two-dimensional electron gas below the source and drain can be retained, enabling enhanced HEMT.
  • the gate, source and drain are all arranged on the gate cap layer, and the gate cap layer has a whole-layer structure covering the barrier layer, there is no need to engrave the gate cap layer when preparing the semiconductor device provided by the embodiment of the present application. eclipse. In this way, enhanced HEMT can be realized while avoiding uneven etching or interface damage caused by etching the gate cap layer, thereby improving the yield, performance and reliability of semiconductor devices.
  • the gate cap layer is a whole layer structure covering the barrier layer, there is no need to use a secondary epitaxial growth process to form the gate cap layer when preparing the semiconductor device provided in the embodiment of the present application. This not only avoids the problem of a large amount of impurities remaining between the barrier layer and the gate cap layer due to interface treatment of the barrier layer, thereby affecting the performance of the semiconductor device, but also improves the quality of the gate cap layer.
  • the hydrogen impurities in the second part of the gate cap layer are uniformly distributed, that is, the hydrogen impurities in the second part are doped into the material forming the gate cap layer during the process of forming the gate cap layer.
  • the semiconductor device provided by the embodiment of the present application does not require hydrogen plasma implantation, the barrier layer is not easily damaged, and the mobility of the two-dimensional electron gas is not easily affected, thereby ensuring the dynamic characteristics of the semiconductor device.
  • the P-type impurities include Group II elements.
  • the P-type impurity includes magnesium.
  • the concentration of the P-type impurity ranges from 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 .
  • the gate voltage is zero, the two-dimensional electron gas in the channel layer below the gate can be depleted better, so that the semiconductor device is in a normally off state and the enhancement mode HEMT is realized.
  • it prevents the content of P-type impurities from being too high, ensuring the performance and quality of the gate cap layer, thereby ensuring the performance and quality of the semiconductor device.
  • the semiconductor device further includes a nucleation layer located between the substrate and the channel layer.
  • a nucleation layer located between the substrate and the channel layer.
  • the material of the nucleation layer includes aluminum nitride.
  • the semiconductor device further includes a buffer layer located between the nucleation layer and the channel layer.
  • a buffer layer located between the nucleation layer and the channel layer.
  • the buffer layer has a superlattice structure.
  • the buffer layer provided in the embodiments of the present application adopts a superlattice structure.
  • it can use two different film layers of materials to alternate to improve the breakdown resistance of the buffer layer, thereby further improving the high voltage resistance of the semiconductor device.
  • the use of a superlattice structure can also regulate the stress of the buffer layer, so that when the channel layer is formed on the side of the buffer layer away from the substrate, the stress change of the buffer layer is smaller and the structural stability of the semiconductor device is improved.
  • the buffer layer is made of aluminum nitride and aluminum gallium nitride. Since aluminum nitride and aluminum gallium nitride have better voltage resistance than gallium nitride, choosing aluminum nitride and aluminum gallium nitride materials to prepare the buffer layer can further improve the voltage resistance of the buffer layer.
  • the semiconductor device further includes an insertion layer located between the channel layer and the barrier layer.
  • an insertion layer located between the channel layer and the barrier layer.
  • the material of the insertion layer includes aluminum nitride.
  • a material of the gate cap layer includes gallium nitride.
  • a two-dimensional electron gas exists in the channel layer, and when the voltage on the gate is zero, the channel layer is located in a region below the first part, and the two-dimensional electron gas The energy is exhausted.
  • the present application provides a method for manufacturing a semiconductor device.
  • the preparation method includes: forming a channel layer on a substrate; forming a barrier layer on a side of the channel layer away from the substrate; The side of the barrier layer away from the substrate forms a gate cap layer; the gate cap layer includes a complex formed by combining P-type impurities and hydrogen impurities, and the gate cap layer includes a first part and a second part, The second part is located at least on both sides of the first part; the chemical bond between the P-type impurity and the hydrogen impurity in the complex located in the first part is broken, so that the chemical bond between the complex in the first part is The concentration is less than the concentration of the composite in the second part; a gate electrode is formed on the first part, and a source electrode and a drain electrode are formed on the second part.
  • breaking the chemical bond between the P-type impurity and the hydrogen impurity in the composite located in the first part includes: forming a mask on a side of the gate cap layer away from the substrate. Film layer, the mask layer has an opening, the opening exposes the first part. Laser annealing is performed on the gate cap layer based on the mask layer to break the chemical bond between the P-type impurity and the hydrogen impurity in the composite in the first part.
  • forming the gate cap layer on the side of the barrier layer away from the substrate includes: based on a reaction gas including ammonia, hydrogen, trimethylgallium and magnocene, or including The reaction gases of ammonia, nitrogen, trimethylgallium and magnocene form a gate cap layer on the side of the barrier layer away from the substrate.
  • the preparation method before forming the channel layer on the substrate, the preparation method further includes: forming a nucleation layer on the substrate.
  • the preparation method further includes: placing the nucleation layer away from the substrate.
  • a buffer layer is formed on the side, and the buffer layer has a superlattice structure.
  • the preparation method further includes: An insertion layer is formed on a side of the channel layer away from the substrate.
  • the present application provides an electronic device, including a circuit board and a semiconductor device as described in any of the above embodiments; the semiconductor device is electrically connected to the circuit board.
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application
  • Figure 2 is a preparation state diagram of a semiconductor device corresponding to the preparation method provided in Figure 1;
  • Figure 3 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 4 to 6 are preparation state diagrams of semiconductor devices corresponding to the preparation method provided in Figure 3;
  • Figure 7 is a flow chart for forming a gate cap layer according to an embodiment of the present application.
  • Figures 8 and 9 are diagrams of the preparation state of the semiconductor device corresponding to the preparation method provided in Figure 3;
  • Figure 10 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 11 and 12 are diagrams of the preparation state of the semiconductor device corresponding to the preparation method provided in Figure 10;
  • Figure 13 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 14 is a preparation state diagram of a semiconductor device corresponding to the preparation method provided in Figure 13;
  • FIG15 is a flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application.
  • Figure 16 is a preparation state diagram of a semiconductor device corresponding to the preparation method provided in Figure 15;
  • Figure 17 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 18 is a preparation state diagram of a semiconductor device corresponding to the preparation method provided in Figure 17;
  • Figure 19 is a structural diagram of a semiconductor device provided by an embodiment of the present application.
  • Figure 20 is a structural diagram of another semiconductor device provided by an embodiment of the present application.
  • Figure 21 is a structural diagram of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 22 is a structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 23 is a working flow diagram of a power switch provided by an embodiment of the present application.
  • plural means two or more than two.
  • At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • words such as “first” and “second” are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit the difference.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner that is easier to understand.
  • a method for preparing a semiconductor device includes:
  • the gate electrode 106 on the side of the p-GaN gate cap layer 105 away from the channel layer 101.
  • the source electrode 107 and the drain electrode 108 may also be formed on a side of the barrier layer 102 away from the channel layer 101.
  • the difference in adhesion coefficients of gallium (Ga) atoms on the surface of the barrier layer 102 and the surface of the hard mask layer 103 is used to selectively grow the p-GaN gate cap layer 105 on the barrier layer 102, thereby eliminating the need for
  • the p-GaN gate cap layer 105 is etched to avoid problems of uneven etching or interface damage caused by etching the p-GaN gate cap layer 105 .
  • the hard mask layer 103 needs to be formed outside the growth chamber, after the barrier layer 102 is formed on the channel layer 101, the unfinished semiconductor device needs to be taken out of the growth chamber, and after the hard mask layer 103 is formed, the semiconductor device with the hard mask layer 103 is placed in the growth chamber again to perform selective epitaxial growth of the p-GaN material. That is, the p-GaN gate cap layer 105 in the above embodiment needs to be formed by a secondary epitaxial growth process. In the early stage of the secondary epitaxial growth process, the quality of the epitaxially formed material is poor, which easily leads to poor quality of the semiconductor device.
  • the preparation method includes:
  • a channel layer 20 is formed on the substrate 10.
  • the material of the substrate 10 may include silicon, silicon carbide (SiC), sapphire, or the like.
  • the substrate 10 may be a silicon on insulator (SOI) substrate.
  • substrate 10 may be a silicon wafer.
  • the material of channel layer 20 may include gallium nitride (GaN).
  • the channel layer 20 may be formed on one side of the substrate 10 using a reactive gas including ammonia (NH 3 ), hydrogen (H 2 ), and trimethyl gallium.
  • a reactive gas including ammonia (NH 3 ), hydrogen (H 2 ), and trimethyl gallium.
  • hydrogen can be used as a carrier gas to transport the reaction gas into the growth chamber.
  • Ammonia can be used as a nitrogen source, and trimethylgallium is used to provide Group III elements.
  • nitrogen (N 2 ) can be used to replace hydrogen and the reaction gas can be transported into the growth chamber.
  • reaction gas for preparing the channel layer 20 is not limited to this.
  • the reaction temperature when the channel layer 20 is formed on one side of the substrate 10, the reaction temperature may be 1050 degrees Celsius (°C).
  • the reaction temperature for forming the channel layer 20 in the embodiment of the present application is not limited to 1050 degrees Celsius, and the reaction temperature can also be other values that are beneficial to the formation of the channel layer 20 .
  • the thickness of channel layer 20 may be 500 nm. It can be understood that the thickness of the channel layer 20 in this application is not limited to this, and the thickness of the channel layer 20 can be adjusted according to the structure and performance requirements of the semiconductor device 100 .
  • a barrier layer 30 is formed on the side of the channel layer 20 away from the substrate 10 .
  • the barrier layer 30 can be used to cooperate with the channel layer 20 to generate two-dimensional electron gas (2DEG) through polarization between the channel layer 20 and the barrier layer 30.
  • the two-dimensional electron gas can be generated under the action of an electric field. Efficiently conduct electrons.
  • the material of the barrier layer 30 may include aluminum gallium nitride (AlGaN).
  • a reactive gas including ammonia, hydrogen (or nitrogen), trimethyl aluminum and trimethyl gallium may be used to form a potential barrier on the side of the channel layer 20 away from the substrate 10 Layer 30.
  • hydrogen or nitrogen can be used as a carrier gas to transport the reaction gas into the growth chamber.
  • Trimethylaluminum and trimethylgallium are used to provide Group III elements, and nitrogen can be used as a nitrogen source.
  • the reaction gas used to prepare the barrier layer 30 is not limited to this.
  • the reaction temperature when the barrier layer 30 is formed on the side of the channel layer 20 away from the substrate 10, the reaction temperature may be 1050 degrees Celsius.
  • the reaction temperature for forming the barrier layer 30 in the embodiment of the present application is not limited to 1050 degrees Celsius, and the reaction temperature can also be other values that are beneficial to the formation of the barrier layer 30 .
  • barrier layer 30 may be formed to a thickness of 12 nanometers (nm). It can be understood that the thickness of the barrier layer 30 in this application is not limited to this, and those skilled in the art can adjust the thickness of the barrier layer 30 according to the structure and performance requirements of the semiconductor device 100 .
  • a gate cap layer 40 is formed on a side of the barrier layer 30 away from the substrate 10.
  • the gate cap layer 40 includes a complex formed by the combination of P-type impurities and hydrogen impurities, and the gate cap layer 40 includes a first portion 41 and a second portion 42, and the second portion 42 is at least located on both sides of the first portion 41.
  • FIG6 shows the microstructure of the gate cap layer 40, and the complex formed by the combination of P-type impurities and hydrogen impurities in the gate cap layer 40 is shown as a black circle.
  • the second part 42 is located at least on both sides of the first part 41
  • the second part 42 is located on both sides of the first part, or it may be that the second part 42 is arranged around the circumference of the first part 41.
  • the material of the gate cap layer 40 may include gallium nitride.
  • P-type impurities may include Group II elements.
  • the P-type impurity may include one or a combination of at least two of Group IIA elements, such as beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).
  • Group IIA elements such as beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).
  • Be beryllium
  • Mg magnesium
  • Ca calcium
  • Ba barium
  • the P-type impurity can more easily combine with the hydrogen impurity to form a complex.
  • the P-type impurity can also be selected from elements in group IIB, such as one or a combination of at least two of zinc (Zn), mercury (Hg), cadmium (Cd).
  • the P-type impurities may include magnesium.
  • the P-type impurities The complex formed by the impurity and the hydrogen impurity may include an Mg-H complex.
  • the gate cap layer 40 may be formed on a side of the barrier layer 30 away from the substrate 10 by doping P-type impurities into the material forming the gate cap layer 40 .
  • step S300 forming a gate cap layer 40 on a side of the barrier layer 30 away from the substrate 10, includes:
  • a gate cap layer 40 is formed on the side of layer 30 away from substrate 10 .
  • magnocene can provide P-type impurities for the gate cap layer 40 .
  • Hydrogen or nitrogen can be used as a carrier gas to transport the gas into the growth chamber.
  • Ammonia gas, hydrogen gas, trimethylgallium, and magnocene all contain hydrogen elements, so the gate cap layer 40 formed may contain hydrogen impurities.
  • the hydrogen impurity may form a complex with the P-type impurity during the formation of the gate cap layer 40 .
  • reaction gas provided in the present application is not limited thereto, and the source of the P-type impurities is not limited to bismuthocene magnesium, and can be selected according to the design requirements of the semiconductor device 100 .
  • the concentration range of P-type impurities may be 1 ⁇ 10 18 cm -3 ⁇ 1 ⁇ 10 21 cm -3 .
  • the concentration of P-type impurities can be 1 ⁇ 10 18 cm -3 , 5 ⁇ 10 18 cm -3 , 1 ⁇ 10 19 cm -3 , 4 ⁇ 10 19 cm -3 , 6 ⁇ 10 19 cm -3 , 1 ⁇ 10 20 cm -3 , 5 ⁇ 10 20 cm -3 , 1 ⁇ 10 21 cm -3 .
  • P-type impurities doped in the gate cap layer 40 can necessarily combine with the H impurities to form a complex, so free P-type impurities may also exist in the gate cap layer 40.
  • the P-type impurities in the "concentration of P-type impurities" described in the above embodiments of the present application include not only P-type impurities used to form a complex, but also free P-type impurities.
  • the concentration of the P-type impurities will not be too high, which will not affect the performance of the gate cap layer 40.
  • the concentration of the P-type impurities will not be too low, so that the voltage applied on the gate will not be too low.
  • the P-type impurities are enough to deplete the electrons (two-dimensional electron gas) in the channel layer, so that the semiconductor device is in a normally off state.
  • not all of the hydrogen impurities doped in the gate cap layer 40 can be combined with the P-type impurities to form a complex, so there may be free hydrogen impurities in the gate cap layer 40 .
  • the free P-type impurities and free hydrogen impurities, as well as the P-type impurities may be evenly distributed in the gate cap layer 40 .
  • the reaction temperature when the gate cap layer 40 is formed on the side of the barrier layer 30 away from the substrate 10, the reaction temperature may be 950 degrees Celsius.
  • the reaction temperature for forming the gate cap layer 40 in the embodiment of the present application is not limited to 950 degrees Celsius, and the reaction temperature can also be other values that are beneficial to the formation of the gate cap layer 40 .
  • the thickness of gate cap layer 40 may be 80 nm. It can be understood that the thickness of the gate cap layer 40 in this application is not limited to this, and the thickness of the gate cap layer 40 can be adjusted according to the structure and performance requirements of the semiconductor device 100.
  • the substrate 10 can be placed in a growth chamber, and metal-organic chemical vapor deposition (MOCVD) can be used as a growth technology to form the above-mentioned channel layer 20 and potential on the substrate 10 .
  • MOCVD metal-organic chemical vapor deposition
  • S400 as shown in Figure 8, break the chemical bond between the P-type impurity and the hydrogen impurity in the complex in the first part 41, so that the concentration of the complex in the first part 41 is smaller than the concentration of the complex in the second part 42. body concentration.
  • the P-type impurity can still exist in the first part 41, and the hydrogen impurity can diffuse into the air in a free state. .
  • “Cleaving the chemical bond between the P-type impurity and the hydrogen impurity in the complex in the first part 41” may mean breaking the chemical bond between the P-type impurity and the hydrogen impurity in all the complexes in the first part 41 , or the chemical bond between the P-type impurity and the hydrogen impurity in the partial complex in the first part 41 can be broken. As long as it can be ensured that after step S400, the activated P-type impurity in the first part 41 can first remove the The two-dimensional electron gas is exhausted.
  • a gate electrode 51 is formed on the first part 41, and a source electrode 52 and a drain electrode 53 are formed on the second part 42.
  • the material of the gate 51 may include metal, such as nickel, gold, etc.
  • the material of the source electrode 52 and the drain electrode 53 may include metal, such as titanium, aluminum, gold, etc.
  • a device processing process may be used to prepare the gate electrode 51 on the first part 41 , and the source electrode 52 and the drain electrode 53 on the second part 42 .
  • the gate electrode 51 forms a Schottky contact with the first part 41 , and the source electrode 52 and the drain electrode 53 form an ohmic contact with the second part 42 .
  • the source electrode 52 and the drain electrode 53 are used to allow two-dimensional electron gas to flow in the channel layer 20 between the source electrode 52 and the drain electrode 53 under the action of an electric field.
  • the gate electrode 51 is located between the source electrode 52 and the drain electrode 53 and is used to allow or prevent the passage of two-dimensional electron gas.
  • the thickness of the gate electrode 51 , the source electrode 52 and the drain electrode 53 there is no limit on the thickness of the gate electrode 51 , the source electrode 52 and the drain electrode 53 , as long as it can meet the performance requirements of the semiconductor device.
  • a whole layer of gate cap layer 40 is first grown on the side of the barrier layer 30 away from the substrate 10 .
  • Both the first part 41 and the second part 42 of the gate cap layer 40 have P-type impurities and hydrogen impurities.
  • the complex formed by combining The first portion 41 of the gate cap layer 40 is then processed to break the chemical bond between the P-type impurity and the hydrogen impurity in the composite in the first portion 41 .
  • the P-type impurities in the first part 41 of the gate cap layer 40 are activated, and the hole concentration in the first part 41 increases, so that the two-dimensional electron gas under the first part 41 can be depleted, and the second part 42
  • the P-type impurities inside are still passivated by hydrogen impurities, and the two-dimensional electron gas under the second part 42 is retained.
  • the gate electrode 51, the source electrode 52 and the drain electrode 53 are formed, when the voltage applied on the gate electrode 51 is zero, there is no two-dimensional electron gas under the gate electrode 51, and the semiconductor device 100 is turned off, so that the enhancement mode HEMT can be realized .
  • the second portion 42 below the source electrode 52 and the drain electrode 53 maintains a high resistance due to the presence of P-type impurities in the form of a complex, which is beneficial to improving current collapse and leakage of the semiconductor device.
  • the preparation method provided by the above embodiments of the present application, there is no need to etch the gate cap layer 40 , which can avoid the problem of uneven etching or interface damage caused by etching the gate cap layer 40 , thereby improving the efficiency of the process. Yield, performance and reliability of prepared semiconductor devices.
  • the preparation process can be made simpler, the process efficiency can be improved, the preparation process does not rely on expensive and complex etching equipment, and the preparation cost can be reduced.
  • the embodiment of the present application does not need to process the interface of the barrier layer, thereby avoiding the risk of impurities such as silicon and oxygen. The existence of it leads to problems such as weakened gate control ability and leakage of semiconductor devices.
  • the gate cap layer 40 can be grown directly on the barrier layer 30 without using secondary epitaxial growth technology. The quality of the epitaxial growth material can be better, and the quality of the semiconductor device 100 formed can also be better. .
  • the method implemented in this application does not require plasma injection, thereby avoiding physical damage to the barrier layer caused by the plasma injection process and adverse effects on the mobility of the two-dimensional electron gas, ensuring the dynamic characteristics of the semiconductor device.
  • Step S400 in the above embodiment breaking the chemical bond between the P-type impurity and the hydrogen impurity in the composite located in the first part 41 will be further described below with reference to FIGS. 10 to 12 .
  • step S400 breaking the chemical bond between the P-type impurity and the hydrogen impurity in the complex located in the first part 41, includes:
  • a mask layer 11 is formed on the side of the gate cap layer 40 away from the substrate 10.
  • the mask layer 11 has an opening 111, and the opening 111 exposes the first part 41.
  • the material of the mask layer 11 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), titanium nitride (TiN), etc.
  • the mask layer 11 can be formed on the side of the gate cap layer 40 away from the substrate 10 through a deposition method.
  • a chemical vapor deposition process can be used to form the mask layer 11 on the side of the gate cap layer 40 away from the substrate 10 . .
  • the semiconductor device on which the gate cap layer 40 is formed may be taken out of the growth chamber to prepare a mask outside the growth chamber.
  • Film layer 11 may be taken out of the growth chamber to prepare a mask outside the growth chamber.
  • a whole layer of mask layer 11 may be first formed on the side of the gate cap layer 40 away from the substrate 10 , and then a photoresist layer may be formed on the side of the mask layer 11 away from the substrate 10 .
  • the photoresist layer is patterned through processes such as development, and finally the mask layer 11 is etched using the patterned photoresist layer to form openings 111 .
  • the number, shape and arrangement position of the openings 111 in the mask layer 11 are not limited, and can be designed according to the requirements of the semiconductor device.
  • the downward arrow in Figure 12 represents the laser.
  • part of the laser light is irradiated onto the mask layer 11
  • another part of the laser light is irradiated onto the first part 41 of the gate cap layer 40 through the opening 111 of the mask layer 11 .
  • the high-energy laser causes the temperature of the first part 41 to increase, thereby breaking the chemical bond between the P-type impurity and the hydrogen impurity in the composite within the first part 41 .
  • the mask layer 11 can be removed.
  • a laser with a wavelength of 355 nanometers and a frequency of 20 kilohertz can be used to perform laser annealing on the gate cap layer 40 .
  • the laser wavelength and laser frequency used in the embodiments of the present application are not limited to these.
  • the laser annealing equipment can be selected according to the energy required to break the chemical bond between the P-type impurity and the hydrogen impurity, thereby adjusting the wavelength and frequency of the laser. .
  • the atmosphere may be a nitrogen atmosphere.
  • the above-mentioned embodiment of the present application utilizes the mask layer 11 with the opening 111 and the laser annealing process to break the chemical bond between the P-type impurity and the hydrogen impurity in the composite in the first part 41 and at the same time break the second part 42
  • the chemical bond between the P-type impurity and the hydrogen impurity in the complex is retained, so that while the two-dimensional electron gas in the channel layer 20 under the first part 41 is depleted, the channel under the second part 42 The two-dimensional electron gas in layer 20 is retained.
  • the enhancement mode HEMT can be realized without etching the gate cap layer 40 .
  • the laser annealing process has the characteristics of high energy, fast speed, small damage to the material and precise and controllable annealing range. Therefore, it can achieve ultra-fast annealing of the gate cap layer 40, improve process efficiency and shorten process time.
  • the preparation method may also include:
  • a nucleation layer 60 is formed on the substrate 10.
  • the nucleation layer 60 can be used to alleviate the lattice coefficient mismatch and thermal expansion coefficient mismatch between the material of the substrate 10 and the material of the channel layer 20, so as to avoid the channel layer 20 being directly formed on the substrate 10.
  • the stress of the channel layer 20 is too large, causing the problem of fracture of the channel layer 20 or other film layers.
  • the material of the nucleation layer 60 may include aluminum nitride.
  • a reaction gas including ammonia, hydrogen, and trimethylaluminum may be used to form the nucleation layer 60 on one side of the substrate 10 .
  • hydrogen can be replaced by nitrogen.
  • the reaction temperature when forming nucleation layer 60 on substrate 10, the reaction temperature may be 1100 degrees Celsius.
  • the thickness of the nucleation layer 60 formed may be 200 nanometers.
  • the reaction gas to form the nucleation layer 60, the reaction temperature, and the thickness of the nucleation layer 60 are not limited to the above-mentioned embodiments and can be adjusted according to actual needs.
  • the substrate 10 may be placed in a growth chamber, and metal organic chemical vapor deposition is used as a growth technique to form a nucleation layer 60 on the substrate 10 .
  • the preparation method further includes:
  • the buffer layer 70 may be a superlattice structure.
  • the material of the buffer layer 70 may include aluminum nitride (AlN) and aluminum gallium nitride (AlGaN). Since aluminum nitride and aluminum gallium nitride have better voltage resistance than gallium nitride, choosing aluminum nitride and aluminum gallium nitride materials to prepare the buffer layer 70 can further improve the voltage resistance of the buffer layer 70 ability.
  • AlN aluminum nitride
  • AlGaN aluminum gallium nitride
  • the number of superlattice pairs in the buffer layer 70 may be 90 pairs.
  • the buffer layer 70 may include 90 aluminum nitride layers and 90 aluminum gallium nitride layers alternately stacked.
  • the thickness of a single layer of aluminum nitride can be 5 nanometers, and the thickness of a single layer of aluminum gallium nitride can be 25 nanometers.
  • the materials of the buffer layer 70 and the superlattice structure provided in the embodiments of the present application are not limited thereto, and can be designed according to the performance requirements of the semiconductor device 100 .
  • the voltage withstand capability of the semiconductor device 100 can be improved, and when the operating voltage of the semiconductor device 100 is relatively high (for example, 650 volts), the semiconductor device can be prevented from being broken down, thereby improving the operating stability of the semiconductor device 100 sex.
  • the buffer layer 70 provided in the embodiment of the present application adopts a superlattice structure.
  • the alternate film layers of two materials can be used to improve the breakdown resistance of the buffer layer 70, thereby further improving the high voltage resistance of the semiconductor device 100.
  • the use of a superlattice structure can also regulate the stress of the buffer layer 70, so that when the channel layer 20 is formed on the side of the buffer layer 70 away from the substrate 10, the stress change of the buffer layer 70 is smaller, improving the semiconductor device. 100% structural stability.
  • the substrate 10 can be placed in a growth chamber, metal-organic compound chemical vapor deposition is used as a growth technology, and the buffer layer 70 is formed on the side of the nucleation layer 60 away from the substrate 10 .
  • a reaction gas including ammonia gas, hydrogen gas (or nitrogen gas), trimethylaluminum and trimethylgallium may be used to form the buffer layer 70 .
  • hydrogen (or nitrogen) can be used as a carrier gas to transport the reaction gas into the growth chamber.
  • the reaction temperature when the buffer layer 70 is formed on the substrate 10, the reaction temperature may be 1000 degrees Celsius.
  • the reaction temperature for forming the buffer layer 70 in the embodiment of the present application is not limited to 1000 degrees Celsius, and the reaction temperature can also be other values that are beneficial to the formation of the buffer layer 70 .
  • the material of the nucleation layer 60 is aluminum nitride and the film layer of the buffer layer 70 closest to the substrate 10 is an aluminum nitride layer
  • forming the nucleation layer 60 before forming the buffer layer 70 can also improve buffering.
  • the formation quality of layer 70 is improved, thereby improving the quality and yield of the semiconductor device.
  • the preparation method may also include:
  • an insertion layer 80 is formed on the side of the channel layer 20 away from the substrate 10 .
  • the polarization effect of the channel layer 20, the insertion layer 80 and the barrier layer 30 can produce a higher two-dimensional electron gas concentration, and the insertion layer 80 can reduce the disordered scattering of the alloy to improve the two-dimensional electron gas mobility, which is beneficial to The output characteristics of the semiconductor device 100 are improved.
  • the material of the insertion layer 80 may include aluminum nitride, and the thickness of the insertion layer 80 may be 0.4 nanometers. It is understood that the material and thickness of the insertion layer 80 in the present application are not limited thereto, and the material and thickness of the insertion layer 80 may be designed according to the performance requirements of the semiconductor device.
  • a reactive gas including ammonia, hydrogen and trimethylaluminum may be used to form the insertion layer 80 on a side of the channel layer 20 away from the substrate 10 .
  • hydrogen can be replaced by nitrogen.
  • the reaction temperature when the insertion layer 80 is formed on a side of the channel layer 20 away from the substrate 10 , the reaction temperature may be 1050 degrees Celsius.
  • the substrate 10 can be placed in a growth chamber, and metal-organic compound chemical vapor deposition is used as a growth technique to form the insertion layer 80 on the substrate 10 .
  • the substrate 10 can be High-temperature surface cleaning to remove the oxide layer on the substrate 10 .
  • the substrate 10 can be subjected to high-temperature surface cleaning under the condition that the atmosphere is hydrogen and the temperature is 1100 degrees Celsius.
  • Hydrogen has reducing properties and can reduce the oxide layer on the surface of the substrate 10 under high temperature conditions.
  • high-temperature surface cleaning of the substrate 10 can be performed in the growth chamber, so that the film layer can be grown directly after cleaning the substrate 10 to avoid re-oxidation of the substrate surface during the process of moving the substrate. situation occurs.
  • the time for performing high-temperature surface cleaning on the substrate 10 may be 5 minutes.
  • the temperature and time for high-temperature surface cleaning of the substrate 10 are not limited, and can be adaptively adjusted according to the processing conditions.
  • some embodiments of the present application provide a semiconductor device 100 .
  • the semiconductor device 100 can be prepared and formed by the manufacturing method of the semiconductor device 100 provided in any of the above embodiments.
  • the semiconductor device 100 includes a substrate 10 , a channel layer 20 , a barrier layer 30 , a gate cap layer 40 , a gate electrode 51 , a source electrode 52 and a drain electrode 53 .
  • the material of the substrate 10 may include silicon, silicon carbide, sapphire, etc.
  • the substrate 10 may be a silicon-on-insulator substrate.
  • substrate 10 may be a silicon wafer.
  • the channel layer 20 is located on one side of the substrate 10.
  • the material of the channel layer 20 may include gallium nitride.
  • the barrier layer 30 is located on a side of the channel layer 20 away from the substrate 10 .
  • the material of the barrier layer 30 may include aluminum gallium nitride.
  • the channel layer 20 and the barrier layer 30 form a heterojunction, and through polarization, a two-dimensional electron gas is formed in the contact area between the channel layer 20 and the barrier layer.
  • Two-dimensional electron gas can efficiently transport electrons under the action of an electric field.
  • the gate cap layer 40 is located on a side of the barrier layer 30 away from the substrate 10 .
  • the gate cap layer 40 includes free P-type impurities and a composite composed of P-type impurities and hydrogen impurities.
  • the gate cap layer 40 includes a first part 41 and a second part 42, and the second part 42 is located at least on both sides of the first part 41.
  • the complex concentration in the first part 41 is smaller than the complex concentration in the second part 42, and the hydrogen impurities in the second part 42 are uniformly distributed.
  • the material of the gate cap layer 40 may include gallium nitride.
  • P-type impurities may include Group II elements.
  • the P-type impurities may include Group IIA elements, such as one or a combination of at least two of beryllium, magnesium, calcium, strontium, and barium.
  • Group IIA elements such as one or a combination of at least two of beryllium, magnesium, calcium, strontium, and barium.
  • the P-type impurity can more easily combine with the hydrogen impurity to form a complex.
  • the P-type impurity can also be selected from elements in group IIB, such as one or a combination of at least two of zinc, mercury, and cadmium.
  • the P-type impurities may include magnesium.
  • the complex formed by the P-type impurity and the hydrogen impurity may include an Mg-H complex.
  • the gate electrode 51 , the source electrode 52 and the drain electrode 53 are located on the side of the gate cap layer 40 away from the substrate 10 .
  • the gate electrode 51 is located on the first part 41
  • the source electrode 52 and the drain electrode 53 are located on the second part 42 .
  • the material of the gate 51 may include metal, such as nickel, gold, etc.
  • the material of the source electrode 52 and the drain electrode 53 may include metal, such as titanium, aluminum, gold, etc.
  • a Schottky contact is formed between the gate electrode 51 and the first part 41 , and an ohmic contact is formed between the source electrode 52 and the drain electrode 53 and the second part 42 .
  • the source electrode 52 and the drain electrode 53 are used to allow two-dimensional electron gas to flow in the channel layer 20 between the source electrode 52 and the drain electrode 53 under the action of an electric field.
  • the gate electrode 51 is located between the source electrode 52 and the drain electrode 53 and is used to allow or prevent the passage of two-dimensional electron gas.
  • the gate cap layer 40 is located on the side of the barrier layer 30 away from the channel layer 20, and the gate cap layer 40 includes free P-type impurities and a complex formed by the combination of P-type impurities and hydrogen impurities.
  • the concentration of the complex in the first part 41 of the gate cap layer 40 is less than the concentration of the complex in the second part 42 of the gate cap layer 40, that is, the free P-type impurities in the first part 41 are more than the free P-type impurities in the second part 42, and the hole concentration in the first part 41 is greater than the hole concentration in the second part 42.
  • the first part 41 is in contact with the gate 51, and the second part 42 is in contact with the source 52 and the drain 53.
  • the two-dimensional electron gas in the region below the gate 51 (or the first part 41) in the channel layer 20 can be depleted by the holes in the first part 41, and the two-dimensional electron gas below the source 52 and the drain 53 can be retained, thereby realizing an enhanced HEMT.
  • the second portion 42 below the source 52 and the drain 53 can maintain high resistance due to the presence of the P-type impurities in the form of a complex, which is beneficial to improving the current collapse and leakage of the semiconductor device 100 .
  • the gate electrode 51, the source electrode 52 and the drain electrode 53 are all disposed on the gate cap layer 40, and the gate cap layer 40 is an entire layer structure covering the barrier layer 30, when preparing the semiconductor device 100 provided in the embodiment of the present application, There is no need to etch the gate cap layer 40 . In this way, it is possible to realize enhanced HEMT while avoiding problems of uneven etching or interface damage caused by etching the gate cap layer, thereby improving the yield, performance, and reliability of the semiconductor device 100 .
  • the gate cap layer has an entire layer structure covering the barrier layer 30, when preparing the semiconductor device 100 provided in the embodiment of the present application, there is no need to use a secondary epitaxial growth process to form the gate cap layer, thereby not only avoiding the Interface treatment of the barrier layer results in a large amount of impurities remaining between the barrier layer and the gate cap layer, which affects the performance of the semiconductor device.
  • the quality of the gate cap layer 40 can be improved.
  • the hydrogen impurities in the second part 42 of the gate cap layer 40 are evenly distributed, that is, the hydrogen impurities in the second part 42 are doped into the gate cap layer during the process of forming the gate cap layer 40 . formed in the material.
  • the semiconductor device provided by the embodiment of the present application There is no need for hydrogen plasma injection, the barrier layer 30 is not easily damaged, and the mobility of the two-dimensional electron gas is not easily affected, ensuring the dynamic characteristics of the semiconductor device.
  • the concentration of P-type impurities ranges from 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 .
  • the two-dimensional electron gas in the channel layer 20 below the gate 51 can be depleted better, so that the semiconductor device 100 is in a normally off state, thereby realizing an enhancement mode HEMT.
  • the content of P-type impurities is not too high, ensuring the performance and quality of the gate cap layer 40, thereby ensuring the performance and quality of the semiconductor device.
  • P-type impurity includes not only free P-type impurities, but also P-type impurities located in the complex.
  • hydrogen impurities include not only free hydrogen impurities, but also hydrogen impurities located in the complex.
  • the semiconductor device 100 may also include The nucleation layer 60 and the nucleation layer 60 are located between the substrate 10 and the channel layer 20 .
  • the nucleation layer 60 By arranging the nucleation layer 60 in the embodiment of the present application, the difference in thermal expansion coefficient of the channel layer 20 and the substrate 10 can be alleviated, and the difference in the lattice coefficient of the channel layer 20 and the lattice coefficient of the substrate can be alleviated, so that The lattice growth of the channel layer 20 is more regular.
  • the nucleation layer 60 can also relieve the stress of the channel layer 20 and prevent the semiconductor device from breaking due to high stress in the channel layer when the channel layer is directly formed on the substrate.
  • the material of nucleation layer 60 may include aluminum nitride.
  • the thickness of nucleation layer 60 may be 200 nanometers. It can be understood that the material and thickness of the nucleation layer 60 are not limited to this, and can be designed according to actual requirements.
  • the semiconductor device 100 may further include a buffer layer 70 located between the nucleation layer 60 and the channel layer 20 .
  • the voltage withstand capability of the semiconductor device 100 can be improved, thereby preventing the semiconductor device from being broken down when the operating voltage of the semiconductor device 100 is relatively high (for example, 650 volts), thereby improving the Operation stability of the semiconductor device 100 .
  • the buffer layer 70 may have a superlattice structure.
  • the superlattice structure is a multilayer film that uses two different materials to grow alternately in thin layers of a few nanometers to tens of nanometers and has periodicity.
  • the buffer layer 70 provided in the embodiment of the present application adopts a superlattice structure.
  • the alternate film layers of two materials can be used to improve the breakdown resistance of the buffer layer 70, thereby further improving the high voltage resistance of the semiconductor device 100.
  • the use of a superlattice structure can also regulate the stress of the buffer layer 70, so that when the channel layer 20 is formed on the side of the buffer layer 70 away from the substrate 10, the stress change of the buffer layer 70 is smaller, improving the semiconductor device. 100% structural stability.
  • the number of superlattice pairs of buffer layer 70 is 90 pairs.
  • the material of the buffer layer 70 may include aluminum nitride and aluminum gallium nitride. Since aluminum nitride and aluminum gallium nitride have better pressure resistance than gallium nitride, the use of aluminum nitride and aluminum gallium nitride materials to prepare the buffer layer 70 can further improve the pressure resistance of the buffer layer 70.
  • the material of the buffer layer 70 includes aluminum nitride and aluminum gallium nitride, that is, the superlattice structure includes alternately arranged aluminum nitride layers and aluminum gallium nitride layers.
  • the thickness of the aluminum nitride layer may be 5 nanometers, and the thickness of the aluminum gallium nitride layer may be 25 nanometers.
  • the semiconductor device 100 may further include an insertion layer 80 located between the channel layer 20 and the barrier layer 30 .
  • the polarization effect of the channel layer 20, the insertion layer 80 and the barrier layer 30 can produce a higher two-dimensional electron gas concentration, and the insertion layer 80 can reduce the disordered scattering of the alloy to improve the two-dimensional electron gas mobility. It is beneficial to improve the output characteristics of semiconductor devices.
  • the material of intercalation layer 80 includes aluminum nitride.
  • the thickness of insert layer 80 may be 0.4 nanometers. It can be understood that the material and thickness of the insertion layer 80 are not limited to this, and can be designed according to actual requirements.
  • an embodiment of the present application provides an electronic device 1000.
  • the electronic device 1000 can be, for example, a charger, a charging small household appliance (such as a soymilk machine, a sweeping robot), a mobile phone, a computer, an electric vehicle, a data center, etc. device.
  • a charging small household appliance such as a soymilk machine, a sweeping robot
  • a mobile phone such as a soymilk machine, a sweeping robot
  • a computer such as a soymilk machine, a sweeping robot
  • a mobile phone such as a soymilk machine, a sweeping robot
  • a computer such as a soymilk machine, a sweeping robot
  • an electric vehicle such as a soymilk machine, a sweeping robot
  • the electronic device 1000 may also include a circuit board 200 (for example, a printed circuit board (PCB)), and the above-mentioned semiconductor device 100 may be electrically connected to the circuit board 200 .
  • a circuit board 200 for example, a printed circuit board (PCB)
  • PCB printed circuit board
  • the semiconductor device 100 may be applied in the power switch 300 of the charger.
  • the power switch 300 may also include an input filter 301 , a rectifier circuit 302 , a switching power transistor 303 , a transformer 304 , an output filter 305 , a pulse width modulation circuit 306 and a switch driver 307 .
  • Semiconductor device 100 serves as a switching power transistor 303 .
  • the output end of the input filter 301 is connected to the input end of the rectifier circuit 302, the output end of the rectifier circuit 302 is connected to the input end of the switching power transistor 303, the output end of the switching power transistor 303 is connected to the input end of the transformer 304, and the transformer
  • the output terminal of 304 is connected to the input terminal of the output filter 305, the output terminal of the output filter 305 is connected to the input terminal of the pulse width modulation circuit 306, the output terminal of the pulse width modulation circuit 306 is connected to the input terminal of the switch driver 307, and the switch The output terminal of the driver 307 is connected to the control terminal of the switching power transistor 303 .
  • FIG23 shows a flowchart of the working process of the power switch 300.
  • the input filter 301 and the rectifier circuit 302 convert the input power into direct current (for example, converting alternating current into direct current, or converting direct current into direct current), and the switching power transistor 303 performs high-speed conduction and cutoff, converting the direct current output by the input filter 301 and the rectifier circuit 302 into high-frequency alternating current, and then providing it to the transformer 304 for voltage transformation, and the transformed power is output by the output filter 305, thereby generating one or more required voltage groups.
  • the output power can also feedback control the switching power transistor 303 through the pulse width modulation circuit 306 and the switch driver 307, thereby further improving the output voltage of the power switch 300.
  • the semiconductor device 100 can also be connected to other circuits through the circuit board 200.
  • the semiconductor device 100 can be connected to the input filter 301, the rectifier circuit 302, the transformer 304, the output filter 305, the pulse width modulation circuit 306 and the switch driver through the circuit board 200. 307 electrical connection.
  • the electronic device 1000 provided in the embodiment of the present application can achieve the same beneficial effects as the semiconductor device 100 and the method for manufacturing the semiconductor device 100 provided in the above embodiments of the present application.

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Abstract

本申请实施例提供一种半导体器件及其制备方法、电子设备，涉及半导体技术领域。半导体器件包括衬底、沟道层、势垒层、栅帽层、栅极、源极和漏极。势垒层位于沟道层远离衬底的一侧。栅帽层位于势垒层远离衬底的一侧，栅帽层包括游离的P型杂质，及由P型杂质和氢杂质结合而成的复合体。栅帽层包括第一部分和第二部分，第一部分中的复合体浓度小于第二部分中的复合体浓度，且第二部分中的氢杂质均匀分布。栅极位于第一部分上，源极和漏极位于第二部分上。半导体器件用于在实现增强型高电子迁移率晶体管的同时，避免因对栅帽层进行刻蚀，导致的刻蚀不均和界面损伤的问题。半导体器件应用于电子设备中，以提高电子设备的性能。

Description

半导体器件及其制备方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制备方法、电子设备。
背景技术
由于氮化镓(GaN)材料更好的开关特性、更快的开关频率、更低的损耗，GaN功率器件提供了更好的开关性能且体积更小，可用于实现更小、更轻、更高效、更节能的电源系统。GaN功率器件主要用于智能手机和电脑的快速充电器上，未来在电动汽车、光伏发电、不间断电源(uninterruptible power supply，UPS)、数据中心等应用中具有良好的前景。
高电子迁移率晶体管(high electron mobility transistor，HEMT)器件是一种半导体器件，由于其具有高击穿电场、高沟道电子浓度、高电子迁移率和高温度稳定性等优点，因而被广泛用于作为射频器件或功率器件。
对于GaN HEMT器件，由于高浓度二维电子气(two-dimensional electron gas，2DEG)的存在，零偏压下栅极无法耗尽沟道中的2DEG，即当栅极电压为零时沟道中仍有电流通过，因此需要在栅极施加负偏置耗尽栅极下的2DEG，将HEMT置于关断状态。然而，这在应用中会降低电路的安全性、增加电路设计的复杂度，同时增大功耗。因此，实现在栅极零偏压下处于关断状态的增强型HEMT对于推进GaN HEMT器件在功率领域的应用至关重要。
目前，GaN HEMT增强型器件主要采用共源共栅(cascode)技术或p-GaN栅技术。cascode技术是将增强型硅基金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)与耗尽型HEMT级联成一个整体器件，通过控制增强型MOSFET实现增强型HEMT器件。然而，该技术所实现的GaN HEMT增强型器件的开关功耗较大，且额外引入的MOSFET还会增大系统的体积、提高封装难度和成本。
p-GaN栅技术是在栅极下设置p-GaN栅帽层，将沟道位置的能带抬高，使沟道中的2DEG耗尽，从而实现增强型HEMT器件。然而采用p-GaN栅技术制备增强型HEMT器件时，需要对p-GaN栅帽层进行刻蚀，刻蚀工艺中粗糙度、均匀性和选择性等条件的控制难度较高，从而易造成刻蚀不均匀和界面损伤的问题。
发明内容
本申请实施例提供一种半导体器件及其制备方法、电子设备，用于在实现增强型高电子迁移率晶体管的同时，避免因对p-GaN栅帽层进行刻蚀，导致的刻蚀不均匀和界面损伤的问题，提高半导体器件的性能。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种半导体器件，该半导体器件包括衬底、沟道层、势垒层、栅帽层、栅极、源极和漏极。沟道层位于所述衬底的一侧；势垒层位于所述沟道层远离所述衬底的一侧；栅帽层位于所述势垒层远离所述衬底的一侧；所述栅帽层 包括游离的P型杂质，及由P型杂质和氢杂质结合而成的复合体；所述栅帽层包括第一部分和第二部分，所述第二部分至少位于所述第一部分的两侧；所述第一部分中的复合体浓度小于所述第二部分中的复合体浓度，且所述第二部分中的氢杂质均匀分布。栅极、源极和漏极位于所述栅帽层远离所述衬底的一侧。所述栅极位于所述第一部分上，所述源极和所述漏极位于所述第二部分上。
在本申请所提供的半导体器件中，栅帽层位于势垒层远离沟道层的一侧，栅帽层包括游离的P型杂质以及有P型杂质与氢杂质结合形成的复合体，栅帽层的第一部分中复合体的浓度小于栅帽层的第二部分中的复合体浓度，也即第一部分中的游离的P型杂质多于第二部分中的游离的P型杂质，第一部分的空穴浓度大于第二部分中的空穴浓度。第一部分与栅极接触，第二部分与源极和漏极接触。这样，在栅极上施加的电压为零时，位于栅极下方的沟道层中的二维电子气可以被第一部分中的空穴耗尽，源极和漏极下方的二维电子气则可以被保留，从而实现增强型HEMT。
且由于栅极、源极和漏极均设置在栅帽层上，栅帽层为覆盖势垒层的整层结构，因此制备本申请实施例所提供的半导体器件时无需对栅帽层进行刻蚀。这样，可以在实现增强型HEMT的同时，避免因刻蚀栅帽层导致的刻蚀不均匀或界面损伤的问题，从而提高半导体器件的良率、性能和可靠性。
同时，由于栅帽层为覆盖势垒层的整层结构，因此制备本申请实施例所提供的半导体器件时，也无需使用二次外延生长工艺形成栅帽层，从而不仅可以避免因对势垒层进行界面处理，导致势垒层与栅帽层之间残留大量杂质，影响半导体器件性能的问题，而且还可以提高栅帽层的质量。
在本申请实施例中，栅帽层的第二部分中的氢杂质均匀分布，即第二部分中的氢杂质是在形成栅帽层的过程中，掺杂进入栅帽层的形成材料中的。这样，与通过先形成整层的栅帽层，再对栅帽层中不与栅极接触的部分进行氢等离子注入的方法制备得到的增强型HEMT相比，本申请实施例所提供的半导体器件无需氢等离子体注入，势垒层不容易被损伤，二维电子气的迁移率也不容易被影响，保证了半导体器件的动态特性。
在一些实施例中，所述P型杂质包括II族元素。
在一些实施例中，所述P型杂质包括镁。
在一些实施例中，所述P型杂质的浓度范围为1×10 18cm -3～1×10 21cm -3。这样，一方面能够在栅极电压为零时，较好的耗尽栅极下方的沟道层中的二维电子气，使半导体器件处于常关状态，实现增强型HEMT。另一方面，使得P型杂质的含量不会过高，保证栅帽层的性能和质量，从而保证半导体器件的性能和质量。
在一些实施例中，所述半导体器件还包括成核层，成核层位于所述衬底与所述沟道层之间。本申请实施例通过设置成核层，能够缓解沟道层的热膨胀系数与衬底的热膨胀系数的差异，缓解沟道层的晶格系数与衬底的晶格系数的差异，使沟道层的晶格生长更加整齐。同时，成核层还可以缓解沟道层的应力，避免在衬底上直接形成沟道层时，沟道层应力较大，使得半导体器件断裂的情况发生。
在一些实施例中，所述成核层的材料包括氮化铝。
在一些实施例中，所述半导体器件还包括缓冲层，缓冲层位于所述成核层与所述 沟道层之间。通过在半导体器件中设置缓冲层，可以提高半导体器件的耐压能力，在半导体器件的工作电压较大的情况下，避免半导体器件被击穿，从而提高半导体器件的工作稳定性。
在一些实施例中，所述缓冲层为超晶格结构。本申请实施例所提供的缓冲层采用超晶格结构，一方面能够利用两种材料不同的膜层交替，提高缓冲层的耐击穿能力，从而进一步提高半导体器件的耐高压能力。另一方面，采用超晶格结构还可调控缓冲层的应力，从而在缓冲层远离衬底的一侧形成沟道层时，使得缓冲层的应力变化较小，提高半导体器件的结构稳定性。
在一些实施例中，所述缓冲层的材料包括氮化铝和氮化铝镓。由于氮化铝和氮化铝镓的耐压能力相比氮化镓的耐压能力更好，因此选用氮化铝和氮化铝镓材料制备缓冲层还可以进一步提高缓冲层的耐压能力。
在一些实施例中，所述半导体器件还包括插入层，插入层位于所述沟道层与所述势垒层之间。这样，沟道层、插入层和势垒层的极化效应可以产生更高的二维电子气浓度，并且通过插入层能够减少合金无序散射从而提高二维电子气迁移率，有利于改善半导体器件的输出特性。
在一些实施例中，所述插入层的材料包括氮化铝。
在一些实施例中，所述栅帽层的材料包括氮化镓。
在一些实施例中，所述沟道层中存在二维电子气，在所述栅极上的电压为零时，所述沟道层位于所述第一部分下方的区域中，所述二维电子气被耗尽。
第二方面，本申请提供一种半导体器件的制备方法，该制备方法包括：在衬底上形成沟道层；在所述沟道层远离所述衬底的一侧形成势垒层；在所述势垒层远离所述衬底的一侧形成栅帽层；所述栅帽层包括P型杂质与氢杂质结合形成的复合体，所述栅帽层包括第一部分和第二部分，所述第二部分至少位于所述第一部分的两侧；使位于所述第一部分内的复合体中的P型杂质与氢杂质之间的化学键断裂，以使所述第一部分内的所述复合体的浓度小于所述第二部分内的所述复合体的浓度；在所述第一部分上形成栅极，在所述第二部分上形成源极和漏极。
在一些实施例中，所述使位于所述第一部分内的复合体中的P型杂质与氢杂质之间的化学键断裂，包括：在所述栅帽层远离所述衬底的一侧形成掩膜层，所述掩膜层具有开口，所述开口暴露出所述第一部分。基于所述掩膜层对所述栅帽层进行激光退火，使所述第一部分内的复合体中P型杂质与氢杂质之间的化学键断裂。
在一些实施例中，所述在所述势垒层远离所述衬底的一侧形成栅帽层，包括：基于包括氨气、氢气、三甲基镓和二茂镁的反应气体，或包括氨气、氮气、三甲基镓和二茂镁的反应气体，在所述势垒层远离所述衬底的一侧形成栅帽层。
在一些实施例中，在衬底上形成沟道层之前，所述制备方法还包括：在所述衬底上形成成核层。
在一些实施例中，在所述衬底上形成成核层之后，在所述衬底上形成沟道层之前，所述制备方法还包括：在所述成核层远离所述衬底的一侧形成缓冲层，所述缓冲层为超晶格结构。
在一些实施例中，所述在衬底上形成沟道层之后，所述在所述沟道层远离所述衬 底的一侧形成势垒层之前，所述制备方法还包括：在所述沟道层远离所述衬底的一侧形成插入层。
第三方面，本申请提供一种电子设备，包括电路板和如上述任一实施例所述的半导体器件；所述半导体器件与所述电路板电连接。
其中，第二方面至第三方面中任一种设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种半导体器件的制备方法的流程图；
图2为图1所提供的制备方法所对应的半导体器件的制备状态图；
图3为本申请实施例提供的另一种半导体器件的制备方法的流程图；
图4～图6为图3所提供的制备方法所对应的半导体器件的制备状态图；
图7为本申请实施例提供的一种形成栅帽层的流程图；
图8和图9为图3所提供的制备方法所对应的半导体器件的制备状态图；
图10为本申请实施例提供的再一种半导体器件的制备方法的流程图；
图11和图12为图10所提供的制备方法所对应的半导体器件的制备状态图；
图13为本申请实施例提供的又一种半导体器件的制备方法的流程图；
图14为图13所提供的制备方法所对应的半导体器件的制备状态图；
图15为本申请实施例提供的又一种半导体器件的制备方法的流程图；
图16为图15所提供的制备方法所对应的半导体器件的制备状态图；
图17为本申请实施例提供的又一种半导体器件的制备方法的流程图；
图18为图17所提供的制备方法所对应的半导体器件的制备状态图；
图19为本申请实施例提供的一种半导体器件的结构图；
图20为本申请实施例提供的另一种半导体器件的结构图；
图21为本申请实施例提供的再一种半导体器件的结构图；
图22为本申请实施例提供的一种电子设备的结构图；
图23为本申请实施例提供的一种电源开关的工作流程框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B。
本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。
在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可 以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
同时，在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
如图1所示，为了避免因对p-GaN栅帽层进行刻蚀，导致的刻蚀不均匀和界面损伤的问题，在一些实施例中，提供了一种半导体器件的制备方法。参阅图2，该制备方法包括：
S101、在沟道层101上形成势垒层102。
S102、在势垒层102远离沟道层101的一侧形成硬掩膜层103，硬掩膜层103具有预设开口104，预设开口104暴露出势垒层102远离沟道层101的部分表面。
S103、在预设开口104中进行p-GaN材料的选区外延生长，形成p-GaN栅帽层105。
S104、在p-GaN栅帽层105远离沟道层101的一侧形成栅极106。示例性的，在形成栅极106的同时，还可以在势垒层102远离沟道层101的一侧形成源极107和漏极108。
上述实施例中，利用镓(Ga)原子在势垒层102表面和硬掩膜层103表面的粘附系数的差异，在势垒层102上选区生长p-GaN栅帽层105，从而无需对p-GaN栅帽层105进行刻蚀，避免了因对p-GaN栅帽层105进行刻蚀，导致的刻蚀不均匀或界面损伤的问题。
然而，由于在实际操作中需要先在势垒层102上先形成整层的硬掩膜层103，再利用光刻胶对硬掩膜层103进行图案化处理，才能够得到具有预设开口104的硬掩膜层103，因此在预设开口104中进行p-GaN材料的选取外延生长之前，需要对预设开口104所暴露出的势垒层102的表面进行处理(例如，刻蚀、清洗等)。这样，在势垒层102与p-GaN栅帽层105接触的界面上会残留大量的硅(Si)、氧(O)等杂质。这些杂质易与势垒层102产生反应形成化合物，从而影响栅极的控制能力，进而影响半导体器件的性能。同时，这些杂质的存在还容易导致半导体器件的漏电。
另外，由于硬掩膜层103需要在生长腔室外形成，因此，在沟道层101上形成势垒层102后，需要将未制备完成的半导体器件由生长腔室内取出，在形成硬掩膜层103形成后，将形成硬掩膜层103的半导体器件再次放置到生长腔室内，进行p-GaN材料的选区外延生长。也即，上述实施例中的p-GaN栅帽层105需要采用二次外延生长工艺形成。而在二次外延生长工艺的初期，外延形成的材料质量较差，因此容易导致半导体器件的质量也较差。
基于上述问题，本申请实施例提供了一种半导体器件100的制备方法，如图3所示，该制备方法包括：
S100、如图4所示，在衬底10上形成沟道层20。
在一些示例中，衬底10的材料可以包括硅、碳化硅(SiC)或者蓝宝石等。当衬底10的材料包括硅时，衬底10可以为绝缘体上硅(silicon on insulator，SOI)衬底。 或者，衬底10可以为硅晶片。
在一些实施例中，沟道层20的材料可以包括氮化镓(GaN)。
在一些实施例中，可以利用包括氨气(NH 3)、氢气(H 2)和三甲基镓(trimethyl gallium)的反应气体，在衬底10的一侧形成沟道层20。其中，氢气可以作为载气将反应气体输送至生长腔室内。氨气可以作为氮源，三甲基镓用于提供III族元素。示例性的，可以利用氮气(N 2)替换氢气，将反应气体输送至生长腔室内。
可以理解的是，在本申请实施例所提供的制备方法中，制备沟道层20反应气体并不局限与此。
在一些实施例中，在衬底10的一侧形成沟道层20时，反应温度可以为1050摄氏度(℃)。本申请实施例中形成沟道层20的反应温度也并不限于1050摄氏度，反应温度还可以是其他有利于沟道层20形成的值。
在一些示例中，沟道层20的厚度可以为500nm。可以理解的是，本申请中沟道层20的厚度并不仅限于此，可以根据半导体器件100的结构和性能需求对沟道层20的厚度进行调整。
S200、如图5所示，在沟道层20远离衬底10的一侧形成势垒层30。
势垒层30可以用于配合沟道层20，以在沟道层20与势垒层30之间通过极化作用产生二维电子气(2DEG)，二维电子气可以在电场的作用下，高效的传导电子。
其中，势垒层30的材料可以包括氮化铝镓(AlGaN)。
在一些实施例中，可以利用包括氨气、氢气(或氮气)、三甲基铝(trimethyl aluminium)和三甲基镓的反应气体，在沟道层20远离衬底10的一侧形成势垒层30。其中，氢气或氮气可以作为载气将反应气体输送至生长腔室内。三甲基铝与三甲基镓用于提供III族元素，氮气可以作为氮源。在本申请实施例所提供的制备方法中，制备势垒层30的反应气体并不局限与此。
在一些实施例中，在沟道层20远离衬底10的一侧形成势垒层30时，反应温度可以为1050摄氏度。本申请实施例中形成势垒层30的反应温度也并不限于1050摄氏度，反应温度还可以是其他有利于势垒层30形成的值。
在一些实施例中，形成的势垒层30的厚度可以为12纳米(nm)。可以理解的是，本申请中势垒层30的厚度并不仅限于此，本领域技术人员可以根据半导体器件100的结构和性能需求对势垒层30的厚度进行调整。
S300、如图6所示，在势垒层30远离衬底10的一侧形成栅帽层40。栅帽层40包括P型杂质与氢杂质结合形成的复合体，栅帽层40包括第一部分41和第二部分42，第二部分42至少位于第一部分41的两侧。其中，图6示出了栅帽层40的微观结构，栅帽层40中由P型杂质与氢杂质结合形成的复合体以黑色圆圈示出。
示例性的，“第二部分42至少位于第一部分41的两侧”，可以是第二部分42位于第一部分的两侧，还可以是第二部分42围绕第一部分41的周侧设置。
在一些实施例中，栅帽层40的材料可包括氮化镓。
在一些实施例中，P型杂质可以包括II族元素。
示例性的，P型杂质可以包括IIA族元素，例如铍(Be)、镁(Mg)、钙(Ca)、锶(Sr)、钡(Ba)中的一种或者至少两种的组合。当P型杂质包括IIA族元素时，P 型杂质可以更加容易的与氢杂质结合，形成复合体。
当然，P型杂质也可以选择IIB族中的元素，例如锌(Zn)、汞(Hg)、镉(Cd)中的一种或者至少两种的组合。
由于在P型杂质中镁相比其他P型杂质的电离能小，容易掺杂，并且也容易与氢结合形成复合体，因此在一些示例中，P型杂质可以包括镁，此时，P型杂质与氢杂质形成的复合体可以包括Mg-H复合体。
在一些示例中，可以通过在形成栅帽层40的材料中掺杂P型杂质，从而在势垒层30远离衬底10的一侧形成栅帽层40。
基于此，如图7所示，步骤S300、在势垒层30远离衬底10的一侧形成栅帽层40，包括：
S310、基于包括氨气、氢气、三甲基镓和二茂镁(C 10H 10Mg)的反应气体，或包括氨气、氮气、三甲基镓和二茂镁的反应气体，在势垒层30远离衬底10的一侧形成栅帽层40。
其中，二茂镁可以为栅帽层40提供P型杂质。氢气或氮气可以作为载气，将气体传输至生长腔室内。在氨气、氢气、三甲基镓和二茂镁中均包含氢元素，因此形成的栅帽层40中可以含有氢杂质。氢杂质可以在形成栅帽层40的过程中，与P型杂质形成复合体。
可以理解的是，本申请所提供的反应气体并不仅限于此，P型杂质的来源也并不仅限于二茂镁，可根据半导体器件100的设计需求进行选择。
在一些实施例中，P型杂质的浓度范围可以为1×10 18cm -3～1×10 21cm -3。例如，P型杂质的浓度可以为1×10 18cm -3、5×10 18cm -3、1×10 19cm -3、4×10 19cm -3、6×10 19cm -3、1×10 20cm -3、5×10 20cm -3、1×10 21cm -3。
可以理解的是，在栅帽层40中掺杂的P型杂质并不一定能够全部与H杂质结合形成复合体，因此在栅帽层40中还可能存在游离的P型杂质。本申请上述实施例中所描述的“P型杂质的浓度”中的P型杂质，不仅包括用于形成复合体的P型杂质，还包括游离的P型杂质。
这样，一方面P型杂质的浓度不会过高，从而不会对栅帽层40的性能造成影响，另一方面，P型杂质的浓度也不会过低，从而在栅极上施加的电压为零时，P型杂质足够将沟道层中的电子(二维电子气)耗尽，从而使得半导体器件处于常关状态。
同样的，在栅帽层40中掺杂的氢杂质也并不一定能够全部与P型杂质结合形成复合体，因此在栅帽层40中还可能存在游离的氢杂质。
由于本申请上述实施例中在形成栅帽层40的反应物中引入P型杂质和氢杂质，因此在形成的栅帽层40后，游离的P型杂质和游离的氢杂质，以及P型杂质与氢杂质结合形成的复合体可以在栅帽层40中均匀分布。
在一些实施例中，在势垒层30远离衬底10的一侧形成栅帽层40时，反应温度可以为950摄氏度。本申请实施例中形成栅帽层40的反应温度也并不限于950摄氏度，反应温度还可以是其他有利于栅帽层40形成的值。
在一些示例中，栅帽层40的厚度可以为80nm。可以理解的是，本申请中栅帽层40的厚度并不仅限于此，可以根据半导体器件100的结构和性能需求对栅帽层40的 厚度进行调整。
在一些实施例中，可以将衬底10放置在生长腔室内，采用金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)作为生长技术，在衬底10形成上述沟道层20、势垒层30和栅帽层40。
S400、如图8所示，使位于第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂，以使第一部分41内的复合体的浓度小于第二部分42内的复合体的浓度。
参阅图8，在第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂后，P型杂质还可以存在于第一部分41，而氢杂质可以以游离态的形式向空气中扩散。
“使位于第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂”，可以是使第一部分41内的所有的复合体中的P型杂质与氢杂质之间的化学键断裂，也可以是使第一部分41内的部分复合体中的P型杂质与氢杂质之间的化学键断裂，只要能够保证步骤S400后，第一部分41内的激活的P型杂质可以先将其下方的二维电子气耗尽即可。
S500、如图9所示，在第一部分41上形成栅极51，在第二部分42上形成源极52和漏极53。
示例性的，栅极51的材料可以包括金属，例如镍、金等。
示例性的，源极52和漏极53的材料可以包括金属，例如钛、铝、金等。
示例性的，可以利用器件加工工艺在第一部分41上制备栅极51、在第二部分42上制备源极52和漏极53。
其中，栅极51与第一部分41形成肖特基接触，源极52和漏极53与第二部分42形成欧姆接触。源极52和漏极53用于在电场的作用下使二维电子气在源极52和漏极53之间的沟道层20内流动。栅极51位于源极52与漏极53之间，用于允许或阻止二维电子气的通过。
本申请实施例中对栅极51、源极52和漏极53的厚度不做限制，只要能够满足半导体器件的性能要求即可。
本申请上述实施例中，先在势垒层30远离衬底10的一侧生长整层的栅帽层40，栅帽层40的第一部分41和第二部分42均具有P型杂质与氢杂质结合形成的复合体。再对栅帽层40的第一部分41进行处理，使第一部分41中的复合体中的P型杂质与氢杂质之间的化学键断裂。这样，栅帽层40中的第一部分41内的P型杂质被激活，第一部分41中的空穴浓度提升，从而使得第一部分41下方的二维电子气可以被耗尽，而第二部分42内的P型杂质依旧被氢杂质钝化，第二部分42下方的二维电子气被保留。在形成栅极51、源极52和漏极53后，当栅极51上施加的电压为零时，栅极51下方不存在二维电子气，半导体器件100关断，从而可以实现增强型HEMT。源极52和漏极53下方的第二部分42由于P型杂质以复合体形式的存在，保持高电阻，从而有利于改善半导体器件的电流崩塌和漏电。
在本申请上述实施例所提供的制备方法中，无需对栅帽层40进行刻蚀，从而可以避免因对栅帽层40进行刻蚀导致的刻蚀不均匀或界面损伤的问题，进而可以提高制备得到的半导体器件的良率、性能和可靠性。同时，由于无需对栅帽层40进行刻蚀，还可以使制备工艺更加简单，提高工艺效率，使制备工艺不依赖于昂贵复杂的刻蚀设备， 降低制备成本。
与利用二次外延生长工艺形成位于栅极下方栅帽层，实现增强型HEMT器件相比，一方面，本申请实施例无需对势垒层的界面进行处理，从而可以避免因硅、氧等杂质的存在导致的栅极控制能力减弱，半导体器件漏电等问题。另一方面，本申请实施例可以直接在势垒层30上生长栅帽层40，无需使用二次外延生长技术，外延生长材料质量可以较好，制备形成的半导体器件100的质量也可以更好。
值得一提的是，与形成整层栅帽层后，对栅帽层中未与栅极接触的部分进行氢等离子体注入，从而得到无需刻蚀的增强型HEMT的方法相比，本申请实施例所提供的制备方法，无需进行等离子体注入，从而可以避免等离子体注入工艺对势垒层造成的物理损伤，以及对二维电子气的迁移率的不良影响，保障半导体器件的动态特性。
下面结合图10～图12，对上述实施例中的步骤S400、使位于第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂，进一步说明。
如图10所示，步骤S400、使位于第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂，包括：
S410、如图11所示，在栅帽层40远离衬底10的一侧形成掩膜层11，掩膜层11具有开口111，开口111暴露出第一部分41。
示例性的，掩膜层11的材料可以包括氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮化钛(TiN)等。
示例性的，可以通过沉积法在栅帽层40远离衬底10的一侧形成掩膜层11，例如可以采用化学气相沉积工艺在栅帽层40远离衬底10的一侧形成掩膜层11。
在一些实施例中，在栅帽层40远离衬底10的一侧形成掩膜层11之前，可以先将形成有栅帽层40的半导体器件由生长腔室内取出，从而在生长腔室外制备掩膜层11。
在一些示例中，可以先在栅帽层40远离衬底10的一侧形成整层的掩膜层11，然后在掩膜层11远离衬底10的一侧形成光刻胶层，利用通过曝光显影等工艺图案化光刻胶层，最后利用图案化后的光刻胶层对掩膜层11进行刻蚀，形成开口111。
本申请实施例中对掩膜层11中的开口111的数量、形状和布置位置不做限制，可以根据半导体器件的需求进行设计。
S420、如图12所示，基于掩膜层11对栅帽层40进行激光退火，使第一部分41内的复合体中P型杂质与氢杂质之间的化学键断裂。
其中图12中向下的箭头表示激光。在基于掩膜层11对栅帽层40进行激光退火时，一部分激光照射至掩膜层11上，另一部分激光穿过掩膜层11的开口111照射至栅帽层40的第一部分41上。高能量激光使得第一部分41温度升高，从而使得第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂。
示例性的，在对栅帽层40进行激光退火后，可以将掩膜层11去除。
示例性的，可以采用波长为355纳米，频率为20千赫兹的激光，对栅帽层40进行激光退火。本申请实施例中所采用的激光波长、激光频率并不仅限于此，可以根据使P型杂质与氢杂质之间的化学键断裂所需要能量，对激光退火设备进行选择，从而调整激光的波长和频率。
示例性的，在基于掩膜层11对栅帽层40激光退火时，气氛可以为氮气气氛。
本申请上述实施例利用具有开口111的掩膜层11以及激光退火工艺，可以在使第一部分41内的复合体中的P型杂质与氢杂质之间的化学键断裂的同时，使第二部分42内的复合体中的P型杂质与氢杂质之间的化学键保留，从而使得在第一部分41下方的沟道层20中的二维电子气被耗尽的同时，第二部分42下方的沟道层20中的二维电子气被保留。这样，无需对栅帽层40进行刻蚀，即可以实现增强型HEMT。
同时，与传统的热退火工艺相比，激光退火工艺具有能量高，速度快，对材料损伤小和退火范围精准可控的特点，因此可以实现对栅帽层40的超快速退火，提升工艺效率，缩短工艺时间。
除上述实施例所提供的制备方法的步骤外，在一些实施例中，如图13所示，在步骤S100、在衬底10上形成沟道层20之前，该制备方法还可以包括：
S110、如图14所示，在衬底10上形成成核层60。
其中，成核层60可以用于缓解因衬底10的材料与沟道层20的材料的晶格系数失配和热膨胀系数失配，避免沟道层20直接形成在衬底10上时，沟道层20应力过大，导致沟道层20或其他膜层断裂的问题。
示例性的，成核层60的材料可以包括氮化铝。
在一些示例中，可以采用包括氨气、氢气和三甲基铝的反应气体，在衬底10的一侧形成成核层60。其中，氢气可以替换为氮气。
在一些示例中，在衬底10上形成成核层60时，反应温度可以是1100摄氏度。形成的成核层60的厚度可以为200纳米。
本申请实施例中形成成核层60的反应气体，反应温度，以及成核层60的厚度并不仅限于上述实施例，可以根据实际需要进行调整。
在一些实施例中，可以将衬底10放置在生长腔室内，采用金属有机化合物化学气相沉淀作为生长技术，在衬底10上形成成核层60。
在一些实施例中，如图15所示，在步骤S110、在衬底10上形成成核层60之后，在步骤S100在衬底10上形成沟道层20之前，所述制备方法还包括：
S120、如图16所示，在成核层60远离衬底10的一侧形成缓冲层70。缓冲层70可以为超晶格结构。
示例性的，缓冲层70的材料可以包括氮化铝(AlN)和氮化铝镓(AlGaN)。由于氮化铝和氮化铝镓的耐压能力相比氮化镓的耐压能力更好，因此选用氮化铝和氮化铝镓材料制备缓冲层70还可以进一步提高缓冲层70的耐压能力。
示例性的，缓冲层70中的超晶格对数可以为90对。例如，在缓冲层70的材料包括氮化铝和氮化铝镓时，缓冲层70可以包括交替堆叠的90层氮化铝层和90氮化铝镓层。其中，单层氮化铝层的厚度可以为5纳米，单层氮化铝镓的厚度可以为25纳米。
可以理解的是，本申请实施例所提供的缓冲层70的材料，以及超晶格结构并不仅限于此，可以根据半导体器件100的性能需求进行设计。
通过形成缓冲层70，可以提高半导体器件100的耐压能力，在半导体器件100的工作电压较大(例如，650伏)的情况下，避免半导体器件被击穿，从而提高半导体器件100的工作稳定性。
本申请实施例所提供的缓冲层70采用超晶格结构，一方面能够利用两种材料不同 的膜层交替，提高缓冲层70的耐击穿能力，从而进一步提高半导体器件100的耐高压能力。另一方面，采用超晶格结构还可调控缓冲层70的应力，从而在缓冲层70远离衬底10的一侧形成沟道层20时，使得缓冲层70的应力变化较小，提高半导体器件100的结构稳定性。
在一些实施例中，可以将衬底10放置在生长腔室内，采用金属有机化合物化学气相沉淀作为生长技术，在成核层60远离衬底10的一侧形成缓冲层70。
当缓冲层70的材料包括氮化铝和氮化铝镓时，可以采用包括氨气、氢气(或氮气)、三甲基铝和三甲基镓的反应气体，形成缓冲层70。其中，氢气(或氮气)可以作为载气，将反应气体输送至生长腔室内。
在一些示例中，在衬底10上形成缓冲层70时，反应温度可以为1000摄氏度。本申请实施例中形成缓冲层70的反应温度也并不限于1000摄氏度，反应温度还可以是其他有利于缓冲层70形成的值。
当成核层60的材料为氮化铝，缓冲层70最靠近衬底10的膜层为氮化铝层时，本申请实施例中，在形成缓冲层70之前形成成核层60还能够改善缓冲层70的形成质量，从而提高半导体器件的质量与良率。
在一些实施例中，如图17所示，在步骤S100、在衬底10上形成沟道层20之后，在步骤S200、在沟道层20远离衬底10的一侧形成势垒层30之前，制备方法还可以包括：
S130、参阅图18和图19，在沟道层20远离衬底10的一侧形成插入层80。沟道层20、插入层80和势垒层30的极化效应可以产生更高的二维电子气浓度，并且通过插入层80能够减少合金无序散射从而提高二维电子气迁移率，有利于改善半导体器件100的输出特性。
示例性的，插入层80的材料可以包括氮化铝，插入层80的厚度可以为0.4纳米。可以理解的是，本申请中插入层80的材料和厚度并不仅限于此，插入层80的材料和厚度可以根据半导体器件的性能需求进行设计。
在一些实施例中，可以包括氨气、氢气和三甲基铝的反应气体，在沟道层20远离衬底10的一侧形成插入层80。其中，氢气可以替换为氮气。
在一些实施例中，在沟道层20远离衬底10的一侧形成插入层80时，反应温度可以为1050摄氏度。
在一些实施例中，可以将衬底10放置在生长腔室内，采用金属有机化合物化学气相沉淀作为生长技术，在衬底10上形成插入层80。
为了更好的在衬底10生长其他膜层(例如，沟道层20、成核层60或缓冲层70等)，在形成衬底10上生长或形成膜层之前，可以对衬底10进行高温表面清洗，以去除衬底10上的氧化层。
示例性的，可以在气氛为氢气，温度为1100摄氏度的条件下，对衬底10进行高温表面清洗。其中氢气具有还原性，在高温条件可以将衬底10表面的氧化层还原。
示例性的，可以在生长腔室内对衬底10进行高温表面清洗，这样可以在对衬底10进行清洗后，直接进行膜层的生长，避免在移动衬底的过程中，衬底表面再次氧化的情况发生。
示例性的，对衬底10进行高温表面清洗的时间可以为5分钟。
可以理解的是，本申请实施例中对衬底10进行高温表面清洗的温度和时间均不做限制，可以根据处理情况进行适应性调整。
如图9所示，本申请一些实施例中提供一种半导体器件100，该半导体器件100可以由上述任一实施例所提供的半导体器件100的制备方法制备形成。
该半导体器件100包括衬底10、沟道层20、势垒层30、栅帽层40、栅极51、源极52和漏极53。
其中，衬底10的材料可以包括硅、碳化硅或者蓝宝石等。当衬底10的材料包括硅时，衬底10可以为绝缘体上硅衬底。或者，衬底10可以为硅晶片。
沟道层20位于衬底10的一侧。示例性的，沟道层20的材料可以包括氮化镓。
势垒层30位于沟道层20远离衬底10的一侧。示例性的，势垒层30的材料可以包括氮化铝镓。
沟道层20与势垒层30形成异质结，通过极化作用，在沟道层20与势垒层接触的区域内形成二维电子气。二维电子气可以在电场的作用下，高效的传输电子。
栅帽层40位于势垒层30远离衬底10的一侧。栅帽层40包括游离的P型杂质，及由P型杂质和氢杂质结合而成的复合体。栅帽层40包括第一部分41和第二部分42，第二部分42至少位于第一部分41的两侧。第一部分41中的复合体浓度小于第二部分42中的复合体浓度，且第二部分42中的氢杂质均匀分布。
“第二部分42至少位于第一部分41的两侧”，可以是第二部分42位于第一部分的两侧，还可以是第二部分42围绕第一部分41的周侧设置。
在一些实施例中，栅帽层40的材料可以包括氮化镓。
在一些实施例中，P型杂质可以包括II族元素。
其中，P型杂质可以包括IIA族元素，例如铍、镁、钙、锶、钡中的一种或者至少两种的组合。当P型杂质包括IIA族元素时，P型杂质可以更加容易的与氢杂质结合，形成复合体。
当然，P型杂质也可以选择IIB族中的元素，例如锌、汞、镉中的一种或者至少两种的组合。
由于在P型杂质中镁相比其他P型杂质的电离能小，容易掺杂，并且也很容易与氢物质结合形成复合体，因此在一些示例中，P型杂质可以包括镁，此时，P型杂质与氢杂质形成的复合体可以包括Mg-H复合体。
栅极51、源极52和漏极53，位于栅帽层40远离衬底10的一侧。栅极51位于第一部分41上，源极52和漏极53位于第二部分42上。
示例性的，栅极51的材料可以包括金属，例如镍、金等。源极52和漏极53的材料可以包括金属，例如钛、铝、金等。
其中，栅极51与第一部分41之间形成肖特基接触，源极52和漏极53与第二部分42之间形成欧姆接触。源极52和漏极53用于在电场的作用下使二维电子气在源极52和漏极53之间的沟道层20内流动。栅极51位于源极52与漏极53之间，用于允许或阻止二维电子气的通过。
在本申请所提供的半导体器件100中，栅帽层40位于势垒层30远离沟道层20 的一侧，栅帽层40包括游离的P型杂质以及有P型杂质与氢杂质结合形成的复合体，栅帽层40的第一部分41中复合体的浓度小于栅帽层40的第二部分42中的复合体浓度，也即第一部分41中的游离的P型杂质多于第二部分42中的游离的P型杂质，第一部分41中的空穴浓度大于第二部分42中的空穴浓度。第一部分41与栅极51接触，第二部分42与源极52和漏极53接触。这样，在栅极51上的电压为零时，沟道层20中位于栅极51(或第一部分41)下方的区域中的二维电子气可以被第一部分41中的空穴耗尽，源极52和漏极53下方的二维电子气则可以被保留，从而实现增强型HEMT。源极52和漏极53下方的第二部分42由于P型杂质以复合体形式的存在，可以保持高电阻，从而有利于改善半导体器件100的电流崩塌和漏电。
且由于栅极51、源极52和漏极53均设置在栅帽层40上，栅帽层40为覆盖势垒层30的整层结构，因此制备本申请实施例所提供的半导体器件100时无需对栅帽层40进行刻蚀。这样，可以在实现增强型HEMT的同时，避免因刻蚀栅帽层导致的刻蚀不均匀或界面损伤的问题，从而提高半导体器件100的良率、性能和可靠性。
同时，由于栅帽层为覆盖势垒层30的整层结构，因此制备本申请实施例所提供的半导体器件100时，也无需使用二次外延生长工艺形成栅帽层，从而不仅可以避免因对势垒层进行界面处理，导致势垒层与栅帽层之间残留大量杂质，影响半导体器件性能的问题出现，而且还可以提高栅帽层40的质量。
在本申请实施例中，栅帽层40的第二部分42中的氢杂质均匀分布，即第二部分42中的氢杂质是在形成栅帽层40的过程中，掺杂进入栅帽层的形成材料中的。这样，与通过先形成整层的栅帽层，再对栅帽层中不与栅极接触的部分进行氢等离子注入的方法制备得到的增强型HEMT相比，本申请实施例所提供的半导体器件无需氢等离子体注入，势垒层30不容易被损伤，二维电子气的迁移率也不容易被影响，保证了半导体器件的动态特性。
在一些实施例中，P型杂质的浓度范围为1×10 18cm -3～1×10 21cm -3。
这样，一方面能够在栅极51电压为零时，较好的耗尽栅极51下方的沟道层20中的二维电子气，使半导体器件100处于常关状态，实现增强型HEMT。另一方面，使得P型杂质的含量不会过高，保证栅帽层40的性能和质量，从而保证半导体器件的性能和质量。
可以理解的是，此处所描述的“P型杂质”不仅包括游离的P型杂质，还包括位于复合体中的P型杂质。
同理上述实施例中所描述的“氢杂质”也不仅仅包括游离的氢杂质，还包括位于复合体中的氢杂质。
考虑到直接在衬底上形成沟道层时，容易因沟道层产生的应力过高而导致半导体器件的破裂，因此在一些实施例中，如图20所示，半导体器件100还可以包括成核层60，成核层60位于衬底10与沟道层20之间。
本申请实施例通过设置成核层60，能够缓解沟道层20的热膨胀系数与衬底10的热膨胀系数的差异，缓解沟道层20的晶格系数与衬底的晶格系数的差异，使沟道层20的晶格生长更加整齐。同时，成核层60还可以缓解沟道层20的应力，避免在衬底上直接形成沟道层时，沟道层应力较大，使得半导体器件断裂的情况发生。
在一些示例中，成核层60的材料可以包括氮化铝。成核层60的厚度可以为200纳米。可以理解的是，成核层60的材料与厚度并不仅限于此，可以根据实际需求进行设计。
在一些实施例中，如图21所示，半导体器件100还可以包括缓冲层70，缓冲层70位于成核层60与沟道层20之间。
通过在半导体器件100中设置缓冲层70，可以提高半导体器件100的耐压能力，从而在半导体器件100的工作电压较大(例如，650伏)的情况下，避免半导体器件被击穿，从而提高半导体器件100的工作稳定性。
在一些实施例中，缓冲层70可以为超晶格结构。
超晶格结构为利用两种不同材料以几纳米到几十纳米的薄层交替生长并具有周期性的多层膜。本申请实施例所提供的缓冲层70采用超晶格结构，一方面能够利用两种材料不同的膜层交替，提高缓冲层70的耐击穿能力，从而进一步提高半导体器件100的耐高压能力。另一方面，采用超晶格结构还可调控缓冲层70的应力，从而在缓冲层70远离衬底10的一侧形成沟道层20时，使得缓冲层70的应力变化较小，提高半导体器件100的结构稳定性。
在一些示例中，缓冲层70的超晶格对数为90对。
在一些实施例中，缓冲层70的材料可以包括氮化铝和氮化铝镓。由于氮化铝和氮化铝镓的耐压能力相比氮化镓的耐压能力更好，因此选用氮化铝和氮化铝镓材料制备缓冲层70还可以进一步提高缓冲层70的耐压能力。
缓冲层70的材料包括氮化铝和氮化铝镓，即超晶格结构包括交替设置氮化铝层和氮化铝镓层。示例性的，氮化铝层的厚度可以为5纳米，氮化铝镓层的厚度可以为25纳米。
可以理解，上述实施例所提供的超晶格对数、超晶格结构中的膜层材料、厚度仅为一种示例性的说明，具体数值和材料可以根据半导体器件的性能需求进行调整。
在一些实施例中，如图19所示，半导体器件100还可以包括插入层80，插入层80位于沟道层20与势垒层30之间。
这样，沟道层20、插入层80和势垒层30的极化效应可以产生更高的二维电子气浓度，并且通过插入层80能够减少合金无序散射从而提高二维电子气迁移率，有利于改善半导体器件的输出特性。
在一些示例中，插入层80的材料包括氮化铝。插入层80的厚度可以为0.4纳米。可以理解的是，插入层80的材料与厚度并不仅限于此，可以根据实际需求进行设计。
如图22所示，本申请实施例提供一种电子设备1000，该电子设备1000例如可以为充电器、充电家用小型电器(例如豆浆机、扫地机器人)、手机、电脑、电动汽车和数据中心等器件。本申请实施例对电子设备的具体形式不作特殊限制。
如图22所示，电子设备1000中还可以包括电路板200(例如，印刷电路板(printed circuit board，PCB))，上述半导体器件100可以与电路板200电连接。
当电子设备1000为充电器时，半导体器件100可以应用于充电器的电源开关300中。如图23所示，电源开关300还可以包括输入滤波器301、整流电路302、开关功率晶体管303、变压器304、输出滤波器305、脉宽调制电路306和开关驱动器307。 半导体器件100作为开关功率晶体管303。
其中，输入滤波器301的输出端与整流电路302的输入端连接，整流电路302的输出端与开关功率晶体管303的输入端相连，开关功率晶体管303的输出端与变压器304的输入端连接，变压器304的输出端与输出滤波器305的输入端相连，输出滤波器305的输出端与脉宽调制电路306的输入端相连，脉宽调制电路306的输出端与开关驱动器307的输入端相连，开关驱动器307的输出端与开关功率晶体管303的控制端相连。
图23示出了电源开关300的工作流程框图，在电源开关300中，输入滤波器301和整流电路302将输入电源转变为直流电(例如，将交流电变为直流电，或将直流电转变为直流电)，开关功率晶体管303进行高速的导通和截止，将经输入滤波器301和整流电路302输出的直流电，转变为高频率的交流电，然后提供给变压器304进行变压，变压后的电源由输出滤波器305输出，从而产生所需要的一组或多组电压。输出电源经脉宽调制电路306和开关驱动器307，还可以反馈控制开关功率晶体管303，从而进一步改善电源开关300的输出电压。
半导体器件100还可以通过电路板200与其余电路相连接，例如半导体器件100可以通过电路板200与输入滤波器301、整流电路302、变压器304、输出滤波器305、脉宽调制电路306和开关驱动器307电连接。
本申请实施例中所提供的电子设备1000能够的达到的有益效果与本申请上述实施例所提供的半导体器件100、半导体器件100的制备方法所能够达到的有益效果相同。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    沟道层，位于所述衬底的一侧；
    势垒层，位于所述沟道层远离所述衬底的一侧；
    栅帽层，位于所述势垒层远离所述衬底的一侧；所述栅帽层包括游离的P型杂质，及由P型杂质和氢杂质结合而成的复合体；所述栅帽层包括第一部分和第二部分，所述第二部分至少位于所述第一部分的两侧；所述第一部分中的复合体浓度小于所述第二部分中的复合体浓度，且所述第二部分中的氢杂质均匀分布；
    栅极、源极和漏极，位于所述栅帽层远离所述衬底的一侧；所述栅极位于所述第一部分上，所述源极和所述漏极位于所述第二部分上。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述P型杂质包括II族元素。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述P型杂质包括镁。
  4. 根据权利要求1～3中任一项所述的半导体器件，其特征在于，所述P型杂质的浓度范围为1×10 18cm -3～1×10 21cm -3。
  5. 根据权利要求1～4中任一项所述的半导体器件，其特征在于，还包括：
    成核层，位于所述衬底与所述沟道层之间。
  6. 根据权利要求5所述的半导体器件，其特征在于，所述成核层的材料包括氮化铝。
  7. 根据权利要求5或6所述的半导体器件，其特征在于，还包括：
    缓冲层，位于所述成核层与所述沟道层之间。
  8. 根据权利要求7所述的半导体器件，其特征在于，所述缓冲层为超晶格结构。
  9. 根据权利要求7或8所述的半导体器件，其特征在于，所述缓冲层的材料包括氮化铝和氮化铝镓。
  10. 根据权利要求1～9中任一项所述的半导体器件，其特征在于，还包括：
    插入层，位于所述沟道层与所述势垒层之间。
  11. 根据权利要求10所述的半导体器件，其特征在于，所述插入层的材料包括氮化铝。
  12. 根据权利要求1～11中任一项所述的半导体器件，其特征在于，所述栅帽层的材料包括氮化镓。
  13. 根据权利要求1～12中任一项所述的半导体器件，其特征在于，所述沟道层中存在二维电子气，在所述栅极上的电压为零时，所述沟道层位于所述第一部分下方的区域中，所述二维电子气被耗尽。
  14. 一种半导体器件的制备方法，其特征在于，包括：
    在衬底上形成沟道层；
    在所述沟道层远离所述衬底的一侧形成势垒层；
    在所述势垒层远离所述衬底的一侧形成栅帽层；所述栅帽层包括P型杂质与氢杂质结合形成的复合体，所述栅帽层包括第一部分和第二部分，所述第二部分至少位于所述第一部分的两侧；
    使位于所述第一部分内的复合体中的P型杂质与氢杂质之间的化学键断裂，以使所述第一部分内的所述复合体的浓度小于所述第二部分内的所述复合体的浓度；
    在所述第一部分上形成栅极，在所述第二部分上形成源极和漏极。
  15. 根据权利要求14所述的制备方法，其特征在于，所述使位于所述第一部分内的复合体中的P型杂质与氢杂质之间的化学键断裂，包括：
    在所述栅帽层远离所述衬底的一侧形成掩膜层，所述掩膜层具有开口，所述开口暴露出所述第一部分；
    基于所述掩膜层对所述栅帽层进行激光退火，使所述第一部分内的复合体中P型杂质与氢杂质之间的化学键断裂。
  16. 根据权利要求14或15所述的制备方法，其特征在于，所述在所述势垒层远离所述衬底的一侧形成栅帽层，包括：
    基于包括氨气、氢气、三甲基镓和二茂镁的反应气体，或包括氨气、氮气、三甲基镓和二茂镁的反应气体，在所述势垒层远离所述衬底的一侧形成栅帽层。
  17. 根据权利要求14～16中任一项所述的制备方法，其特征在于，在衬底上形成沟道层之前，所述制备方法还包括：
    在所述衬底上形成成核层。
  18. 根据权利要求17所述的制备方法，其特征在于，在所述衬底上形成成核层之后，在所述衬底上形成沟道层之前，所述制备方法还包括：
    在所述成核层远离所述衬底的一侧形成缓冲层，所述缓冲层为超晶格结构。
  19. 根据权利要求14～18中任一项所述的制备方法，其特征在于，所述在衬底上形成沟道层之后，所述在所述沟道层远离所述衬底的一侧形成势垒层之前，所述制备方法还包括：
    在所述沟道层远离所述衬底的一侧形成插入层。
  20. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1～13中任一项所述的半导体器件；所述半导体器件与所述电路板电连接。
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