WO2024057695A1 - 過電流保護回路、半導体装置、負荷駆動装置、及び車両 - Google Patents

過電流保護回路、半導体装置、負荷駆動装置、及び車両 Download PDF

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Publication number
WO2024057695A1
WO2024057695A1 PCT/JP2023/025704 JP2023025704W WO2024057695A1 WO 2024057695 A1 WO2024057695 A1 WO 2024057695A1 JP 2023025704 W JP2023025704 W JP 2023025704W WO 2024057695 A1 WO2024057695 A1 WO 2024057695A1
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WIPO (PCT)
Prior art keywords
transistor
current
output
overcurrent protection
field effect
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Ceased
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PCT/JP2023/025704
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English (en)
French (fr)
Japanese (ja)
Inventor
克明 山田
誠 佐田
俊太郎 高橋
直樹 ▲高▼橋
徹 宅間
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024546729A priority Critical patent/JPWO2024057695A1/ja
Publication of WO2024057695A1 publication Critical patent/WO2024057695A1/ja
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

Definitions

  • the invention disclosed herein relates to an overcurrent protection circuit, a semiconductor device, a load driving device, and a vehicle.
  • Patent Document 2 As a related technology of an overcurrent protection circuit incorporated in a semiconductor device, for example, Patent Document 2 can be cited.
  • an overcurrent protection circuit built into a semiconductor device, it tolerates the rush current that flows when a capacitive load such as a bulb lamp is driven by a semiconductor device such as an in-vehicle IPD, but also prevents rush current that exceeds the allowable range in the event of a load short circuit.
  • an overcurrent protection circuit may be used to limit the current to a low value lower than the rush current in order to suppress heat generation in the semiconductor device in the event of a load short circuit.
  • An overcurrent protection circuit that tolerates the above-mentioned rush current, but limits it to a low current lower than the rush current after a rush current exceeding the allowable range flows due to a load short circuit, etc., has a configuration that can suppress increases in circuit scale. It is hoped that
  • the overcurrent protection circuit disclosed herein includes a first transistor and a second transistor configured to form an amplifier input stage that receives an input of a detection signal corresponding to a current to be monitored; a third transistor configured to form an amplifier output stage that inputs the current output signal as negative feedback to the amplifier input stage while generating a current output signal according to the difference between the current output signal and the reference signal; and a fourth transistor configured to output a comparison result between the signal and the reference signal.
  • the value of the reference signal is configured to be switched based on the comparison result.
  • the overcurrent protection circuit is configured to limit the monitored current based on the current output signal output from the third transistor.
  • the semiconductor device disclosed in this specification includes an output transistor and an overcurrent protection circuit configured as described above configured to set the output current flowing through the output transistor as the current to be monitored.
  • the load driving device disclosed herein includes a semiconductor device having the above configuration and a capacitive load connected in series to the output transistor.
  • the vehicle disclosed herein includes the load drive device configured as described above.
  • FIG. 1 is a diagram showing an example of the configuration of a load driving device including a semiconductor device.
  • FIG. 2 is a state transition diagram of the semiconductor device.
  • FIG. 3 is a diagram showing the configuration of a load driving device according to a comparative example.
  • FIG. 4 is a timing chart showing an example of the waveforms of the detection signal and the reference signal.
  • FIG. 5 is a diagram showing the state of the overcurrent protection circuit at the first timing.
  • FIG. 6 is a diagram showing the state of the overcurrent protection circuit at the second timing.
  • FIG. 7 is a diagram showing the state of the overcurrent protection circuit at the third timing.
  • FIG. 8 is a diagram showing the state of the overcurrent protection circuit at the fourth timing.
  • FIG. 9 is a diagram showing the state of the overcurrent protection circuit at the fifth timing.
  • FIG. 10 is an external view of the vehicle.
  • a MOS field effect transistor is defined as having a gate structure that is a "layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," “an insulating layer,” and "P-type, A transistor consisting of at least three layers of "N-type or intrinsic semiconductor layers”. That is, the structure of the gate of the MOS field effect transistor is not limited to the three-layer structure of metal, oxide, and semiconductor.
  • FIG. 1 is a diagram showing an example of the configuration of a load driving device including a semiconductor device.
  • the load driving device 10A of this configuration example includes a semiconductor device 1A, a capacitive load LD1 such as a bulb lamp, and DC power supplies VS1 and VS2.
  • the semiconductor device 1A is a low-side switch IC (a type of IPD) that conducts/interrupts conduction between the capacitive load LD1 and the ground potential.
  • the semiconductor device 1A includes terminals T1 to T5 as means for establishing electrical connection with the outside of the device.
  • Terminal T1 is connected to the first end of capacitive load LD1.
  • the second end of capacitive load LD1 is connected to the positive electrode of DC power supply VS1.
  • Terminal T2 is connected to ground potential.
  • Terminal T3 receives input signal IN.
  • Terminal T4 receives the enable signal EN.
  • the enable signal EN When the enable signal EN is at a HIGH level, a control circuit 2 and a latch circuit 4, which will be described later, are in an on state (operating state).
  • a control circuit 2 and a latch circuit 4, which will be described later are in an off state (non-operating state).
  • the enable signal EN switches from a LOW level to a HIGH level, a control circuit 2 and a latch circuit 4, which will be described later, enter an initial state and start operating.
  • Terminal T5 is connected to the positive electrode of DC power supply VS2.
  • Each negative electrode of the DC power supplies VS1 and VS2 is connected to ground potential.
  • DC power supply VS1 outputs voltage VCC.
  • DC power supply VS2 outputs voltage VDD.
  • Voltage VCC and voltage VDD may have the same value or may have different values.
  • the semiconductor device 1A includes an overcurrent protection circuit OCP1, a control circuit 2, and a MOS field effect transistor M16 that is an output transistor.
  • the control circuit 2 is connected to terminals T3 and T4.
  • the control circuit 2 turns off the MOS field effect transistor M16 when the input signal IN is at a LOW level, and turns on the MOS field effect transistor M16 when the input signal IN is at a HIGH level.
  • the control circuit 2 has an overheat protection function, and turns off the MOS field effect transistor M16 when the temperature near the MOS field effect transistor M16 exceeds a predetermined value, regardless of the level of the input signal IN.
  • the MOS field effect transistor M16 is an N-channel MOS field effect transistor.
  • the drain of the MOS field effect transistor M16 is connected to the terminal T1.
  • the source and back gate of the MOS field effect transistor M16 are connected to the terminal T2.
  • MOS field effect transistor M16 is connected in series to capacitive load LD1 via terminal T1.
  • the overcurrent protection circuit OCP1 monitors the output current Ip (source current of the MOS field effect transistor M16) and protects the MOS field effect transistor M16.
  • the overcurrent protection circuit OCP1 determines whether the output current Ip, which is the current to be monitored, exceeds the first threshold TH1 in the detection mode, and determines whether the output current Ip exceeds the first threshold TH2, which is the current to be monitored, in the limit mode. Determine whether or not it exceeds.
  • Overcurrent protection circuit OCP1 does not limit output current Ip in detection mode.
  • the overcurrent protection circuit OCP1 limits the output current Ip when the output current Ip exceeds the second threshold TH2 in the limit mode.
  • the overcurrent protection circuit OCP1 is in the detection mode in an initial state (when the semiconductor device 1A is started or when the semiconductor device 1A is reset).
  • the overcurrent protection circuit OCP1 includes MOS field effect transistors M1 to M15, resistors R1 to R4, an inverter 3, and a latch circuit 4.
  • the MOS field effect transistors M11 to M13 are P-channel MOS field effect transistors. Each source and each back gate of the MOS field effect transistors M11 to M13 are connected to the terminal T5.
  • the control circuit 2 supplies a bias voltage Bias1 to each gate of the MOS field effect transistors M11 to M13.
  • the control circuit 2 sets the bias voltage Bias1 to the LOW level when the input signal IN is at the HIGH level and overheat protection is not performed.
  • each of the MOS field effect transistors M11 to M13 operates as a current source that outputs a reference current.
  • control circuit 2 sets the bias voltage Bias1 to the HIGH level when at least one of the first condition that the input signal IN is at the LOW level and the second condition that the overheating protection is performed is satisfied. At this time, each drain current of the MOS field effect transistors M11 to M13 becomes zero.
  • the MOS field effect transistors M1 to M4 are N-channel MOS field effect transistors.
  • the drain of the MOS field effect transistor M11 is connected to the drain and gate of the MOS field effect transistor M2, and the gate of the MOS field effect transistor M1.
  • the drain of the MOS field effect transistor M12 is connected to the drain of the MOS field effect transistor M1 and each gate of the MOS field effect transistors M3 and M4.
  • the drain of the MOS field effect transistor M13 is connected to the drain of the MOS field effect transistor M4 and the input terminal of the inverter 3.
  • the output signal of the inverter 3 is supplied to the latch circuit 4.
  • the source and back gate of the MOS field effect transistor M1 are connected to the first end of the resistor R1 and the source and back gate of the MOS field effect transistor M15, which is an N-channel MOS field effect transistor.
  • a second end of the resistor R1 is connected to the ground potential via a terminal T2.
  • the source and back gate of the MOS field effect transistor M2 are connected to the first end of the resistor R2 and the source and back gate of the MOS field effect transistor M3.
  • the second end of resistor R2 is connected to the first end of resistor R3 and the drain of MOS field effect transistor M10, which is an N-channel MOS field effect transistor.
  • the second end of the resistor R3 and the source and back gate of the MOS field effect transistor M10 are connected to the ground potential via the terminal T2.
  • the output of the latch circuit 4 is supplied to the gate of the MOS field effect transistor M10.
  • the circuit constituted by the resistors R2 and R3 and the MOS field effect transistor M10 is a variable resistor whose resistance value is switched depending on whether the MOS field effect transistor M10 is turned on or off.
  • the source and back gate of the MOS field effect transistor M4 are connected to the ground potential via the terminal T2.
  • the drain current of the MOS field effect transistor M3 is transmitted through a current mirror formed by MOS field effect transistors M5 and M6, which are P-channel MOS field effect transistors, and MOS field effect transistors M7 and M8, which are N-channel MOS field effect transistors. a current mirror constructed by , and replicated by . Therefore, the drain current of the MOS field effect transistor M14, which is a P-channel MOS field effect transistor, is a current that is a copy of the drain current of the MOS field effect transistor M3.
  • the drain current of the MOS field effect transistor M14 becomes a current limit signal for limiting the output current Ip in the limit mode.
  • a MOS field effect transistor M9 which is an N-channel MOS field effect transistor, is connected in parallel to the MOS field effect transistor M7.
  • the output of the latch circuit 4 is supplied to the gate of the MOS field effect transistor M9.
  • Each source and each back gate of MOS field effect transistors M5, M6, and M14 are connected to terminal T5.
  • the drain and gate of the MOS field effect transistor M5 and the gate of the MOS field effect transistor M6 are connected to the drain of the MOS field effect transistor M3.
  • the drain of the MOS field effect transistor M6 is connected to the drain and gate of the MOS field effect transistor M7, the gate of the MOS field effect transistor M8, and the drain of the MOS field effect transistor M9.
  • Each source and each back gate of the MOS field effect transistors M7 to M9 are connected to the ground potential via the terminal T2.
  • the drain of the MOS field effect transistor M8 is connected to the drain of the MOS field effect transistor M14 and the first end of the resistor R4.
  • the control circuit 2 supplies a bias voltage Bias2 to the gate of the MOS field effect transistor M14.
  • the control circuit 2 sets the bias voltage Bias2 to the LOW level when the input signal IN is at the HIGH level and overheat protection is not performed. At this time, the MOS field effect transistor M14 operates as a current source.
  • control circuit 2 sets the bias voltage Bias2 to the HIGH level when at least one of the first condition that the input signal IN is at the LOW level and the second condition that the overheating protection is performed is satisfied. At this time, the drain current of the MOS field effect transistor M14 becomes zero.
  • the second end of the resistor R4 is connected to each gate of the MOS field effect transistors M15 and M16.
  • the MOS field effect transistor M15 outputs a sense current Is according to the output current Ip.
  • the resistor R1 converts the sense current Is into a detection signal (detection voltage) S1 according to the output current Ip.
  • MOS field effect transistors M1 and M2 form an amplifier input stage that receives an input of a detection signal (detection voltage) S1 corresponding to the output current Ip.
  • the MOS field effect transistor M1 receives an input of a detection signal (detection voltage) S1 corresponding to the output current Ip.
  • MOS field effect transistor M2 receives input of reference signal (reference voltage) S2.
  • the MOS field effect transistor M3 generates a current output signal (source current and drain current of the MOS field effect transistor M3) S3 according to the difference between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2.
  • An amplifier output stage is formed which inputs a current output signal (source current of MOS field effect transistor M3) S3 in negative feedback to the amplifier input stage.
  • the MOS field effect transistor M4 outputs a comparison result S4 between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2.
  • the value of the reference signal (reference voltage) is switched based on the comparison result S4.
  • the MOS field effect transistor M16 is controlled based on the current output signal S3, and the overcurrent protection circuit OCP1 limits the output current Ip based on the current output signal S3 in the limit mode.
  • the detection signal (detection voltage) S1 also increases. Then, when the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2 substantially match, the comparison result S4 switches from HIGH level to LOW level, MOS field effect transistor M10 is turned on, and the reference signal (reference voltage ) S2 tries to go down. However, since the current output signal S3 is input as negative feedback to the amplifier input stage, the reference signal (reference voltage) S2 tends to rise when the MOS field effect transistor M3 is on. Due to the balance between the two, the reference signal (reference voltage) S2 decreases while maintaining the substantially coincident state between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2.
  • the MOS field effect transistor M8 since the MOS field effect transistor M8 becomes half-on, the gate potential of each of the MOS field effect transistors M15 and M16 decreases, and the sense current IS and therefore the detection signal (detection voltage) S1 also decreases. Since the detection signal (detection voltage) S1 is input as a negative feedback to the above amplifier input stage, the MOS field effect transistor M15 is connected so that the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2 substantially match. The gate potentials of M16 and M16 are controlled.
  • FIG. 3 is a diagram showing the configuration of a load driving device according to a comparative example.
  • the load driving device 10B according to the comparative example includes a semiconductor device 1B according to the comparative example, a capacitive load LD1, and DC power supplies VS1 and VS2.
  • a semiconductor device 1B according to a comparative example has a configuration in which the overcurrent protection circuit OCP1 in the semiconductor device 1A is replaced with an overcurrent protection circuit OCP2.
  • the overcurrent protection circuit OCP2 does not include the MOS field effect transistors M5 to M9, and the drain of the MOS field effect transistor M3 is connected to the drain of the MOS field effect transistor M14 and the first end of the resistor R4. This differs from the overcurrent protection circuit OCP1 in that the source and back gate are connected to the ground potential via the terminal T2.
  • the detection signal (detection voltage) S1 also increases. Then, when the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2 substantially match, the comparison result S4 switches from HIGH level to LOW level, MOS field effect transistor M10 is turned on, and the reference signal (reference voltage ) S2 goes down. As a result, the MOS field effect transistor M3 is fully turned on, so the gate potential of each of the MOS field effect transistors M15 and M16 drops to the ground potential, and the output transistor MOS field effect transistor M16 is turned off, cutting off the output current Ip. Therefore, a limiting mode in which the output current Ip continues to flow while limiting the output current Ip cannot be realized. To solve this problem with a circuit configuration similar to the overcurrent protection circuit OCP2, it is necessary to separately provide a reference signal (reference voltage) for the detection mode and a reference signal (reference voltage) for the limit mode. , the circuit scale increases.
  • the overcurrent protection circuit OCP1 allows rush current in the detection mode, but after a rush current exceeding the allowable range flows due to a load short circuit, etc., the overcurrent protection circuit OCP1 can limit the current to a low current lower than the rush current in the limit mode. , Furthermore, an increase in circuit scale can be suppressed.
  • FIG. 4 is a timing chart showing waveform examples of the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2.
  • the first timing TM1 in FIG. 4 is a timing when the overcurrent protection circuit OCP1 is in the detection mode, the MOS field effect transistor M16, which is an output transistor, is on, and the overcurrent protection circuit OCP1 is waiting for overcurrent detection. It is.
  • the MOS field effect transistors M3 to M8 are off, the MOS field effect transistor M9 is on, and the MOS field effect transistor M10 is off.
  • the second timing TM2 in FIG. 4 is the timing at which the overcurrent protection circuit OCP1 is in the detection mode, the MOS field effect transistor M16, which is the output transistor, is on, and the overcurrent protection circuit OCP1 detects the overcurrent detection. It is.
  • the MOS field effect transistor M3 is off
  • the MOS field effect transistor M4 is on
  • the MOS field effect transistors M5 to M8 are off
  • the MOS Field effect transistor M9 is on and MOS field effect transistor M10 is off.
  • the MOS field effect transistor M4 Since the MOS field effect transistor M4 is turned on, at the third timing TM3, which is immediately after the second timing TM2 in FIG. The field effect transistor M10 is turned on and the overcurrent protection circuit OCP1 shifts to the limit mode.
  • the MOS field effect transistor M3 is off, the MOS field effect transistor M4 is on, the MOS field effect transistors M5 to M8 are off, and the MOS Field effect transistor M9 is off and MOS field effect transistor M10 is on.
  • the MOS field effect transistor M10 is turned on and the reference signal (reference voltage) S2 is lowered, so that the MOS field effect transistors M3 and M5 to M8 are turned half on, and the MOS field effect transistor M10 is turned on and the reference signal (reference voltage) S2 is lowered.
  • This is the timing at which charge extraction from the gates of the transistors M15 and M16 is started, and the limitation of the output current Ip is actually started.
  • the fourth timing TM4 in FIG. 4 as shown in FIG.
  • the MOS field effect transistor M3 is half-on, the MOS field-effect transistor M4 is on, the MOS field-effect transistors M5 to M8 are half-on, and the MOS Field effect transistor M9 is off and MOS field effect transistor M10 is on.
  • the fifth timing TM5 in FIG. 4 is a timing when the overcurrent protection circuit OCP1 is in the limit mode, the MOS field effect transistor M16 which is the output transistor is on, and overheating is detected and overheating protection is performed.
  • the MOS field effect transistors M3 to M8 are off, and the latch circuit 4 latches the signal supplied to each gate of the MOS field effect transistors M9 and M10. Therefore, the MOS field effect transistor M9 is on and the MOS field effect transistor M10 is off. Therefore, at the fifth timing TM5 in FIG. 4, the overcurrent protection circuit OCP1 can maintain the limit mode.
  • a sixth timing TM6 in FIG. 4 is a timing when the overcurrent protection circuit OCP1 is in the limit mode, the MOS field effect transistor M16 which is the output transistor is on, and the overheating protection is released.
  • the overcurrent protection circuit OCP1 performs the same operation as at the fourth timing TM4 in FIG.
  • the seventh timing TM7 in FIG. 4 is the timing when the overcurrent protection circuit OCP1 is in the limit mode and the MOS field effect transistor M16, which is the output transistor, is off.
  • the overcurrent protection circuit OCP1 performs the same operation as at the fifth timing TM5 in FIG.
  • the eighth timing TM8 in FIG. 4 is the timing at which the overcurrent protection circuit OCP1 is reset. By resetting the overcurrent protection circuit OCP1, the latch circuit 4 also returns to its initial state. Therefore, at the eighth timing TM8 in FIG. 4, the overcurrent protection circuit OCP1 performs the same operation as at the first timing TM1 in FIG.
  • FIG. 10 is an external view showing an example of the configuration of a vehicle.
  • the vehicle X of this configuration example is equipped with various load drive devices that operate by receiving power supply from a battery.
  • vehicle such as fuel cell electric vehicle/fuel cell vehicle
  • xEV fuel cell electric vehicle/fuel cell vehicle
  • the vehicle X can be equipped with, for example, the load drive device 10A described above.
  • the overcurrent protection circuit (OCP1) of the present disclosure includes a first transistor (M1) and a second transistor (M2) configured to form an amplifier input stage that receives an input of a detection signal according to a current to be monitored; a third transistor configured to form an amplifier output stage that generates a current output signal according to the difference between the detection signal and the reference signal and inputs the current output signal as negative feedback to the amplifier input stage; M3) and a fourth transistor (M4) configured to output a comparison result between the detection signal and the reference signal, and the value of the reference signal is configured to be switched based on the comparison result.
  • a configuration (first configuration) configured to limit the monitored current based on the current output signal output from the third transistor.
  • the first main electrode of the first transistor is connected to the control electrodes of the third transistor and the fourth transistor, and the first main electrode of the second transistor is connected to the control electrode of the third transistor and the fourth transistor.
  • a first main electrode of the third transistor connected to the output node of the current output signal, and a second main electrode of the first transistor
  • the second main electrode of the second transistor is connected to the second main electrode of the third transistor
  • the first main electrode of the fourth transistor is connected to the first potential node. It may be a configuration (second configuration) in which the terminals are connected to.
  • a fixed resistor configured to be connected between the second main electrode of the first transistor and the first potential node
  • a configuration (fourth configuration) further comprising: a variable resistor (R2, R3, M10) configured to be connected between the second main electrode of the second transistor and the first potential node.
  • the overcurrent protection circuit of the fourth configuration further includes a latch circuit (4) configured to latch the comparison result, and the resistance value of the variable resistor is variable based on the output of the latch circuit.
  • a configuration (fifth configuration) may be used.
  • the overcurrent protection circuit further includes a current mirror (M5 to M8) configured to generate a current limit signal by replicating the current output signal (the 6).
  • a semiconductor device (1A) of the present disclosure includes an output transistor (M16) and overcurrent protection according to any one of the first to sixth configurations, wherein the output current flowing through the output transistor is configured to be the monitored current.
  • This is a configuration (seventh configuration) including a circuit.
  • the overcurrent protection circuit is configured to limit the output current by controlling a drive signal for the output transistor based on the current output signal ( 8).
  • a load driving device (10A) of the present disclosure has a configuration (ninth configuration) including the semiconductor device of the seventh or eighth configuration and a capacitive load connected in series to the output transistor.
  • the vehicle (X) disclosed herein is configured (tenth configuration) to include a load driving device of the ninth configuration described above.

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PCT/JP2023/025704 2022-09-15 2023-07-12 過電流保護回路、半導体装置、負荷駆動装置、及び車両 Ceased WO2024057695A1 (ja)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020031672A1 (ja) * 2018-08-06 2020-02-13 ローム株式会社 スイッチ装置及びこれを用いたモータ駆動装置
JP2021065040A (ja) * 2019-10-15 2021-04-22 ローム株式会社 スイッチ装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020031672A1 (ja) * 2018-08-06 2020-02-13 ローム株式会社 スイッチ装置及びこれを用いたモータ駆動装置
JP2021065040A (ja) * 2019-10-15 2021-04-22 ローム株式会社 スイッチ装置

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