WO2024055475A1 - 一种联合钝化背接触电池及其制备方法 - Google Patents

一种联合钝化背接触电池及其制备方法 Download PDF

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WO2024055475A1
WO2024055475A1 PCT/CN2022/144016 CN2022144016W WO2024055475A1 WO 2024055475 A1 WO2024055475 A1 WO 2024055475A1 CN 2022144016 W CN2022144016 W CN 2022144016W WO 2024055475 A1 WO2024055475 A1 WO 2024055475A1
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layer
semiconductor layer
laser
type doped
doped silicon
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French (fr)
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林楷睿
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金阳(泉州)新能源科技有限公司
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Definitions

  • the present application belongs to the technical field of back contact batteries, and specifically relates to a jointly passivated back contact battery and a preparation method thereof.
  • heterojunction high-temperature diffusion
  • the back contact battery does not have the optical shielding of conventional batteries, and its structural feature is to transfer all the electrodes to the back of the battery. Due to the unique advantages of back contact technology in power generation efficiency and appearance, Panasonic's heterojunction department has successively invested in the development of heterojunction low-temperature back contact technology since 2014.
  • the back electrode opening technology consists of ink printing and chemical etching.
  • the space for cost reduction is relatively limited, so there are currently obstacles in mass production promotion.
  • the process route using the back contact technology route is more complicated. Frequent battery surface contact causes damage to the surface passivation.
  • it is not conducive to reducing the production cost of the battery.
  • it is not conducive to improving the mass production efficiency. It is estimated that every additional Due to the printing process, the absolute efficiency of the battery is reduced by 0.2%. Therefore, the key to mass production promotion of back contact technology is to reduce production steps and reduce efficiency damage caused by mechanical contact.
  • Laser processing of the battery surface is a non-contact method, which can reduce the efficiency reduction of the battery due to processing technology.
  • lasers have been applied in the production of other types of batteries, including PERC's back metal contact opening, TOPCON's selective emitter, and IBC's back electrode opening. These processes have made sufficient progress in industrialization.
  • traditional heterojunction technology generally adopts low-temperature processes.
  • HBC heterojunction back contact battery
  • amorphous silicon films are sensitive to the thermal effects introduced by laser processing, the configuration of the laser in the heterojunction back contact technology route needs to be independently studied and optimized.
  • CN114068731A is the applicant's previous research result and provides a back-contact heterojunction solar cell characterized by low laser damage and a preparation method thereof.
  • the laser is absorbed and the damage of the laser to the first conductive type film is reduced.
  • all thin film layers have pinhole defects, causing leakage.
  • the solar structure used is still based on traditional HIT technology, the laser thermal effect will still affect the performance of the amorphous silicon film, making it impossible to fully utilize the photoelectric conversion efficiency advantages of the heterojunction structure.
  • TOPCON is a high-efficiency passivation technology similar to heterojunction technology. It is characterized by high-quality silicon oxide as a tunnel oxide layer. The polysilicon in contact with it is doped with phosphorus to form an N electrode that collects electrons. The polysilicon in contact with it is doped with boron. The hybrid forms a P electrode that collects holes.
  • SUNPOWER of the United States invented the first commercial IBC battery technology and officially introduced tunneling oxide passivation technology into mass production in 2009. Later, Fraunhofer in Europe promoted this technology academically, achieving a conversion efficiency higher than 26.0% in a small size, and officially named it POLO or TOPCON technology.
  • the passivation film layer related to TOPCON technology is grown using high-temperature technology and is not sensitive to the attenuation of technical processing, which can greatly reduce the complexity of engineering design.
  • the heterojunction itself is a low-temperature process (less than 200°C)
  • the grown film layer is sensitive to the thermal effect of the laser and has poor corrosion resistance.
  • it requires a variety of complex physical or chemical methods to combine openings, resulting in pinhole defects. It is more common, resulting in lower actual fill factor FF and photoelectric conversion efficiency, and lower yield.
  • the purpose of this application is to provide a jointly passivated back contact cell and its preparation in order to overcome the shortcomings of the existing technology of traditional heterojunction back contact cells in terms of actual fill factor FF, photoelectric conversion efficiency, low yield and complex process.
  • Method Compared with conventional heterojunction cells, this jointly passivated back contact cell can significantly improve the filling factor FF, photoelectric conversion efficiency, and yield.
  • the preparation method is relatively simple and can be industrialized, which is conducive to improving mass production efficiency.
  • the present application provides a jointly passivated back contact battery, including an N-type doped silicon substrate with a light-receiving surface and a back surface, a first semiconductor layer and a second semiconductor layer disposed on the back surface,
  • the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer that are sequentially disposed along the vertical back surface outward direction
  • the first semiconductor layer includes a tunnel oxide layer that is sequentially disposed along the vertical back surface outward direction.
  • N-type doped silicon crystal layer including an N-type doped silicon substrate with a light-receiving surface and a back surface, a first semiconductor layer and a second semiconductor layer disposed on the back surface,
  • the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer that are sequentially disposed along the vertical back surface outward direction
  • the first semiconductor layer includes a tunnel oxide layer that is sequentially disposed along the vertical back surface outward direction. and N-type doped silicon crystal layer.
  • the thickness ratio of the intrinsic silicon layer to the tunnel oxide layer is 1.2-11:1, preferably 1.5-5:1.
  • the thickness ratio of the tunnel oxide layer, N-type doped silicon crystal layer, intrinsic silicon layer and P-type doped silicon layer is 1:11-300:1.2-11:3- 50, preferably 1:20-100:1.5-5:4-20.
  • the ratio of the surface doping index of the N-type doped silicon crystal layer to the surface doping index of the P-type doped silicon layer is 0.07-40:1, preferably 0.07-20:1, and more Preferably, it is 0.07-5:1, and further preferably, 0.07-1:1; wherein, the surface doping index is the ratio of the effective doping concentration of the corresponding doped layer to the thickness of the doped layer.
  • the intrinsic silicon layer is intrinsic amorphous silicon
  • the P-type doped silicon layer is P-type doped amorphous silicon or P-type doped microcrystalline silicon
  • the mixed silicon crystal layer is N-type doped polysilicon.
  • the P-type doped silicon layer includes an incubation layer, and a P-type oxygen-containing microcrystalline layer and a P-type oxygen-free microcrystalline layer, wherein the P-type oxygen-containing microcrystalline layer and the P-type oxygen-free microcrystalline layer
  • the thickness ratio of the layers is 1:0.25-7.
  • the P-type doped silicon layer is P-type doped amorphous silicon.
  • the N-type doped silicon substrate is a Czochralski single crystal or an ingot single crystal.
  • the light-receiving surface of the N-type doped silicon substrate is a textured surface, and the back surface is a polished surface.
  • the jointly passivated back contact cell further includes:
  • a dielectric insulating film is provided on the surface of the first semiconductor layer, and the first semiconductor layer and the dielectric insulating film thereon as a whole are arranged at intervals along the parallel direction of the back surface, and the second semiconductor layer is provided on the surface of the first semiconductor layer.
  • the surface of the dielectric insulating film covers the surface of the intervals, and an opening exposing the first semiconductor layer is opened on the second semiconductor layer between adjacent intervals;
  • the passivation film layer, the doping film layer and the anti-reflection film layer are all arranged on the surface of the light-receiving surface and are arranged in sequence along the vertical and outward direction of the light-receiving surface.
  • the passivation film layer is intrinsic amorphous silicon; the doped film layer is an N-type amorphous film layer or an N-type oxygen-containing microcrystalline film layer; the anti-reflection film layer is nitride At least one of silicon, silicon dioxide, silicon oxide, and silicon oxynitride.
  • this application provides a method for preparing a jointly passivated back contact battery according to the first aspect, which includes the following steps:
  • S101 Provide N-type doped silicon substrate
  • the first semiconductor layer includes a tunnel oxide layer and an N-type doped silicon crystal layer;
  • a second semiconductor layer is formed to fully cover the back side of the N-type doped silicon substrate obtained in S103.
  • the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer; wherein, the opening and the third semiconductor layer on it are A second conductive region is formed on the second semiconductor layer;
  • the etching adopts laser ablation combined with optional chemical etching, wherein the first semiconductor layer, the second semiconductor layer or the transparent conductive film are removed respectively by laser ablation, and the dielectric is removed.
  • the insulating film is laser ablated or chemically etched.
  • the first semiconductor layer is removed from the etching opening using the first laser ablation method with partial overlap of continuously scanning light spots, wherein the amount of laser absorption of the first semiconductor layer to be removed is D1 is more than 70% of the total absorption of each film layer.
  • the conditions for the first laser ablation include: using a pulsed laser with a pulse width less than 20 nanoseconds; the light spot formed by the laser on the back is circular, elliptical or rectangular; the laser used is spatially shaped into a square shape. , circular or oval flat-top laser.
  • the second semiconductor layer is removed from the etching opening using a second laser ablation method of discontinuous openings or continuous openings.
  • the formed light spots do not overlap, and the laser absorption D2 of the second semiconductor layer to be removed is more than 70%, preferably more than 80%, of the total absorption of each film layer;
  • the formed light spots partially overlap, in which the first laser exposure of adjacent light spots removes the top second semiconductor layer.
  • the amount of laser absorption required to remove the corresponding layer is D 201 is more than 70% of the total absorption of each film layer; the second laser exposure caused by partial spot overlap removes the dielectric insulating film below and part of the top N-type doped silicon crystal layer at the bottom.
  • the laser absorption amount D 202 required to remove the corresponding layer is more than 50% of the total absorption amount of each film layer.
  • the conditions for the second laser ablation include: using a pulsed laser with a pulse width less than 20 nanoseconds; the light spot formed by the laser on the back is circular, elliptical or rectangular; the laser used is spatially shaped into a rectangle. , circular or oval flat-top laser.
  • the insulating groove is etched using a third laser ablation method in which continuous scanning light spots partially overlap, and the laser absorption amount of the transparent conductive film to be etched and the second semiconductor layer overlapping it is D 3 It is more than 70%, preferably more than 85%, of the total absorption of each film layer.
  • the conditions for the third laser ablation include: using a pulsed laser with a pulse width of less than 100 nanoseconds; and the light spot formed by the laser on the back is circular, elliptical or rectangular.
  • heterojunction back contact battery technology As mentioned above in the background art, the inventor of the present application has discovered that using laser etching is a feasible solution for mass production of heterojunction back contact battery technology, which can greatly simplify the process flow of back contact technology.
  • traditional heterojunction back contact cells are unstable when using lasers.
  • Heterojunction films mainly composed of amorphous silicon will undergo significant changes when the temperature exceeds 220°C, such as intrinsic amorphous silicon and N-type amorphous silicon.
  • the TOPCON process can use high-temperature lasers and has good conductivity and can achieve a passivation level that matches heterojunction passivation, its actual passivation level is still lower than that of heterojunction, especially the second semiconductor is responsible for passivation.
  • the electrode area is the bottleneck that restricts its electrical properties.
  • the open circuit voltage is roughly 710-730 millivolts, which is lower than the typical 745 millivolts of heterojunction. Compared with the photoelectric conversion performance that traditional heterojunction cells can achieve, it is still at a disadvantage.
  • the equipment used in the traditional heterojunction passivation process and the TOPCON process belong to two different equipment systems. In the existing technology, the two processes are usually independently researched and improved.
  • This application innovatively combines the traditional heterojunction passivation structure and the TOPCON structure for the first time to form a jointly passivated back contact battery, using a tunnel oxide layer and an N-type doped silicon crystal layer (TOPCON passivation film layer)
  • TOPCON passivation film layer As the first semiconductor layer, the second semiconductor layer uses a traditional heterojunction passivation film layer, that is, TOPCON and heterojunction are organically combined to achieve joint passivation, and the TOPCON passivation film layer produced by a high-temperature process is used to replace conventional heterojunction passivation.
  • the back contact battery structure using the above structure can expand the process window, improve the yield and final conversion efficiency compared to conventional heterojunction cells, and can significantly improve the conversion efficiency of the fill factor FF (in some cases In specific examples, it can be increased by more than 3%).
  • the first semiconductor layer with a specific structure is resistant to high temperatures (800-870°C), and the first semiconductor layer prepared by high-temperature laser ablation can enable the subsequent opening of the second semiconductor layer or the formation of an insulating groove.
  • high temperature tolerance of other preparation processes makes the entire preparation process of the backside highly compatible with laser processing technology, so that laser ablation can be used for each opening or hole on the backside, which has good stability and can achieve mass production.
  • the production method is simple, the yield is high, the material cost is low, and there is no need for exposure, development, corrosion and photoresist materials in the traditional heterojunction back contact battery preparation method.
  • Figure 1a is a comparison diagram of the theoretically predicted electrical performance JSC of conventional heterojunction back contact battery B and joint passivation back contact battery C of this application;
  • Figure 1b is a comparison chart of the theoretically predicted electrical performance Voc of the conventional heterojunction back contact battery B and the jointly passivated back contact battery C of the present application;
  • Figure 1c is a comparison chart of the theoretically predicted electrical performance fill factor FF of the conventional heterojunction back contact battery B and the application's combined passivation back contact battery C;
  • Figure 1d is a comparison diagram of the theoretically predicted electrical performance conversion efficiency of conventional heterojunction back contact battery B and joint passivation back contact battery C of the present application.
  • Figure 2 is a top view of a specific embodiment of a jointly passivated back contact battery of the present application.
  • Figure 3 is a cross-sectional view along line A-A in Figure 2 .
  • Figure 4a is a process flow chart for preparing the first semiconductor layer and the second semiconductor layer in the combined passivation back contact battery of the present application;
  • Figure 4b is a subsequent preparation process flow chart of Figure 4a.
  • Figure 5a is the first nearly circular laser beam spot scanning method formed by etching holes on the back, in which adjacent light spots partially overlap and the next adjacent light spots do not overlap;
  • Figure 5b is the second nearly square laser spot scanning method formed by etching holes on the back, in which adjacent spots partially overlap and the next adjacent spots do not overlap;
  • Figure 5c is the third nearly square laser spot scanning method formed by etching holes on the back.
  • the first column of scanning spots does not overlap, and the second column of retracement spots does not overlap front and back in the direction of the moving trajectory.
  • the first column of scanning spots does not overlap in the moving trajectory direction.
  • the light spots in the first column partially overlap with the light spots in the second column.
  • Figure 6a is the first single-row rectangular discontinuous laser beam spot scanning method formed by etching openings on the back;
  • Figure 6b shows the second dual-row rectangular discontinuous laser beam spot scanning method formed by etching openings on the back.
  • Figure 7 is the E 2 (square value of electric field intensity) distribution diagram of the laser formed on the first semiconductor layer and the second semiconductor layer when a laser with a wavelength of about 532 nm is incident on the back surface of the battery obtained in Example 1 of the present application; where X is based on the back surface of the substrate is the thickness of the starting zero point.
  • Figure 8 is a comparison chart of the minority carrier lifetime of the jointly passivated back contact battery in Embodiment 1 of the present application and the TOPCON passivation method and the traditional heterojunction passivation method.
  • the “a-Si 2-side” sample adopts heterojunction passivation on both sides of the substrate
  • the “TOPCON/a-Si” sample is the jointly passivated back contact battery of Example 1 of this application
  • the “TOPCON 2-side” sample uses heterojunction passivation on both sides of the substrate.
  • the sample uses TOPCON passivation on both sides of the substrate.
  • the minority carrier lifetime collection is obtained when the carrier density is 5e15/cm 3 .
  • N-type doped silicon substrate 01. Backside, 02. Light-receiving surface; 10. Sacrificial layer, 11. Tunnel oxide layer, 12. N-type doped silicon crystal layer, 13. Dielectric insulating film, 14. Open hole; 21. intrinsic silicon layer, 22. P-type doped silicon layer, 23. opening; 30. transparent conductive film, 31. insulating groove; 41. passivation film layer, 42. doped film layer, 43. minus Reflective coating layer; 51, fine grid lines, 52, main grid lines.
  • HBC characterized by heterojunction passivation layer
  • the first semiconductor layer prepared first will undergo multiple high-temperature heat treatments including laser processes. and chemical cleaning and corrosion steps.
  • the TOPCON passivation film layer produced by high-temperature process is used to replace the conventional heterojunction passivation film layer.
  • the process window can be expanded and the yield rate and final conversion efficiency can be improved.
  • the present application provides a jointly passivated back contact battery, including an N-type doped silicon substrate having a light-receiving surface and a back surface, a first semiconductor layer and a second semiconductor layer disposed on the back surface, the The second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer that are sequentially disposed along the vertical back surface outward direction.
  • the first semiconductor layer includes a tunnel oxide layer and an N-type doped silicon layer that are sequentially disposed along the vertical back surface outward direction. type doped silicon crystal layer.
  • junction between the second semiconductor layer and the N-type doped silicon substrate is a heterojunction.
  • Figures 1a, 1b, 1c, and 1d show the relevant theoretically predicted photoelectric conversion performance of conventional heterojunction back contact cells and the jointly passivated back contact cell provided in this application. It can be seen from the figure that the fill factor FF and photoelectric conversion efficiency of the jointly passivated back-contact cell have been improved, and the fill factor has been significantly improved.
  • Figures 1a, 1b, 1c, and 1d are theoretical simulation values, in which the increase in fill factor FF is due to the increase in conductivity of the first semiconductor layer caused by the introduction of TOPCON technology. In the actual experimental electrical comparison, the FF improvement is more obvious because the laser opening eliminates the possibility of pinhole leakage.
  • the thickness ratio of the intrinsic silicon layer to the tunnel oxide layer is 1.2-11:1, preferably 1.5-5:1.
  • the tunnel oxide layer has the above appropriate thickness compared with the intrinsic silicon layer, which is more conducive to improving the electrical conversion efficiency of the back contact battery; it is speculated that the reason may be that the relatively appropriate thickness of the tunnel.
  • the oxide layer provides fewer interface defects, impurity energy levels are annihilated during high-temperature annealing, and its conduction mechanism is through quantum tunneling or occasional pinhole defects.
  • the main passivation is provided by a layer of hydrogenated amorphous silicon, which itself also has certain conductive capabilities. Electrons or holes transition through the band gap impurity energy level in this layer of amorphous silicon.
  • the thickness ratio of the tunnel oxide layer, N-type doped silicon crystal layer, intrinsic silicon layer and P-type doped silicon layer is 1:11-300:1.2-11:3- 50, preferably 1:20-100:1.5-5:4-20.
  • it is more conducive to improving the FF of the back-contact battery. It is speculated that the reason may be that the introduction of the first semiconductor layer of TOPCON in this application allows carriers to conduct laterally first (due to hundreds of times improvement in conductivity) If collected vertically, the design of the aperture ratio has greater freedom.
  • the mobility of the introduced high-temperature polycrystalline can reach 200-300, and the high-temperature polycrystalline in this application can increase the thickness of the film layer arbitrarily, improving the conductivity of the entire back contact battery. Performance and FF have been significantly improved. While the carrier mobility of traditional heterojunction amorphous is low (taking electrons as an example, the mobility is roughly 0.5-1), microcrystalline silicon has slightly improved, around 10; and traditional amorphous silicon films, Increasing the thickness of the film layer may actually decrease the FF of the battery.
  • the ratio of the surface doping index of the N-type doped silicon crystal layer to the surface doping index of the P-type doped silicon layer is 0.07-40:1, preferably 0.07-20:1, and more Preferably, it is 0.07-5:1, and further preferably, 0.07-1:1; wherein, the surface doping index is the ratio of the effective doping concentration of the corresponding doped layer to the thickness of the doped layer. In the preferred solution of the present application, it is more conducive to improving the overall electrical conversion efficiency of the back contact battery.
  • the reason may be that the N-type doped silicon crystal layer with a relatively suitable surface doping index introduced in the first semiconductor layer of the present application , so that high-temperature polycrystalline can ensure that the limited doping and nominal doping are almost exactly the same, that is, all phosphorus elements are activated.
  • traditional amorphous silicon films especially B-doped P-type amorphous films, very little B is activated in the film, only 5-7% of the nominal doping, and the rest are reflected as defects in the film.
  • the thickness of the tunnel oxide layer is 10-22 angstroms, preferably 15-20 angstroms.
  • the balance of optimal passivation and conductivity can be ensured, while the process is simple and controllable.
  • the reason is that the thickness saturation value of the natural silicon oxide layer (native oxide) is 15-20 angstroms, and the thickness is not impossible. Control the rise.
  • the thickness of the N-type doped silicon crystal layer is 30-250 nm, and the effective doping concentration is greater than 5e18cm -3 . More preferably, the thickness of the N-type doped silicon crystal layer is 150-200nm, and the effective doping concentration is 1e19-8e19cm -3 .
  • the lateral conductivity of the first semiconductor is greatly enhanced, which can eliminate natural or design fluctuations caused by the insufficient long mean free path of carriers and weak conductivity of the transparent conductive film, ensuring the maximum FF change.
  • the sheet resistance of the N-type doped silicon crystal layer can be 30-200 ⁇ / ⁇ , preferably 40-70 ⁇ / ⁇ .
  • the thickness of the intrinsic silicon layer is 3-10 nm; the thickness of the P-type doped silicon layer is 7-45 nm, and the effective doping concentration is 2e18-1e20cm -3 .
  • the vertical conductivity of the device can be ensured, and at the same time, the weak P-type second semiconductor and the extremely strong conductivity will not cause a short circuit of the device.
  • the thickness of the N-type doped silicon substrate described in this application can be selected by those skilled in the art according to needs, and the thickness is preferably 110-150 microns. Under the preferred solution of this application, the highest power generation efficiency can be achieved, and at the same time, the use of silicon material is the most economically feasible.
  • the intrinsic silicon layer in the second semiconductor layer is a hydrogenated intrinsic amorphous silicon film (traditional heterojunction film layer).
  • the P-type doped silicon layer is P-type doped amorphous silicon. This solution belongs to traditional heterojunction technology and has the advantage of lower cost.
  • the P-type doped silicon layer is P-type doped microcrystalline silicon, which is expensive, has little benefit in back contact, and is difficult to be damaged by corrosion with HF acid.
  • the P-type doped silicon layer includes an incubation layer, a P-type oxygen-containing microcrystalline layer and a P-type oxygen-free microcrystalline layer, a P-type oxygen-containing microcrystalline layer and a P-type oxygen-free microcrystalline layer.
  • the thickness ratio is 1:0.25-7.
  • the appropriate thickness ratio of the P-type oxygen-containing microcrystalline layer and the P-type oxygen-free microcrystalline layer is more conducive to improving the battery's open circuit voltage Voc, fill factor FF, and conversion efficiency Eta; it is speculated that the reason may be that the oxygen-containing microcrystalline layer
  • the conductivity of the microcrystalline layer is weak, and the appropriate film thickness is equivalent to the Debye length, which can fully improve the electrical properties.
  • the oxygen-free microcrystalline layer needs a gradual transition to chemically protect the oxygen-containing microcrystalline layer.
  • the thickness ratio of the P-type oxygen-containing microcrystalline layer to the incubation layer is 1:0.1-20.
  • the N-type doped silicon crystal layer is N-type doped polysilicon.
  • the N-type doped polysilicon can be directly formed into polysilicon, or formed from microcrystalline silicon or amorphous silicon film layers through high-temperature modification.
  • the high-temperature modification process at least includes one or more steps above 600°C.
  • the tunnel oxide layer described in this application is preferably tunnel silicon oxide.
  • the N-type doped silicon substrate is a Czochralski single crystal or an ingot single crystal.
  • the light-receiving surface of the N-type doped silicon substrate is a textured surface
  • the back surface is a polished surface. This preferred solution can meet the consistency requirements of laser processing on the back side, making the laser processing surface have a polished structure instead of the traditional textured light-trapping structure.
  • the jointly passivated back contact battery described in this application may also include other conventional components in the art, such as an insulating layer partially provided between the first semiconductor layer and the second semiconductor layer, a conductive layer provided above the second semiconductor layer, etc. , forming metallized patterns such as fine grid lines, main grid lines and welding pads on the back, as well as a passivation layer on the light-receiving surface.
  • the jointly passivated back contact cell further includes:
  • a dielectric insulating film is provided on the surface of the first semiconductor layer, and the first semiconductor layer and the dielectric insulating film thereon as a whole are arranged at intervals along the parallel direction of the back surface, and the second semiconductor layer is provided on the surface of the first semiconductor layer.
  • the surface of the dielectric insulating film covers the surface of the intervals, and an opening exposing the first semiconductor layer is opened on the second semiconductor layer between adjacent intervals;
  • a dielectric insulating film is provided between the first semiconductor layer and the second semiconductor layer to prevent leakage of the device, and openings and insulation grooves required for back contacting the battery are provided to avoid the first semiconductor layer and
  • the electrical short circuit between the second semiconductor layers also avoids damage caused by mechanical contact. It also avoids pinhole defects in the dielectric insulation film and improves the power generation conversion efficiency of the battery.
  • those skilled in the art can set the overall arrangement of the openings and the insulating grooves according to needs, for example, by adjusting the degree of overlap or the size of the light spots.
  • the back surface includes a region in direct contact between the second semiconductor and the N-type doped silicon substrate, a region in direct contact between the first semiconductor and the N-type doped silicon substrate, and a region between the two.
  • the vertical N-type doped silicon substrate in the transition region and the outward direction includes a first semiconductor layer, a dielectric insulating film, and a second semiconductor layer distributed in sequence.
  • Each of the above areas also includes a transparent conductive film located on the back surface, and does not include a transparent conductive film at the insulating groove.
  • the jointly passivated back contact cell further includes two electrodes formed over the first semiconductor layer and over the second semiconductor layer.
  • the jointly passivated back contact battery further includes: a first gate line disposed above the second semiconductor layer on the surface of the spacer; forming a first metal electrode; a second gate line, It is arranged above the first semiconductor layer at the opening; forming a second metal electrode.
  • the jointly passivated back contact battery further includes: a passivation film layer, a doping film layer and an anti-reflection film layer, which are all disposed on the surface of the light-receiving surface and vertically along the light-receiving surface.
  • the outer direction is set in sequence.
  • the second semiconductor layer is substantially completely covered on the dielectric insulating film with intervals on the back (the coverage interval includes the bottom and sides of the intervals), and is only provided between adjacent intervals. said opening.
  • the passivation film layer is intrinsic amorphous silicon
  • the doped film layer is an N-type amorphous film layer or an N-type oxygen-containing microcrystalline film layer, preferably an N-type oxygen-containing microcrystalline film layer.
  • type microcrystalline film layer, and the anti-reflection film layer is at least one of silicon nitride, silicon dioxide, silicon oxide, and silicon oxynitride. This embodiment is more conducive to improving the transmittance of sunlight.
  • this application provides a method for preparing a jointly passivated back contact battery according to the first aspect, which includes the following steps:
  • S101 Provide N-type doped silicon substrate
  • the first semiconductor layer includes a tunnel oxide layer and an N-type doped silicon crystal layer;
  • a second semiconductor layer is formed to fully cover the back side of the N-type doped silicon substrate obtained in S103.
  • the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer; wherein, the opening and the third semiconductor layer on it are A second conductive region is formed on the two semiconductor layers; it can be understood that the second semiconductor layer at the opening is in direct contact with the N-type doped silicon substrate;
  • the second semiconductor layer can be formed by PECVD or Hot-wire.
  • the first semiconductor layer can be formed by PECVD or Hot-wire.
  • the passivation film layer, the doped film layer and the anti-reflection layer can be formed by PECVD or Hot-wire.
  • the film layer can be formed using PECVD or Hot-wire methods.
  • S101 also includes: cleaning the N-type doped silicon substrate through chemical cleaning, where the chemical cleaning can use alkali solution, for example.
  • the S101 process includes: Czochralski single crystal or ingot single crystal is cut with diamond wire or mortar to form a silicon wafer substrate with a thickness of 100-250 microns; optionally, the silicon wafer is also passed through a tank solution Perform pre-cleaning to remove organic contamination and large particles on the surface, then use alkali solution to damage and texturize to form a roughened light-trapping structure, then undergo RCA cleaning (or a solution formula equivalent to RCA cleaning), and finally pass through HF The solution removes the surface oxide layer, and then goes through the deionized water cleaning and surface drying process.
  • S101 also includes: making the N-type doped silicon substrate have a single-sided texturing and single-sided polishing structure. More preferably, the process includes: using a silicon nitride or silicon oxide film layer as a protective sacrificial layer on the light-receiving surface, maintaining the suede light-trapping structure of the light-receiving surface of the substrate to achieve back polishing, so that the light-receiving surface of the N-type doped silicon substrate It has a suede surface and a polished surface on the back.
  • the process of plating the first semiconductor layer in S102 may be: using wet oxidation, dry oxidation or plasma oxidation to form a tunnel oxide layer on the back side of the N-type doped silicon substrate. ; Then use LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) method to prepare a silicon film layer on the surface of the tunnel oxide layer, and The polycrystalline film layer is doped with phosphorus (phosphorus doping can be achieved by in-situ doping or high-temperature phosphorus expansion) to form an N-type doped silicon crystal layer, thereby obtaining the first semiconductor layer.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • PVD physical vapor deposition
  • the tunnel oxide layer can be formed by wet oxidation, including ozone oxidation, nitric acid oxidation, hydrogen peroxide oxidation, etc., such as introducing oxygen, ozone or hydrogen peroxide into a heated solution; for example, soaking the silicon wafer in In heated nitric acid solution; dry oxidation can also be used, including thermal oxidation, PECVD in-situ oxidation, etc., for example, placing the silicon wafer in a furnace tube equipment and heating it to 500-700°C, and passing oxygen or oxygen into the equipment.
  • wet oxidation including ozone oxidation, nitric acid oxidation, hydrogen peroxide oxidation, etc., such as introducing oxygen, ozone or hydrogen peroxide into a heated solution; for example, soaking the silicon wafer in In heated nitric acid solution; dry oxidation can also be used, including thermal oxidation, PECVD in-situ oxidation, etc., for example, placing the silicon
  • the thermal oxidation method is preferably used, and the conditions include: the thermal oxidation temperature is 550-650°C, the gas source is oxygen, and the oxidation time is 10-30 minutes; it can also be done by Plasma assisted oxidation.
  • the process of in-situ doping is such as introducing a phosphorus source (such as phosphane gas) into the gas atmosphere in which polycrystalline silicon, amorphous silicon or microcrystalline silicon is grown; the process of high-temperature phosphorus expansion
  • a layer of polycrystalline silicon, amorphous silicon or microcrystalline silicon film layer can be grown first (for example, it can be prepared by PECVD, or obtained by PVD sputtering), annealed at high temperature, and then used in a diffusion furnace containing a phosphorus source.
  • first deposit a layer of PSG glass on the surface to form effective diffusion of phosphorus; it is preferred to use LPCVD to deposit a polycrystalline silicon, amorphous silicon or microcrystalline silicon film layer and then diffuse it.
  • the diffusion temperature is 830-880°C, and the diffusion source is trichloride.
  • Oxygen phosphorus or oxygen, diffusion time is 80-180min. They all belong to mature existing technologies in this field and will not be described in detail here.
  • PECVD method can be used for plating dielectric insulation film in S102.
  • the etching opening adopts conventional photolithography.
  • the process may be, for example: using photoresist material to expose and develop to form a protective pattern, and then forming the unprotected area of the photoresist material through wet chemical etching. Open area, and finally remove the photoresist material.
  • the etching described in this application adopts laser ablation combined with optional chemical etching (preferably wet chemical etching, such as using a hydrofluoric acid-containing solution for chemical etching), wherein the first The semiconductor layer, the second semiconductor layer or the transparent conductive film are each removed by laser ablation, and the dielectric insulating film is removed by laser ablation or chemical etching, which will not cause perforation of the dielectric insulating film.
  • optional chemical etching preferably wet chemical etching, such as using a hydrofluoric acid-containing solution for chemical etching
  • the process of etching openings is: using a laser beam to perform first laser ablation on the first semiconductor layer and the dielectric insulation film thereon, combined with wet chemical etching Partial openings are made to remove the first semiconductor layer on the back side and the dielectric insulating film thereon at intervals to expose the N-type doped silicon substrate.
  • the first semiconductor layer in the etching opening is removed by using the first laser ablation method of partially overlapping continuous scanning light spots, and the laser absorption amount D1 of the first semiconductor layer to be removed is for each film layer More than 70% of the total absorption.
  • the first semiconductor layer to be removed can absorb most of the laser energy and avoid causing deep cracks in the N-type doped silicon substrate; this is due to the film depth and laser wavelength directly absorbed by the film layer.
  • the direct absorption depth of polysilicon caused by 532nm laser is 100-200 nanometers
  • the direct absorption depth of polysilicon caused by 355nm laser is 10-20 nanometers. Therefore, most of the laser can be concentrated on the first semiconductor layer to be removed. Reduce the laser's effect on the substrate to avoid causing deep cracks in the substrate.
  • total absorption of each film layer refers to the total absorption of all film layers at the current moment, including the substrate, the film layers on its back, and its light-receiving surface.
  • the conditions for the first laser ablation include: using a pulsed laser with a pulse width of less than 20 nanoseconds.
  • the light spot formed by the laser on the back side is circular, elliptical or rectangular, and can be arranged in various partially overlapping manners as shown in Figure 5a, Figure 5b and Figure 5c.
  • the laser used is spatially shaped into a flat-top laser, and its spatial distribution on the processing surface is a square, circular or elliptical flat-top shape, preferably a rectangle.
  • the laser wavelength can be around 355 nanometers or around 532 nanometers.
  • the laser used may be, for example, a laser with a wavelength of about 355 nanometers obtained by tripling the frequency of a YAG laser, or a laser with a wavelength of about 532 nanometers obtained by doubling the frequency of a YAG laser.
  • the absorption depth of polysilicon or crystalline silicon by a laser with a wavelength of about 355nm is 10-20 nanometers
  • the absorption depth of polysilicon or crystalline silicon by a laser with a wavelength of about 532nm is 100-200 nanometers.
  • the first laser ablation uses an ultraviolet pulse light source with a wavelength of 355 nm.
  • the absorption body of the first laser ablation in this application is the first semiconductor layer, and there is no need to provide an additional optical sacrificial layer of CN114068731A for absorption. Therefore, the preparation method is simple and can be industrialized for mass production.
  • PECVD equipment power supply can be 13.56MHz, 26MHz or 40MHz.
  • the second semiconductor layer is fully coated to cover the partially opened back dielectric insulating film; and then in S105, laser drilling is used to eliminate the upper second semiconductor layer.
  • the dielectric insulating film is then removed by chemical etching to expose the underlying first semiconductor layer.
  • the process gas used to form the intrinsic silicon layer can include, for example, silane (SiH 4 ), H 2 , CO 2 and CH 4 all or several combinations;
  • the process gas to form the P-type doped silicon layer may include, for example, SiH 4 , H 2 , CO 2 , B 2 H 6 (diborane) or TMB (trimethylborane) all or several combinations.
  • the etching opening can be formed by conventional photolithography.
  • the process can be, for example: using photoresist material to expose and develop to form a protective pattern, and then forming the unprotected area of the photoresist material through wet chemical etching. Open area, and finally remove the photoresist material.
  • the process of etching the opening is: using a laser beam to remove the second semiconductor layer in a partial area of the back side, performing a second laser ablation, and etching the dielectric insulating film under the partial area by chemical corrosion to obtain an opening exposing the first semiconductor layer thereunder, so as to form a first conductive area arranged alternately with the second conductive area.
  • the second laser ablation method of discontinuous opening or continuous opening is used to remove the second semiconductor layer from the etching opening.
  • the latter is preferred.
  • the formed light spots do not overlap, and the laser absorption D 2 of the second semiconductor layer to be removed is 70% of the total absorption of each film layer. More than 80%, preferably more than 80%.
  • the second semiconductor layer to be removed can absorb most of the laser energy, and the opening cross-section is clearly demarcated, while causing little or no damage to the underlying film layer and substrate.
  • chemical etching can be applied to remove the exposed dielectric insulating film; or secondary laser ablation can be repeated at the original opening position to remove the exposed dielectric insulating film. If this method is used, the N-type will be removed during the secondary laser ablation.
  • the laser absorption amount of the doped polycrystalline layer is more than 50% of the total absorption amount of each film layer.
  • Those skilled in the art can further optimize the thickness and refractive index of the dielectric insulating film to form an interference superposition effect at the vertical spatial position where the second semiconductor layer is located.
  • the formed light spots partially overlap, and the first laser exposure of adjacent light spots removes the top second semiconductor layer.
  • the laser absorption amount D 201 required to remove the corresponding layer is more than 70% of the total absorption amount of each film layer; the second laser exposure caused by partial spot overlap ablate the dielectric insulation film below and part of the top N at the bottom type doped silicon crystal layer.
  • the laser absorption amount D 202 required to remove the corresponding layer is more than 50% of the total absorption amount of each film layer.
  • the conditions for the second laser ablation include: using pulsed laser, and the pulse width is less than 20 nanoseconds, preferably less than 100 picoseconds.
  • the laser wavelength can be around 355 nanometers or around 532 nanometers. It is more preferred to use a green laser with a pulse width of less than 100 picoseconds.
  • the light spot formed by the laser on the back side is circular, elliptical or rectangular (as shown in Figure 6a and Figure 6b), which can be in a single row or multiple rows, which can avoid the reduction in power generation efficiency caused by laser damage.
  • the laser used is spatially shaped into a rectangular, circular or elliptical flat-top laser, preferably a rectangular shape, that is, its spatial distribution on the processing surface is a rectangular, circular or elliptical flat-top shape to ensure the processing area The internal energy tends to be consistent.
  • the laser used is preferably a laser with a wavelength of 355 nanometers obtained by tripling the frequency of a YAG laser, or a laser with a wavelength of 532 nanometers obtained by doubling the frequency of a YAG laser.
  • the first laser ablation is used to partially remove the first semiconductor layer
  • the second laser ablation removes part of the second semiconductor layer
  • the function of the first semiconductor layer underneath is not damaged
  • the third laser ablation is used to remove part of the second semiconductor layer.
  • Laser ablation builds an insulating trench without damaging the second semiconductor layer underneath it. It has good stability and high yield.
  • the cleaning in S103 and S105 includes chemical cleaning and smoothing treatment of the silicon surface in the exposed area to provide a low-defect interface for the effective preparation of subsequent film layers. This is a common technique in this field and will not be described in detail here.
  • the deposited transparent conductive film may be covered by PVD in a full-area manner.
  • PVD target materials and doping materials can be pure indium oxide, and then hydrogen or water vapor is introduced into the process gas to form a hydrogen-doped indium oxide film.
  • the etching of the insulating trench can be performed using conventional photolithography, and the process can be, for example: using a photoresist material to expose and develop to form a protective pattern, and then etching the unprotected areas of the photoresist material through wet chemistry. An opening area is formed, and the photoresist material is finally removed.
  • the process of etching the insulating groove is: using a laser beam to perform third laser ablation to remove part of the transparent conductive film located between the first conductive area and the second conductive area, An insulating groove is formed between two adjacent conductive areas. The arrangement of the insulating groove can physically insulate the N electrode in the first conductive area and the P electrode in the second conductive area.
  • the insulating groove is etched using a third laser ablation method in which continuous scanning light spots partially overlap, and the laser absorption amount D 3 of the transparent conductive film to be etched and the second semiconductor layer overlapping with it is 70% or more of the total absorption, preferably 85% or more.
  • the location of maximum optical interference is at the second semiconductor or the transparent conductive film in contact with it.
  • the transparent conductive film to be etched can absorb most of the laser energy and protect the underlying dielectric insulating film and the first semiconductor layer. Complete and undamaged. It can be understood that, under this solution, the total absorption of each film layer includes the total absorption of each film layer of the substrate, the first semiconductor layer and the second semiconductor layer above it, and the light-receiving surface below it.
  • the conditions for the third laser ablation include: using a pulsed laser with a pulse width of less than 100 nanoseconds.
  • the laser wavelength can be approximately 355 nanometers. More preferably, the light spot formed by the laser on the back side is circular, oval or rectangular.
  • the laser ablation described in this application can use ultraviolet laser, violet laser or green laser.
  • the partial overlap of the continuous scanning light spots means that adjacent light spots overlap among the formed light spots.
  • the process of forming the first electrode or the second electrode described in S106 includes: applying conductive silver paste on the back side of the obtained N-type doped silicon substrate to form a main gate line including a fine gate line and perpendicular to the fine gate line.
  • the method of applying the conductive silver paste may be screen printing or inkjet printing.
  • the passivation film layer, doping film layer and anti-reflection film layer described in S107 can be deposited by PECVD method.
  • the process gas of the passivation film layer may contain, for example, all or several combinations of SiH 4 , H 2 , CO 2 and CH 4 .
  • a jointly passivated back contact battery as shown in Figures 2 and 3 is prepared through the following steps as shown in Figures 4a and 4b:
  • N-type doped Czochralski single crystal silicon wafer substrate is cleaned by chemical texturing to form an N-type doped silicon substrate 00 with a double-sided texturing structure.
  • the process of preparing the first semiconductor layer includes: first, N-type doped silicon substrate 00 Place it in a furnace tube type equipment and heat it to 600°C. Oxygen is introduced into the equipment for oxidation. The oxidation time is 10-30 minutes to form a tunnel oxide layer 11 on the back side 01. Then use LPCVD to deposit polysilicon and then add a diffusion source to diffuse to form N. Type doped silicon crystal layer 12, the diffusion temperature is 850°C, the diffusion source is phosphorus oxychloride, and the diffusion time is 100 minutes.
  • step (d) Perform the first laser ablation on the back surface 01 obtained in step (c) and combine it with wet chemical etching to remove parts of the first semiconductor layer and the dielectric insulating film 13 thereon at intervals, exposing the N-type doping
  • the opening 14 is formed on the silicon substrate; wherein, the laser absorption amount D1 of the first semiconductor layer to be removed is more than 70% of the total absorption amount of each film layer.
  • the conditions for the first laser ablation include: using an ultraviolet pulse laser with a wavelength of approximately 355 nm and a pulse width of 15 nanoseconds with partially overlapping scanning spots.
  • the spot formed by the laser used on the back 01 is circular, as shown in Figure 5a.
  • the laser used is spatially shaped into a flat-top laser.
  • PECVD full-area coverage is used to prepare the second semiconductor layer on the back 01, that is, the intrinsic silicon layer 21 and the P-type doped silicon layer 22 are sequentially formed, and the PECVD method is used to sequentially prepare passivation on the light-receiving surface 02.
  • Chemical film layer 41 intrinsic amorphous silicon
  • doped film layer 42 N-type amorphous film layer
  • anti-reflection film layer 43 silicon nitride
  • step (f) Perform a second laser ablation on the back surface 01 obtained in step (e), and perform two laser exposure ablations to remove the second semiconductor layer and part of the dielectric insulating film 13 below it and part of the top N-type doped layer at the bottom.
  • the hybrid silicon crystal layer 12 forms the opening 23 without chemical etching; in the first laser exposure ablation, the laser absorption amount D 201 of the second semiconductor layer to be removed is more than 70% of the total absorption amount of each film layer; In the secondary laser exposure ablation, the laser absorption D 202 of removing the lower dielectric insulating film 13 and the bottom part of the top N-type doped silicon layer is more than 50% of the total absorption of each layer.
  • the conditions for the second laser ablation include: using a green light pulsed laser with a continuous opening of a wavelength of about 532 nm and a pulse width of 20 picoseconds, which can avoid the decrease in power generation efficiency caused by laser damage.
  • the spot formed by the laser used on the back side is rectangular, and adjacent laser spots partially overlap.
  • the laser used is spatially shaped into a rectangular flat-top laser to ensure that the energy in the processing area tends to be consistent.
  • the third laser ablation condition includes: using a pulsed laser with a laser wavelength of 355 nanometers and a pulse width of 10 nanoseconds.
  • the spot formed by the laser used on the back 01 is circular.
  • the tunnel oxide layer 11 the N-type doped silicon crystal layer 12 (N-type doped polysilicon), the intrinsic silicon layer 21 (intrinsic amorphous silicon) and the P-type doped silicon layer 22 (P-type doped non-crystalline silicon)
  • the thickness ratio of crystalline silicon is 1:88:2.9:4.
  • the ratio of the surface doping index of the N-type doped silicon layer 12 to the surface doping index of the P-type doped silicon layer 22 is 0.3:1, where the surface doping index is the effective doping concentration of the corresponding doped layer and The ratio of the doped layer thickness.
  • the resulting jointly passivated back contact battery was tested for short circuit current Isc, open circuit voltage Voc, fill factor FF, and conversion efficiency Eta, and the yield and material cost of the batch were measured. The results are shown in Table 1.
  • a laser with a wavelength of approximately 532 nm is incident on the back of the jointly passivated back contact cell obtained in Example 1, and the E 2 (square value of electric field intensity) distribution of the formed laser in the first semiconductor layer and the second semiconductor layer is shown in Figure 7 .
  • the optical absorption experienced by the first semiconductor is more than 4-5 times that of the bottom layer, and the thickness of the dielectric insulating film 13 can be adjusted accordingly to ensure that the second semiconductor layer is effectively opening while requiring no additional chemical smoothing correction.
  • the comparison chart of the minority carrier lifetime of the combined passivated back contact battery and the TOPCON passivation method and the traditional heterojunction passivation method is shown in Figure 8.
  • the surface passivation ability of N-type passivated TOPCON is equal to or stronger than the passivation ability of heterojunction films.
  • the doping film layer 42 is an N-type oxygen-containing microcrystalline film layer. And carry out corresponding tests, the results are shown in Table 1.
  • the difference is that the P-type doped silicon layer 22 is composed of an incubation layer, a P-type oxygen-containing microcrystalline layer and a P-type oxygen-free microcrystalline layer.
  • the thickness ratio of the oxygen microcrystalline layer and the incubation layer is 1:2.5:0.5. And carry out corresponding tests, the results are shown in Table 1.
  • the first semiconductor layer is composed of intrinsic amorphous silicon prepared at low temperature and N-type doped amorphous silicon, and the thickness ratio and surface doping index of each layer are the same as those in Embodiment 1. ; And its preparation or etching method refers to CN114068731A. And carry out corresponding tests, the results are shown in Table 1.
  • the specific back contact cell includes a crystalline silicon substrate (N-type doped silicon substrate), and its light-receiving surface is a tunnel oxide layer, a thin film silicon layer, and Low-temperature process anti-reflective film layer, with a tunnel oxide layer on the backlight surface, p-type and n-type heavily doped amorphous silicon layers at intervals on the tunnel oxide layer, p-type and n-type heavily doped amorphous silicon layers
  • the silicon layer is provided with a transparent conductive film layer and a metal electrode layer in sequence; the thickness and effective doping concentration of the crystalline silicon substrate, tunnel oxide layer, p-type and n-type heavily doped amorphous silicon layer are the same as those in the embodiment. 1.
  • Its preparation method refers to CN110634961A. And carry out corresponding tests, the results are shown in Table 1.
  • Example number Isc/KA Voc/V FF Eta Yield Material cost/yuan/piece Example 1 1 1 1 1 100% 0.95
  • Example 2 1 1 0.99 0.99 92% 1.2
  • Example 3 0.99 1 0.98 0.97 97% 0.96
  • Example 4 1 0.99 0.97 0.96 97% 0.94
  • Example 5 1.01 1 1 1.01 100% 0.95
  • Example 6 1 1.002 1.005 1.007 95% 1.1 Comparative example 1 1 1 0.99 0.99 95% 1.2 Comparative example 2 1.022 0.962 1 0.983 100% 0.95
  • Example 1 and Example 2 it can be seen from Example 1 and Example 2 that adopting the preferred preparation method for laser ablation of the present application is more conducive to improving the filling factor FF, conversion efficiency Eta and yield. It can be seen from Example 1 and Examples 3-4 that adopting the scheme of the present application to optimize the structure of the first semiconductor layer and the second semiconductor layer is more conducive to the overall electrical conversion efficiency. It can be seen from Example 1 and Example 5 that adopting the solution of doping the film layer preferred in this application is more conducive to improving the short-circuit current Isc and the conversion efficiency Eta.
  • Example 6 of the present application is more conducive to improving the open circuit voltage Voc, fill factor FF, and conversion efficiency of the battery compared to Example 1 Eta; from the perspective of balancing cost and conversion efficiency, adopting the solution of the preferred embodiment 1 of the present application is more conducive to balancing manufacturing cost stability and conversion efficiency, and is most beneficial to promoting the mass production of heterojunction back contacts.
  • the optical absorption amount of the first semiconductor layer and the second semiconductor layer and the relative selectivity of the two are shown in Table 2.
  • the relative selectivity is characterized by a selectivity ratio. The higher the selectivity ratio, the easier it is to remove the upper second semiconductor layer without damaging the first semiconductor layer close to the substrate.
  • the selectivity ratio is calculated as: absorption amount of the second semiconductor layer/absorption amount of the first semiconductor layer.
  • the thickness of the dielectric insulating film can ensure that the upper second semiconductor layer can be more easily removed during laser ablation without damaging the first semiconductor layer close to the substrate.

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Abstract

本申请属于背接触电池技术领域，具体涉及一种联合钝化背接触电池及其制备方法，包括具有受光面和背面的N型掺杂硅基底，设置在背面的第一半导体层和第二半导体层，所述第二半导体层包括沿垂直背面向外的方向依次设置的本征硅层和P型掺杂硅层，所述第一半导体层包括沿垂直背面向外的方向依次设置的隧穿氧化层和N型掺杂硅晶层。本申请联合钝化背接触电池相比于常规异质结电池，能够显著提升填充因子FF和光电转换效率以及良率等，且制备方法相对简单，可工业化，利于提升量产效率。

Description

一种联合钝化背接触电池及其制备方法
相关申请的交叉引用
本申请要求于2022年9月16日提交中国国家知识产权局的申请号为202211125435.X、名称为“一种联合钝化背接触电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于背接触电池技术领域，具体涉及一种联合钝化背接触电池及其制备方法。
背景技术
Sanyo在1994申请了HIT(异质结)光伏电池技术，其特征是工艺制造比较简洁，只有制绒清洗、CVD镀膜、ITO镀膜和银浆印刷等步骤。相比于其他目前占主导地位的高温扩散为特征的光伏制造技术，异质结技术具有低表面复合速率和高开路电压等特征，但其对表面的接触损伤比较敏感。背接触电池没有常规电池的光学遮挡，其结构特征在于把电极全部转移到电池背面。由于背接触技术在发电效率和外观上的独特优势，Panasonic异质结部门从2014开始，陆续投入异质结低温背接触技术的发展，但是目前为止，背面电极开口的技术由油墨印刷和化学蚀刻为主，降本的空间比较有限，因此至今在量产推广上存在障碍。同时，采用背接触技术路线的工艺路线较复杂，频繁的电池表面接触对表面钝化造成损伤一方面不利于降低电池的生产成本，另一方面也不利于提升量产效率，据估算每增加一道印刷工艺，电池绝对效率降低0.2％。由此，背接触技术在量产推广上的关键是减少生产步骤，减少机械接触带来的效率损伤。
激光对电池表面的加工，属于非接触方式，能够减少电池因加工技术带来的效率降低。目前，激光在其他类型的电池生产上已经获得了应用，包括PERC的背面金属接触开口，TOPCON的selective emitter，IBC的背电极开口，这些工艺已经取得了足够的产业化进展。但传统的异质结技术普遍采用低温工艺，异质结技术怕高温和机械磨损的弱点限制了HBC(异质结背接触电池)的发展，尤其限制了具成本优势的激光技术的导入。由于非晶硅薄膜对激光加工导入的热效应敏感，激光在异质结背接触技术路线的配置需要独立研究和优化。
CN114068731A为申请人前期的研究成果，提供了一种以低激光损伤为特征的背接触异质结太阳能电池及其制备方法。通过设置激光吸收牺牲层，对激光进行吸收，减少激光对第一导电型膜的损伤，但是凡是薄膜层都有针孔缺陷，造成漏电。且由于所采用的太阳能结构仍然基于的是传统的HIT技术所构建的，激光热效应仍然会影响非晶硅薄膜的性能，由此使得无法更充分发挥异质结结构光电转换效率优势。
TOPCON是和异质结技术相似的高效钝化技术，其特点是优质氧化硅作为隧穿氧化层，与之接触的多晶硅进行磷掺杂形成收集电子的N电极，与之接触的多晶硅进行硼掺杂形成收集空穴的P电极。美国SUNPOWER发明了首个商业化IBC电池技术，并于2009年将隧穿氧化层钝化技术正式导入量产。之后欧洲的Fraunhofer在学术上推广了这种技术，在小尺寸上获得了高于26.0％的转化效率，并正式命名为POLO或TOPCON技术。TOPCON技术相关钝化膜层采用高温技术生长获得，对技术加工的衰减不敏感，可以极大降低工程设计的复杂度。
总之，由于异质结本身是低温工艺(低于200℃)，所生长膜层对激光的热效应较敏感，耐腐蚀能力不强，另外需要多种复杂物理或化学方式组合开口，造成针孔缺陷较普遍，从而导致实际填充因子FF和光电转换效率较为低下，良率低。
发明内容
本申请的目的是为了克服现有技术存在的传统异质结背接触电池的实际填充因子FF和光电转换效率以及良率低且工艺复杂的缺陷，提供一种联合钝化背接触电池及其制备方法，该联合钝化背接触电池相比于常规异质结电池，能够显著提升填充因子FF和光电转换效率以及良率等，且制备方法相对简单，可工业化，利于提升量产效率。
为了实现上述目的，第一方面，本申请提供了一种联合钝化背接触电池，包括具有受光面和背面的 N型掺杂硅基底，设置在背面的第一半导体层和第二半导体层，所述第二半导体层包括沿垂直背面向外的方向依次设置的本征硅层和P型掺杂硅层，所述第一半导体层包括沿垂直背面向外的方向依次设置的隧穿氧化层和N型掺杂硅晶层。
在一些优选实施方式中，所述本征硅层与所述隧穿氧化层的厚度比为1.2-11:1，优选1.5-5:1。
在一些更优选实施方式中，所述隧穿氧化层、N型掺杂硅晶层、本征硅层与P型掺杂硅层的厚度比为1:11-300:1.2-11:3-50，优选1:20-100:1.5-5:4-20。
在一些优选实施方式中，所述N型掺杂硅晶层的面掺杂指数与P型掺杂硅层的面掺杂指数的比值为0.07-40:1，优选0.07-20:1，更优选0.07-5:1，进一步优选0.07-1:1；其中，面掺杂指数为相应掺杂层的有效掺杂浓度与该掺杂层厚度的比值。
在一些优选实施方式中，所述本征硅层为本征非晶硅，所述P型掺杂硅层为P型掺杂非晶硅或P型掺杂微晶硅，所述N型掺杂硅晶层为N型掺杂多晶硅。
在一些实施方式中，所述P型掺杂硅层包括孵育层，及P型含氧微晶层与P型无氧微晶层，其中P型含氧微晶层与P型无氧微晶层的厚度比为1:0.25-7。
在一些优选实施方式中，所述P型掺杂硅层为P型掺杂非晶硅。
在一些优选实施方式中，所述N型掺杂硅基底为直拉单晶或铸锭单晶。
在一些优选实施方式中，所述N型掺杂硅基底的受光面为制绒面，背面为抛光面。
在一些优选实施方式中，所述联合钝化背接触电池还包括：
介电绝缘膜，其设置在所述第一半导体层表面，且所述第一半导体层及其上的介电绝缘膜作为整体沿背面平行方向间隔排布，所述第二半导体层设置在所述介电绝缘膜的表面且覆盖所述间隔处表面，且在相邻间隔之间的第二半导体层上开设有暴露第一半导体层的开口；
透明导电膜，其设置在所述第二半导体层表面以及在所述开口处暴露的第一半导体层表面，且在相邻的间隔和开口之间的透明导电膜上开设有裸露第二半导体层的绝缘槽；
钝化膜层、掺杂膜层和减反膜层，其均设置在所述受光面的表面且沿受光面垂直向外方向依次设置。
更优选地，所述钝化膜层为本征非晶硅；所述掺杂膜层为N型非晶膜层或N型含氧型微晶膜层；所述减反膜层为氮化硅、二氧化硅、氧化硅、氮氧化硅中的至少一种。
第二方面，本申请提供一种第一方面所述联合钝化背接触电池的制备方法，包括以下步骤：
S101、提供N型掺杂硅基底；
S102、在所述N型掺杂硅基底的背面依次镀第一半导体层、介电绝缘膜，第一半导体层包含隧穿氧化层和N型掺杂硅晶层；
S103、在S102所得N型掺杂硅基底的背面间隔的蚀刻开孔，以间隔的移除背面的第一半导体层及其上的介电绝缘膜，再进行清洗，得到间隔排布的第一半导体层和介电绝缘膜；
S104、然后在S103所得N型掺杂硅基底的背面全覆盖的形成第二半导体层，第二半导体层包含本征硅层和P型掺杂硅层；其中，在开孔及其上的第二半导体层处形成第二导电区；
S105、在S104所得N型掺杂硅基底的背面蚀刻开口，以在相邻间隔之间的部分第二半导体层上暴露第一半导体层，再进行清洗，形成与第二导电区交替排布的第一导电区；
S106、然后在S105所得N型掺杂硅基底的背面沉积透明导电膜；再在位于所述开口和开孔之间的透明导电膜上蚀刻绝缘槽；并在所述开孔表面形成第一电极，在所述开口表面形成第二电极；
S107、在所述N型掺杂硅基底的受光面依次形成钝化膜层、掺杂膜层和减反膜层。
在一些优选实施方式中，所述蚀刻采用激光消融结合任选的化学腐蚀的方式，其中，移除第一半导体层、第二半导体层或透明导电膜分别通过激光消融的方式，移除介电绝缘膜采用激光消融或化学腐蚀的方式。
在一些更优选实施方式中，S103中，所述蚀刻开孔中移除第一半导体层采用连续扫描光斑部分交叠的第一激光消融方式，其中，待移除第一半导体层的激光吸收量D 1为各膜层总吸收量的70％以上。
进一步优选地，所述第一激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于20纳秒；所用激光在背面形成的光斑为圆形、椭圆形或矩形；所用激光经过空间整形为方形、圆形或椭圆形平顶激光。
在一些更优选实施方式中，S105中，所述蚀刻开口中移除第二半导体层采用非连续开孔或连续开孔的第二激光消融方式。其中，在采用非连续开孔的方式时，所形成的光斑不交叠，待移除第二半导体层的激光吸收量D 2为各膜层总吸收量的70％以上、优选80％以上；在采用连续开孔的方式时，所形成的光斑部分交叠，其中在相邻光斑的第一次激光曝光消融移除顶部的第二半导体层，此时移除相应层所需的激光吸收量D 201为各膜层总吸收量的70％以上；部分光斑交叠引起的第二次激光曝光消融移除下方的介电绝缘膜以及底部的部分顶部N型掺杂硅晶层，此时移除相应层所需的激光吸收量D 202为各膜层总吸收量的50％以上。
进一步优选地，所述第二激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于20纳秒；所用激光在背面形成的光斑为圆形、椭圆形或矩形；所用激光经过空间整形为矩形、圆形或椭圆形平顶激光。
在一些更优选实施方式中，S106中，所述蚀刻绝缘槽采用连续扫描光斑部分交叠的第三激光消融方式，待蚀刻透明导电膜以及与其交叠的第二半导体层的激光吸收量D 3为各膜层总吸收量的70％以上、优选85％以上。
进一步优选地，所述第三激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于100纳秒；所用激光在背面形成的光斑为圆形、椭圆形或矩形。
如前文背景技术所述，本申请发明人发现，采用激光蚀刻是异质结背接触电池技术走向量产的可行方案，可以极大简化背接触技术的工艺流程。然而，传统异质结背接触电池采用激光时不稳定，以非晶硅为主的异质结薄膜，在温度超过220℃时会发生显著的变化，如本征非晶硅与N型非晶/微晶硅激光加工后氢原子会大幅外溢，导致少子寿命下降；为了避免这种热衰减，需要复杂的工程学设计；且良率低，且工艺制备复杂，无法实现较低成本的量产及获得高光电转化效率的成品。
而TOPCON工艺虽然可采用高温激光，且导电性好，可以达到和异质结钝化相匹配的钝化水平，但其实践钝化水平还是较异质结低，尤其是第二半导体负责钝化的电极区域是制约其电性的瓶颈，开路电压大致在710-730毫伏，低于异质结典型的745毫伏。相对于传统异质结电池能达到的光电转化性能仍处于劣势。
传统异质结钝化工艺和TOPCON工艺所采用的设备属于两种不同的设备体系，现有技术中通常分别对两种工艺进行各自独立研究、改进。本申请创新性的首次将传统异质结钝化结构和TOPCON结构相结合，形成了联合钝化的背接触电池，采用隧穿氧化层和N型掺杂硅晶层(TOPCON钝化膜层)作为第一半导体层，而第二半导体层采用传统异质结钝化膜层，即将TOPCON和异质结有机结合实现联合钝化，用高温制程的TOPCON钝化膜层替代常规异质结钝化膜层，研究发现，采用上述结构的背接触电池结构，可以拓展工艺窗口，相比于常规异质结电池，提高良率和最终转化效率，同时能够显著提升填充因子FF的转化效率(在一些具体实例中能够提升3％以上)。
在本申请优选的制备方法中，特定结构的第一半导体层耐高温(800-870℃)，高温激光消融制备的第一半导体层能使得后续的针对第二半导体层开口，或者绝缘槽形成工艺等制备工艺的耐受温度高，从而使得背面全程制备工艺与激光加工技术有较高的契合度，使得背面各开口或开孔等均能采用激光消融方式，其稳定性好；能实现量产，且制作方法简单，良率高，材料成本低，不需要传统异质结背接触电池制备方法中曝光显影腐蚀及光阻材料等。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1a是常规异质结背接触电池B与本申请联合钝化背接触电池C的理论预测电学性能JSC的对比图；
图1b是常规异质结背接触电池B与本申请联合钝化背接触电池C的理论预测电学性能Voc的对比图；
图1c是常规异质结背接触电池B与本申请联合钝化背接触电池C的理论预测电学性能填充因子FF的对比图；
图1d是常规异质结背接触电池B与本申请联合钝化背接触电池C的理论预测电学性能转化效率的对比图。
图2是本申请联合钝化背接触电池的一种具体实施方式的俯视图。
图3是图2中A-A剖视图。
图4a是本申请联合钝化背接触电池中制备第一半导体层和第二半导体层的工艺流程图；
图4b是图4a的后续制备工艺流程图。
图5a是背面蚀刻开孔形成的第一种近圆形的激光束斑扫描方式，其中相邻光斑部分交叠，次相邻光斑不交叠；
图5b是背面蚀刻开孔形成的第二种近方形的激光光斑扫描方式，其中相邻光斑部分重叠，次相邻光斑不交叠；
图5c是背面蚀刻开孔形成的第三种近方形的激光光斑扫描方式，其中第一列扫描光斑不交叠，第二列回扫的光斑在移动轨迹方向上前后不交叠，但是第一列光斑和第二列光斑部分交叠。
图6a是背面蚀刻开口形成的第一种单列矩形的非连续激光束斑扫描方式；
图6b是背面蚀刻开口形成的第二种双列矩形的非连续激光束斑扫描方式。
图7是本申请实施例1得到的电池背面入射约532nm波长的激光，形成的激光在第一半导体层和第二半导体层的E 2(电场强度平方值)分布图；其中X为以基底背面为起始零点的厚度。
图8是本申请实施例1的联合钝化背接触电池与采用TOPCON钝化方式和传统异质结钝化方式的少子寿命对比图。其中，“a-Si 2-side”样品为基底双面都采用异质结钝化，“TOPCON/a-Si”样品为本申请实施例1的联合钝化背接触电池，“TOPCON 2-side”样品为基底双面都采用TOPCON钝化。其中少子寿命采集在载流子密度为5e15/cm 3的情况下取得。
附图标记说明
00、N型掺杂硅基底，01、背面，02、受光面；10、牺牲层，11、隧穿氧化层，12、N型掺杂硅晶层，13、介电绝缘膜，14、开孔；21、本征硅层，22、P型掺杂硅层，23、开口；30、透明导电膜，31、绝缘槽；41、钝化膜层，42、掺杂膜层，43、减反膜层；51、细栅线，52、主栅线。
具体实施方式
在本文中所披露的范围的端点和任何值都不限于该精确的范围或值，这些范围或值应当理解为包含接近这些范围或值的值。对于数值范围来说，各个范围的端点值之间、各个范围的端点值和单独的点值之间，以及单独的点值之间可以彼此组合而得到一个或多个新的数值范围，这些数值范围应被视为在本文中具体公开。
传统上背接触电池通过掩模在背面上蚀刻形成P型电极和N型电极，最后形成交叉指状的电极结构。不同于高温扩散为特征的IBC或TBC，异质结钝化层为特征的HBC对表面的接触和机械损伤比较敏感，尤其是首先制备的第一半导体层会经历多重包括激光工艺的高温热处理，及化学清洗腐蚀步骤。而本申请用高温制程的TOPCON钝化膜层替代常规异质结钝化膜层，作为第一半导体层，可以拓展工艺窗口，提高良率和最终转化效率。
具体的，第一方面，本申请提供了一种联合钝化背接触电池，包括具有受光面和背面的N型掺杂硅基底，设置在背面的第一半导体层和第二半导体层，所述第二半导体层包括沿垂直背面向外的方向依次设置的本征硅层和P型掺杂硅层，所述第一半导体层包括沿垂直背面向外的方向依次设置的隧穿氧化层和N型掺杂硅晶层。
可以理解的是，所述第二半导体层与所述的N型掺杂硅基底之间的结是异质结。
图1a、图1b、图1c、图1d显示了常规异质结背接触电池与本申请提供的联合钝化背接触电池的相关理论预测光电转换性能。从图中可知，联合钝化背接触电池的填充因子FF和光电转化效率均获得了提高，其中填充因子获得了显著的提高。图1a、图1b、图1c、图1d为理论模拟值，其中填充因子FF的提升是由于TOPCON技术导入引起的第一半导体层导电性提升。在实际实验电性的对比中，FF提升更为明显，是因为激光开口消除了针孔漏电的可能性。
在一些优选实施方式中，所述本征硅层与所述隧穿氧化层的厚度比为1.2-11:1，优选1.5-5:1。本申 请的优选方案中，隧穿氧化层相比于本征硅层具有以上适宜的薄厚程度，更利于提升背接触电池的电性转化效率；推测其原因可能在于，相对适宜的厚度的隧穿氧化层提供的界面缺陷更少，杂质能级在高温退火中湮灭，其导电机理是通过量子隧穿或偶然出现的针孔缺陷。而在传统异质结电池结构中，主要的钝化有一层氢化的非晶硅提供，其本身也有一定的导电能力，电子或空穴通过这层非晶硅中的带隙杂质能级跃迁。
在一些更优选实施方式中，所述隧穿氧化层、N型掺杂硅晶层、本征硅层与P型掺杂硅层的厚度比为1:11-300:1.2-11:3-50，优选1:20-100:1.5-5:4-20。本申请的优选方案中，更利于提升背接触电池的FF，推测其原因可能在于，本申请的TOPCON第一半导体层的引入，载流子可以先横向传导(由于数百倍的导电性提升)再垂直收集，开口率的设计有更大的自由度，引入的高温多晶迁移率可以到200-300，且本申请中的高温多晶可以任意增加膜层厚度，对整个背接触电池的导电性和FF有显著提升。而传统异质结的非晶的载流子迁移率较低(以电子为例，迁移率大致在0.5-1)，微晶硅稍有提升，在10左右；且传统的非晶硅薄膜，增加膜层的厚度电池的FF反而有可能下降。
在一些优选实施方式中，所述N型掺杂硅晶层的面掺杂指数与P型掺杂硅层的面掺杂指数的比值为0.07-40:1，优选0.07-20:1，更优选0.07-5:1，进一步优选0.07-1:1；其中，面掺杂指数为相应掺杂层的有效掺杂浓度与该掺杂层厚度的比值。本申请的优选方案中，更利于提升背接触电池总体的电性转化效率，推测其原因可能在于，本申请第一半导体层中引入的相对适宜的面掺杂指数的N型掺杂硅晶层，使得高温多晶可以保证有限掺杂和名义掺杂几乎完全一致，即所有的磷单质都被激活。而传统的非晶硅膜层尤其是B掺杂的P型非晶薄膜，膜层中B被激活的极少，只有名义掺杂的5-7％，其他都体现为膜层的缺陷。
在满足本申请第一半导体层和第二半导体层中的上述厚度比和/或面掺杂指数比的基础上，本领域技术人员可以根据实际需求选择各层的厚度和有效掺杂浓度。
示例性的，在一些实施方式中，所述隧穿氧化层的厚度为10-22埃，优选厚度为15-20埃。该优选方案下，能够保证最优钝化和导电性的平衡，同时工艺简洁可控，其原因在于自然界本征氧化硅层(native oxide)的厚度饱和值在15-20埃，厚度不至于不可控上升。
示例性的，在一些实施方式中，所述N型掺杂硅晶层的厚度为30-250nm，有效掺杂浓度大于5e18cm -3。更优选地，所述N型掺杂硅晶层的厚度为150-200nm，有效掺杂浓度为1e19-8e19cm -3。在本申请的优选方案下，第一半导体的横向导电性极大增强，可以消除载流子平均自由程不够长和透明导电膜导电性不强的自然或设计上的波动，保证了FF的最大化。本领域技术人员可以根据需求选择所述N型掺杂硅晶层的方阻，例如方阻可以为30-200Ω/□，优选为40-70Ω/□。
示例性的，在一些实施方式中，所述本征硅层的厚度为3-10nm；所述P型掺杂硅层的厚度为7-45nm，有效掺杂浓度为2e18-1e20cm -3。在本申请的优选方案下，能够保证器件的垂直导电性，同时较弱的P型第二半导体和极强导电性搭接时不会造成器件的短路。
本申请所述N型掺杂硅基底的厚度，本领域技术人员可以根据需求选择，其厚度优选为110-150微米。在本申请的优选方案下，能够达到最高发电效率，同时硅料使用最为经济可行。
在本申请中，所述第二半导体层中的本征硅层是氢化本征非晶硅薄膜(传统异质结膜层)。
在一些实施方式中，所述P型掺杂硅层为P型掺杂非晶硅。该方案，属于传统异质结技术，具有成本较低的优势。
在一些实施方式中，所述P型掺杂硅层为P型掺杂微晶硅，其成本高昂，在背接触中益处不大，同时很难通过HF酸的腐蚀破环。
在一些实施方式中，所述P型掺杂硅层包括孵育层，及P型含氧微晶层与P型无氧微晶层，P型含氧微晶层与P型无氧微晶层的厚度比为1:0.25-7。该优选方案下，适宜厚度比的P型含氧微晶层与P型无氧微晶层，更利于提升电池的开路电压Voc、填充因子FF、转换效率Eta；推测其原因可能在于，含氧微晶层的导电性较弱，适宜的膜厚和德拜长度相当，对电性的提升可充分达成，无氧微晶层需要渐变过渡，起到对含氧微晶层的化学保护作用。
本领域技术人员可以根据实际需求选择所述孵育层的厚度，其不需要付出创造性劳动；示例性的， P型含氧微晶层与孵育层的厚度比为1:0.1-20。
在一些实施方式中，所述N型掺杂硅晶层为N型掺杂多晶硅。该N型掺杂多晶硅可以是直接形成多晶硅，或者由微晶硅、非晶硅膜层通过高温改性形成，该高温改性过程至少包含600℃以上的一步或多步工艺。
本申请所述隧穿氧化层优选为隧穿氧化硅。
在一些优选实施方式中，所述N型掺杂硅基底为直拉单晶或铸锭单晶。
在一些优选实施方式中，所述N型掺杂硅基底的受光面为制绒面，背面为抛光面。该优选方案，能够满足背面激光加工一致性的要求，使得激光加工面为抛光结构，而不是传统的制绒陷光结构。
本申请所述联合钝化背接触电池还可以包括其他本领域的常规部件，例如在第一半导体层和第二半导体层之间部分设置的绝缘层，在第二半导体层上方设置的导电层等，在背面形成细栅线、主栅线及焊接用焊盘等金属化图形，以及在受光面设置的钝化层等。
在一些优选实施方式中，所述联合钝化背接触电池还包括：
介电绝缘膜，其设置在所述第一半导体层表面，且所述第一半导体层及其上的介电绝缘膜作为整体沿背面平行方向间隔排布，所述第二半导体层设置在所述介电绝缘膜的表面且覆盖所述间隔处表面，且在相邻间隔之间的第二半导体层上开设有暴露第一半导体层的开口；
透明导电膜，其设置在所述第二半导体层表面以及在所述开口处暴露的第一半导体层表面，且在相邻的间隔和开口之间的透明导电膜上开设有裸露第二半导体层的绝缘槽。在该优选方案下，在第一半导体层和第二半导体层之间设置介电绝缘膜能防止器件的漏电，且设置了背接触电池所需的开口和绝缘槽，能避免第一半导体层和第二半导体层之间的电短路，还避免了机械接触带来的损伤，同时可避免介电绝缘膜的针孔缺陷，提升电池的发电转换效率。其中，开口和绝缘槽的整体排布，本领域技术人员可以根据需求设置，例如可以通过调节光斑的交叠程度或光斑的大小的方式。
可以理解的是，在上述优选实施方式中，背面由包括第二半导体和N型掺杂硅基底直接接触的区域、包括第一半导体和N型掺杂硅基底直接接触的区域、及两者之间的过渡区域；在过渡区域的垂直N型掺杂硅基底且向外的方向包括依次分布的第一半导体层、介电绝缘膜、第二半导体层。在上述各区域中还包括位于背面表面的透明导电膜，且在绝缘槽处不包括透明导电膜。
本申请中，应当理解的是，所述联合钝化背接触电池还包括在所述第一半导体层上方和第二半导体层上方形成的两个电极。在一些更优选实施方式中，所述联合钝化背接触电池还包括：第一栅线，其设置在所述间隔处表面的第二半导体层上方；形成第一金属电极；第二栅线，其设置在所述开口处的第一半导体层上方；形成第二金属电极。
在一些更优选实施方式中，所述联合钝化背接触电池还包括：钝化膜层、掺杂膜层和减反膜层，其均设置在所述受光面的表面且沿受光面垂直向外方向依次设置。
在上述优选实施方式中，可以理解的是，第二半导体层基本全面覆盖在背面具有间隔的介电绝缘膜之上(覆盖区间包括间隔的底部和侧面)，仅在相邻间隔之间设有所述开口。
本领域技术人员可以根据实际需求选择所述介电绝缘膜、透明导电膜的成分和厚度等，以及所述钝化膜层、掺杂膜层和减反膜层的各层厚度，其不需要付出创造性劳动，在此不再赘述。
在一些具体实施方式中，所述钝化膜层为本征非晶硅，所述掺杂膜层为N型非晶膜层或N型含氧型微晶膜层、优选为N型含氧型微晶膜层，所述减反膜层为氮化硅、二氧化硅、氧化硅、氮氧化硅中的至少一种。该实施方式中更利于提高太阳光的透过率。
本领域技术人员可以根据实际需求选择开设的绝缘槽、开口以及开孔在其相应膜层上的面积占比。本申请中绝缘槽、开口以及开孔的占比或比例均以面积计。
第二方面，本申请提供一种第一方面所述联合钝化背接触电池的制备方法，包括以下步骤：
S101、提供N型掺杂硅基底；
S102、在所述N型掺杂硅基底的背面依次镀第一半导体层、介电绝缘膜，第一半导体层包含隧穿氧化层和N型掺杂硅晶层；
S103、在S102所得N型掺杂硅基底的背面间隔的蚀刻开孔，以间隔的移除背面的第一半导体层及 其上的介电绝缘膜，再进行清洗，得到间隔排布的第一半导体层和介电绝缘膜；
S104、然后在S103所得N型掺杂硅基底的背面全覆盖的形成第二半导体层，第二半导体层包含本征硅层和P型掺杂硅层；其中，在开孔及其上的第二半导体层处形成第二导电区；可以理解的是，开孔处的第二半导体层和N型掺杂硅基底直接接触；
S105、在S104所得N型掺杂硅基底的背面蚀刻开口，以在相邻间隔之间的部分第二半导体层上暴露第一半导体层，再进行清洗，形成与第二导电区交替排布的第一导电区；
S106、然后在S105所得N型掺杂硅基底的背面沉积透明导电膜；再在位于所述开口和开孔之间的透明导电膜上蚀刻绝缘槽；并在所述开孔表面形成第一电极，在所述开口表面形成第二电极；
S107、在所述N型掺杂硅基底的受光面依次形成钝化膜层、掺杂膜层和减反膜层。
本申请中，所述第二半导体层可以采用PECVD或Hot-wire方式形成，所述第一半导体层可以采用PECVD或Hot-wire方式形成，所述钝化膜层、掺杂膜层和减反膜层可以采用PECVD或Hot-wire方式形成。
S101中还包括：通过化学清洗清洁N型掺杂硅基底，其中化学清洗例如可以采用碱液。
在一些具体实施方式中，S101的过程包括：直拉单晶或铸锭单晶经过金刚线或砂浆切割，形成厚度为100-250微米的硅片基底；可选的硅片还通过槽式溶液进行预清洁，除去表面的有机污染和大型颗粒，然后用碱液去损伤和制绒，形成粗糙化的陷光结构，再经过RCA清洁(或等效于RCA清洁的溶液配方)，最后通过HF溶液去表面氧化层，再通过去离子水清洁及表面干燥去水过程。其中，虽然铸锭单晶的单晶比例较高，但是电池内部仍有较大比例的多晶晶界和晶格缺陷；如果使用的基底为铸锭单晶硅片，在导入异质结生产工艺之前，需要经过不同温度段的预处理以达到吸杂和悬挂键饱和的效果，其均属于本领域成熟的现有技术，在此不再赘述。
在一些具体实施方式中，S101中还包括：使得N型掺杂硅基底具有单面制绒、单面抛光结构。更优选地，其过程包括：用氮化硅或氧化硅膜层在受光面做保护牺牲层，保持基底受光面的绒面陷光结构而实现背面抛光，使得N型掺杂硅基底的受光面为制绒面，背面为抛光面。
在一些具体实施方式中，S102中镀第一半导体层的过程可以为：采用湿法氧化、干法氧化或等离子体氧化，在所述N型掺杂硅基底的背面形成一层隧穿氧化层；再用LPCVD(低压力化学气相沉积)、PECVD(等离子体增强化学的气相沉积)或PVD(物理气相沉积)的方法，在所述隧穿氧化层的表面制备一层硅膜层，并对所述多晶膜层进行磷掺杂(磷掺杂可以用原位掺杂的方式或者高温磷扩的方式实现)，形成N型掺杂硅晶层，从而得到第一半导体层。
其中，隧穿氧化层的形成，具体可以通过湿法氧化，包含臭氧氧化法、硝酸氧化法、双氧水氧化法等，比如在加热的溶液中通入氧气、臭氧或双氧水；比如把硅片浸泡在加热的硝酸溶液中；还可以通过干法氧化，包含热氧化法、PECVD原位氧化法等，例如把硅片放在炉管式设备中加热至500-700℃，在设备中通入氧气或水蒸气或利用管壁或硅片表面吸附的水汽氧化，优选采用热氧化法，且其条件包括：热氧化温度为550-650℃，气源为氧气，氧化时间为10-30min；还可以通过等离子体辅助氧化。
其中，N型掺杂硅晶层的形成中，原位掺杂的过程例如在生长多晶硅、非晶硅或微晶硅的气体氛围中引入磷源(比如磷烷气体)；高温磷扩的过程例如具体可以为先生长一层多晶硅、非晶硅或微晶硅膜层(例如可以采用PECVD的方式制备，或者采用PVD溅射的方式获得)，经过高温退火，然后用含磷源的扩散炉(比如先在表面沉积一层PSG玻璃)形成磷的有效扩散；优选的采用LPCVD沉积多晶硅、非晶硅或微晶硅膜层后扩散形成，扩散温度为830-880℃，扩散源为三氯氧磷或氧气，扩散时间为80-180min。其均属于本领域成熟的现有技术，在此不再赘述。
S102中镀介电绝缘膜可以采用PECVD方法。
在一些具体实施方式中，S103中，所述蚀刻开孔采用常规光刻的方式，其过程例如可以为：采用光阻材料曝光显影形成保护图案，之后通过湿化学腐蚀光阻材料未保护区域形成开口区，最后去除光阻材料。
在另外一些更优选实施方式中，本申请所述蚀刻采用激光消融结合任选的化学腐蚀(优选湿法化学腐蚀，例如采用含氢氟酸溶液进行化学腐蚀)的方式，其中，移除第一半导体层、第二半导体层或透明 导电膜分别通过激光消融的方式，移除介电绝缘膜采用激光消融或化学腐蚀的方式，其不会对介电绝缘膜造成穿孔现象。
在一些具体优选实施方式中，S103中，所述蚀刻开孔的过程为：用激光束对所述第一半导体层及其上的介电绝缘膜进行第一激光消融，并结合湿法化学腐蚀的方式进行部分开孔，以间隔的移除背面的第一半导体层及其上的介电绝缘膜，用于暴露N型掺杂硅基底。
更优选地，S103中，所述蚀刻开孔中移除第一半导体层采用连续扫描光斑部分交叠的第一激光消融方式，待移除第一半导体层的激光吸收量D 1为各膜层总吸收量的70％以上。本申请的优选方案中，对于待移除第一半导体层能吸收掉大部分激光能量，避免造成N型掺杂硅基底的深度隐裂；这是由于膜层直接吸收的膜层深度和激光波长相关，532nm激光造成的多晶硅直接吸收深度为100-200纳米，355纳米激光照成的多晶硅直接吸收深度为10-20纳米，故可通过将激光大部分集中在待移除第一半导体层上，减小激光作用于基底，避免造成基底的深度隐裂。
本申请中“各膜层总吸收量”是指当下时刻包括基底及其背面各膜层、其受光面的所有膜层的总吸收量。
本领域技术人员可以通过控制激光波长、脉冲宽度、照射时间等来满足上述激光吸收量以及上述比例。更优选地，所述第一激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于20纳秒。更优选地，所用激光在背面形成的光斑为圆形、椭圆形或矩形，可以如图5a、图5b、图5c所示，以各种部分重叠方式排布。更优选地，所用激光经过空间整形为平顶激光，其在加工面上的空间分布为方形、圆形或椭圆形平顶形状，优选矩形。激光波长可以为355纳米左右或532纳米左右。所采用的激光器例如可以为YAG激光器三倍频得到的波长约为355纳米的激光器，或者为YAG激光器二倍频得到的波长约为532纳米的激光器。
本领域技术人员可以根据第一半导体层的厚度，选择紫外或绿光等不同波长的激光进行所述第一激光消融，移除部分第一半导体层，同时避免对N型掺杂硅基底造成过度损伤。其中，波长约为355nm激光对多晶硅或晶硅的吸收深度在10-20纳米，而波长约为532nm激光对多晶硅或晶硅的吸收深度在100-200纳米。优选地，第一激光消融采用波长为355nm的紫外脉冲光源。本申请的第一激光消融的吸收主体为第一半导体层，无需设置CN114068731A的额外光学牺牲层来吸收，从而制备方法简单，可量产工业化。
S104中，所述形成第二半导体层采用PECVD全面积覆盖的方式。PECVD设备电源可以采用13.56MHz、26MHz或40MHz。
本申请可以理解的是，S104中，用第二半导体层全面积镀膜的方式覆盖在部分开孔的背面介电绝缘膜之上；然后在S105中采用激光开孔消除上层的第二半导体层，然后用化学腐蚀的方式去除介电绝缘膜，以暴露底层的第一半导体层。
本领域技术人员可以采用现有方法形成第二半导体层中的本征硅层和P型掺杂硅层；其中形成本征硅层的工艺气体例如可以包含硅烷(SiH 4)、H 2、CO 2和CH 4的全部或几种组合；形成P型掺杂硅层的工艺气体例如可以包含SiH 4、H 2、CO 2、B 2H 6(乙硼烷)或TMB(三甲基硼)的全部或几种组合。
在一些具体实施方式中，S105中，所述蚀刻开口可以采用常规光刻的方式，其过程例如可以为：采用光阻材料曝光显影形成保护图案，之后通过湿化学腐蚀光阻材料未保护区域形成开口区，最后去除光阻材料。
在另外一些更优选实施方式中，S105中，所述蚀刻开口的过程为：用激光束移除背面部分区域的第二半导体层，进行第二激光消融，并用化学腐蚀的方式蚀刻该部分区域下面的介电绝缘膜，得到暴露其下的第一半导体层的开口，以形成与所述第二导电区交替排布的第一导电区。
更优选地，S105中，所述蚀刻开口中移除第二半导体层采用非连续开孔或连续开孔的第二激光消融方式。优选后者。
其中在一种具体实施方式中，在采用非连续开孔的方式时，所形成的光斑不交叠，待移除第二半导体层的激光吸收量D 2为各膜层总吸收量的70％以上、优选80％以上。本申请的该方案中，待移除第二半导体层能吸收掉大部分激光能量，开口截面分界清晰，同时对底层膜层和基底损伤较小或完全无损。 该方案下，可以施加化学腐蚀移除已暴露的介电绝缘膜；或者在原开口位置重复施加二次激光消融移除已暴露的介电绝缘膜，如采用该方式，二次激光消融时N型掺杂多晶层的激光吸收量为各膜层总吸收量的50％以上。
本领域技术人员可以进一步优选介电绝缘膜的厚度和折射率，在第二半导体层所在的垂直空间位置上，形成干涉叠加的效果。
其中，在更优选的实施方案中，在采用连续开孔的方式时，所形成的光斑部分交叠，其中在相邻光斑的第一次激光曝光消融移除顶部的第二半导体层，此时移除相应层所需的激光吸收量D 201为各膜层总吸收量的70％以上；部分光斑交叠引起的第二次激光曝光消融移除下方的介电绝缘膜以及底部的部分顶部N型掺杂硅晶层，此时移除相应层所需的激光吸收量D 202为各膜层总吸收量的50％以上。该优选方案下，连续开孔的第二激光消融方式中，会进行两次激光曝光消融；由于本申请的膜层结构耐高温，故可以通过第二次激光曝光消融移除下方的介电绝缘膜以及底部的部分顶部N型掺杂硅晶层，无需进行化学腐蚀。
本领域技术人员可以通过控制激光波长、脉冲宽度、照射时间等来满足上述激光吸收量以及上述比例。更优选地，所述第二激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于20纳秒、优选小于100皮秒。激光波长可以为355纳米左右或532纳米左右。更优选采用脉冲宽度小于100皮秒的绿光激光。更优选地，所用激光在背面形成的光斑为圆形、椭圆形或矩形(如图6a和图6b所示)，其可以为单列或多列，能够避免激光损伤导致的发电效率下降。更优选地，所用激光经过空间整形为矩形、圆形或椭圆形平顶激光，优选矩形，也即其在加工面上的空间分布为矩形、圆形或椭圆形平顶形状，以保证加工区域内能量趋于一致。所采用的激光器优选为YAG激光器三倍频得到的波长为355纳米的激光器，或者为YAG激光器二倍频得到的波长为532纳米的激光器。
本申请优选方案中，采用第一次激光消融来部分移除第一半导体层，第二次激光消融移除部分第二半导体层，而其下的第一半导体层功能不受破坏，第三次激光消融构建绝缘槽，但是不损伤其下的第二半导体层，稳定性好，良率高。
本申请中，S103、S105中的清洗包括化学清洗和对暴露区域的硅表面的平滑处理，为后续膜层的有效制备提供低缺陷界面。其为本领域的常规技术，在此不再赘述。
S106中，所述沉积透明导电膜可以采用PVD全面积覆盖的方式。本领域技术人员可以根据需求选择PVD的靶材和掺杂材料。例如PVD采用的靶材可以是纯氧化铟，然后在工艺气体中导入氢气或水蒸气，形成氢掺杂的氧化铟薄膜。
在一些具体实施方式中，S106中，所述蚀刻绝缘槽可以采用常规光刻的方式，其过程例如可以为：采用光阻材料曝光显影形成保护图案，之后通过湿化学腐蚀光阻材料未保护区域形成开口区，最后去除光阻材料。
在另外一些更优选实施方式中，S106中，所述蚀刻绝缘槽的过程为：用激光束进行第三激光消融，移除位于第一导电区和第二导电区之间的部分透明导电膜，形成相邻两个导电区之间的绝缘槽。绝缘槽的设置，能够物理绝缘第一导电区的N电极和第二导电区的P电极。
更优选地，S106中，所述蚀刻绝缘槽采用连续扫描光斑部分交叠的第三激光消融方式，待蚀刻透明导电膜以及与其交叠的第二半导体层的激光吸收量D 3为各膜层总吸收量的70％以上、优选85％以上。本申请的优选方案中，光学干涉极大的位置在第二半导体或与其接触的透明导电膜，待蚀刻透明导电膜能吸收掉大部分激光能量，保护底下的介电绝缘膜和第一半导体层完整不受损伤。可以理解的是，该方案下，各膜层总吸收量包括基底以及其上的第一半导体层和第二半导体层以及其下的受光面的各膜层的总吸收量。
本领域技术人员可以通过控制激光波长、脉冲宽度、照射时间等来满足上述激光吸收量以及上述比例。进一步优选地，所述第三激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于100纳秒。激光波长可以约为355纳米。更优选地，所用激光在背面形成的光斑为圆形、椭圆形或矩形。
本申请中所述激光消融可以采用紫外激光、紫光激光或绿光激光。
可以理解的是，本申请S103、S106中，所述连续扫描光斑部分交叠是指形成的光斑中，相邻光斑 交叠。
在一些实施方式中，S106中所述形成第一电极或第二电极的过程包括：在所得N型掺杂硅基底的背面施加导电银浆，形成包括细栅线、垂直于细栅线的主栅线及焊接用焊盘的金属化图形，其有利于实现有效电接触。所述施加导电银浆的方式可以为丝网印刷或喷墨打印的方式。
S107中所述钝化膜层、掺杂膜层和减反膜层可以用PECVD方法沉积。其中，钝化膜层的工艺气体例如可以包含SiH 4、H 2、CO 2和CH 4的全部或几种组合。
下面结合具体实施例对本申请进行进一步详细的阐述。
实施例1
一种如图2、图3所示的联合钝化背接触电池，通过如图4a、图4b所示的下述步骤制备得到：
(a)N型掺杂的直拉单晶硅片基底，通过化学制绒清洗，形成双面制绒结构的N型掺杂硅基底00。
(b)在受光面02镀保护性牺牲层10，通过化学腐蚀背面01抛光，形成受光面02制绒、背面01抛光结构的N型掺杂硅基底00。
(c)然后在背面01制备第一半导体层，并且采用PECVD方法在第一半导体层上方镀介电绝缘膜13；其中，制备第一半导体层的过程包括：先把N型掺杂硅基底00放在炉管式设备中加热至600℃，在设备中通入氧气氧化，氧化时间为10-30min，在背面01上形成隧穿氧化层11；然后采用LPCVD沉积多晶硅后加入扩散源扩散形成N型掺杂硅晶层12，扩散温度为850℃，扩散源为三氯氧磷，扩散时间为100min。
(d)对步骤(c)所得背面01进行第一次激光消融并结合湿法化学腐蚀的方式，间隔的移除部分第一半导体层及其上的介电绝缘膜13，暴露N型掺杂硅基底，形成开孔14；其中，待移除第一半导体层的激光吸收量D 1为各膜层总吸收量的70％以上。第一激光消融的条件包括：采用连续扫描光斑部分交叠的波长约为355nm的紫外脉冲式激光，且脉冲宽度为15纳秒。所用激光在背面01形成的光斑为圆形，如图5a所示。所用激光经过空间整形为平顶激光。
(e)之后经过清洗，采用PECVD全面积覆盖方式在背面01制备第二半导体层，即依次形成本征硅层21、P型掺杂硅层22，并且在受光面02用PECVD方法依次制备钝化膜层41(本征非晶硅)、掺杂膜层42(N型非晶膜层)和减反膜层43(氮化硅)。
(f)对步骤(e)所得背面01进行第二次激光消融，进行两次激光曝光消融，以移除第二半导体层以及其下方的部分介电绝缘膜13以及底部的部分顶部N型掺杂硅晶层12，形成开口23，无需化学腐蚀；其中，第一次激光曝光消融中，待移除第二半导体层的激光吸收量D 201为各膜层总吸收量的70％以上；第二次激光曝光消融中，移除下方的介电绝缘膜13以及底部的部分顶部N型掺杂硅晶层的激光吸收量D 202为各膜层总吸收量的50％以上。第二激光消融的条件包括：采用连续开孔的波长约为532nm的绿光脉冲式激光，且脉冲宽度为20皮秒，能够避免激光损伤导致的发电效率下降。所用激光在背面形成的光斑为矩形，相邻激光光斑部分交叠。所用激光经过空间整形为矩形平顶激光，以保证加工区域内能量趋于一致。
(g)在所得背面01全覆盖的制备透明导电膜30。
(h)对背面01上的透明导电膜30进行第三次激光消融，形成绝缘槽35，绝缘槽35两侧的部分透明导电膜30互相电绝缘；其中第三次激光消融采用连续扫描光斑部分交叠的方式，待蚀刻透明导电膜的激光吸收量D 3为各膜层总吸收量的85％以上。第三激光消融条件包括：采用激光波长为355纳米的脉冲式激光，且脉冲宽度为10纳秒。所用激光在背面01形成的光斑为圆形。
(i)用丝网印刷方式，在所述开孔14表面形成主栅线52电极，在所述开口23表面形成垂直于主栅线52的细栅线51电极，以及焊接用焊盘的金属化图形，其有利于实现有效电接触。
其中，隧穿氧化层11、N型掺杂硅晶层12(N型掺杂多晶硅)、本征硅层21(本征非晶硅)与P型掺杂硅层22(P型掺杂非晶硅)的厚度比为1:88:2.9:4。N型掺杂硅晶层12的面掺杂指数与P型掺杂硅层22的面掺杂指数的比值为0.3:1，其中，面掺杂指数为相应掺杂层的有效掺杂浓度与该掺杂层厚度的比值。
对所得联合钝化背接触电池进行短路电流Isc、开路电压Voc、填充因子FF、转换效率Eta进行测 试，并对该批次的良率和材料成本进行测量，其结果如表1所示。
对实施例1得到的联合钝化背接触电池背面入射波长约为532nm的激光，形成的激光在第一半导体层和第二半导体层的E 2(电场强度平方值)分布如图7所示。从图7中可以看出，由于干涉效应第一半导体感受到的光学吸收为底层的4-5倍以上，且随介电绝缘膜13的厚度可以相应有序调节，保证第二半导体层被有效开口，同时不需要额外的化学光滑修正。
且其联合钝化背接触电池和采用TOPCON钝化方式和传统异质结钝化方式的少子寿命对比图如图8所示。从图8中可以看出，在钝化能力方面，N型钝化TOPCON的表面钝化能力相等或强于异质结薄膜钝化能力。
实施例2
参照实施例1的方法，不同的是，采用常规制备方法，而不采用激光消融，具体如下：
步骤(d)：第一半导体的移除采用丝网印刷的方式涂抹膏状蚀刻材料，晶固化后中等温度(80-120℃)下进行烧结反应，移除用非晶硅镀膜方式制作的第一半导体层，并通过化学腐蚀方式移除其上的介电绝缘膜13，然后进行重复多道工艺清洗，去除高残留的蚀刻膏。
步骤(f)：同样用蚀刻膏印刷方式选择性移除第二半导体层，并通过化学腐蚀方式移除其下的介电绝缘膜13，其中由于第二半导体层中有P型掺杂，烧结反应的设置温度更高为200℃。由于温度较高，迁移性腐蚀气体也会对电池其他表面造成腐蚀，需要多道保护油墨施加在正反面。
步骤(h)：用印刷保护油墨的方式，流出待开槽的绝缘槽位置，用全电池浸泡的方式，化学腐蚀透明导电膜，保证N型电极和P型电极之间互不短接。
并进行相应的测试，其结果如表1所示。
实施例3
参照实施例1的方法，不同的是，本征硅层与所述隧穿氧化层的厚度比为6:1。并进行相应的测试，其结果如表1所示。
实施例4
参照实施例1的方法，不同的是，N型掺杂硅晶层的面掺杂指数与P型掺杂硅层的面掺杂指数的比值为3:1。并进行相应的测试，其结果如表1所示。
实施例5
参照实施例1的方法，不同的是，掺杂膜层42为N型含氧型微晶膜层。并进行相应的测试，其结果如表1所示。
实施例6
参照实施例1的方法，不同的是，P型掺杂硅层22由孵育层，P型含氧微晶层与P型无氧微晶层组成，P型含氧微晶层与P型无氧微晶层、孵育层的厚度比为1:2.5:0.5。并进行相应的测试，其结果如表1所示。
对比例1
参照实施例1的方法，不同的是，所述第一半导体层由低温制备的本征非晶硅和N型掺杂非晶硅组成，且各层厚度比、面掺杂指数同实施例1；且其制备或刻蚀方法参照CN114068731A。并进行相应的测试，其结果如表1所示。
对比例2
本对比例采用TOPCON钝化N型和P型的交错结构，具体的背接触电池包括晶体硅衬底(N型掺杂硅基底)，其受光面上依次为隧穿氧化层、薄膜硅层、低温工艺抗反射膜层，背光面上设有隧穿氧化层，隧穿氧化层上设有间隔设置的p型和n型重掺杂非晶硅层，p型和n型重掺杂非晶硅层分别依次设有透明导电薄膜层和金属电极层；其中晶体硅衬底、隧穿氧化层、p型和n型重掺杂非晶硅层各层厚度及有效掺杂浓度均同实施例1。其制备方法参照CN110634961A。并进行相应的测试，其结果如表1所示。
表1
实施例编号 Isc/KA Voc/V FF Eta 良率 材料成本/元/片
实施例1 1 1 1 1 100％ 0.95
实施例2 1 1 0.99 0.99 92％ 1.2
实施例3 0.99 1 0.98 0.97 97％ 0.96
实施例4 1 0.99 0.97 0.96 97％ 0.94
实施例5 1.01 1 1 1.01 100％ 0.95
实施例6 1 1.002 1.005 1.007 95％ 1.1
对比例1 1 1 0.99 0.99 95％ 1.2
对比例2 1.022 0.962 1 0.983 100％ 0.95
通过上述实施例和对比例以及表1可知，本申请的实施例所得电池的短路电流Isc、开路电压Voc、填充因子FF、转换效率Eta均处于较高水平，且能兼顾较高的良率和适宜低的材料成本。而对比例的方案的综合效果无法达到本申请的效果水平。
其中，通过实施例1和实施例2可知，采用本申请的激光消融的优选制备方法的方案，更利于提高填充因子FF、转换效率Eta和良率。通过实施例1和实施例3-4可知，采用本申请优选第一半导体层和第二半导体层结构的方案，更利于总体的电性转化效率。通过实施例1和实施例5可知，采用本申请优选掺杂膜层的方案，更利于提高短路电流Isc和转换效率Eta。通过实施例1和实施例6可知，从追求电池性能更优的角度来看，本申请实施例6的方案相比于实施例1，更利于提升电池的开路电压Voc、填充因子FF、转换效率Eta；而从兼顾成本和转化效率的角度看，采用本申请优选实施例1的方案，更利于平衡制造成本稳定性和转化效率，对推广异质结背接触的量产最有利。
测试例
以实施例1的联合钝化背接触电池为例，在其介电绝缘膜为50-100nm氮化硅的前提下，在联合钝化背接触电池背面入射532nm波长的激光，形成的脉冲激光引起的第一半导体层和第二半导体层的光学吸收量及两者的相对选择性，其结果如表2所示。其中相对选择性以选择比来表征，选择比越高，就越容易移除上层第二半导体层而不损伤靠近基底的第一半导体层。其中选择比的计算方式为：第二半导体层吸收量/第一半导体层吸收量。
表2
Figure PCTCN2022144016-appb-000001
由上述表2可以看出，随着介电绝缘膜厚度的增加，选择比逐渐降低，表明介电绝缘膜厚度对于第一半导体层和第二半导体层的光吸收产生重要影响，适宜的介电绝缘膜厚度能够保证在激光消融时更容 易移除上层第二半导体层而不损伤靠近基底的第一半导体层。
以上详细描述了本申请的优选实施方式，但是，本申请并不限于此。在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，包括各个技术特征以任何其它的合适方式进行组合，这些简单变型和组合同样应当视为本申请所公开的内容，均属于本申请的保护范围。

Claims (17)

  1. 一种联合钝化背接触电池，包括具有受光面和背面的N型掺杂硅基底，设置在背面的第一半导体层和第二半导体层，所述第二半导体层包括沿垂直背面向外的方向依次设置的本征硅层和P型掺杂硅层，其特征在于，所述第一半导体层包括沿垂直背面向外的方向依次设置的隧穿氧化层和N型掺杂硅晶层。
  2. 根据权利要求1所述的联合钝化背接触电池，其特征在于，所述本征硅层与所述隧穿氧化层的厚度比为1.2-11:1。
  3. 根据权利要求2所述的联合钝化背接触电池，其特征在于，所述隧穿氧化层、N型掺杂硅晶层、本征硅层与P型掺杂硅层的厚度比为1:11-300:1.2-11:3-50。
  4. 根据权利要求1所述的联合钝化背接触电池，其特征在于，所述N型掺杂硅晶层的面掺杂指数与P型掺杂硅层的面掺杂指数的比值为0.07-40:1，其中，面掺杂指数为相应掺杂层的有效掺杂浓度与该掺杂层厚度的比值。
  5. 根据权利要求1所述的联合钝化背接触电池，其特征在于，所述本征硅层为本征非晶硅，所述P型掺杂硅层为P型掺杂非晶硅或P型掺杂微晶硅，所述N型掺杂硅晶层为N型掺杂多晶硅。
  6. 根据权利要求1所述的联合钝化背接触电池，其特征在于，所述P型掺杂硅层包括孵育层，及P型含氧微晶层与P型无氧微晶层，其中P型含氧微晶层与P型无氧微晶层的厚度比为1:0.25-7。
  7. 根据权利要求1所述的联合钝化背接触电池，其特征在于，所述N型掺杂硅基底为直拉单晶或铸锭单晶；和/或，所述N型掺杂硅基底的受光面为制绒面，背面为抛光面。
  8. 根据权利要求1所述的联合钝化背接触电池，其特征在于，所述联合钝化背接触电池还包括：
    介电绝缘膜，其设置在所述第一半导体层表面，且所述第一半导体层及其上的介电绝缘膜作为整体沿背面平行方向间隔排布，所述第二半导体层设置在所述介电绝缘膜的表面且覆盖所述间隔处表面，且在相邻间隔之间的第二半导体层上开设有暴露第一半导体层的开口；
    透明导电膜，其设置在所述第二半导体层表面以及在所述开口处暴露的第一半导体层表面，且在相邻的间隔和开口之间的透明导电膜上开设有裸露第二半导体层的绝缘槽；
    钝化膜层、掺杂膜层和减反膜层，其均设置在所述受光面的表面且沿受光面垂直向外方向依次设置。
  9. 根据权利要求8所述的联合钝化背接触电池，其特征在于，所述钝化膜层为本征非晶硅；所述掺杂膜层为N型非晶膜层或N型含氧型微晶膜层；所述减反膜层为氮化硅、二氧化硅、氧化硅、氮氧化硅中的至少一种。
  10. 一种如权利要求1-9中任一项所述联合钝化背接触电池的制备方法，其特征在于，包括以下步骤：
    S101、提供N型掺杂硅基底；
    S102、在所述N型掺杂硅基底的背面依次镀第一半导体层、介电绝缘膜，第一半导体层包含隧穿氧化层和N型掺杂硅晶层；
    S103、在S102所得N型掺杂硅基底的背面间隔的蚀刻开孔，以间隔的移除背面的第一半导体层及其上的介电绝缘膜，再进行清洗，得到间隔排布的第一半导体层和介电绝缘膜；
    S104、然后在S103所得N型掺杂硅基底的背面全覆盖的形成第二半导体层，第二半导体层包含本征硅层和P型掺杂硅层；其中，在开孔及其上的第二半导体层处形成第二导电区；
    S105、在S104所得N型掺杂硅基底的背面蚀刻开口，以在相邻间隔之间的部分第二半导体层上暴露第一半导体层，再进行清洗，形成与第二导电区交替排布的第一导电区；
    S106、然后在S105所得N型掺杂硅基底的背面沉积透明导电膜；再在位于所述开口和开孔之间的透明导电膜上蚀刻绝缘槽；并在所述开孔表面形成第一电极，在所述开口表面形成第二电极；
    S107、在所述N型掺杂硅基底的受光面依次形成钝化膜层、掺杂膜层和减反膜层。
  11. 根据权利要求10所述的制备方法，其特征在于，所述蚀刻采用激光消融结合任选的化学腐蚀的方式，其中，移除第一半导体层、第二半导体层或透明导电膜分别通过激光消融的方式，移除介电绝缘膜采用激光消融或化学腐蚀的方式。
  12. 根据权利要求11所述的制备方法，其特征在于，S103中，所述蚀刻开孔中移除第一半导体层采用连续扫描光斑部分交叠的第一激光消融方式，其中，待移除第一半导体层的激光吸收量D 1为各膜层总吸收量的70％以上。
  13. 根据权利要求12所述的制备方法，其特征在于，所述第一激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于20纳秒；所用激光在背面形成的光斑为圆形、椭圆形或矩形；所用激光经过空间整形为方形、圆形或椭圆形平顶激光。
  14. 根据权利要求11所述的制备方法，其特征在于，S105中，所述蚀刻开口中移除第二半导体层采用非连续开孔或连续开孔的第二激光消融方式，其中，
    在采用非连续开孔的方式时，所形成的光斑不交叠，待移除第二半导体层的激光吸收量D 2为各膜层总吸收量的70％以上；
    在采用连续开孔的方式时，所形成的光斑部分交叠，其中在相邻光斑的第一次激光曝光消融移除顶部的第二半导体层，此时移除相应层所需的激光吸收量D 201为各膜层总吸收量的70％以上；部分光斑交叠引起的第二次激光曝光消融移除下方的介电绝缘膜以及底部的部分顶部N型掺杂硅晶层，此时移除相应层所需的激光吸收量D 202为各膜层总吸收量的50％以上。
  15. 根据权利要求14所述的制备方法，其特征在于，所述第二激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于20纳秒；所用激光在背面形成的光斑为圆形、椭圆形或矩形；所用激光经过空间整形为矩形、圆形或椭圆形平顶激光。
  16. 根据权利要求11所述的制备方法，其特征在于，S106中，所述蚀刻绝缘槽采用连续扫描光斑部分交叠的第三激光消融方式，待蚀刻透明导电膜以及与其交叠的第二半导体层的激光吸收量D 3为各膜层总吸收量的70％以上。
  17. 根据权利要求16所述的制备方法，其特征在于，所述第三激光消融的条件包括：采用脉冲式激光，且脉冲宽度小于100纳秒；所用激光在背面形成的光斑为圆形、椭圆形或矩形。
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