WO2024050907A1 - 一种半导体结构的制造方法及半导体结构 - Google Patents

一种半导体结构的制造方法及半导体结构 Download PDF

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WO2024050907A1
WO2024050907A1 PCT/CN2022/123898 CN2022123898W WO2024050907A1 WO 2024050907 A1 WO2024050907 A1 WO 2024050907A1 CN 2022123898 W CN2022123898 W CN 2022123898W WO 2024050907 A1 WO2024050907 A1 WO 2024050907A1
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layer
lower electrode
support
electrode layer
mask
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PCT/CN2022/123898
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English (en)
French (fr)
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彭敏
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a manufacturing method of a semiconductor structure and a semiconductor structure.
  • Dynamic random access memory is a semiconductor structure commonly used in electronic devices that contains multiple memory cells, each memory cell containing a transistor and a capacitor.
  • the capacitance of the capacitor is usually increased by increasing the height of the capacitor pillar to improve storage density.
  • the feature size is reduced below a certain value, forming a capacitor column with a high aspect ratio will face problems such as instability of the capacitor column due to increased film stress. Therefore, how to form a stable and reliable columnar capacitor structure has become an urgent technical problem that needs to be solved. .
  • embodiments of the present disclosure provide a manufacturing method of a semiconductor structure and a semiconductor structure to solve the technical problems existing in the background art.
  • a method for manufacturing a semiconductor structure including:
  • a first lower electrode layer and a second lower electrode layer are formed in the capacitor hole.
  • the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole.
  • the second lower electrode layer The electrode layer fills the cavity; wherein,
  • the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
  • the material of the second lower electrode layer includes a silicon-containing crystalline material.
  • the silicon-containing crystalline material has a grain size less than 1 nm.
  • the first lower electrode layer and the second lower electrode layer are jointly defined as a lower electrode, and the diameter of the lower electrode is no greater than 40 nm.
  • the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15 nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15-15 nm. 30nm.
  • forming a stacked structure on the substrate, and etching the stacked structure to form the capacitor hole includes:
  • the laminated structure at least includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer;
  • the stacked structure is etched in a direction perpendicular to the substrate to expose the substrate and form the capacitor hole.
  • a first lower electrode layer and a second lower electrode layer are formed in the capacitor hole, and the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole.
  • the second lower electrode layer fills the cavity, including:
  • first lower electrode material layer covering the inner surface of the capacitor hole and the upper surface of the stacked structure, the first lower electrode material layer forming a cavity in the capacitor hole body;
  • the method further includes:
  • a mask layer and a patterned photoresist layer located on the mask layer are formed above the first lower electrode layer, the second lower electrode layer and the third support layer; the mask layer It includes a first mask layer, a second mask layer and a third mask layer, wherein the material of the first mask layer is the same as the material of the third support layer.
  • the method further includes:
  • the mask layer is etched, and the photoresist layer pattern is transferred to the first mask layer to form a first opening, and the first opening exposes at least one of the A partial region of the first lower electrode layer and a portion of the third support layer;
  • the first sacrificial layer is removed to expose the first support layer, and the remaining first support layer, second support layer and third support layer are defined as a support structure.
  • a first lower electrode layer and a second lower electrode layer are formed in the capacitor hole, and the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole.
  • the second lower electrode layer fills the cavity, including:
  • first lower electrode material layer covering the inner surface of the capacitor hole and the upper surface of the stacked structure, the first lower electrode material layer forming a cavity in the capacitor hole body;
  • the top of the first lower electrode material layer is removed to expose the third support layer.
  • the remaining first lower electrode material layer is defined as a first lower electrode layer.
  • the first lower electrode layer is in the capacitor. A cavity is formed within the hole;
  • the second lower electrode material layer is formed, the second lower electrode material layer fills the cavity and covers the tops of the first lower electrode layer and the third support layer.
  • the method further includes:
  • a mask layer and a patterned photoresist layer located on the mask layer are formed above the second lower electrode material layer; the mask layer includes a second mask layer and a third mask layer, so The top of the second lower electrode material layer serves as a partial mask layer.
  • the method further includes:
  • the top of the third mask layer, the second mask layer and the second lower electrode material layer is etched, and the photoresist layer pattern is transferred to the
  • the second lower electrode material layer forms a first opening, and the first opening exposes at least a partial area of the first lower electrode layer and a portion of the third support layer;
  • the first sacrificial layer is removed to expose the first support layer, and the remaining first support layer, second support layer and third support layer are defined as a support structure.
  • forming the second lower electrode material layer includes:
  • the second lower electrode material layer is formed at a temperature ranging from 470°C to 530°C.
  • the method further includes:
  • a semiconductor structure including:
  • a lower electrode located in the capacitor hole wherein the lower electrode includes a first lower electrode layer and a second lower electrode layer, the first lower electrode layer covers the bottom and side walls of the capacitor hole and forms a cavity body, the second lower electrode layer is filled in the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
  • the material of the second lower electrode layer includes a silicon-containing crystalline material.
  • the silicon-containing crystalline material has a grain size less than 1 nm.
  • the diameter of the lower electrode is no greater than 40 nm.
  • the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15 nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15-15 nm. 30nm.
  • the semiconductor structure further includes:
  • a dielectric layer covering the lower electrode and the support structure and an upper electrode covering the dielectric layer.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming a stacked structure on the substrate; etching the stacked structure to form a capacitor hole; forming a first capacitor hole in the capacitor hole.
  • a lower electrode layer and a second lower electrode layer, the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, and the second lower electrode layer fills the cavity; wherein , the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
  • the present disclosure first forms a capacitor hole in a stacked structure on a substrate, and then forms a first lower electrode layer and a second lower electrode layer in the capacitor hole.
  • the first lower electrode layer covers the inner surface of the capacitor hole and is in the capacitor hole.
  • a cavity is formed, the second lower electrode layer fills the cavity, and the first lower electrode layer and the second lower electrode layer together form a lower electrode.
  • the second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is less than the stress in the first lower electrode layer, excessive stress of a single first lower electrode can be improved.
  • the capacitor column is prone to tilting.
  • Embodiments of the present disclosure can eliminate film stress, and the second lower electrode layer can play a stable and good supporting role for the first lower electrode layer, so that the stability of the capacitor column can be enhanced during the process. Not prone to tilting.
  • FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • FIGS. 2a to 2q are schematic structural diagrams of the semiconductor structure during the manufacturing process according to embodiments of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.
  • the capacitance of the capacitor is usually increased by increasing the height of the capacitor pillar to increase storage density.
  • the formation of a capacitor pillar structure with a high aspect ratio will face structural problems such as tilting of the capacitor pillars due to increased film stress, etc., which will result in the inability to open normally in the subsequent manufacturing process of the capacitor structure, so the lower layer The oxide layer cannot be fully removed, resulting in insufficient space reserved for the upper electrodes of the capacitor, leading to the problem of capacitor failure.
  • the present disclosure provides a method for manufacturing a semiconductor structure. Please refer to Figure 1 for details. As shown in the figure, the method includes:
  • Step 101 Provide a substrate
  • Step 102 Form a stacked structure on the substrate; etching the stacked structure to form a capacitor hole;
  • Step 103 Form a first lower electrode layer and a second lower electrode layer in the capacitor hole.
  • the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole.
  • the second lower electrode layer fills the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
  • step 101 is performed, see Figure 2a, to provide a substrate 10.
  • the substrate 10 includes, for example, but is not limited to, a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium (SiGe) substrate). substrate, etc.), or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.
  • the substrate may be doped or undoped, or contain both doped and undoped regions therein.
  • the substrate may also include one or more doped ( n- or p- ) regions; if the substrate includes multiple doped regions, these regions may have the same or different conductivities and/or doping concentrations.
  • the substrate 10 includes a doped or undoped silicon substrate 101, and a conductive contact layer 102 is included above the substrate 101.
  • the conductive material may include a metal material, such as metal tungsten (W). ).
  • step 102 is performed. Referring to FIGS. 2 a and 2 b , a stacked structure 11 is formed on the substrate 10 ; the stacked structure 11 is etched to form a capacitor hole 12 .
  • forming the stacked structure 11 on the substrate 10 and etching the stacked structure 11 to form the capacitor hole 12 includes: forming the stacked structure 11 on the substrate 10, and the stacked structure 11.
  • the structure 11 at least includes a first support layer 111, a first sacrificial layer 112, a second support layer 113, a second sacrificial layer 114 and a third support layer 115 (as shown in Figure 2a); along the direction perpendicular to the substrate 10
  • the stacked structure 11 is etched to expose the substrate 10 and form the capacitor hole 12 (as shown in FIG. 2b).
  • the above-mentioned laminated structure includes two layers of sacrificial layers and three layers of support layers, which can better support the formed capacitor structure while ensuring the height of the formed capacitor structure.
  • the first support layer 111 , the first sacrificial layer 112 , the second support layer 113 , the second sacrificial layer 114 and the third support layer 115 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or Formed by one or more processes in an atomic layer deposition (ALD) process; etching the stacked structure 11 to form the capacitor hole 12 may be formed by using an anisotropic etching process, such as a plasma etching process.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • etching the stacked structure 11 to form the capacitor hole 12 may be formed by using an anisotropic etching process, such as a plasma etching process.
  • the materials sequentially deposited on the substrate 10 to form the first support layer 111 , the second support layer 113 and the third support layer 115 include but are not limited to nitride.
  • the second support layer 113 and the third support layer 115 are The material of layer 115 may be an insulating material containing C, such as SiCN. Because SiCN material has very good hardness, it can provide good support for the subsequently formed capacitor structure.
  • the material of the first support layer 111 and the first sacrificial layer 112 may be an insulating material containing B.
  • the material of the first support layer 111 may be SiBN, and the material of the first sacrificial layer 112 may be borophosphosilicate glass (BPSG).
  • both the first sacrificial layer 112 and the first supporting layer 111 are made of material doped with boron element, the hardness of the material is reduced, making the etching process easier to complete, and ensuring the morphology of the capacitor hole 12 .
  • step 103 is performed to form a first lower electrode layer 14 and a second lower electrode layer 15 in the capacitor hole 12 .
  • the first lower electrode layer 14 covers the inner surface of the capacitor hole 12 and is in the capacitor hole 12 .
  • a cavity 121 is formed in the hole 12 , and the second lower electrode layer 15 fills the cavity 121 ; wherein the stress in the second lower electrode layer 15 is less than the stress in the first lower electrode layer 14 .
  • the second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is less than the stress in the first lower electrode layer, it can provide stable and good support to the first lower electrode layer.
  • the supporting function enhances the stability of the capacitor column during the process and prevents it from tilting. This can further improve the problem that when the etching opening is deflected due to the tilt of the capacitor pillar, the support layer cannot be opened normally, so that the bottom oxide layer cannot be fully removed, making it impossible to reserve sufficient space for the upper electrode, resulting in the failure of the entire capacitor. question.
  • the material of the second lower electrode layer 15 may include conductive or non-conductive materials, preferably materials with good filling properties and low film stress, such as but not limited to crystalline materials containing silicon.
  • the material of the second lower electrode layer 15 may include doped or undoped silicon-containing crystalline material.
  • the materials of the second lower electrode layer 15 include, but are not limited to, polysilicon, silicon germanium, etc.
  • the above materials have excellent filling properties and can be fully filled in the cavity of the first lower electrode layer 14 and form a film.
  • the layer stress is relatively small, which can provide good support to the first lower electrode layer 14 and avoid problems such as tilt and offset of the capacitor column.
  • the silicon-containing crystalline material has a grain size less than 1 nm.
  • the silicon-containing crystalline material has a grain size of less than 0.1 nm.
  • the smaller the grain size of the material the better the filling performance, and it is easier to fill in the cavity of the first lower electrode layer with a size of tens of nanometers; in addition, the smaller the grain size of the material, the smaller the lattice stress formed. , the stress of the finally formed second lower electrode layer will be smaller, and it will have a better supporting effect on the first lower electrode layer.
  • the second lower electrode layer 15 may include a single layer of material; in some other embodiments, the second lower electrode layer 15 may include multiple layers of material, for example, the second lower electrode layer may be formed along the path of the capacitor hole. In the direction from the axis to the periphery, it includes the first sub-layer...the N-th sub-layer, where N is a positive integer greater than or equal to 2. In some more specific embodiments, the hardness and/or film stress of each of the first sublayer...Nth sublayer may be different. Specifically, for example, in some embodiments, along the diameter of the capacitor hole In the direction from the axis to the periphery, the hardness of the first sublayer...Nth sublayer decreases in sequence, and the film stress gradually decreases. In this way, the supporting effect of the second lower electrode layer 15 on the first lower electrode layer 14 can be further improved, thereby further enhancing the stability of the lower electrode 16 .
  • the first lower electrode layer 14 and the second lower electrode layer 15 are jointly defined as a lower electrode 16, and the diameter of the lower electrode 16 is no greater than 40 nm.
  • the capacitor preparation method provided by the embodiments of the present disclosure is compatible with extremely small-sized capacitor preparation processes (such as Pillar capacitors), and can be applied to the process of preparing small-sized capacitors, for example, the diameter of the lower electrode 16 is not greater than 40 nm, not greater than 30 nm, or not greater than 20 nm. , in order to alleviate and avoid problems such as tilt and offset in the preparation process of extremely small capacitors, which may cause difficulties in subsequent steps of manufacturing the dielectric layer and upper electrode of the capacitor, thereby providing an extremely small-sized, stable and reliable capacitor structure. .
  • the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15 nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15 nm. -30nm.
  • the second lower electrode layer 15 mainly functions to support the first lower electrode layer 14, and the first lower electrode layer 14 mainly functions as a capacitor electrode plate.
  • the thickness of the second lower electrode layer 15 is different from the thickness of the first lower electrode layer 14,
  • the thickness ratio of the lower electrode layer 14 is small, since the thickness of the second lower electrode layer 15 in the lower electrode 16 is relatively small, the effect on improving the tilt and offset of the capacitor column is limited;
  • the thickness of the second lower electrode layer 15 When the ratio to the thickness of the first lower electrode layer 14 is large, the performance of the capacitor structure will be affected to a certain extent because the thickness of the first lower electrode layer 14 in the lower electrode 16 is relatively small. Therefore, making the thickness of the second lower electrode layer 15 slightly larger than the thickness of the first lower electrode layer 14 can achieve a better beneficial effect of improving the tilt and offset of the capacitor column while taking into account the capacitance performance of the capacitor structure.
  • the embodiment of the present disclosure provides two implementation methods for preparing the lower electrode 16, as shown in FIGS. 2c to 2e.
  • the first lower electrode layer 14 and the second lower electrode layer 14 are formed in the capacitor hole 12.
  • Electrode layer 15, the first lower electrode layer 14 covers the inner surface of the capacitor hole 12 and forms a cavity 121 in the capacitor hole 12, the second lower electrode layer 15 fills the cavity 121, including : forming a first lower electrode material layer 141, which covers the inner surface of the capacitor hole 12 and the upper surface of the stacked structure 11, where the first lower electrode material layer 141 is A cavity 121 is formed in the capacitor hole 12 (see Figure 2c); a second lower electrode material layer 151 is formed, and the second lower electrode material layer 151 fills the cavity 121 and covers the first lower electrode material layer 141 The top of the second lower electrode material layer 151 and the first lower electrode material layer 141 is etched to expose the third support layer 115 and the remaining first lower electrode The material layer 141 and the second lower electrode material layer 151 are respectively defined as the first
  • the first lower electrode layer 14 may be deposited using a physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) process at 550°C to 650°C.
  • the material of layer 14 includes, but is not limited to, titanium (Ti), titanium nitride (TiN) or tungsten (W).
  • the step of etching the second lower electrode material layer 151 and the top of the first lower electrode material layer 141 to expose the third support layer 115 may use a wet or dry etching process, such as plasma. Etching process, chemical mechanical polishing process (CMP), etc.
  • the second lower electrode layer 15 and/or the first lower electrode layer 14 and the third support layer The upper surface of 115 is flush. It should be understood that in some other embodiments, the upper surfaces of the second lower electrode layer 15 , the first lower electrode layer 14 and the third support layer 115 may not be flush, and the third support layer 115 only needs to be exposed. .
  • forming the second lower electrode material layer 151 includes: forming the second lower electrode material layer 151 at a temperature ranging from 470°C to 530°C.
  • one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes can be used to prepare the second lower electrode layer 15 at 470°C to 530°C. .
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the size and shape of the filling material grains are better, the lattice stress formed is more controllable, the hardness of the prepared second lower electrode layer 15 is moderate, and the film stress is small enough, so that the first lower electrode layer 15 can be
  • the lower electrode layer 14 produces a relatively excellent stress improvement effect.
  • the first lower electrode layer 14 and the second lower electrode layer 15 formed in the above-mentioned first embodiment together constitute the lower electrode 16 .
  • the method further includes: forming the first lower electrode layer 14, the second lower electrode layer 15 and the third A mask layer 17 and a patterned photoresist layer 18 located on the mask layer 17 are formed above the support layer 115; the mask layer 17 includes a first mask layer 171, a second mask layer 172 and a third mask layer 172. Three mask layers 173 , wherein the first mask layer 171 is made of the same material as the third support layer 115 .
  • the first mask layer and the third support layer are made of the same material, which can make the support structure have a better support effect on the lower electrode, thereby better improving the problem of tilt and offset of the lower electrode, and thus avoiding subsequent modifications to the support structure.
  • the first mask layer can protect the surfaces of the third support layer, the first lower electrode layer and the second lower electrode layer from being etched during the etching process, thereby ensuring the support effect of the support structure and the performance of the capacitor structure.
  • the arrangement of the first mask layer made of the same material as the third support layer can also control the height difference between the third support layer and the first lower electrode layer, thereby controlling the surface topography of the capacitor.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • Photolithography is an important process in making semiconductor structures. As the feature size continues to decrease, the difficulty of photolithography continues to increase.
  • the semiconductor substrate including Metal layer and dielectric layer
  • DARC dielectric anti-reflective coating
  • the material of the dielectric anti-reflective coating is generally silicon oxynitride, etc.
  • the third mask layer 173 in the above embodiment can function as a dielectric anti-reflective coating.
  • the method further includes: based on the pattern The photoresist layer 18 is etched, and the photoresist layer pattern is transferred to the first mask layer 171 to form a first opening 191.
  • the first opening 191 exposes at least one of the Partial area of the first lower electrode layer 14 and part of the third support layer 115; use the first mask layer 171 as a mask to etch the third support layer 115 to form the second opening 19.
  • the second opening 19 exposes the second sacrificial layer 114 (see Figure 2g); removes the second sacrificial layer 114 to expose the second support layer 113 (see Figure 2h); etches the second support layer 113 , forming a third opening 20, the third opening 20 exposing the first sacrificial layer 112 (see Figure 2i); removing the first sacrificial layer 112, exposing the first support layer 111 (see Figure 2j),
  • the remaining first support layer 111 , the second support layer 113 and the third support layer 115 are defined as support structures.
  • first lower electrode layer and the second lower electrode layer jointly form a stable lower electrode structure, during the process of forming the opening using photolithography technology and etching process, there will be no alignment deviation caused by the tilt or offset of the lower electrode. , leading to the failure to form the opening, thus avoiding the problem that the etching solution is difficult to fully contact the first sacrificial layer in the subsequent wet etching process due to the failure of the opening, thereby avoiding the capacitance caused by the failure of the first sacrificial layer to be completely removed Structure production failure problem.
  • photolithography and etching processes may be used to etch the third support layer 115 and the second support layer 113 to form the first opening 191 , the second opening 19 and the third opening 20 .
  • Methods for removing the first sacrificial layer 112 and the second sacrificial layer 114 include, but are not limited to, wet etching using dilute hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH 4 F).
  • DHF dilute hydrofluoric acid
  • HF hydrofluoric acid
  • NH 4 F ammonium fluoride
  • An etching method is used to selectively etch and remove the materials of the first sacrificial layer 112 and the second sacrificial layer 114, leaving the first lower electrode layer 14 and the second lower electrode layer 15, the first support layer 111, the second support layer 113 and Third support layer 115.
  • the first sacrificial layer 112 and the second sacrificial layer 114 are etched separately in sequence.
  • the second sacrificial layer 114 is etched first, and then the first sacrificial layer 112 is etched.
  • the first lower electrode layer 14 and the second lower electrode layer 15 are formed in the capacitor hole 12, and the first lower electrode layer 14 is formed in the capacitor hole 12.
  • the lower electrode layer 14 covers the inner surface of the capacitor hole 12 and forms a cavity 121 in the capacitor hole 12.
  • the second lower electrode layer 15 fills the cavity 121, including: forming a first lower electrode material layer 141.
  • the first lower electrode material layer 141 covers the inner surface of the capacitor hole 12 and the upper surface of the stacked structure 11 , and the first lower electrode material layer 141 forms a cavity in the capacitor hole 12 121 (see Figure 2c); remove the top of the first lower electrode material layer 141 to expose the third support layer 115, and the remaining first lower electrode material layer 141 is defined as the first lower electrode layer 14,
  • the first lower electrode layer 14 forms a cavity 121 in the capacitor hole 12 (see FIG. 2k); the second lower electrode material layer 151 is formed, and the second lower electrode material layer 151 fills the cavity. 121 and covers the tops of the first lower electrode layer 14 and the third support layer 115 (see Figure 2l).
  • the method further includes: forming a mask layer 17 above the second lower electrode material layer 151 and located on the mask layer 17.
  • the above-mentioned second lower electrode material layer not only fills the cavity, but also covers the top of the first lower electrode layer and the third support layer, which has a better supporting effect on the first lower electrode layer and can better improve the first lower electrode layer. Problems such as tilt and offset may easily occur due to stress.
  • the top of the second lower electrode material layer can function as the first mask layer in the mask layer. Therefore, compared with the above-mentioned first embodiment, the process of forming the first mask layer can be saved.
  • first lower electrode material layer 141 and the second lower electrode material layer 151 and forming the second mask layer 172 and the third mask layer 173 in the mask layer 17 can all adopt the same method as the first lower electrode material layer 141 and the second lower electrode material layer 151 . Similar methods are used in the above embodiments, which will not be described again here.
  • the step of removing the top of the first lower electrode material layer 141 to expose the third support layer 115 may use a wet or dry etching process, such as plasma etching process, chemical mechanical polishing process (CMP), etc.
  • the method further includes: based on the pattern The photoresist layer 18 is etched, etching the third mask layer 173, the second mask layer 172 and the top of the second lower electrode material layer 151, and transferring the photoresist layer pattern to the
  • the second lower electrode material layer 151 forms a first opening 191, which exposes at least a partial area of the first lower electrode layer 14 and a portion of the third support layer 115; so as to form the first opening 191 after patterning.
  • the second lower electrode material layer 151 is used as a mask to etch the third support layer 115 to form a second opening 19, and the second opening 19 exposes the second sacrificial layer 114 (see FIG. 2n); remove the The second sacrificial layer 114 exposes the second support layer 113 (see FIG. 2o); the second support layer 113 is etched to form the third opening 20, and the covering of the third support layer 115 and the third opening 20 is removed.
  • the second lower electrode material layer on top of the lower electrode layer 14, the third opening 20 exposes the first sacrificial layer 112, and the remaining second lower electrode material layer is defined as the second lower electrode layer 15 (see Figure 2p); remove the first sacrificial layer 112, expose the first support layer 111 (see Figure 2q), and the remaining first support layer 111, the second support layer 113 and the
  • the third support layer 115 is defined as a support structure.
  • first opening 191 , the second opening 19 and the third opening 20 , and removing the first sacrificial layer 112 and the second sacrificial layer 114 can be formed by using a method similar to that in the first embodiment. , which will not be described in detail here.
  • the first sacrificial layer 112 and the second sacrificial layer 114 have a high etching selectivity ratio relative to the second lower electrode material layer 151 .
  • an opening is formed in the support layer to remove the first sacrificial layer and the second sacrificial layer, thereby facilitating the subsequent process of manufacturing the capacitor structure.
  • the first sacrificial layer 112 and the second sacrificial layer 114 have a high etching selectivity ratio relative to the second lower electrode material layer 151, so that when wet etching is used to remove the first sacrificial layer and the second sacrificial layer, the second lower electrode material
  • the layer has basically no effect, so it will not affect the supporting effect of the second lower electrode material layer on the first lower electrode layer, thereby avoiding problems such as tilt and offset of the capacitor column.
  • the above is to form the lower electrode 16 composed of the second lower electrode layer 15 and the first lower electrode layer 14 according to the second embodiment.
  • the lower electrode 16 is formed according to either of the above two embodiments and the first sacrificial layer 112 is removed.
  • the method further includes: A dielectric layer 32 is formed on the exposed surfaces of the first lower electrode layer 14 and the second lower electrode layer 15 and the first support layer 111 and the third support layer 115; an upper electrode 33 is formed on the surface of the dielectric layer 32. .
  • An embodiment of the present disclosure also provides a semiconductor structure. Please refer to Figure 3 for details. As shown in the figure, the semiconductor structure includes:
  • the lower electrode 16 is located in the capacitor hole 12 , wherein the lower electrode 16 includes a first lower electrode layer 14 and a second lower electrode layer 15 , and the first lower electrode layer 14 covers the bottom of the capacitor hole 12 and side walls, and form a cavity 121.
  • the second lower electrode layer 15 is filled in the cavity 121; wherein, the stress in the second lower electrode layer 15 is less than that in the first lower electrode layer 14. stress.
  • the second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is less than the stress in the first lower electrode layer, it can provide stable and good support to the first lower electrode layer.
  • the supporting function enhances the stability of the capacitor column and prevents it from tilting.
  • the substrate 10 includes, for example, but is not limited to, a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium (SiGe) substrate). substrate, etc.), or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.
  • the substrate may be doped or undoped, or contain both doped and undoped regions therein.
  • the substrate may also include one or more doped ( n- or p- ) regions; if the substrate includes multiple doped regions, these regions may have the same or different conductivities and/or doping concentrations.
  • the substrate 10 includes a doped or undoped silicon substrate 101, and a conductive contact layer 102 is included above the substrate 101.
  • the conductive material may include a metal material, such as metal tungsten (W). ).
  • the support assembly 30 includes a first support layer 111 , a second support layer 113 and a third support layer 115 , wherein the materials of the first support layer 111 , the second support layer 113 and the third support layer 115 include but are not only Limited to nitride, the materials of the first support layer 111 , the second support layer 113 and the third support layer 115 may be the same or different.
  • the material of the first support layer 111 may be a B-containing insulating material, such as SiBN. , because doping B can reduce the hardness of the material, so that the capacitor hole 12 formed by etching, for example, has a better morphology.
  • the material of the second support layer 113 and the third support layer 115 can be an insulating material containing C, such as SiCN. Because the SiCN material has very good hardness, it can provide good support to the lower electrode 16 .
  • the material of the first lower electrode layer 14 includes but is not limited to titanium (Ti), titanium nitride (TiN), or tungsten (W). The thickness of the first lower electrode layer 14 may be, for example, 10 nm to 15 nm.
  • the material of the second lower electrode layer 15 may include conductive or non-conductive materials, preferably materials with good filling properties and low film stress, such as but not limited to silicon-containing crystalline materials.
  • the materials of the second lower electrode layer 15 include, but are not limited to, polysilicon, silicon germanium, etc. The above materials have excellent filling properties and can fully fill the cavity 121 of the first electrode layer 14 and form a film. The layer stress is relatively small, which can provide good support to the first lower electrode layer 14 and avoid problems such as tilt and offset of the capacitor column.
  • the silicon-containing crystalline material has a grain size less than 1 nm.
  • the silicon-containing crystalline material has a grain size of less than 0.1 nm.
  • the smaller the grain size of the material the better the filling performance, and it is easier to fill in the cavity of the first lower electrode layer with a size of tens of nanometers; in addition, the smaller the grain size of the material, the greater the lattice stress formed. Small, the stress of the finally formed second lower electrode layer will be smaller, and it will have a better supporting effect on the first lower electrode layer.
  • the diameter of the lower electrode 16 is no greater than 40 nm.
  • the diameter of the pillar capacitor is often on the scale of tens of nanometers, so it is very easy for the capacitor to tilt and shift.
  • the capacitor structure provided by the embodiments of the present disclosure is manufactured using the manufacturing method in the previous embodiment, and can produce a very small capacitor structure, such as a small capacitor with a diameter of the lower electrode 16 not greater than 40 nm, not greater than 30 nm, or not greater than 20 nm.
  • the above-mentioned lower electrode structure can alleviate and avoid problems such as tilt and offset in the prepared extremely small-sized capacitor, and achieve an extremely small-sized, stable and reliable capacitor structure.
  • the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15 nm
  • the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 10-15 nm. Thickness is 15-30nm.
  • the second lower electrode layer 15 mainly functions to support the first lower electrode layer 14, and the first lower electrode layer 14 mainly functions as a capacitor electrode plate.
  • the thickness of the second lower electrode layer 15 is different from the thickness of the first lower electrode layer 14,
  • the thickness ratio of the lower electrode layer 14 is small, since the thickness of the second lower electrode layer 15 in the lower electrode 16 is relatively small, the effect on improving the tilt and offset of the capacitor column is limited;
  • the thickness of the second lower electrode layer 15 When the ratio to the thickness of the first lower electrode layer 14 is large, the performance of the capacitor structure will be affected to a certain extent because the thickness of the first lower electrode layer 14 in the lower electrode 16 is relatively small. Therefore, making the thickness of the second lower electrode layer 15 slightly larger than the thickness of the first lower electrode layer 14 can achieve a better beneficial effect of improving the tilt and offset of the capacitor column while taking into account the performance of the capacitor structure.
  • the semiconductor structure further includes: a dielectric layer 32 covering the lower electrode 16 and the support structure 30 and an upper electrode 33 covering the dielectric layer 32 .
  • the material of the dielectric layer 32 includes but is not limited to aluminum oxide, silicon nitride, silicon oxide, zirconium oxide or combinations thereof.
  • the material of the upper electrode 33 includes but is not limited to titanium (Ti), titanium nitride (TiN) or tungsten (W). The above-mentioned lower electrode 16, dielectric layer 32 and upper electrode 33 together form a complete capacitor structure.
  • the present disclosure first forms a capacitor hole in a stacked structure on a substrate, and then forms a first lower electrode layer and a second lower electrode layer in the capacitor hole.
  • the first lower electrode layer covers the inner surface of the capacitor hole.
  • a cavity is formed in the capacitor hole, the second lower electrode layer fills the cavity, and the first lower electrode layer and the second lower electrode layer together form a lower electrode.
  • the second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is less than the stress in the first lower electrode layer, excessive stress of the single first lower electrode can be improved. As a result, the capacitor column is prone to tilting.
  • Embodiments of the present disclosure can eliminate film stress.
  • the second lower electrode layer can provide stable and good support to the first lower electrode layer, thereby enhancing the stability of the capacitor column during the process. Not prone to tilting. This can further improve the problem that when the etching opening is deflected due to the tilt of the capacitor pillar, the support layer cannot be opened normally, so that the bottom oxide layer cannot be fully removed, making it impossible to reserve sufficient space for the upper electrode, resulting in the failure of the entire capacitor. question.
  • Embodiments of the present disclosure can eliminate film stress, and the second lower electrode layer can play a stable and good supporting role for the first lower electrode layer, so that the stability of the capacitor column is enhanced during the process and is less likely to tilt. This can further improve the problem that when the etching opening is deflected due to the tilt of the capacitor pillar, the support layer cannot be opened normally, so that the bottom oxide layer cannot be fully removed, making it impossible to reserve sufficient space for the upper electrode, resulting in the failure of the entire capacitor. question.

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Abstract

本公开实施例公开了一种半导体结构的制造方法及半导体结构。所述半导体结构的制造方法包括：提供基底；在所述基底上形成叠层结构；刻蚀所述叠层结构以形成电容孔；在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体；其中，所述第二下电极层中的应力小于所述第一下电极层中的应力。

Description

一种半导体结构的制造方法及半导体结构
相关申请的交叉引用
本公开基于申请号为202211091178.2、申请日为2022年09月07日、发明名称为“一种半导体结构的制造方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构的制造方法及半导体结构。
背景技术
动态随机存取存储器(DRAM)是电子设备中常用的半导体结构，其包含多个存储单元，每个存储单元包含晶体管和电容器。随着DRAM特征尺寸不断微缩，通常通过增加电容柱的高度来增加电容器的电容，以提升存储密度。在特征尺寸减小至一定数值以下时，形成高深宽比的电容柱会面临因薄膜应力增加等导致的电容柱不稳定等问题，因此如何形成稳定可靠的柱状电容结构成为目前亟待解决的技术问题。
发明内容
有鉴于此，本公开实施例为解决背景技术中存在的技术问题而提供一种半导体结构的制造方法及半导体结构。
根据本公开实施例的第一方面，提供了一种半导体结构的制造方法，包括：
提供基底；
在所述基底上形成叠层结构；
刻蚀所述叠层结构以形成电容孔；
在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体；其中，
所述第二下电极层中的应力小于所述第一下电极层中的应力。
在一些实施例中，所述第二下电极层的材料包括含硅的结晶材料。
在一些实施例中，所述含硅的结晶材料的晶粒尺寸小于1nm。
在一些实施例中，所述第一下电极层与所述第二下电极层共同定义为下电极，所述下电极的直径不大于40nm。
在一些实施例中，所述第一下电极层沿所述电容孔的径向方向的厚度为10-15nm，所述第二下电极层沿所述电容孔的径向方向的厚度为15-30nm。
在一些实施例中，在所述基底上形成叠层结构，以及刻蚀所述叠层结构以形成所述电容孔，包括：
形成所述叠层结构于所述基底上，所述叠层结构至少包括第一支撑层、第一牺牲层、第二支撑层、第二牺牲层以及第三支撑层；
沿垂直于所述基底的方向刻蚀所述叠层结构，暴露出所述基底，形成所述电容孔。
在一些实施例中，在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体，包括：
形成第一下电极材料层，所述第一下电极材料层覆盖所述电容孔的内表面以及所述叠层结构的上表面，所述第一下电极材料层在所述电容孔内形成腔体；
形成第二下电极材料层，所述第二下电极材料层填充所述腔体并覆盖所述第一下电极材料层的顶部；
刻蚀所述第二下电极材料层及所述第一下电极材料层的顶部，暴露出所述第三支撑层，剩余的所述第一下电极材料层与所述第二下电极材料层分别定义为所述第一下电极层和所述第二下电极层。
在一些实施例中：刻蚀所述第二下电极层及所述第一下电极层的顶部，暴露出所述第三支撑层后，所述方法还包括：
在所述第一下电极层、所述第二下电极层及所述第三支撑层上方形成掩膜层和位于所述掩膜层上的图形化的光刻胶层；所述掩膜层包括第一掩膜层、第二掩膜层及第三掩膜层，其中，所述第一掩模层的材料与所述第三支撑层的材料相同。
在一些实施例中，形成所述掩膜层和位于所述掩膜层上的所述图形化的光刻胶层后，所述方法还包括：
基于所述图形化的光刻胶层，刻蚀所述掩膜层，将光刻胶层图案转移至所述第一掩膜层，形成第一开口，所述第一开口暴露至少一个所述第一下电极层的部分区域和部分所述第三支撑层；
以所述第一掩模层为掩膜刻蚀所述第三支撑层，形成第二开口，所述第二开口暴露所述第二牺牲层；
去除所述第二牺牲层，暴露所述第二支撑层；
刻蚀所述第二支撑层，形成第三开口，所述第三开口暴露所述第一牺牲层；
去除所述第一牺牲层，暴露所述第一支撑层，剩余的所述第一支撑层、所述第二支撑层及所述第三支撑层定义为支撑结构。
在一些实施例中，在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体，包括：
形成第一下电极材料层，所述第一下电极材料层覆盖所述电容孔的内表面以及所述叠层结构的上表面，所述第一下电极材料层在所述电容孔内形成腔体；
去除所述第一下电极材料层的顶部，暴露出所述第三支撑层，剩余的所述第一下电极材料层定义为第一下电极层，所述第一下电极层在所述电容孔内形成腔体；
形成所述第二下电极材料层，所述第二下电极材料层填充所述腔体并覆盖所 述第一下电极层和所述第三支撑层的顶部。
在一些实施例中，形成所述第二下电极材料层后，所述方法还包括：
在所述第二下电极材料层上方形成掩膜层和位于所述掩膜层上的图形化的光刻胶层；所述掩膜层包括第二掩膜层与第三掩膜层，所述第二下电极材料层的顶部充当部分掩膜层使用。
在一些实施例中，形成所述掩膜层和位于所述掩膜层上的所述图形化的光刻胶层后，所述方法还包括：
基于所述图形化的光刻胶层，刻蚀所述第三掩膜层、所述第二掩膜层以及所述第二下电极材料层的顶部，将光刻胶层图案转移至所述第二下电极材料层，形成第一开口，所述第一开口暴露至少一个所述第一下电极层的部分区域和部分所述第三支撑层；
以图案化之后的所述第二下电极材料层为掩膜刻蚀所述第三支撑层，形成第二开口，所述第二开口暴露所述第二牺牲层；
去除所述第二牺牲层，暴露所述第二支撑层；
刻蚀所述第二支撑层，形成第三开口，并去除覆盖所述第三支撑层和所述第一下电极层顶部的所述第二下电极材料层，所述第三开口暴露所述第一牺牲层，剩余的所述第二下电极材料层定义为所述第二下电极层；
去除所述第一牺牲层，暴露所述第一支撑层，剩余的所述第一支撑层、所述第二支撑层及所述第三支撑层定义为支撑结构。
在一些实施例中，形成所述第二下电极材料层，包括：
在温度范围为470-530℃的温度下形成所述第二下电极材料层。
在一些实施例中，在去除所述第一牺牲层，暴露所述第一支撑层之后，所述方法还包括：
在所述第一下电极层与第二下电极层以及第一支撑层与第三支撑层暴露的表面上形成介电层；
在所述介电层的表面上形成上电极。根据本公开实施例的第二方面，提供了一种半导体结构，包括：
基底；
位于所述基底上方的支撑结构，所述支撑结构中包括贯穿所述支撑结构的电容孔；
位于所述电容孔内的下电极，其中，所述下电极包括第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的底部和侧壁，并构成腔体，所述第二下电极层填充于所述腔体；其中，所述第二下电极层中的应力小于所述第一下电极层中的应力。
在一些实施例中，所述第二下电极层的材料包括含硅的结晶材料。
在一些实施例中，所述含硅的结晶材料的晶粒尺寸小于1nm。
在一些实施例中，所述下电极的直径不大于40nm。
在一些实施例中，所述第一下电极层沿所述电容孔的径向方向的厚度为10-15nm，所述第二下电极层沿所述电容孔的径向方向的厚度为15-30nm。
在一些实施例中，所述半导体结构还包括：
覆盖所述下电极及所述支撑结构的介电层和覆盖所述介电层的上电极。
本公开实施例提供了一种半导体结构的制造方法，包括：提供基底；在所述基底上形成叠层结构；刻蚀所述叠层结构以形成电容孔；在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体；其中，所述第二下电极层中的应力小于所述第一下电极层中的应力。本公开首先在位于基底上的叠层结构中形成电容孔，然后在电容孔内形成第一下电极层和第二下电极层，第一下电极层覆盖电容孔的内表面并在电容孔内形成腔体，第二下电极层填充腔体，第一下电极层与第二下电极层共同构成下电极。其中，由于第二下电极层填充了第一下电极层的腔体，且第二下电极层中的应力小于第一下电极层中的应力，因此能够改善单一第一下电极的应力过大导致电容柱易倾斜的情况，本公开实施例可以消除薄膜应力，第二下电极层可以对第一下电极层起到稳定、良好的支撑作用，使得工艺过程中电容柱的稳定性得以增强，不易发生倾斜。进而能够改善因电容柱倾斜导致的刻蚀开口偏斜时，所造成的支撑层无法正常打开，以至于无法充分去除底部氧化层，使得无法给上电极预留充分空间，从而导致整个电容失效的问题。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
图1为本公开一实施例的半导体结构的制造方法的流程图；
图2a至图2q为本公开实施例提供的半导体结构在制造过程中的结构示意图；
图3为本公开一实施例的半导体结构的剖面示意图。
附图标记：
10-基底；101-衬底；102-导电接触层；11-叠层结构；111-第一支撑层；112-第一牺牲层；113-第二支撑层；114-第二牺牲层；115-第三支撑层；12-电容孔；121-腔体；14-第一下电极层；141-第一下电极材料层；15-第二下电极层；151-第二下电极材料层；16-下电极；17-掩膜层；171-第一掩膜层；172-第二掩膜层；173-第三掩膜层；18-图形化的光刻胶层；191-第一开口；19-第二开口；20-第三开口；30-支撑结构；32-介电层；33-上电极。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公 知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
随着动态随机存取存储器(DRAM)特征尺寸不断微缩，通常通过增加电容柱的高度来增加电容器的电容，以提升存储密度。在特征尺寸减小至一定数值以下时，形成高深宽比的电容柱结构会面临结构上因薄膜应力增加等导致的电容柱倾斜等问题，进而导致后续电容结构制造工艺中无法正常打开，因此下层氧化层无法充分去除，造成预留给电容上电极的空间不足，导致电容失效的问题。
基于此，本公开提供了一种半导体结构的制造方法，具体请参见图1，如图所示，所述方法包括：
步骤101：提供基底；
步骤102：在所述基底上形成叠层结构；刻蚀所述叠层结构以形成电容孔；
步骤103：在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体；其中，所述第二下电极层中的应力小于所述第一下电极层中的应 力。
下面结合具体实施例对本公开提供的半导体结构的制造方法再作进一步详细的说明。
首先，执行步骤101，参见图2a，提供基底10。
在实际操作中，基底10例如包括但不限于单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。衬底可以是掺杂的或未掺杂的，或者在其中包含掺杂区域和未掺杂区域二者。衬底还可以包括一个或多个掺杂(n -或p -)区域；如果衬底包括多个掺杂区域，则这些区域可以具有相同或者不同的导电性和/或掺杂浓度。这些掺杂区域被称为“阱”，并且可以用于限定各个器件区域。参见图2a，在一具体实施例中，基底10包括经掺杂或未经掺杂的硅衬底101，衬底101上方包括导电接触层102，导电材料可以包括金属材料，例如金属钨(W)。
接下来，执行步骤102，参见图2a和图2b，在所述基底10上形成叠层结构11；刻蚀所述叠层结构11以形成电容孔12。
具体的，在所述基底10上形成叠层结构11以及刻蚀所述叠层结构11以形成所述电容孔12包括：形成所述叠层结构11于所述基底10上，所述叠层结构11至少包括第一支撑层111、第一牺牲层112、第二支撑层113、第二牺牲层114以及第三支撑层115(如图2a所示)；沿垂直于所述基底10的方向刻蚀所述叠层结构11，暴露出所述基底10，形成所述电容孔12(如图2b所示)。
上述叠层结构中包含两层牺牲层和三层支撑层，在保证形成的电容结构的高度条件下，还能够较好地支撑形成的电容结构。
在实际操作中，第一支撑层111、第一牺牲层112、第二支撑层113、第二牺牲层114以及第三支撑层115可以采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种工艺形成；刻蚀叠层结构11形成电容孔12可以采用各向异性刻蚀工艺，例如等离子体刻蚀工艺形成。在基底10上依次沉积形成第一支撑层111、第二支撑层113及第三支撑层115的材料包括但不限于氮化物，在一具体的实施例中，第二支撑层113和第三支撑层115的材料可以为含C的绝缘材料，例如SiCN，因SiCN材料硬度很好，可以对后续形成的电容结构起到很好的支撑作用。第一支撑层111和第一牺牲层112的材料可以为含B的绝缘材料，例如第一支撑层111的材料可以为SiBN，第一牺牲层112的材料可以为硼磷硅玻璃(BPSG)，因第一牺牲层112和第一支撑层111均采用掺杂了硼元素的材料，降低了材料的硬度，使刻蚀工艺更容易完成，可保证电容孔12的形貌。
可以理解的是，上述叠层结构11包含的膜层种类和膜层数可以根据电容结构的高度而变化，在此不作具体限制。
最后，执行步骤103，在所述电容孔12内形成第一下电极层14和第二下电极层15，所述第一下电极层14覆盖所述电容孔12的内表面并在所述电容孔12内形成腔体121，所述第二下电极层15填充所述腔体121；其中所述第二下电极层15中的应力小于所述第一下电极层14中的应力。
由于第二下电极层填充了第一下电极层的腔体，且第二下电极层中的应力小 于第一下电极层中的应力，因此能够对第一下电极层起到稳定、良好的支撑作用，使得工艺过程中电容柱的稳定性得以增强，不易发生倾斜。进而能够改善因电容柱倾斜导致的刻蚀开口偏斜时，所造成的支撑层无法正常打开，以至于无法充分去除底部氧化层，使得无法给上电极预留充分空间，从而导致整个电容失效的问题。
这里，第二下电极层15的材料可以包括导电或非导电的材料，优选为填充性好且薄膜应力小的材料，例如包括但不限于含硅的结晶材料。
在一些具体的实施例中，第二下电极层15的材料可以包括掺杂或未掺杂的含硅的结晶材料。
在实际操作中，第二下电极层15的材料例如包括但不限于多晶硅、硅锗等，上述材料具有优良的填充性，可充分填充于第一下电极层14的腔体内，且形成的膜层应力比较小，可以对第一下电极层14起到很好的支撑作用，避免电容柱倾斜、偏移等问题。
在一些具体实施例中，所述含硅的结晶材料的晶粒尺寸小于1nm。
优选地，含硅的结晶材料的晶粒尺寸小于0.1nm。材料的晶粒尺寸越小，填充性能越好，更容易填充在尺寸为几十纳米级的第一下电极层的腔体内；此外，材料的晶粒尺寸越小，形成的晶格应力越小，最后形成的第二下电极层的应力会更小，对第一下电极层有更好的支撑作用。
在一些实施例中，第二下电极层15可以包括单层材料；在一些其他实施例中，第二下电极层15可以包括多层材料，例如，第二下电极层沿着电容孔的径向从轴心指向外围的方向，依次包括第1子层……第N子层，其中N为大于或等于2的正整数。在一些更具体的实施方式中，所述第1子层……第N子层中各层的硬度和/或薄膜应力可以不同，具体的，例如，在一些实施方式中，沿电容孔的径向从轴心指向外围的方向，第1子层……第N子层的硬度依次减小，薄膜应力逐渐减小。如此，能够进一步提高第二下电极层15对第一下电极层14的支撑作用，从而进一步增强下电极16的稳定性。
在一些实施例中，参见图2e和图2p，所述第一下电极层14与所述第二下电极层15共同定义为下电极16，所述下电极16的直径不大于40nm。
电容的尺寸越小，越容易发生倾斜、倒塌等问题。柱状(Pillar)电容的直径往往在几十纳米的尺度，因此非常容易发生电容的倾斜和偏移。本公开实施例提供的电容制备方法与极小尺寸的电容制备工艺(例如Pillar电容)兼容，能够应用于制备例如下电极16直径不大于40nm、不大于30nm或不大于20nm的小尺寸电容工艺中，以缓解和避免极小尺寸电容制备工艺中存在的倾斜、偏移进而引起的后续制作电容的介电层及上电极的步骤难以顺利进行等问题，从而提供极小尺寸且稳定可靠的电容结构。
在一些具体实施例中，所述第一下电极层沿所述电容孔的径向方向的厚度为10-15nm，所述第二下电极层沿所述电容孔的径向方向的厚度为15-30nm。
在上述实施例中，第二下电极层15主要起到支撑第一下电极层14的作用，第一下电极层14主要作为电容器电极板发挥作用，当第二下电极层15的厚度与第一下电极层14的厚度的比值较小时，由于下电极16中第二下电极层15的厚度占比较小，对改善电容柱倾斜、偏移的效果有限；当第二下电极层15的厚度 与第一下电极层14的厚度的比值较大时，由于下电极16中第一下电极层14的厚度占比较小，会使电容结构的性能受到一定影响。因此，使第二下电极层15的厚度稍大于第一下电极层14的厚度，能够在获得较好的改善电容柱倾斜、偏移的有益效果的同时，兼顾电容结构的容量性能。
本公开实施例提供两种制备下电极16的实施方式，如图2c至图2e所示，在第一种实施方式中，在所述电容孔12内形成第一下电极层14和第二下电极层15，所述第一下电极层14覆盖所述电容孔12的内表面并在所述电容孔12内形成腔体121，所述第二下电极层15填充所述腔体121，包括：形成第一下电极材料层141，所述第一下电极材料层141覆盖所述电容孔12的内表面以及所述叠层结构11的上表面，所述第一下电极材料层141在所述电容孔12内形成腔体121(参见图2c)；形成第二下电极材料层151，所述第二下电极材料层151填充所述腔体121并覆盖所述第一下电极材料层141的顶部(参见图2d)；刻蚀所述第二下电极材料层151及所述第一下电极材料层141的顶部，暴露出所述第三支撑层115，剩余的所述第一下电极材料层141与所述第二下电极材料层151分别定义为所述第一下电极层14和所述第二下电极层15(参见图2e)。
在实际操作中，可以在550℃～650℃下，采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺，沉积形成第一下电极层14，第一下电极层14的材料包括但不限于钛(Ti)、氮化钛(TiN)或钨(W)等。刻蚀所述第二下电极材料层151及所述第一下电极材料层141的顶部，暴露出所述第三支撑层115的步骤，可以采用湿法或干法刻蚀工艺，例如等离子体刻蚀工艺、化学机械研磨工艺(CMP)等。在一些具体实施例中，如图2e所示，在进行上述刻蚀工艺暴露出所述第三支撑层115之后，第二下电极层15和/或第一下电极层14与第三支撑层115的上表面齐平。应当理解的是，在一些其他实施方式中，第二下电极层15、第一下电极层14与第三支撑层115的上表面可以不齐平，只需暴露出第三支撑层115即可。
在一具体的实施例中，形成所述第二下电极材料层151，包括：在温度范围为470-530℃的温度下形成所述第二下电极材料层151。
在实际操作中，可以采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺中的一种或多种，在470℃～530℃下制备第二下电极层15。在上述温度范围下，填充材料晶粒的尺寸及形态较好，形成的晶格应力更可控，制备得到的第二下电极层15的硬度适中，且薄膜应力足够小，进而能够对第一下电极层14产生较优异的应力改善效果。
上述第一种实施方式中形成的第一下电极层14和第二下电极层15共同构成下电极16。
在按照上述第一种实施方式形成下电极16后，接下来，参见图2f，所述方法还包括：在所述第一下电极层14、所述第二下电极层15及所述第三支撑层115上方形成掩膜层17和位于所述掩膜层17上的图形化的光刻胶层18；所述掩膜层17包括第一掩膜层171、第二掩膜层172及第三掩膜层173，其中，所述第一掩模层171的材料与所述第三支撑层115的材料相同。
第一掩膜层和第三支撑层的材料相同，可以使得支撑结构对下电极的支撑效果更好，从而更好地改善下电极倾斜、偏移的问题，因此可避免后续在对支撑结 构进行刻蚀形成开口时受下电极倾斜、偏移的影响导致开口失败，进而导致后续电容制作步骤不能顺利进行的问题。此外，第一掩膜层可以在刻蚀工艺中保护第三支撑层、第一下电极层以及第二下电极层的表面不被刻蚀，进而保证支撑结构的支撑效果和电容结构的性能。进一步的，与第三支撑层相同的材料的第一掩膜层的设置还可以控制第三支撑层和第一下电极层之间的高度差，从而控制电容的表面形貌。
在实际操作中，可采用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)工艺，沉积形成掩膜层17，其中第一掩膜层171的材料可以包括但不限于SiCN，第二掩膜层172的材料可以包括但不限于碳，第三掩膜层173的材料可以包括但不限于SiON。
光刻是制作半导体结构中的一个重要的工艺，随着特征尺寸的不断减小，使得光刻的难度不断增加，在光刻胶层中定义图形时，由于光刻胶下方的半导体基底(包括金属层和介质层)具有较高的反射系数，使得曝光光源容易在半导体基底表面发生反射，造成光刻胶图形的变形或尺寸偏差，导致掩膜板图形的不正确转移。为了消除光源的反射现象，通常在半导体基底的表面形成一层介电抗反射涂层(Dielectric Anti-Reflective Coating，DARC)，介电抗反射涂层的材料一般为氮氧化硅等。上述实施例中的第三掩膜层173可作为介电抗反射涂层发挥作用。
接下来，参见图2g至图2j，在形成所述掩膜层17和位于所述掩膜层17上的所述图形化的光刻胶层18后，所述方法还包括：基于所述图形化的光刻胶层18，刻蚀所述掩膜层17，将光刻胶层图案转移至所述第一掩膜层171，形成第一开口191，所述第一开口191暴露至少一个所述第一下电极层14的部分区域和部分所述第三支撑层115；以所述第一掩模层171为掩膜刻蚀所述第三支撑层115，形成第二开口19，所述第二开口19暴露所述第二牺牲层114(参见图2g)；去除所述第二牺牲层114，暴露所述第二支撑层113(参见图2h)；刻蚀所述第二支撑层113，形成第三开口20，所述第三开口20暴露所述第一牺牲层112(参见图2i)；去除所述第一牺牲层112，暴露所述第一支撑层111(参见图2j)，剩余的所述第一支撑层111、所述第二支撑层113及所述第三支撑层115定义为支撑结构。
由于第一下电极层和第二下电极层共同形成了稳定的下电极结构，在采用光刻技术和蚀刻工艺形成开口的过程中，不会因为下电极出现倾斜或偏移而引起对准偏差，导致形成开口失败，因此避免了因开口失败引起的在后续湿法刻蚀工艺中刻蚀液难以充分接触第一牺牲层的问题，进而避免了因第一牺牲层不能被完全去除而引起电容结构制作失败的问题。
在实际操作中，可以采用例如光刻和蚀刻工艺刻蚀第三支撑层115和第二支撑层113，以形成第一开口191、第二开口19和第三开口20。去除第一牺牲层112和第二牺牲层114的方法包括但不限于采用稀释的氢氟酸(DHF)或氢氟酸(HF)和氟化氨(NH 4F)的混合液以湿法刻蚀的方法，选择性地蚀刻去除第一牺牲层112和第二牺牲层114的材料，保留第一下电极层14及第二下电极层15和第一支撑层111、第二支撑层113及第三支撑层115。具体地，第一牺牲层112和第二牺牲层114是依顺序分别进行蚀刻的，首先蚀刻第二牺牲层114，然后再蚀刻第一牺牲层112。
如图2c、2k至图2p所示，在形成下电极16的第二种实施方式中，在所述 电容孔12内形成第一下电极层14和第二下电极层15，所述第一下电极层14覆盖所述电容孔12的内表面并在所述电容孔12内形成腔体121，所述第二下电极层15填充所述腔体121，包括：形成第一下电极材料层141，所述第一下电极材料层141覆盖所述电容孔12的内表面以及所述叠层结构11的上表面，所述第一下电极材料层141在所述电容孔12内形成腔体121(参见图2c)；去除所述第一下电极材料层141的顶部，暴露出所述第三支撑层115，剩余的所述第一下电极材料层141定义为第一下电极层14，所述第一下电极层14在所述电容孔12内形成腔体121(参见图2k)；形成所述第二下电极材料层151，所述第二下电极材料层151填充所述腔体121并覆盖所述第一下电极层14和所述第三支撑层115的顶部(参见图2l)。
接下来，参见图2m，在形成所述第二下电极材料层151之后，所述方法还包括：在所述第二下电极材料层151上方形成掩膜层17和位于所述掩膜层17上的图形化的光刻胶层18；所述掩膜层17包括第二掩膜层172与第三掩膜层173，所述第二下电极材料层151的顶部充当部分掩膜层使用。
上述第二下电极材料层不仅填充于腔体内，还覆盖第一下电极层和第三支撑层的顶部，对第一下电极层的支撑效果更好，可更好地改善第一下电极层因应力等易发生倾斜、及偏移的问题。此外，第二下电极材料层的顶部可以作为掩膜层中的第一掩膜层发挥作用，因此相对于上述第一种实施方式，可节省形成第一掩膜层的工艺。
在实际操作中，形成第一下电极材料层141、第二下电极材料层151以及形成掩膜层17中的第二掩膜层172与第三掩膜层173，均可以采用与上述第一种实施方式中类似的方法形成，在此不再赘述。去除第一下电极材料层141的顶部，暴露出第三支撑层115的步骤，可以采用湿法或干法刻蚀工艺，例如等离子体刻蚀工艺、化学机械研磨工艺(CMP)等。
接下来，参见图2n至图2q，在形成所述掩膜层17和位于所述掩膜层17上的所述图形化的光刻胶层18后，所述方法还包括：基于所述图形化的光刻胶层18，刻蚀所述第三掩膜层173、所述第二掩膜层172以及所述第二下电极材料层151的顶部，将光刻胶层图案转移至所述第二下电极材料层151，形成第一开口191，所述第一开口191暴露至少一个所述第一下电极层14的部分区域和部分所述第三支撑层115；以图案化之后的所述第二下电极材料层151为掩膜刻蚀所述第三支撑层115，形成第二开口19，所述第二开口19暴露所述第二牺牲层114(参见图2n)；去除所述第二牺牲层114，暴露所述第二支撑层113(参见图2o)；刻蚀所述第二支撑层113，形成第三开口20，并去除覆盖所述第三支撑层115和所述第一下电极层14顶部的所述第二下电极材料层，所述第三开口20暴露所述第一牺牲层112，剩余的所述第二下电极材料层定义为所述第二下电极层15(参见图2p)；去除所述第一牺牲层112，暴露所述第一支撑层111(参见图2q)，剩余的所述第一支撑层111、所述第二支撑层113及所述第三支撑层115定义为支撑结构。
在实际操作中，形成第一开口191、第二开口19和第三开口20，以及去除第一牺牲层112和第二牺牲层114，均可以采用与上述第一种实施方式中类似的方法形成，在此不再赘述。
在一些具体的实施例中，所述第一牺牲层112和所述第二牺牲层114相对于所述第二下电极材料层151具有高蚀刻选择比。
上述实施例中，在支撑层中形成开口，以去除第一牺牲层和第二牺牲层，从而便于进行后续制作电容结构的工艺。第一牺牲层112和第二牺牲层114相对于第二下电极材料层151具有高蚀刻选择比，使得采用湿法刻蚀去除第一牺牲层和第二牺牲层时，对第二下电极材料层基本没有影响，因此不会影响第二下电极材料层对第一下电极层的支撑效果，进而避免电容柱倾斜、偏移等问题。
上述为按照第二种实施方式形成由第二下电极层15和第一下电极层14共同构成的下电极16。
接下来，按照上述两种实施方式中的任一种形成下电极16并去除所述第一牺牲层112，暴露所述第一支撑层111之后，参见图3，所述方法还包括：在所述第一下电极层14与第二下电极层15以及第一支撑层111与第三支撑层115暴露的表面上形成介电层32；在所述介电层32的表面上形成上电极33。
本公开实施例还提供了一种半导体结构，具体请参见图3，如图所示，半导体结构包括：
基底10；
位于所述基底10上方的支撑结构30，所述支撑结构30中包括贯穿所述支撑结构30的电容孔12；
位于所述电容孔12内的下电极16，其中，所述下电极16包括第一下电极层14和第二下电极层15，所述第一下电极层14覆盖所述电容孔12的底部和侧壁，并构成腔体121，所述第二下电极层15填充于所述腔体121；其中，所述第二下电极层15中的应力小于所述第一下电极层14中的应力。
由于第二下电极层填充了第一下电极层的腔体，且第二下电极层中的应力小于第一下电极层中的应力，因此能够对第一下电极层起到稳定、良好的支撑作用，使得电容柱的稳定性得以增强，不易发生倾斜。
在实际操作中，基底10例如包括但不限于单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。衬底可以是掺杂的或未掺杂的，或者在其中包含掺杂区域和未掺杂区域二者。衬底还可以包括一个或多个掺杂(n -或p -)区域；如果衬底包括多个掺杂区域，则这些区域可以具有相同或者不同的导电性和/或掺杂浓度。这些掺杂区域被称为“阱”，并且可以用于限定各个器件区域。参见图3，在一具体实施例中，基底10包括经掺杂或未经掺杂的硅衬底101，衬底101上方包括导电接触层102，导电材料可以包括金属材料，例如金属钨(W)。
参见图3，支撑组件30包括第一支撑层111、第二支撑层113以及第三支撑层115，其中，第一支撑层111、第二支撑层113以及第三支撑层115的材料包括但不仅限于氮化物，第一支撑层111、第二支撑层113以及第三支撑层115的材料可以相同，也可以不同，具体地，第一支撑层111的材料可以为含B的绝缘材料，例如SiBN，因掺杂B可降低材料的硬度，使得例如采用刻蚀方法形成的电容孔12的形貌较好。第二支撑层113及第三支撑层115的材料可以为含C的绝缘材料，例如SiCN，因SiCN材料硬度很好，可以对下电极16起到很好的支撑 作用。第一下电极层14的材料包括但不限于钛(Ti)、氮化钛(TiN)或钨(W)等，第一下电极层14的厚度例如可以为10nm～15nm。
在一些实施例中，第二下电极层15的材料可以包括导电或非导电的材料，优选为填充性好且薄膜应力小的材料，例如包括但不限于含硅的结晶材料。在实际操作中，第二下电极层15的材料例如包括但不限于多晶硅、硅锗等，上述材料具有优良的填充性，可充分填充第一电极层14的腔体121内，且形成的膜层应力比较小，可以对第一下电极层14起到很好的支撑作用，避免电容柱倾斜、偏移等问题。
在一些具体实施例中，所述含硅的结晶材料的晶粒尺寸小于1nm。
优选地，含硅的结晶材料的晶粒尺寸小于0.1nm。材料的晶粒尺寸越小，填充性能越好，更容易填充在尺寸为几十纳米级的第一下电极层的腔体中；此外，材料的晶粒尺寸越小，形成的晶格应力越小，最后形成的第二下电极层的应力会更小，对第一下电极层有更好的支撑作用。
在一些实施例中，参见图3，所述下电极16的直径不大于40nm。
电容的尺寸越小，越容易发生倾斜、倒塌等问题。Pillar电容的直径往往在几十纳米的尺度，因此非常容易发生电容的倾斜和偏移。本公开实施例提供的电容结构是采用前述实施例中的制造方法制得，可以制备很小尺寸的电容结构，例如下电极16直径不大于40nm、不大于30nm或不大于20nm的小尺寸电容，上述下电极结构可缓解和避免制备的极小尺寸的电容存在的倾斜、偏移等问题，实现了极小尺寸且稳定可靠的电容结构。
在一些实施例中，参见图3，所述第一下电极层沿所述电容孔的径向方向的厚度为10-15nm，所述第二下电极层沿所述电容孔的径向方向的厚度为15-30nm。
在上述实施例中，第二下电极层15主要起到支撑第一下电极层14的作用，第一下电极层14主要作为电容器电极板发挥作用，当第二下电极层15的厚度与第一下电极层14的厚度的比值较小时，由于下电极16中第二下电极层15的厚度占比较小，对改善电容柱倾斜、偏移的效果有限；当第二下电极层15的厚度与第一下电极层14的厚度的比值较大时，由于下电极16中第一下电极层14的厚度占比较小，会使电容结构的性能受到一定影响。因此，使第二下电极层15的厚度稍大于第一下电极层14的厚度，能够在获得较好的改善电容柱倾斜、偏移的有益效果的同时，兼顾电容结构的性能。
在一些实施例中，参见图3，所述半导体结构还包括：覆盖所述下电极16及所述支撑结构30的介电层32和覆盖所述介电层32的上电极33。
在实际操作中，介电层32的材料包括但不限于氧化铝、氮化硅、氧化硅、氧化锆或其组合等。上电极33的材料包括但不限于钛(Ti)、氮化钛(TiN)或钨(W)等。上述下电极16和介电层32及上电极33共同组成完整的电容结构。
综上所述，本公开首先在位于基底上的叠层结构中形成电容孔，然后在电容孔内形成第一下电极层和第二下电极层，第一下电极层覆盖电容孔的内表面并在电容孔内形成腔体，第二下电极层填充腔体，第一下电极层与第二下电极层共同构成下电极。其中，由于第二下电极层填充了第一下电极层的腔体，且第二下电极层中的应力小于第一下电极层中的应力，从而能够改善单一第一下电极的应力过大导致电容柱易倾斜的情况，本公开实施例可以消除薄膜应力，第二下电极层 可以对第一下电极层起到稳定、良好的支撑作用，使得工艺过程中电容柱的稳定性得以增强，不易发生倾斜。进而能够改善因电容柱倾斜导致的刻蚀开口偏斜时，所造成的支撑层无法正常打开，以至于无法充分去除底部氧化层，使得无法给上电极预留充分空间，从而导致整个电容失效的问题。
需要说明的是，本公开实施例提供的半导体结构的制造方法及半导体结构可以应用于任何包括该结构的集成电路中。各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例可以消除薄膜应力，第二下电极层可以对第一下电极层起到稳定、良好的支撑作用，使得工艺过程中电容柱的稳定性得以增强，不易发生倾斜。进而能够改善因电容柱倾斜导致的刻蚀开口偏斜时，所造成的支撑层无法正常打开，以至于无法充分去除底部氧化层，使得无法给上电极预留充分空间，从而导致整个电容失效的问题。

Claims (20)

  1. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底上形成叠层结构；
    刻蚀所述叠层结构以形成电容孔；
    在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体；其中，
    所述第二下电极层中的应力小于所述第一下电极层中的应力。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，所述第二下电极层的材料包括含硅的结晶材料。
  3. 根据权利要求2所述的半导体结构的制造方法，其中，所述含硅的结晶材料的晶粒尺寸小于1nm。
  4. 根据权利要求1所述的半导体结构的制造方法，其中，所述第一下电极层与所述第二下电极层共同定义为下电极，所述下电极的直径不大于40nm。
  5. 根据权利要求1或4所述的半导体结构的制造方法，其中，所述第一下电极层沿所述电容孔的径向方向的厚度为10-15nm，所述第二下电极层沿所述电容孔的径向方向的厚度为15-30nm。
  6. 根据权利要求1所述的半导体结构的制造方法，其中，在所述基底上形成叠层结构，以及刻蚀所述叠层结构以形成所述电容孔，包括：
    形成所述叠层结构于所述基底上，所述叠层结构至少包括第一支撑层、第一牺牲层、第二支撑层、第二牺牲层以及第三支撑层；
    沿垂直于所述基底的方向刻蚀所述叠层结构，暴露出所述基底，形成所述电容孔。
  7. 根据权利要求6所述的半导体结构的制造方法，其中，在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体，包括：
    形成第一下电极材料层，所述第一下电极材料层覆盖所述电容孔的内表面以及所述叠层结构的上表面，所述第一下电极材料层在所述电容孔内形成腔体；
    形成第二下电极材料层，所述第二下电极材料层填充所述腔体并覆盖所述第一下电极材料层的顶部；
    刻蚀所述第二下电极材料层及所述第一下电极材料层的顶部，暴露出所述第三支撑层，剩余的所述第一下电极材料层与所述第二下电极材料层分别定义为所述第一下电极层和所述第二下电极层。
  8. 根据权利要求7所述的半导体结构的制造方法，其中，刻蚀所述第二下电极层及所述第一下电极层的顶部，暴露出所述第三支撑层后，所述方法还包括：
    在所述第一下电极层、所述第二下电极层及所述第三支撑层上方形成掩膜层和位于所述掩膜层上的图形化的光刻胶层；所述掩膜层包括第一掩膜层、第二掩膜层及第三掩膜层，其中，所述第一掩模层的材料与所述第三支撑层的材料相同。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，形成所述掩膜层和位于所述掩膜层上的所述图形化的光刻胶层后，所述方法还包括：
    基于所述图形化的光刻胶层，刻蚀所述掩膜层，将光刻胶层图案转移至所述第一掩膜层，形成第一开口，所述第一开口暴露至少一个所述第一下电极层的部分区域和部分所述第三支撑层；
    以所述第一掩模层为掩膜刻蚀所述第三支撑层，形成第二开口，所述第二开口暴露所述第二牺牲层；
    去除所述第二牺牲层，暴露所述第二支撑层；
    刻蚀所述第二支撑层，形成第三开口，所述第三开口暴露所述第一牺牲层；
    去除所述第一牺牲层，暴露所述第一支撑层，剩余的所述第一支撑层、所述第二支撑层及所述第三支撑层定义为支撑结构。
  10. 根据权利要求6所述的半导体结构的制造方法，其中，在所述电容孔内形成第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的内表面并在所述电容孔内形成腔体，所述第二下电极层填充所述腔体，包括：
    形成第一下电极材料层，所述第一下电极材料层覆盖所述电容孔的内表面以及所述叠层结构的上表面，所述第一下电极材料层在所述电容孔内形成腔体；
    去除所述第一下电极材料层的顶部，暴露出所述第三支撑层，剩余的所述第一下电极材料层定义为第一下电极层，所述第一下电极层在所述电容孔内形成腔体；
    形成所述第二下电极材料层，所述第二下电极材料层填充所述腔体并覆盖所述第一下电极层和所述第三支撑层的顶部。
  11. 根据权利要求10所述的半导体结构的制造方法，其中，形成所述第二下电极材料层后，所述方法还包括：
    在所述第二下电极材料层上方形成掩膜层和位于所述掩膜层上的图形化的光刻胶层；所述掩膜层包括第二掩膜层与第三掩膜层，所述第二下电极材料层的顶部充当部分掩膜层使用。
  12. 根据权利要求11所述的半导体结构的制造方法，其中，形成所述掩膜层和位于所述掩膜层上的所述图形化的光刻胶层后，所述方法还包括：
    基于所述图形化的光刻胶层，刻蚀所述第三掩膜层、所述第二掩膜层以及所述第二下电极材料层的顶部，将光刻胶层图案转移至所述第二下电极材料层，形成第一开口，所述第一开口暴露至少一个所述第一下电极层的部分区域和部分所述第三支撑层；
    以图案化之后的所述第二下电极材料层为掩膜刻蚀所述第三支撑层，形成第二开口，所述第二开口暴露所述第二牺牲层；
    去除所述第二牺牲层，暴露所述第二支撑层；
    刻蚀所述第二支撑层，形成第三开口，并去除覆盖所述第三支撑层和所述第一下电极层顶部的所述第二下电极材料层，所述第三开口暴露所述第一牺牲层，剩余的所述第二下电极材料层定义为所述第二下电极层；
    去除所述第一牺牲层，暴露所述第一支撑层，剩余的所述第一支撑层、所述第二支撑层及所述第三支撑层定义为支撑结构。
  13. 根据权利要求7-12中任一项所述的半导体结构的制造方法，其中，形成 所述第二下电极材料层，包括：
    在温度范围为470-530℃的温度下形成所述第二下电极材料层。
  14. 根据权利要求9或12所述的半导体结构的制造方法，其中，
    在去除所述第一牺牲层，暴露所述第一支撑层之后，所述方法还包括：
    在所述第一下电极层与第二下电极层以及第一支撑层与第三支撑层暴露的表面上形成介电层；
    在所述介电层的表面上形成上电极。
  15. 一种半导体结构，包括：
    基底；
    位于所述基底上方的支撑结构，所述支撑结构中包括贯穿所述支撑结构的电容孔；
    位于所述电容孔内的下电极，其中，所述下电极包括第一下电极层和第二下电极层，所述第一下电极层覆盖所述电容孔的底部和侧壁，并构成腔体，所述第二下电极层填充于所述腔体；其中，所述第二下电极层中的应力小于所述第一下电极层中的应力。
  16. 根据权利要求15所述的半导体结构，其中，所述第二下电极层的材料包括含硅的结晶材料。
  17. 根据权利要求16所述的半导体结构，其中，所述含硅的结晶材料的晶粒尺寸小于1nm。
  18. 根据权利要求15所述的半导体结构，其中，所述下电极的直径不大于40nm。
  19. 根据权利要求15或18所述的半导体结构，其中，所述第一下电极层沿所述电容孔的径向方向的厚度为10-15nm，所述第二下电极层沿所述电容孔的径向方向的厚度为15-30nm。
  20. 根据权利要求15所述的半导体结构，其中，所述半导体结构还包括：
    覆盖所述下电极及所述支撑结构的介电层和覆盖所述介电层的上电极。
PCT/CN2022/123898 2022-09-07 2022-10-08 一种半导体结构的制造方法及半导体结构 WO2024050907A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030142458A1 (en) * 2001-12-05 2003-07-31 Jae-Hyun Joo Storage nodes of stacked capacitors and methods for manufacturing the same
US20120098132A1 (en) * 2010-10-25 2012-04-26 Hynix Semiconductor Inc. Semiconductor device and method of manufacturing the same
CN114520195A (zh) * 2020-11-19 2022-05-20 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构
CN114824083A (zh) * 2021-01-29 2022-07-29 中国科学院微电子研究所 一种半导体器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030142458A1 (en) * 2001-12-05 2003-07-31 Jae-Hyun Joo Storage nodes of stacked capacitors and methods for manufacturing the same
US20120098132A1 (en) * 2010-10-25 2012-04-26 Hynix Semiconductor Inc. Semiconductor device and method of manufacturing the same
CN114520195A (zh) * 2020-11-19 2022-05-20 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构
CN114824083A (zh) * 2021-01-29 2022-07-29 中国科学院微电子研究所 一种半导体器件及其制备方法

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