WO2024045988A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2024045988A1
WO2024045988A1 PCT/CN2023/110368 CN2023110368W WO2024045988A1 WO 2024045988 A1 WO2024045988 A1 WO 2024045988A1 CN 2023110368 W CN2023110368 W CN 2023110368W WO 2024045988 A1 WO2024045988 A1 WO 2024045988A1
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WIPO (PCT)
Prior art keywords
line
signal
group
display
transistor
Prior art date
Application number
PCT/CN2023/110368
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English (en)
French (fr)
Inventor
杜瑞芳
余娅
钱海蛟
马小叶
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024045988A1 publication Critical patent/WO2024045988A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • LCD panel occupies an important position in the display field.
  • the present disclosure provides a display substrate, including a display area and a peripheral area located on at least one side of the display area.
  • the display substrate includes:
  • the gate line driving circuit is respectively connected to the plurality of signal lines and the gate line, and includes a multi-level driving unit cascaded with each other.
  • the driving unit includes a first element group, and the first element group includes at least one first electronic component;
  • the plurality of signal lines are arranged along a first direction, the first direction is the extension direction of the gate line, and at least one of the plurality of signal lines is located in the first element group close to the display area. one side.
  • At least one of the plurality of signal lines is located on a side of the driving unit close to the display area.
  • the driving unit further includes:
  • a second component group located on the side of the first component group close to the display area, including at least one second electronic component
  • the plurality of signal lines are divided into a first line group and a second line group, the first line group is located between the first element group and the second element group, and the second line group is located between the The second element group is close to one side of the display area.
  • the plurality of signal lines include: a first signal line located in the first line group, and a second signal line located in the second line group;
  • the current on the first signal line is less than or equal to the current on the second signal line.
  • the first signal line is connected to a DC signal input terminal, and the DC signal input terminal is used to input a DC signal to the first signal line;
  • the second signal line is connected to an AC signal input terminal, and the AC signal input terminal is used to input an AC signal to the second signal line.
  • the orthogonal projected area of the first electronic component on the substrate is greater than or equal to the orthogonal projected area of the second electronic component on the substrate.
  • the driving unit includes:
  • a signal input terminal, a signal output terminal and a first transistor The control electrode of the first transistor is connected to the signal input terminal.
  • the first electrode of the first transistor is connected to the control electrode of the first transistor or a high level.
  • the signal line is connected, and the signal output terminal is connected to the gate line;
  • the signal input terminal of the i-th stage driving unit is connected to the first starting signal line or the signal output terminal of the i-jth stage driving unit, the i and the j are both positive integers, and the j is smaller than the i.
  • the first transistor is located in the second element group and is located away from the display area, and the high-level signal line is located in the first line group and is close to the display area. regional settings.
  • the first starting signal line is located in the second line group and is located close to the display area.
  • the plurality of signal lines further include:
  • the low-level signal line is located in the first line group and is arranged on the side of the high-level signal line away from the display area.
  • the driving unit includes:
  • a signal output terminal, a second transistor and a capacitor A signal output terminal, a second transistor and a capacitor.
  • the control electrode of the second transistor is connected to the first electrode of the capacitor.
  • the first electrode of the second transistor is connected to the clock signal line.
  • the third electrode of the second transistor is connected to the clock signal line.
  • the two poles are connected to the second pole of the capacitor and the signal output terminal, and the signal output terminal is connected to the gate line;
  • the second transistor and the capacitor are both located in the first element group, and the clock signal line is located in the second line group.
  • the driving unit includes:
  • a third transistor and a fourth transistor, the control electrode of the third transistor and the control electrode of the fourth transistor are both connected to the second starting signal line;
  • the third transistor and the fourth transistor are located in the second element group and are arranged close to the display area, and the second starting signal line is located in the second line group and is away from the display area. set up.
  • the plurality of signal lines include power supply voltage signal lines and clock signal lines
  • the driving unit includes a plurality of transistors
  • the number of transistors connected to the power supply voltage signal line is greater than the number of transistors connected to the clock signal line, both the power supply voltage signal line and the clock signal line are located in the second line group, and the power supply voltage signal line The line is located on a side of the clock signal line away from the display area.
  • the first line group includes at least one of the following signal lines: a high-level signal line and a low-level signal line;
  • the second line group includes at least one of the following signal lines: a low-level signal line, a power supply voltage signal line, a clock signal line, and a start signal line.
  • both the first component group and the second component group include at least one of the following electronic components: a transistor and a capacitor.
  • the driving unit includes a transistor, and the control electrode of the transistor, the signal line and the gate line are all located in the same film layer and made of the same material.
  • the display substrate includes two gate line driving circuits, the two gate line driving circuits are a first gate line driving circuit and a second gate line driving circuit respectively, and the third gate line driving circuit A gate line driving circuit is connected to the gate lines located in the even-numbered rows, and the second gate line driving circuit is connected to the gate lines located in the odd-numbered rows;
  • the first gate line driving circuit and a plurality of signals connected to the first gate line driving circuit The signal line is located on the first side of the display area.
  • the second gate line driving circuit and a plurality of signal lines connected to the second gate line driving circuit are located on the second side of the display area.
  • the first side and the second side are two opposite sides along the first direction.
  • the present disclosure provides a display panel, including the display substrate described in any embodiment.
  • the display panel further includes:
  • the box substrate is arranged opposite to the display substrate;
  • Frame sealing glue is provided between the box alignment substrate and the display substrate, and the orthographic projection of the frame sealing glue on the substrate is located in the peripheral area;
  • the driving unit further includes: a second component group, located on a side of the first component group close to the display area, including at least one second electronic component; the plurality of signal lines are divided into a first line group and a second line group, the first line group is located between the first element group and the second element group, the second line group is located on a side of the second element group close to the display area;
  • the orthographic projection of the frame sealant on the substrate covers the orthographic projection of the first element group, the first line group and at least part of the second element group on the substrate.
  • the present disclosure provides a display device, including:
  • a display panel as in any embodiment is a display panel as in any embodiment.
  • a driving chip is connected to the plurality of signal lines and used to provide driving signals to the plurality of signal lines.
  • Figure 1 schematically shows a schematic plan view of a display substrate in the related art
  • Figure 2 schematically shows a schematic plan view of a display substrate provided by the present disclosure
  • Figure 3 schematically shows the structural schematic diagram of the dotted frame E in the display substrate provided by the present disclosure
  • Figure 4 schematically shows a microscope image at the dotted box E in the display substrate provided by the present disclosure
  • Figure 5 schematically shows the structural schematic diagram of the dotted boxes D, E and F in the display substrate provided by the present disclosure
  • Figure 6 schematically shows the circuit structure diagram of the first driving unit
  • Figure 7 schematically shows the circuit structure diagram of the second driving unit
  • Figure 8 schematically shows a schematic circuit structure diagram of the first gate line driving circuit
  • Figure 9 schematically shows a schematic circuit structure diagram of the second gate line driving circuit
  • Figure 10 schematically shows the simulated waveforms output by the signal output terminals of the two driving units after the high temperature test is completed
  • Figure 11 schematically shows the timing diagram of the input and output signals of a driving unit
  • Figure 12 schematically shows a cross-sectional structural diagram of a display panel
  • FIG. 13 schematically shows a partial plan view of a display panel.
  • the display substrate includes a display area 11 and frame areas 12 located on both sides of the display area 11 .
  • the frame area 12 includes a gate line driving circuit area 13 and a signal line area 14.
  • the gate line driving circuit area 13 is provided with a gate line driving circuit
  • the signal line area 14 is provided with a signal line.
  • the gate line driving circuit and the signal line pass through via holes. connect.
  • the signal line area 14 is located on the side of the gate line driving circuit area 13 away from the display area 11 , so that the distance between the signal line and the outer edge of the frame sealant (not shown in the figure) ( This distance needs to be greater than or equal to a specified value (such as 25mm), which causes the connection vias between the signal lines and the gate line driving circuit to easily corrode.
  • a specified value such as 25mm
  • the present disclosure provides a display substrate, which is schematically shown with reference to FIG. 2 A schematic plan view of a display substrate provided by the present disclosure is shown.
  • the display substrate includes a display area AA and a peripheral area BB located on at least one side of the display area AA.
  • the peripheral area BB is located around the display area AA.
  • FIG. 4 is a microscope diagram corresponding to FIG. 3 .
  • the display substrate includes: a substrate 30, a gate line driving circuit 31, a plurality of signal lines 32 and a plurality of gate lines 33 provided on one side of the substrate 30.
  • the gate line driving circuit 31 and a plurality of gate lines The signal lines 32 are located in the peripheral area BB, and the gate lines 33 are located in the display area AA.
  • the gate line driving circuit 31 is connected to the plurality of signal lines 32 and the gate lines 33 respectively, and is used to output scanning signals to the gate lines 33 according to the driving signals input by the plurality of signal lines 32 .
  • the gate line driving circuit 31 includes mutually cascaded multi-stage driving units RS.
  • the driving units RS include a first element group 34 , and the first element group 34 includes at least one first electronic element.
  • the first electronic component is an electronic component located in the first component group 34 .
  • the first component group 34 may include at least one of the following electronic components: a transistor, a capacitor, and the like.
  • the first component group 34 may include one first electronic component or a plurality of first electronic components.
  • the number of first electronic components included in the first component group 34 is greater than or equal to 1, and less than or equal to the number of all electronic components included in the driving unit RS.
  • the plurality of signal lines 32 are arranged along a first direction, which is the extension direction of the gate line 33 . At least one of the plurality of signal lines 32 is located on the side of the first element group 34 close to the display area AA. That is, one or more signal lines 32 connected to the gate line driving circuit 31 may be located on the side of the first element group 34 in the gate line driving circuit 31 close to the display area AA.
  • the first component group 34 includes two first electronic components, namely a transistor M3 and a capacitor C.
  • the driving unit RS includes 18 electronic components such as a plurality of transistors (M1 to M3 and M5 to M18 as shown in Figure 3) and a capacitor (C as shown in Figure 3).
  • the 10 signal lines 32 include a high level signal line VGH, a low level signal line VGL, two power supply voltage signal lines VDD1 and VDD2, four clock signal lines CLK1, CLK3, CLK5 and CLK7, and two start signal lines STV0 and STV1.
  • all the signal lines (ie, 10 signal lines 32) connected to the gate line driving circuit 31 shown in FIG. 3 are located in the first element group 34 in the gate line driving circuit 31 close to the display area AA. side.
  • the number of signal lines located on the side of the first element group 34 close to the display area AA is greater than or equal to 1, and less than or equal to the total number of signal lines connected to the same gate line driving circuit 31 .
  • the gate line driving circuit 31 and the signal line 32 are connected through a via H.
  • the distance between the one or more signal lines 32 and The distance between the outer edges of the frame sealant can further reduce the probability of corrosion in the connection vias between the signal lines 32 and the gate line driving circuit 31, improve the high-temperature life of the display substrate, and improve the quality and reliability of the display product.
  • the present disclosure can increase the distance between the signal line and the outer edge of the frame sealant without increasing the width of the frame, thus helping to achieve a narrow frame.
  • the gate lines 33 located in the display area AA extend along the first direction, and the plurality of gate lines 33 are arranged along the second direction.
  • the signal line 32 may extend along a second direction, and the first direction and the second direction cross each other or are perpendicular to each other (as shown in FIG. 3 ).
  • the multi-level driving units RS are arranged along the second direction.
  • At least one of the plurality of signal lines 32 is located on a side of the driving unit RS close to the display area AA. That is, one or more signal lines 32 connected to the gate line driving circuit 31 may be located on the side of the driving unit RS in the gate line driving circuit 31 close to the display area AA.
  • the gate line driving circuit 31 shown in FIG. 3 has 10 signal lines connected to the gate line driving circuit 31, of which 8 signal lines are: two power supply voltage signal lines VDD1 and VDD2, and four clock signals.
  • the lines CLK1, CLK3, CLK5 and CLK7, as well as the two start signal lines STV0 and STV1, are all located on the side of the driving unit RS close to the display area AA.
  • the distance between the one or more signal lines 32 and The distance between the outer edges of the frame sealant further reduces the probability of corrosion in the connection vias between these signal lines 32 and the gate line drive circuit 31, improves the high-temperature life of the display substrate, and improves the quality and reliability of the display product.
  • all signal lines 32 connected to the gate line driving circuit 31 may be located on the side of the driving unit RS in the gate line driving circuit 31 close to the display area AA, so that the maximum possible Minimize the probability of corrosion in the via holes connecting the signal line 32 and the gate line drive circuit 31; or, some of the signal lines (i.e. one or more, 10 signals as shown in Figure 3) connected to the gate line drive circuit 31 8 of the lines) are located on the side of the driving unit RS in the gate line driving circuit 31 close to the display area AA.
  • other signal lines 32 can be set according to requirements such as wiring space, and this disclosure does not limit this. .
  • the driving unit RS also includes: a second component group 35 located on a side of the first component group 34 close to the display area AA, including at least one second electronic component.
  • the plurality of signal lines 32 connected to the same gate line driving circuit 31 are divided into a first line group 36 and a second line group 37.
  • the second element group 35 and the first line group 36 are located between the first element group 34 and the second element group 37.
  • the second line group 37 is located on the side of the second element group 35 close to the display area AA.
  • the second electronic component is an electronic component located in the second wire group 37 .
  • the second component group 35 may include at least one of the following electronic components: a transistor and a capacitor.
  • the second wire group 37 may include one second electronic component or a plurality of second electronic components.
  • the number of second electronic components included in the second wire group 37 is greater than or equal to 1, and less than the number of all electronic components included in the driving unit RS.
  • the second component group 35 includes 16 second electronic components, namely transistors M1 to M2 and M5 to M18.
  • the driving unit RS includes 18 electronic components such as a plurality of transistors (M1 to M3 and M5 to M18 as shown in Figure 3) and a capacitor (C as shown in Figure 3).
  • the first line group 36 includes two signal lines 32 , namely a high-level signal line VGH and a low-level signal line VGL.
  • the second line group 37 includes eight signal lines 32, namely two power supply voltage signal lines VDD1 and VDD2, four clock signal lines CLK1, CLK3, CLK5 and CLK7, and two start signal lines STV0 and STV1.
  • the first element group 34 is arranged outside the second element group 35 (that is, on the side close to the edge of the display substrate), and the first line group 36 is arranged between the first element group 34 and the second element group 35 .
  • the second line group 37 is disposed on the inner side of the second element group 35 (that is, on the side closer to the display area AA).
  • the first element group 34, the first line group 36, the second element group 35 and the second line group 37 are sequentially arrangement.
  • some of the signal lines 32 connected to the gate line driving circuit 31 (ie, the second line group The signal line 32) in 37 is located on the side of the driving unit RS in the gate line driving circuit 31 close to the display area AA.
  • Other signal lines 32 ie, the signal lines 32 in the first line group 36 ) are provided between the first element group 34 and the second element group 35 .
  • the plurality of signal lines 32 include: a first signal line 321 located in the first line group 36 , and a second signal line 322 located in the second line group 37 . Wherein, the current on the first signal line 321 is less than or equal to the current on the second signal line 322 .
  • the via holes connecting the larger current signal lines 32 are more likely to corrode, by arranging the second signal lines 322 with larger currents in the second line group 37 closer to the display area AA, the connection between the second signal lines 322 and the frame sealant can be increased. distance from the outer edge, thereby effectively reducing the probability of corrosion of the via holes on the second signal line 322 .
  • the first signal line 321 is connected to a DC signal input terminal (not shown in the figure), and the DC signal input terminal is used to input a DC signal to the first signal line 321 .
  • the DC signal may be, for example, a high-level DC signal or a low-level DC signal.
  • the DC signal does not switch between high and low levels, there is basically no current on the first signal line 321 that transmits the DC signal. Even if the first signal line 321 is placed in the first line group 36 on the outside, the risk of corrosion will not be increased. , and at the same time, the distance between the second wire group 37 and the outer edge of the frame sealant can be further increased to reduce the risk of corrosion in the via hole connecting the second signal line 322 .
  • the first line group 36 includes at least one of the following signal lines: a high-level signal line VGH, a low-level signal line VGL, and other signal lines 32 for transmitting DC signals.
  • the high-level signal line VGH is used to transmit high-level DC signals.
  • the low-level signal line VGL is used to transmit low-level DC signals.
  • the first line group 36 includes two first signal lines 321 , namely a high-level signal line VGH and a low-level signal line VGL.
  • the second signal line 322 is connected to an AC signal input terminal (not shown in the figure), and the AC signal input terminal is used to input the AC signal to the second signal line 322 .
  • the AC signal may be, for example, a pulse square wave signal or the like.
  • the AC signal Since the AC signal has frequent high and low level switching, there is a large current on the second signal line 322 that transmits the AC signal.
  • the second signal line 322 in the second line group 37 By arranging the second signal line 322 in the second line group 37 on the inner side, the current can be increased. The distance between it and the outer edge of the frame sealant reduces the probability of corrosion.
  • the second wire group 37 includes at least one of the following signal wires: supply voltage signal wires; Signal lines 32 such as signal line VDD, clock signal line CLK and start signal line STV are used to transmit AC signals.
  • the power supply voltage signal line VDD can be any one of the two power supply voltage signal lines VDD1 and VDD2 shown in Figure 3
  • the clock signal line CLK can be the four clock signal lines CLK1, CLK3, Either one of CLK5 and CLK7
  • the start signal line STV can be any one of the two start signal lines STV0 and STV1 shown in Figure 3.
  • the second line group 37 includes eight second signal lines 322 , namely two power supply voltage signal lines VDD1 and VDD2 , four clock signal lines CLK1 , CLK3 , CLK5 and CLK7 , and two starting lines. Start signal lines STV0 and STV1.
  • the orthogonal projected area of the first electronic component on the substrate 30 is greater than or equal to the orthogonal projected area of the second electronic component on the substrate 30 .
  • the distance between each signal line 32 and the outer edge of the frame sealant can be further increased, and the connection via holes can be reduced. Corrosion risk, helps reduce frame width.
  • the driving unit RS includes: a signal input terminal Input, a signal output terminal Output and a first Transistor M1, the control electrode of the first transistor M1 is connected to the signal input terminal Input, the first electrode of the first transistor M1 is connected to the control electrode of the first transistor M1 (as shown in Figure 6) or the high-level signal line VGH (as shown in Figure 6) (shown in 7) is connected, and the signal output terminal Output is connected to the gate line 33.
  • the signal input terminal Input of the i-th stage driving unit RS i is connected to the first starting signal line STV1 or the signal output terminal Output of the i-j-th stage driving unit RS i-j.
  • i and j are both positive integers, and j is less than i.
  • the signal input terminal Input of the i-th stage driving unit RS i can be connected to the first starting signal line STV1; when i is greater than j, the signal input terminal Input of the i-th stage driving unit RS i Connect the signal output terminal Output of the i-jth stage drive unit RS i-j.
  • j is equal to 2, that is, the signal input terminal Input of the first-stage driving unit RS1 and the second-stage driving unit RS2 is connected to the first start signal line STV1.
  • the signal input terminal Input of the third-level drive unit RS 3 is connected to the signal output terminal Output of the first-level drive unit RS 1
  • the signal input terminal Input of the fourth-level drive unit RS 4 is connected to the signal output terminal of the second-level drive unit RS 2. Output, and so on.
  • the multi-level driving units RS can be connected to different gate lines 33 respectively.
  • the driving units RS are connected to the gate lines 33 in a one-to-one correspondence.
  • the second pole of the first transistor M1 is connected to the pull-up node PU.
  • the first transistor M1 is used to turn on or off the connection between the first pole and the second pole according to the signal of the control pole. connection, and when the first pole and the second pole are turned on, the signal of the first pole is written to the pull-up node PU.
  • the first electrode of the first transistor M1 is connected to the control electrode of the first transistor M1 .
  • the signal input terminal Input of the i-th stage driving unit RS i is connected to the signal output terminal Output of the i-j-th stage driving unit RS i-j
  • the first pole of the first transistor M1 is connected to the i-j-th stage driving unit RS i-j.
  • the signal output terminal Output of the stage driving unit RS i-j is connected.
  • the sub-pixel load in the display area AA is relatively large, resulting in a delay in the signal output by the signal output terminal Output, thereby causing the i-th
  • the pull-up node PU signal in the first-level drive unit RS i is delayed, which affects the charging of the pull-up node PU.
  • the display substrate is prone to display defects after the reliability test.
  • the first pole of the first transistor M1 is connected to the high-level signal line VGH.
  • the first transistor M1 is turned on, the first pole and the second pole are turned on, so that the high-level signal input from the high-level signal line VGH can be written into the pull-up node PU to charge the pull-up node PU.
  • the high-level signal line VGH is a high-level signal source with no load connected and no delay, even if the threshold voltage of the first transistor M1 drifts after the reliability test, the pull-up node PU can be charged within a limited time. to the highest level, thereby improving product reliability.
  • Figure 10 shows the simulated waveforms output by the signal output terminals of the two driving units after the high temperature test is completed.
  • the delay of the analog waveform output by the signal output terminal Output of the drive unit shown in Figure 7 is small, and the falling edge of the analog waveform output by the signal output terminal Output of the drive unit shown in Figure 6 is obviously tilted, showing obvious delay.
  • the high-temperature test time prolongs its warping will become higher and higher, eventually leading to abnormal display of the display substrate.
  • the inventor also used simulation software to simulate the life of the display substrate using the two drive unit structures of Figure 6 and Figure 7 under high temperature testing. By comparison, it was found that using the structure shown in Figure 7, the life of the display substrate can be increased from 50hr to 20000hr, effectively improving high temperature reliability and the life of the display substrate.
  • the first transistor M1 is located in the second element group 35 And is arranged far away from the display area AA, and the high-level signal line VGH is located in the first line group 36 and is arranged close to the display area AA.
  • the high-level signal line VGH is only connected to the first transistor M1, by arranging the high-level signal line VGH in the first line group 36 and close to the first transistor M1, as shown in FIG. 3, wiring can be saved. space and reduce the border width.
  • the first start signal line STV1 is located in the second line group 37 and is disposed close to the display area AA.
  • the plurality of signal lines 32 also include: a low-level signal line VGL, located in the first line group 36 and disposed at a distance away from the high-level signal line VGH from the display area AA. side. Tests have found that by arranging the low-level signal line VGL in the first line group 36, the length of the connection line between the electronic components and the low-level signal line VGL can be reduced, and the line power consumption can be reduced.
  • the low-level signal line VGL can also be provided in the first line group 36 as needed and located on the side of the high-level signal line VGH close to the display area AA, or in the second line group 37. This disclosure There is no limit to this.
  • the driving unit RS includes: a signal output terminal Output, a second transistor M3 and a capacitor C.
  • the control electrode of the second transistor M3 is connected to the first electrode of the capacitor C.
  • the first pole of the second transistor M3 is connected to the clock signal line CLK, the second pole of the second transistor M3 is connected to the second pole of the capacitor C and the signal output terminal Output, and the signal output terminal Output is connected to the gate line 33 .
  • the second transistor M3 and the capacitor C are both located in the first element group 34 , and the clock signal line CLK is located in the second line group 37 .
  • the second transistor M3 Since the second pole of the second transistor M3 is connected to the signal output terminal Output, and the signal output terminal Output is also connected to the gate line 33, the sub-pixel load in the display area AA is larger. Therefore, compared with other transistors, the second transistor M3 It can have a larger channel width-to-length ratio, so that it has a larger on-state current to improve its load capacity.
  • the second transistor M3 can be disposed in the first element group 34 .
  • a larger plate area can be set, causing the capacitor C to occupy a larger space. Therefore, the capacitor C can be set in the first element group 34 .
  • the driving unit RS includes: a third transistor M17 and the fourth transistor M18, the control electrodes of the third transistor M17 and the fourth transistor M18 are all connected to the second start signal line STV0.
  • the third transistor M17 and the fourth transistor M18 are located in the second element group 35 and are located close to the display area AA, and the second start signal line STV0 is located in the second line group 37 and is located away from the display area AA. .
  • the second start signal line STV0 By arranging the second start signal line STV0 in the second line group 37 and close to the third transistor M17 and the fourth transistor M18 without any other signal lines 32 in between, the second start signal line STV0 can be shortened from the third transistor M17 and the fourth transistor M18 respectively.
  • the length of the connection line connecting the three transistors M17 or the fourth transistor M18 can reduce line losses and avoid via-hole connections (when there are other signal lines between the second starting signal line STV0 and the third transistor M17 and the fourth transistor M18 , in order to prevent short circuit, the connection line between the second start signal line STV0 and the third transistor M17 or the fourth transistor M18 needs to be transferred to other film layers through via holes to cross other signal lines), saving wiring space, Reduce border width.
  • control electrode of the third transistor M17, the control electrode of the fourth transistor M18 and the second start signal line STV0 can all be located on the same film layer and made of the same material.
  • the plurality of signal lines 32 include a power supply voltage signal line VDD and a clock signal line CLK
  • the driving unit RS includes a plurality of transistors (17 transistors M1 to M3, M5 to M18 are shown in FIG. 3).
  • the number of transistors connected to the power supply voltage signal line VDD is greater than the number of transistors connected to the clock signal line CLK.
  • the power supply voltage signal line VDD and the clock signal line CLK are both located in the second line group 37, and the power supply The voltage signal line VDD is located on a side of the clock signal line CLK away from the display area AA.
  • the number of transistors connected to the power supply voltage signal line VDD is larger than the number of transistors connected to the clock signal line CLK, by arranging the power supply voltage signal line VDD at a position close to the clock signal line CLK close to the first element group 34 and the second element group 35, it is possible to Save wiring space, shorten the length of connecting wires, and reduce line losses.
  • the number of transistors (M5 and M6 shown in Figures 6 and 7) connected to the power supply voltage signal line VDD1 is 2, and the number of transistors connected to the power supply voltage signal line VDD2 ( Figures 6 and 7
  • the number of M11 and M12 shown is 2, and the number of transistors (M3 shown in Figure 6 and Figure 7) connected to the clock signal line CLK is 1, that is, the number of transistors connected to the power supply voltage signal line VDD is greater than the number of transistors connected to the clock signal line.
  • the number of transistors in CLK is the number of transistors (M5 and M6 shown in Figures 6 and 7) connected to the power supply voltage signal line VDD1
  • the number of transistors connected to the power supply voltage signal line VDD2 Figures 6 and 7
  • the number of M11 and M12 shown is 2
  • the number of transistors (M3 shown in Figure 6 and Figure 7) connected to the clock signal line CLK is 1, that is, the number of transistors connected to the power supply voltage signal line VDD is greater than
  • two power supply voltage signal lines VDD1 and VDD2 are located on a side of four clock signal lines CLK1, CLK3, CLK5 and CLK7 away from the display area AA.
  • the driving unit RS includes a transistor, and the control electrode of the transistor, the signal line 32 and the gate line 33 are all located on the same film layer and made of the same material.
  • the signal line 32 may also be located on the same film layer and made of the same material as the first electrode and the second electrode of the transistor, which is not limited in this disclosure.
  • the display substrate may include one or more gate line driving circuits 31 described above. Multiple gate line driving circuits 31 are respectively connected to different signal lines 32 , that is, different signal lines 32 are connected to different gate line driving circuits 31 . Referring to FIGS. 8 and 9 , two gate line driving circuits driven alternately on both sides are shown. 31 cascading relationship.
  • the display substrate includes two gate line driving circuits 31.
  • the two gate line driving circuits 31 are respectively a first gate line driving circuit GOA1 (as shown in FIG. 8) and a second gate line driving circuit GOA2 (as shown in FIG. 8).
  • the first gate line driving circuit GOA1 is connected to the gate lines 33 located in the even-numbered rows (gate2, gate4... as shown in Figure 8)
  • the second gate line driving circuit GOA2 is connected to the gate lines 33 located in the odd-numbered rows. (gate1, gate3... as shown in Figure 9) connection.
  • the first gate line driving circuit GOA1 and the plurality of signal lines 32 connected to the first gate line driving circuit GOA1 are located on the first side of the display area AA (as shown in Figure 2, the right side of the display area AA), and the second gate line
  • the driving circuit GOA2 and the plurality of signal lines 32 connected to the second gate line driving circuit GOA2 are located on the second side of the display area AA (the left side of the display area AA as shown in FIG. 2), and the first side and the second side are along the second side of the display area AA. Opposite sides in one direction.
  • both the first gate line driving circuit GOA1 (shown in FIG. 8) and the second gate line driving circuit GOA2 (shown in FIG. 9) include a plurality of driving units RS1 to RSk cascaded with each other.
  • the reset signal terminal Reset of the p-th level driving unit RS p is connected to the p+j-th level driving unit
  • the signal output terminal Output of RS p+j; when p is greater than k-j, the reset signal terminal Reset of the p-th stage driving unit RS is connected to the second start signal line STV0.
  • k, p and j are all positive integers, and p and j are both smaller than k.
  • j is equal to 2.
  • the driving unit shown in Figure 7 includes four phases in a refresh cycle: phase a, phase b, phase c and phase d.
  • the signal input terminal Input inputs a low-level signal
  • the transistor M1 is turned off, and the power supply voltage signals VDD1 and VDD2 perform noise reduction on the driving unit.
  • phase b the signal input terminal Input inputs a high-level signal, the transistor M1 is turned on, the high-level signal line VGH charges the pull-up node PU to a high level through the transistor M1, the transistor M3 is turned on, and the signal output terminal Output outputs the clock signal line CLK (Corresponding to CLK1, CLK3, CLK5 or CLK7 in Figure 9, the same below) low level.
  • CLK Corresponding to CLK1, CLK3, CLK5 or CLK7 in Figure 9, the same below
  • stage c the signal input terminal Input inputs a low-level signal, the transistor M1 is turned off, the clock signal line CLK is high level, the pull-up node PU is bootstrapped to a higher level, the transistor M3 is still open, and the signal output terminal Output outputs the clock The high level of signal line CLK.
  • the reset signal terminal Reset inputs a low level signal, the clock signal line CLK is low level, the pull-up node PU is still high level, the transistor M3 is turned on, and the signal output terminal Output outputs the clock signal line CLK Low level; in the latter part, the reset signal terminal Reset inputs a high-level signal, the transistor M2 is turned on, and the low-level signal line VGL pulls the pull-up node PU to low level.
  • FIG. 5 a schematic structural diagram of the second gate line driving circuit GOA2 located on the left side of FIG. 2 at the dotted boxes D, E, and F is shown.
  • the first component group 34 , the first wire group 36 , the second component group 35 and the second wire group 37 may be located in the second wiring area 22 .
  • the display substrate may further include: a first wiring area 21 located on a side of the second wiring area 22 away from the display area AA; and a third wiring area 23 located between the second wiring area 22 and the display area. Between areas AA. Among them, the first wiring area 21 can be provided with a first common voltage line, a ground line, etc., and the second wiring area 23 can be provided with a second common voltage line, etc.
  • the present disclosure provides a display panel, referring to FIG. 12 , including the display substrate 121 provided in any embodiment.
  • the display panel has the advantages of a front display substrate.
  • the display panel provided by the present disclosure can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, a quantum light emitting diode (Quantum Dot Light-Emitting Diode, QLED) display panel, a sub-millimeter light-emitting diode (Mini Light- Emitting Diode (Mini LED) display panel, Micro Light-Emitting Diode (Micro LED) display panel, Polymer Light-Emitting Diode (Polymer Light-Emitting Diode (PLED) display panel, plasma display panel (Plasma Display Panel, PDP), etc. There are no specific restrictions on the specific type of display panel here.
  • the display panel also includes: a box alignment substrate 122 , which is arranged opposite to the display substrate 121 ; and a frame sealing glue 123 , which is arranged between the box alignment substrate 122 and the display substrate 121 .
  • the orthographic projection of the glue 123 on the substrate is located in the peripheral area BB.
  • the driving unit RS includes a first element group 34 and a second element group 35.
  • Multiple signal lines 32 connected to the same gate line driving circuit 31 are divided into a first line group 36 and a second line group 37.
  • the two element group 35 is located on the side of the first element group 34 close to the display area AA
  • the first line group 36 is located between the first element group 34 and the second element group 35
  • the second line group 37 is located on the second element group 35 close to the display One side of area AA.
  • the orthographic projection of the frame sealant 123 on the substrate covers the orthographic projection of the first element group 34 , the first line group 36 and at least part of the second element group 35 on the substrate.
  • the present disclosure provides a display device, including the display panel provided in any embodiment.
  • the display device has the advantage of a front display substrate.
  • the display device provided by the present disclosure may further include a driver chip connected to a plurality of signal lines for providing driving signals to the plurality of signal lines.
  • the orthographic projection of the driver chip on the display substrate may be located in the peripheral area.
  • the display device may further include a backlight module disposed on the backlight side of the liquid crystal display panel to provide backlight.
  • the display device may include, for example, any product or component with a display function such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display product, or the like.
  • pluricity means two or more, and “at least one” means one or more, unless otherwise explicitly and specifically limited.
  • orientation or positional relationship indicated by terms such as “upper” and “lower” is based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply what is meant. Devices or elements must be oriented, constructed, and operate in a particular orientation and therefore are not to be construed as limitations on the disclosure.
  • the grating adjustment device and display device provided by the present disclosure have been introduced in detail above. Specific examples are used to illustrate the principles and implementations of the present disclosure. The description of the above embodiments is only used to help understand the present disclosure. methods and their core ideas.

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Abstract

一种显示基板、显示面板及显示装置，涉及显示技术领域。显示基板包括显示区域（AA）以及位于显示区域(AA)至少一侧的周边区域(BB)，显示基板包括：衬底(30)，以及设置在衬底(30)一侧的栅线驱动电路(31)、多条信号线(32)和栅线(33)，栅线驱动电路(31)和多条信号线(32)均位于周边区域(BB)，栅线(33)位于显示区域(AA)；其中，栅线驱动电路(31)分别与多条信号线(32)以及栅线(33)连接，包括相互级联的多级驱动单元(RS)，驱动单元(RS)包括第一元件组(34)，第一元件组(34)包括至少一个第一电子元件；多条信号线(32)沿第一方向排布，第一方向为栅线(33)的延伸方向，多条信号线(32)中的至少一条位于第一元件组(34)靠近显示区域(AA)的一侧。

Description

显示基板、显示面板及显示装置
相关申请的交叉引用
本公开要求在2022年9月1日提交中国专利局、申请号为202211065795.5、名称为“显示基板、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别是涉及一种显示基板、显示面板及显示装置。
背景技术
随着显示技术的发展，人们对显示产品的显示效果以及信赖性等方面的要求越来越高。液晶显示面板作为一种广泛使用的显示面板，在显示领域占有重要地位。
概述
本公开提供了一种显示基板，包括显示区域以及位于所述显示区域至少一侧的周边区域，所述显示基板包括：
衬底，以及设置在所述衬底一侧的栅线驱动电路、多条信号线和栅线，所述栅线驱动电路和所述多条信号线均位于所述周边区域，所述栅线位于所述显示区域；
其中，所述栅线驱动电路分别与所述多条信号线以及所述栅线连接，包括相互级联的多级驱动单元，所述驱动单元包括第一元件组，所述第一元件组包括至少一个第一电子元件；
所述多条信号线沿第一方向排布，所述第一方向为所述栅线的延伸方向，所述多条信号线中的至少一条位于所述第一元件组靠近所述显示区域的一侧。
在一些可选的实施方式中，所述多条信号线中的至少一条位于所述驱动单元靠近所述显示区域的一侧。
在一些可选的实施方式中，所述驱动单元还包括：
第二元件组，位于所述第一元件组靠近所述显示区域的一侧，包括至少一个第二电子元件；
其中，所述多条信号线分为第一线组和第二线组，所述第一线组位于所述第一元件组和所述第二元件组之间，所述第二线组位于所述第二元件组靠近所述显示区域的一侧。
在一些可选的实施方式中，所述多条信号线包括：位于所述第一线组内的第一信号线，以及位于所述第二线组内的第二信号线；
其中，所述第一信号线上的电流小于或等于所述第二信号线上的电流。
在一些可选的实施方式中，所述第一信号线与直流信号输入端连接，所述直流信号输入端用于输入直流信号至所述第一信号线；
所述第二信号线与交流信号输入端连接，所述交流信号输入端用于输入交流信号至所述第二信号线。
在一些可选的实施方式中，所述第一电子元件在所述衬底上的正投影面积大于或等于所述第二电子元件在所述衬底上的正投影面积。
在一些可选的实施方式中，所述驱动单元包括：
信号输入端、信号输出端和第一晶体管，所述第一晶体管的控制极与所述信号输入端连接，所述第一晶体管的第一极与所述第一晶体管的控制极或者高电平信号线连接，所述信号输出端与所述栅线连接；
其中，第i级驱动单元的信号输入端连接第一起始信号线或者第i-j级驱动单元的信号输出端，所述i和所述j均为正整数，且所述j小于所述i。
在一些可选的实施方式中，所述第一晶体管位于所述第二元件组中且远离所述显示区域设置，所述高电平信号线位于所述第一线组中且靠近所述显示区域设置。
在一些可选的实施方式中，所述第一起始信号线位于所述第二线组中且靠近所述显示区域设置。
在一些可选的实施方式中，所述多条信号线还包括：
低电平信号线，位于所述第一线组中，且设置在所述高电平信号线远离所述显示区域的一侧。
在一些可选的实施方式中，所述驱动单元包括：
信号输出端、第二晶体管和电容，所述第二晶体管的控制极与所述电容的第一极连接，所述第二晶体管的第一极与时钟信号线连接，所述第二晶体管的第二极与所述电容的第二极以及所述信号输出端连接，所述信号输出端与所述栅线连接；
其中，所述第二晶体管和所述电容均位于所述第一元件组中，所述时钟信号线位于所述第二线组中。
在一些可选的实施方式中，所述驱动单元包括：
第三晶体管和第四晶体管，所述第三晶体管的控制极和所述第四晶体管的控制极均与第二起始信号线连接；
其中，所述第三晶体管和所述第四晶体管位于所述第二元件组中且靠近所述显示区域设置，所述第二起始信号线位于所述第二线组中且远离所述显示区域设置。
在一些可选的实施方式中，所述多条信号线包括电源电压信号线和时钟信号线，所述驱动单元包括多个晶体管；
其中，连接所述电源电压信号线的晶体管数量大于连接所述时钟信号线的晶体管数量，所述电源电压信号线和所述时钟信号线均位于所述第二线组中，且所述电源电压信号线位于所述时钟信号线远离所述显示区域的一侧。
在一些可选的实施方式中，所述第一线组包括以下信号线至少之一：高电平信号线和低电平信号线；
所述第二线组包括以下信号线至少之一：低电平信号线、电源电压信号线、时钟信号线和起始信号线。
在一些可选的实施方式中，所述第一元件组和所述第二元件组均包括以下电子元件至少之一：晶体管和电容。
在一些可选的实施方式中，所述驱动单元包括晶体管，所述晶体管的控制极、所述信号线以及所述栅线均位于同一膜层且材料相同。
在一些可选的实施方式中，所述显示基板包括两个所述栅线驱动电路，两个所述栅线驱动电路分别为第一栅线驱动电路和第二栅线驱动电路，所述第一栅线驱动电路与位于偶数行的栅线连接，所述第二栅线驱动电路与位于奇数行的栅线连接；
其中，所述第一栅线驱动电路以及连接所述第一栅线驱动电路的多条信 号线位于所述显示区域的第一侧，所述第二栅线驱动电路以及连接所述第二栅线驱动电路的多条信号线位于所述显示区域的第二侧，所述第一侧和所述第二侧为沿所述第一方向上相对的两侧。
本公开提供了一种显示面板，包括任一实施方式所述的显示基板。
在一些可选的实施方式中，所述显示面板还包括：
对盒基板，与所述显示基板相对设置；以及
封框胶，设置在所述对盒基板与所述显示基板之间，所述封框胶在所述衬底上的正投影位于所述周边区域内；
其中，所述驱动单元还包括：第二元件组，位于所述第一元件组靠近所述显示区域的一侧，包括至少一个第二电子元件；所述多条信号线分为第一线组和第二线组，所述第一线组位于所述第一元件组和所述第二元件组之间，所述第二线组位于所述第二元件组靠近所述显示区域的一侧；
所述封框胶在所述衬底上的正投影，覆盖所述第一元件组、所述第一线组以及至少部分所述第二元件组在所述衬底上的正投影。
本公开提供了一种显示装置，包括：
如任一实施方式所述的显示面板；以及
驱动芯片，与所述多条信号线连接，用于向所述多条信号线提供驱动信号。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。需要说明的是，附图中的比例仅作为示意并不代表实际比例。
图1示意性地示出了相关技术中的一种显示基板的平面结构示意图；
图2示意性地示出了本公开提供的一种显示基板的平面结构示意图；
图3示意性地示出了本公开提供的显示基板中虚线框E处的结构示意图；
图4示意性地示出了本公开提供的显示基板中虚线框E处的显微镜图；
图5示意性地示出了本公开提供的显示基板中虚线框D、E和F处的结构示意图；
图6示意性地示出了第一种驱动单元的电路结构示意图；
图7示意性地示出了第二种驱动单元的电路结构示意图；
图8示意性地示出了第一栅线驱动电路的电路结构示意图；
图9示意性地示出了第二栅线驱动电路的电路结构示意图；
图10示意性地示出了两种驱动单元的信号输出端在高温测试完成后输出的模拟波形；
图11示意性地示出了一个驱动单元的输入输出信号的时序图；
图12示意性地示出了一种显示面板的剖面结构示意图；
图13示意性地示出了一种显示面板的局部平面结构示意图。
详细描述
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
参照图1示意性地示出了相关技术中的一种显示基板的平面结构示意图，如图1所示，显示基板包括显示区域11以及位于显示区域11两侧的边框区域12。边框区域12包括栅线驱动电路区域13和信号线区域14，栅线驱动电路区域13中设置有栅线驱动电路，信号线区域14中设置有信号线，栅线驱动电路与信号线通过过孔连接。
相关技术中，如图1所示，信号线区域14位于栅线驱动电路区域13远离显示区域11的一侧，使得信号线与封框胶外边缘(图中未示出)之间的距离(该距离需要大于或等于指定值如25mm)较近，导致信号线与栅线驱动电路之间的连接过孔容易发生腐蚀。
为了解决上述问题，本公开提供了一种显示基板，参照图2示意性地示 出了本公开提供的一种显示基板的平面结构示意图，如图2所示，该显示基板包括显示区域AA以及位于显示区域AA至少一侧的周边区域BB。在图2中，周边区域BB位于显示区域AA的四周。
参照图3示意性地示出了图2所示显示基板在虚线框E处的平面结构示意图，图4是与图3对应的显微镜图。如图3或图4所示，显示基板包括：衬底30，以及设置在衬底30一侧的栅线驱动电路31、多条信号线32和栅线33，栅线驱动电路31和多条信号线32均位于周边区域BB，栅线33位于显示区域AA。
其中，栅线驱动电路31，分别与多条信号线32以及栅线33连接，用于根据多条信号线32输入的驱动信号，输出扫描信号至栅线33。
如图3所示，栅线驱动电路31包括相互级联的多级驱动单元RS，驱动单元RS包括第一元件组34，第一元件组34包括至少一个第一电子元件。第一电子元件为位于第一元件组34中的电子元件。第一元件组34可以包括以下电子元件至少之一：晶体管和电容等。
在具体实现中，第一元件组34可以包括一个第一电子元件或者多个第一电子元件。第一元件组34中所包含的第一电子元件的数量大于或等于1，且小于或等于驱动单元RS所包含的所有电子元件的数量。
其中，多条信号线32沿第一方向排布，第一方向为栅线33的延伸方向，多条信号线32中的至少一条位于第一元件组34靠近显示区域AA的一侧。也就是，与栅线驱动电路31连接的一条或多条信号线32，可以位于该栅线驱动电路31中的第一元件组34靠近显示区域AA的一侧。
示例性地，如图3所示，第一元件组34包括两个第一电子元件，即晶体管M3和电容C。驱动单元RS包括多个晶体管(如图3所示的M1至M3，以及M5至M18)以及一个电容(如图3所示的C)等18个电子元件。
如图3所示的栅线驱动电路31，与该栅线驱动电路31连接的信号线32有10条，这10条信号线包括高电平信号线VGH、低电平信号线VGL、两条电源电压信号线VDD1和VDD2、四条时钟信号线CLK1、CLK3、CLK5和CLK7，以及两条起始信号线STV0和STV1。
其中，与图3所示栅线驱动电路31连接的全部信号线(即10条信号线32)，均位于该栅线驱动电路31中的第一元件组34靠近显示区域AA的一 侧。
在具体实现中，位于第一元件组34靠近显示区域AA一侧的信号线数量大于或等于1，且小于或等于连接同一个栅线驱动电路31的信号线的总数量。
在具体实现中，如图3或图4所示，栅线驱动电路31与信号线32之间通过过孔H连接。
本公开提供的显示基板，通过将连接栅线驱动电路31的一条或多条信号线32设置于第一元件组34靠近显示区域AA的一侧，可以增大上述一条或多条信号线32与封框胶外边缘之间的距离，进而可以降低这些信号线32与栅线驱动电路31之间的连接过孔发生腐蚀的概率，提高显示基板的高温寿命，提升显示产品品质和信赖性。另外，本公开无需通过加大边框宽度就能够实现信号线与封框胶外边缘之间距离的增大，因此有助于实现窄边框。
在一些实施方式中，如图3所示，位于显示区域AA内的栅线33沿第一方向延伸，多条栅线33沿第二方向排布。可选地，信号线32可以沿第二方向延伸，第一方向与第二方向相互交叉或相互垂直(如图3所示出的)。
在一些实施方式中，如图3所示的栅线驱动电路31，多级驱动单元RS沿第二方向排布。
在一些实施方式中，多条信号线32中的至少一条位于驱动单元RS靠近显示区域AA的一侧。也就是，与栅线驱动电路31连接的一条或多条信号线32，可以位于该栅线驱动电路31中的驱动单元RS靠近显示区域AA的一侧。
示例性地，如图3所示的栅线驱动电路31，与该栅线驱动电路31连接的信号线有10条，其中8条信号线：两条电源电压信号线VDD1和VDD2、四条时钟信号线CLK1、CLK3、CLK5和CLK7，以及两条起始信号线STV0和STV1，均位于驱动单元RS靠近显示区域AA的一侧。
通过将连接栅线驱动电路31的一条或多条信号线32设置于该栅线驱动电路31中的驱动单元RS靠近显示区域AA的一侧，可以进一步增大上述一条或多条信号线32与封框胶外边缘之间的距离，进一步降低这些信号线32与栅线驱动电路31的连接过孔发生腐蚀的概率，提高显示基板的高温寿命，提升显示产品品质和信赖性。
在具体实现中，与栅线驱动电路31连接的所有信号线32可以都位于该栅线驱动电路31中的驱动单元RS靠近显示区域AA的一侧，从而可以最大 程度地降低信号线32与栅线驱动电路31的连接过孔发生腐蚀的概率；或者，与栅线驱动电路31连接的部分信号线(即一条或多条，如图3所示的10条信号线中的8条)位于该栅线驱动电路31中的驱动单元RS靠近显示区域AA的一侧，这种情况下，其它信号线32可以根据布线空间等需求进行设置，本公开对此不作限定。
在一些实施方式中，如图3所示，驱动单元RS还包括：第二元件组35，位于第一元件组34靠近显示区域AA的一侧，包括至少一个第二电子元件。
本实施方式中，连接同一个栅线驱动电路31的多条信号线32分为第一线组36和第二线组37，第二元件组35第一线组36位于第一元件组34和第二元件组35之间，第二线组37位于第二元件组35靠近显示区域AA的一侧。
其中，第二电子元件为位于第二线组37中的电子元件。第二元件组35可以包括以下电子元件至少之一：晶体管和电容。
在具体实现中，第二线组37可以包括一个第二电子元件或者多个第二电子元件。第二线组37中所包含的第二电子元件的数量大于或等于1，且小于驱动单元RS所包含的所有电子元件的数量。
示例性地，如图3所示，第二元件组35包括16个第二电子元件，即晶体管M1至M2，M5至M18。驱动单元RS包括多个晶体管(如图3所示的M1至M3，以及M5至M18)以及一个电容(如图3所示的C)等18个电子元件。
示例性地，如图3所示，第一线组36包括两条信号线32，即高电平信号线VGH和低电平信号线VGL。第二线组37包括8条信号线32，即两条电源电压信号线VDD1和VDD2、四条时钟信号线CLK1、CLK3、CLK5和CLK7，以及两条起始信号线STV0和STV1。
其中，如图3所示，第一元件组34设置在第二元件组35的外侧(即靠近显示基板边缘的一侧)设置，第一线组36设置在第一元件组34与第二元件组35之间，第二线组37设置在第二元件组35的里侧(即靠近显示区域AA的一侧)设置。如图3所示，沿着靠近显示区域AA的方向(如图3所示的第三方向)上，第一元件组34、第一线组36、第二元件组35和第二线组37依次排布。
本实施方式中，与栅线驱动电路31连接的部分信号线32(即第二线组 37中的信号线32)位于该栅线驱动电路31中的驱动单元RS靠近显示区域AA的一侧。其它信号线32(即第一线组36中的信号线32)设置在第一元件组34和第二元件组35之间。
在一些实施方式中，多条信号线32包括：位于第一线组36内的第一信号线321，以及位于第二线组37内的第二信号线322。其中，第一信号线321上的电流小于或等于第二信号线322上的电流。
由于连接较大电流信号线32的过孔更容易腐蚀，因此，通过将电流较大的第二信号线322设置在更靠近显示区域AA的第二线组37中，可以增大其与封框胶外边缘的距离，从而有效地降低第二信号线322上的过孔发生腐蚀的概率。
在一些实施方式中，第一信号线321与直流信号输入端(图中未示出)连接，直流信号输入端用于输入直流信号至第一信号线321。其中，直流信号例如可以是高电平直流信号或低电平直流信号等。
由于直流信号没有高低电平切换，因此传输直流信号的第一信号线321上基本没有电流，即使将第一信号线321放置在靠外侧的第一线组36中，也不会加大腐蚀风险，同时还可以进一步增大第二线组37与封框胶外边缘之间的距离，降低连接第二信号线322的过孔发生腐蚀的风险。
在一些实施方式中，如图3所示，第一线组36包括以下信号线至少之一：高电平信号线VGH和低电平信号线VGL等用于传输直流信号的信号线32。其中，高电平信号线VGH用于传输高电平直流信号。低电平信号线VGL用于传输低电平直流信号。
示例性地，如图3所示，第一线组36包括两条第一信号线321，即高电平信号线VGH和低电平信号线VGL。
在一些实施方式中，第二信号线322与交流信号输入端(图中未示出)连接，交流信号输入端用于输入交流信号至第二信号线322。其中，交流信号例如可以是脉冲方波信号等。
由于交流信号具有频繁的高低电平切换，因此传输交流信号的第二信号线322上有较大的电流，通过将第二信号线322设置在靠里侧的第二线组37中，可以增大其与封框胶外边缘之间的距离，降低发生腐蚀的概率。
在一些实施方式中，第二线组37包括以下信号线至少之一：电源电压信 号线VDD、时钟信号线CLK和起始信号线STV等用于传输交流信号的信号线32。
本文中如无特别说明，电源电压信号线VDD可以是图3所示两条电源电压信号线VDD1和VDD2中的任意一条，时钟信号线CLK可以是图3所示四条时钟信号线CLK1、CLK3、CLK5和CLK7中的任意一条，起始信号线STV可以是图3所示两条起始信号线STV0和STV1中的任意一条。
示例性地，如图3所示，第二线组37包括8条第二信号线322，即两条电源电压信号线VDD1和VDD2、四条时钟信号线CLK1、CLK3、CLK5和CLK7，以及两条起始信号线STV0和STV1。
在一些实施方式中，如图3所示，第一电子元件在衬底30上的正投影面积大于或等于第二电子元件在衬底30上的正投影面积。
通过将占用空间较大的第一电子元件放置在距离显示区域AA较远的第一元件组34中，可以进一步增大各信号线32与封框胶外边缘之间的距离，降低连接过孔腐蚀风险，有助于减小边框宽度。
在一些实施方式中，参照图6和图7示出了两种驱动单元的电路结构示意图，如图6和图7所示，驱动单元RS包括：信号输入端Input、信号输出端Output和第一晶体管M1，第一晶体管M1的控制极与信号输入端Input连接，第一晶体管M1的第一极与第一晶体管M1的控制极(如图6所示)或者高电平信号线VGH(如图7所示)连接，信号输出端Output与栅线33连接。
参照图9，第i级驱动单元RS i的信号输入端Input连接第一起始信号线STV1或者第i-j级驱动单元RS i-j的信号输出端Output，i和j均为正整数，且j小于i。
具体地，当i小于或等于j时，第i级驱动单元RS i的信号输入端Input可以连接第一起始信号线STV1；当i大于j时，第i级驱动单元RS i的信号输入端Input连接第i-j级驱动单元RS i-j的信号输出端Output。
在图9中，j等于2，即第1级驱动单元RS 1和第2级驱动单元RS 2的信号输入端Input连接第一起始信号线STV1。第3级驱动单元RS 3的信号输入端Input连接第1级驱动单元RS 1的信号输出端Output，第4级驱动单元RS 4的信号输入端Input连接第2级驱动单元RS 2的信号输出端Output，依此类推。
如图9所示，多级驱动单元RS可以分别连接不同的栅线33，在图9中，驱动单元RS与栅线33一一对应连接。
如图6和图7所示，第一晶体管M1的第二极与上拉节点PU连接，第一晶体管M1用于根据控制极的信号，导通或关断第一极和第二极之间的连接，并在第一极和第二极导通时，将第一极的信号写入上拉节点PU。
可选地，如图6所示，第一晶体管M1的第一极与第一晶体管M1的控制极连接。当第i级驱动单元RS i的信号输入端Input与第i-j级驱动单元RS i-j的信号输出端Output连接时，在第i级驱动单元RS i中，第一晶体管M1的第一极与第i-j级驱动单元RS i-j的信号输出端Output连接，由于信号输出端Output还与栅线33连接，显示区域AA中的子像素负载较大，导致信号输出端Output输出的信号有延迟，进而使得第i级驱动单元RS i中的上拉节点PU信号产生延迟，影响上拉节点PU的充电，图6所示显示基板在信赖性测试之后很容易出现显示不良。
为了解决上述问题，可选地，如图7所示，第一晶体管M1的第一极与高电平信号线VGH连接。当第一晶体管M1打开时，第一极和第二极导通，从而可以将高电平信号线VGH输入的高电平信号写入上拉节点PU，为上拉节点PU充电。由于高电平信号线VGH为高电平信号源，不连接负载，没有延迟，即使信赖性测试后，第一晶体管M1的阈值电压产生漂移，也可以在有限的时间内将上拉节点PU充电至高电平，从而提高产品的信赖性。
参照图10，发明人对图7所示驱动单元进行85℃，40hr的高温测试(图10中虚线)，对图6所示驱动单元进行85℃，20hr的高温测试(图10中实线)，图10示出了两种驱动单元的信号输出端在高温测试完成后输出的模拟波形。对比发现，图7所示驱动单元的信号输出端Output输出的模拟波形延迟较小，图6所示驱动单元的信号输出端Output输出的模拟波形的下降沿有明显翘起，表现出明显的延迟，并且随着高温测试时间的延长，其翘起会越来越高，最终导致显示基板显示异常。
发明人还用模拟软件模拟了分别采用图6和图7两种驱动单元结构的显示基板在高温测试下的寿命，对比发现，采用图7所示结构，可以使显示基板的寿命从50hr提升至20000hr，有效提高高温信赖性和显示基板的寿命。
在一些实施方式中，如图3所示，第一晶体管M1位于第二元件组35中 且远离显示区域AA设置，高电平信号线VGH位于第一线组36中且靠近显示区域AA设置。
由于高电平信号线VGH只连接第一晶体管M1，通过将高电平信号线VGH设置在第一线组36中且靠近第一晶体管M1的位置，如图3所示出的，可以节省布线空间，减小边框宽度。
在一些实施方式中，如图3所示，第一起始信号线STV1位于第二线组37中且靠近显示区域AA设置。
在一些实施方式中，如图3所示，多条信号线32还包括：低电平信号线VGL，位于第一线组36中，且设置在高电平信号线VGH远离显示区域AA的一侧。测试发现，通过将低电平信号线VGL设置在第一线组36中，可以减少电子元件与低电平信号线VGL之间的连接线长度，降低线路功耗。
需要说明的是，低电平信号线VGL也可以根据需要设置在第一线组36中且位于高电平信号线VGH靠近显示区域AA的一侧，或者设置在第二线组37中，本公开对此不作限定。
在一些实施方式中，如图6和图7所示，驱动单元RS包括：信号输出端Output、第二晶体管M3和电容C，第二晶体管M3的控制极与电容C的第一极连接，第二晶体管M3的第一极与时钟信号线CLK连接，第二晶体管M3的第二极与电容C的第二极以及信号输出端Output连接，信号输出端Output与栅线33连接。
其中，如图3所示，第二晶体管M3和电容C均位于第一元件组34中，时钟信号线CLK位于第二线组37中。
由于第二晶体管M3的第二极与信号输出端Output连接，信号输出端Output还与栅线33连接，显示区域AA中的子像素负载较大，因此，与其它晶体管相比，第二晶体管M3可以具有较大的沟道宽长比，从而使其具有较大的开态电流，以提高其带载能力。
如图3所示，由于第二晶体管M3的沟道宽长比较大，导致其占用空间比其它晶体管大，因此可以将第二晶体管M3设置在第一元件组34中。为了提高电容C的电荷存储能力，可以设置较大的极板面积，导致电容C占用空间较大，因此可以将电容C设置在第一元件组34中。
在一些实施方式中，如图6和图7所示，驱动单元RS包括：第三晶体管 M17和第四晶体管M18，第三晶体管M17的控制极和第四晶体管M18的控制极均与第二起始信号线STV0连接。
其中，如图3所示，第三晶体管M17和第四晶体管M18位于第二元件组35中且靠近显示区域AA设置，第二起始信号线STV0位于第二线组37中且远离显示区域AA设置。
通过将第二起始信号线STV0设置在第二线组37中且靠近第三晶体管M17和第四晶体管M18的位置，中间无其它信号线32间隔，可以缩短第二起始信号线STV0分别与第三晶体管M17或第四晶体管M18连接的连接线长度，降低线路损耗，同时避免过孔连接(当第二起始信号线STV0与第三晶体管M17和第四晶体管M18之间间隔有其它信号线时，为了防止短路，第二起始信号线STV0与第三晶体管M17或第四晶体管M18之间的连接线需要通过过孔转接到其它膜层，以跨过其它信号线)，节省布线空间，减小边框宽度。
为了进一步减少过孔数量，第三晶体管M17的控制极、第四晶体管M18的控制极以及第二起始信号线STV0可以均位于同一膜层且材料相同，
在一些实施方式中，多条信号线32包括电源电压信号线VDD和时钟信号线CLK，驱动单元RS包括多个晶体管(如图3示出了17个晶体管M1至M3，M5至M18)。
其中，如图6和图7所示，连接电源电压信号线VDD的晶体管数量大于连接时钟信号线CLK的晶体管数量，电源电压信号线VDD和时钟信号线CLK均位于第二线组37中，且电源电压信号线VDD位于时钟信号线CLK远离显示区域AA的一侧。
由于电源电压信号线VDD连接的晶体管数量比时钟信号线CLK连接的晶体管数量多，通过将电源电压信号线VDD设置在时钟信号线CLK靠近第一元件组34和第二元件组35的位置，可以节省布线空间，缩短连接线长度，降低线路损耗。
如图6和图7所示，连接电源电压信号线VDD1的晶体管(如图6和图7所示的M5和M6)数量为2，连接电源电压信号线VDD2的晶体管(如图6和图7所示的M11和M12)数量为2，连接时钟信号线CLK的晶体管(如图6和图7所示的M3)数量为1，也就是连接电源电压信号线VDD的晶体管数量大于连接时钟信号线CLK的晶体管数量。
示例性地，如图3所示，两条电源电压信号线VDD1和VDD2位于四条时钟信号线CLK1、CLK3、CLK5和CLK7远离显示区域AA的一侧。
在一些实施方式中，驱动单元RS包括晶体管，晶体管的控制极、信号线32以及栅线33均位于同一膜层且材料相同。
在具体实现中，信号线32还可以与晶体管的第一极和第二极位于同一膜层且材料相同，本公开对此不作限定。
在具体实现中，显示基板可以包括一个或多个上述的栅线驱动电路31。多个栅线驱动电路31分别连接不同的信号线32，即不同的栅线驱动电路31连接的信号线32不同，参照图8和图9示出的是双边交替驱动的两个栅线驱动电路31的级联关系。
在一些实施方式中，显示基板包括两个栅线驱动电路31，两个栅线驱动电路31分别为第一栅线驱动电路GOA1(如图8所示)和第二栅线驱动电路GOA2(如图9所示)，第一栅线驱动电路GOA1与位于偶数行的栅线33(如图8所示的gate2,gate4…)连接，第二栅线驱动电路GOA2与位于奇数行的栅线33(如图9所示的gate1,gate3…)连接。
其中，第一栅线驱动电路GOA1以及连接第一栅线驱动电路GOA1的多条信号线32位于显示区域AA的第一侧(如图2所示显示区域AA的右侧)，第二栅线驱动电路GOA2以及连接第二栅线驱动电路GOA2的多条信号线32位于显示区域AA的第二侧(如图2所示显示区域AA的左侧)，第一侧和第二侧为沿第一方向上相对的两侧。
可选地，第一栅线驱动电路GOA1(如图8所示)和第二栅线驱动电路GOA2(如图9所示)均包括相互级联的多个驱动单元RS 1至RS k。
如图8和图9所示，当栅线驱动电路31包括k级驱动单元RS，且p小于或等于k-j时，第p级驱动单元RS p的复位信号端Reset连接第p+j级驱动单元RS p+j的信号输出端Output；当p大于k-j时，第p级驱动单元RS的复位信号端Reset连接第二起始信号线STV0。其中，k、p和j均为正整数，p和j均小于k。在图8和图9中，j等于2。
下面对图7所示驱动单元的工作过程进行说明。参照图11示出了各信号在不同阶段的时序图。图7所示驱动单元在一个刷新周期中包括四个阶段：a阶段、b阶段、c阶段和d阶段。
其中，在a阶段，信号输入端Input输入低电平信号，晶体管M1关闭，电源电压信号VDD1和VDD2对驱动单元进行降噪。
在b阶段，信号输入端Input输入高电平信号，晶体管M1打开，高电平信号线VGH通过晶体管M1给上拉节点PU充电至高电平，晶体管M3打开，信号输出端Output输出时钟信号线CLK(对应图9中的CLK1、CLK3、CLK5或CLK7，下同)的低电平。
在c阶段，信号输入端Input输入低电平信号，晶体管M1关闭，时钟信号线CLK为高电平，上拉节点PU自举至更高电平，晶体管M3仍打开，信号输出端Output输出时钟信号线CLK的高电平。
在d阶段，前一部分，复位信号端Reset输入低电平信号，时钟信号线CLK为低电平，上拉节点PU仍为高电平，晶体管M3打开，信号输出端Output输出时钟信号线CLK的低电平；后一部分，复位信号端Reset输入高电平信号，晶体管M2打开，低电平信号线VGL将上拉节点PU拉至低电平。
参照图5示出了位于图2左侧的第二栅线驱动电路GOA2在虚线框D、E和F处的结构示意图。
如图2和图3所示，第一元件组34、第一线组36、第二元件组35和第二线组37可以位于第二布线区22中。
如图2和图3所示，显示基板还可以包括：第一布线区21，位于第二布线区22远离显示区域AA的一侧；以及第三布线区23，位于第二布线区22与显示区域AA之间。其中，第一布线区21可以设置第一公共电压走线以及地线等，第二布线区23可以设置第二公共电压走线等。
本公开提供了一种显示面板，参照图12，包括如任一实施方式提供的显示基板121。
本领域技术人员可以理解，该显示面板具有前面显示基板的优点。
本公开提供的显示面板可以为液晶显示面板、有机发光二极管(Organic Light Emitting Diode，OLED)显示面板、量子发光二极管(Quantum Dot Light-Emitting Diode，QLED)显示面板、次毫米发光二极管(Mini Light-Emitting Diode，Mini LED)显示面板、微型发光二极管(Micro Light-Emitting Diode，Micro LED)显示面板、高分子发光二极管(Polymer  Light-Emitting Diode，PLED)显示面板、等离子显示面板(Plasma Display Panel，PDP)等，这里对于显示面板的具体类型不做具体的限制。
在一些实施方式中，如图12所示，显示面板还包括：对盒基板122，与显示基板121相对设置；以及封框胶123，设置在对盒基板122与显示基板121之间，封框胶123在衬底上的正投影位于周边区域BB内。
如图3所示，驱动单元RS包括第一元件组34和第二元件组35，连接同一个栅线驱动电路31的多条信号线32分为第一线组36和第二线组37，第二元件组35位于第一元件组34靠近显示区域AA的一侧，第一线组36位于第一元件组34和第二元件组35之间，第二线组37位于第二元件组35靠近显示区域AA的一侧。
如图13所示，封框胶123在衬底上的正投影，覆盖第一元件组34、第一线组36以及至少部分第二元件组35在衬底上的正投影。
本公开提供了一种显示装置，包括如任一实施方式提供的显示面板。
本领域技术人员可以理解，该显示装置具有前面显示基板的优点。
本公开提供的显示装置，还可以包括驱动芯片，与多条信号线连接，用于向多条信号线提供驱动信号。驱动芯片在显示基板上的正投影可以位于周边区域。
若该显示面板为液晶显示面板，则该显示装置还可以包括背光模组，设置在液晶显示面板的背光侧，以提供背光。
本公开提供的显示装置，例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪、车载显示产品等任何具有显示功能的产品或部件。
本公开中，“多个”的含义是两个或两个以上，“至少一个”的含义是一个或一个以上，除非另有明确具体的限定。
本公开中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求 的限制。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、产品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的一种光栅调节装置及显示装置进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种显示基板，包括显示区域以及位于所述显示区域至少一侧的周边区域，所述显示基板包括：
    衬底，以及设置在所述衬底一侧的栅线驱动电路、多条信号线和栅线，所述栅线驱动电路和所述多条信号线均位于所述周边区域，所述栅线位于所述显示区域；
    其中，所述栅线驱动电路分别与所述多条信号线以及所述栅线连接，包括相互级联的多级驱动单元，所述驱动单元包括第一元件组，所述第一元件组包括至少一个第一电子元件；
    所述多条信号线沿第一方向排布，所述第一方向为所述栅线的延伸方向，所述多条信号线中的至少一条位于所述第一元件组靠近所述显示区域的一侧。
  2. 根据权利要求1所述的显示基板，其中，所述多条信号线中的至少一条位于所述驱动单元靠近所述显示区域的一侧。
  3. 根据权利要求1所述的显示基板，其中，所述驱动单元还包括：
    第二元件组，位于所述第一元件组靠近所述显示区域的一侧，包括至少一个第二电子元件；
    其中，所述多条信号线分为第一线组和第二线组，所述第一线组位于所述第一元件组和所述第二元件组之间，所述第二线组位于所述第二元件组靠近所述显示区域的一侧。
  4. 根据权利要求3所述的显示基板，其中，所述多条信号线包括：位于所述第一线组内的第一信号线，以及位于所述第二线组内的第二信号线；
    其中，所述第一信号线上的电流小于或等于所述第二信号线上的电流。
  5. 根据权利要求4所述的显示基板，其中，所述第一信号线与直流信号输入端连接，所述直流信号输入端用于输入直流信号至所述第一信号线；
    所述第二信号线与交流信号输入端连接，所述交流信号输入端用于输入交流信号至所述第二信号线。
  6. 根据权利要求3所述的显示基板，其中，所述第一电子元件在所述衬底上的正投影面积大于或等于所述第二电子元件在所述衬底上的正投影面积。
  7. 根据权利要求3所述的显示基板，其中，所述驱动单元包括：
    信号输入端、信号输出端和第一晶体管，所述第一晶体管的控制极与所述信号输入端连接，所述第一晶体管的第一极与所述第一晶体管的控制极或者高电平信号线连接，所述信号输出端与所述栅线连接；
    其中，第i级驱动单元的信号输入端连接第一起始信号线或者第i-j级驱动单元的信号输出端，所述i和所述j均为正整数，且所述j小于所述i。
  8. 根据权利要求7所述的显示基板，其中，所述第一晶体管位于所述第二元件组中且远离所述显示区域设置，所述高电平信号线位于所述第一线组中且靠近所述显示区域设置。
  9. 根据权利要求7所述的显示基板，其中，所述第一起始信号线位于所述第二线组中且靠近所述显示区域设置。
  10. 根据权利要求8所述的显示基板，其中，所述多条信号线还包括：
    低电平信号线，位于所述第一线组中，且设置在所述高电平信号线远离所述显示区域的一侧。
  11. 根据权利要求3所述的显示基板，其中，所述驱动单元包括：
    信号输出端、第二晶体管和电容，所述第二晶体管的控制极与所述电容的第一极连接，所述第二晶体管的第一极与时钟信号线连接，所述第二晶体管的第二极与所述电容的第二极以及所述信号输出端连接，所述信号输出端与所述栅线连接；
    其中，所述第二晶体管和所述电容均位于所述第一元件组中，所述时钟信号线位于所述第二线组中。
  12. 根据权利要求3所述的显示基板，其中，所述驱动单元包括：
    第三晶体管和第四晶体管，所述第三晶体管的控制极和所述第四晶体管的控制极均与第二起始信号线连接；
    其中，所述第三晶体管和所述第四晶体管位于所述第二元件组中且靠近所述显示区域设置，所述第二起始信号线位于所述第二线组中且远离所述显示区域设置。
  13. 根据权利要求3所述的显示基板，其中，所述多条信号线包括电源电压信号线和时钟信号线，所述驱动单元包括多个晶体管；
    其中，连接所述电源电压信号线的晶体管数量大于连接所述时钟信号线的晶体管数量，所述电源电压信号线和所述时钟信号线均位于所述第二线组 中，且所述电源电压信号线位于所述时钟信号线远离所述显示区域的一侧。
  14. 根据权利要求3所述的显示基板，其中，所述第一线组包括以下信号线至少之一：高电平信号线和低电平信号线；
    所述第二线组包括以下信号线至少之一：低电平信号线、电源电压信号线、时钟信号线和起始信号线。
  15. 根据权利要求3所述的显示基板，其中，所述第一元件组和所述第二元件组均包括以下电子元件至少之一：晶体管和电容。
  16. 根据权利要求1至15任一项所述的显示基板，其中，所述驱动单元包括晶体管，所述晶体管的控制极、所述信号线以及所述栅线均位于同一膜层且材料相同。
  17. 根据权利要求1至15任一项所述的显示基板，其中，所述显示基板包括两个所述栅线驱动电路，两个所述栅线驱动电路分别为第一栅线驱动电路和第二栅线驱动电路，所述第一栅线驱动电路与位于偶数行的栅线连接，所述第二栅线驱动电路与位于奇数行的栅线连接；
    其中，所述第一栅线驱动电路以及连接所述第一栅线驱动电路的多条信号线位于所述显示区域的第一侧，所述第二栅线驱动电路以及连接所述第二栅线驱动电路的多条信号线位于所述显示区域的第二侧，所述第一侧和所述第二侧为沿所述第一方向上相对的两侧。
  18. 一种显示面板，包括如权利要求1至17任一项所述的显示基板。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板还包括：
    对盒基板，与所述显示基板相对设置；以及
    封框胶，设置在所述对盒基板与所述显示基板之间，所述封框胶在所述衬底上的正投影位于所述周边区域内；
    其中，所述驱动单元还包括：第二元件组，位于所述第一元件组靠近所述显示区域的一侧，包括至少一个第二电子元件；所述多条信号线分为第一线组和第二线组，所述第一线组位于所述第一元件组和所述第二元件组之间，所述第二线组位于所述第二元件组靠近所述显示区域的一侧；
    所述封框胶在所述衬底上的正投影，覆盖所述第一元件组、所述第一线组以及至少部分所述第二元件组在所述衬底上的正投影。
  20. 一种显示装置，包括：
    如权利要求18或19所述的显示面板；以及
    驱动芯片，与所述多条信号线连接，用于向所述多条信号线提供驱动信号。
PCT/CN2023/110368 2022-09-01 2023-07-31 显示基板、显示面板及显示装置 WO2024045988A1 (zh)

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