WO2024045732A1 - 聚酰亚胺过孔及晶圆级半导体封装结构的制备方法 - Google Patents

聚酰亚胺过孔及晶圆级半导体封装结构的制备方法 Download PDF

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Publication number
WO2024045732A1
WO2024045732A1 PCT/CN2023/097808 CN2023097808W WO2024045732A1 WO 2024045732 A1 WO2024045732 A1 WO 2024045732A1 CN 2023097808 W CN2023097808 W CN 2023097808W WO 2024045732 A1 WO2024045732 A1 WO 2024045732A1
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Prior art keywords
layer
polyimide
via hole
preset
metal
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PCT/CN2023/097808
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English (en)
French (fr)
Inventor
刘翔
尹佳山
周祖源
薛兴涛
林正忠
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盛合晶微半导体(江阴)有限公司
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Publication of WO2024045732A1 publication Critical patent/WO2024045732A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins

Definitions

  • the present invention relates to the field of advanced semiconductor packaging technology, and in particular to a method for preparing a polyimide via hole and a wafer-level semiconductor packaging structure.
  • PI polyimide
  • polyimide vias are usually prepared through coating, exposure, development and curing to connect the upper and lower redistribution layers (Redistribution Layer, RDL) , but the polyimide via profile changes greatly from top to bottom, and the process is not precise, and there will be residue at the bottom of the via.
  • RDL redistribution Layer
  • Advanced semiconductor packaging technology requires smaller-sized polyimide vias to improve chip performance, thus requiring process optimization and improvement.
  • the object of the present invention is to provide a method for preparing polyimide vias and wafer-level semiconductor packaging structures to avoid residues at the bottom of small-sized polyimide vias problem, the upper and lower contours of the polyimide vias are basically consistent, and the preparation process is refined, thereby improving the product yield and greatly improving the performance of the chip.
  • the present invention provides a method for preparing polyimide vias.
  • the preparation method includes:
  • S4 Form a preset layer on the metal layer, and form a first pre-via hole on the preset layer.
  • the first pre-via hole is located vertically directly above the metal pad.
  • the aperture size of the via hole is less than or equal to 2 ⁇ m;
  • S6 Based on the second pre-via hole, etch the polyimide layer to form a third pre-via hole.
  • the third pre-via hole is located vertically directly above the metal pad and is soldered to the metal. disc in direct contact;
  • the first pre-via hole, the second pre-via hole and the third pre-via hole have the same aperture size.
  • the steps of forming the polyimide layer include coating, total exposure and curing.
  • the step of forming the preset layer includes: forming a patterned preset photoresist layer on the metal layer, and the preset photoresist layer is located perpendicular to the metal pad.
  • the diameter of the preset photoresist layer is less than or equal to 2 ⁇ m; metal is electroplated on the metal layer to form the preset layer, and the preset layer fills the gaps between the preset photoresist layers. gap, the preset layer is flush with the top of the preset photoresist layer; etching away all of the preset photoresist layer, thereby forming the first pre-via hole at the position of the preset photoresist layer .
  • the preset layer is a photoresist layer.
  • the steps of forming the preset layer include coating, exposure and development, and etching to form the first layer on the preset layer.
  • Pre-via hole, the first pre-via hole is located vertically directly above the metal pad, the aperture size of the first pre-via hole is less than or equal to 2 ⁇ m, in step S5, after forming the second pre-via hole, including the step of removing the preset layer.
  • step S4 the material of the preset layer is polyimide, and the steps of forming the preset layer include coating, exposure, development and curing, so that the preset layer is formed with the A first pre-via hole, the first pre-via hole is located vertically directly above the metal pad, the aperture size of the first pre-via hole is less than or equal to 2 ⁇ m, in step S5, the second pre-via hole is formed
  • the step further includes the step of removing the preset layer.
  • the material of the metal pad is one or a combination of two or more of aluminum, copper and gold.
  • the metal layer is a single-layer structure of an Al layer or a stacked structure of a Ti layer and a Cu layer.
  • a method of forming the polyimide via hole is dry etching the polyimide layer.
  • the present invention also provides a method for preparing a wafer-level semiconductor packaging structure.
  • the preparation method includes: the method for preparing polyimide vias described in any one of the above.
  • the method for preparing polyimide vias and wafer-level semiconductor packaging structures of the present invention has the following beneficial effects: the present invention avoids the problem of residues at the bottom of small-sized polyimide vias, making the polyimide vias
  • the upper and lower contours of the imide vias are basically the same, and the preparation process is refined, thereby improving the product yield; in the present invention, in wafer-level semiconductor packaging, smaller polyimide vias can make the product design more complex and detailed , greatly improving chip performance.
  • Figure 1 shows a schematic diagram of the structure presented by coating according to the preparation method of polyimide vias in the prior art.
  • FIG. 2 shows a schematic structural diagram of the exposure of a polyimide via preparation method in the prior art.
  • Figure 3 shows a schematic structural diagram of the development and curing of the polyimide via preparation method in the prior art.
  • Figure 4 shows a schematic flow chart of the preparation method of the polyimide via hole of the present invention.
  • FIG. 5 shows a schematic structural diagram of step S1 of the polyimide via preparation method of the present invention.
  • FIG. 6 shows a schematic structural diagram of step S2 of the polyimide via preparation method of the present invention.
  • FIG. 7 shows a schematic structural diagram of step S3 of the polyimide via preparation method of the present invention.
  • FIG. 8 shows a schematic structural diagram of step S4 of the polyimide via preparation method of the present invention.
  • FIG. 9 shows a schematic structural diagram of step S5 of the polyimide via preparation method of the present invention.
  • FIG. 10 shows a schematic structural diagram of step S6 of the polyimide via preparation method of the present invention.
  • Figure 11 shows a schematic structural diagram of step S7 of the polyimide via preparation method of the present invention.
  • FIG. 12 shows a schematic structural diagram of forming a preset photoresist layer in step S4 of the method for preparing polyimide vias of the present invention.
  • Figure 13 shows the formation of presets in step S4 of the preparation method of polyimide vias of the present invention. Schematic diagram of the structure presented by the layer.
  • FIG. 14 shows a schematic structural diagram of removing the preset layer where the first pre-via hole is located in step S5 of the method for preparing polyimide via holes of the present invention.
  • 15 is a schematic structural diagram of forming a first pre-via hole in a preset layer made of polyimide material in step S4 of the polyimide via-preparation method of the present invention.
  • FIG. 16 shows a schematic structural diagram of forming a second pre-via hole based on the first pre-via hole in FIG. 15 .
  • Component label description 10 substrate; 20, metal pad; 30, polyimide layer; 40, metal layer; 50, preset photoresist layer; 60, preset layer; 71, first pre-via hole; 72, second pre-via hole; 73, third pre-via hole; 74, polyimide via hole.
  • spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used to describe a structure or structure shown in the drawings. The relationship of a characteristic to other structures or characteristics. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the figures.
  • a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between” means including both endpoint values.
  • structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, as well as may include additional features formed between the first and second features. Embodiments between second features such that the first and second features may not be in direct contact.
  • Polyimide is one of the most important interlayer dielectric materials in the field of semiconductor packaging.
  • the method for preparing polyimide vias in the prior art is usually mainly through coating (as shown in Figure 1), exposure (as shown in Figure 2), development and curing (such as (shown in Figure 3) to prepare polyimide vias by connecting the upper and lower redistribution layers, but the profile of the polyimide vias prepared by the existing technology changes greatly from top to bottom (as shown in Figure 3 (shown as shown), especially there will be residues at the bottom of the vias, making the upper and lower outline dimensions of the polyimide vias inconsistent, resulting in a low product yield.
  • the inventor proposed a method for preparing polyimide vias to solve the problem of residues at the bottom of the polyimide vias, so that the upper and lower contours of the polyimide vias are basically consistent.
  • the preparation process has been refined, thereby improving product yield and greatly improving chip performance.
  • the preparation method of the polyimide via in this embodiment will be described in detail below with reference to the accompanying drawings.
  • this embodiment provides a method for preparing polyimide vias.
  • the method for preparing polyimide vias includes the following steps:
  • S1 Provide a substrate 10 with a metal pad 20 attached to the surface;
  • S4 Form a preset layer 60 on the metal layer 40, and form a first pre-via hole 71 on the preset layer.
  • the first pre-via hole 71 is located vertically directly above the metal pad 20, so The aperture size of the first pre-via hole 71 is less than or equal to 2 ⁇ m;
  • This embodiment avoids the problem of residues at the bottom of the small-sized polyimide via hole 74, making the upper and lower contours of the polyimide via hole 74 basically consistent, and the preparation process is refined, thereby improving the product yield. ;
  • the smaller polyimide via 74 can make the product design more complex and detailed, greatly improving the chip performance.
  • step S1 is first performed to provide a substrate 10 with a metal pad 20 attached to the surface.
  • the substrate 10 is one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.
  • a glass layer is preferably used because the glass layer has lower cost and can reduce subsequent The difficulty of the stripping process.
  • the material of the metal pad 20 is one or a combination of two or more of aluminum, copper and gold. This embodiment does not place any restrictions on the thickness of the substrate 10 and the metal pad 20 and can be set according to actual needs, as long as the above requirements are met.
  • step S2 is then performed to form a polyimide layer 30 on the substrate 10 , with the top of the polyimide layer 30 being higher than the metal pad 20 .
  • the steps of forming the polyimide layer 30 include coating, total exposure and curing. It should be noted here that the steps for forming the polyimide layer 30 in this embodiment are different from those in the prior art.
  • polyimide is usually prepared mainly through the steps of coating, exposure, development and curing.
  • Amine vias that is to say, the polyimide vias are prepared at the same time as the polyimide layer is formed. They are patterned in the exposure step to form the prototype of the polyimide vias, which are then developed. and curing to form a polyimide layer with polyimide via holes.
  • polyimide is coated on the substrate 10 , and the entire polyimide is exposed and cured to form the polyimide layer 30 . At this time, the polyimide layer 30 is formed. Amine layer 30 is solid and does not contain the polyimide vias 74 .
  • step S3 is then performed to form a metal layer 40 on the polyimide layer 30 .
  • the metal layer 40 is a single-layer structure of an Al layer or a stacked structure of a Ti layer and a Cu layer. Only the stacked structure of a Ti layer and a Cu layer is shown in FIG. 7 .
  • the method of forming the metal layer 40 is a sputtering process.
  • the metal layer 40 has a single-layer structure of an Al layer, that is, an Al layer is sputtered on the polyimide layer 30; when the metal layer 40 has a laminated structure of a Ti layer and a Cu layer, that is, a layer of Al is sputtered on the polyimide layer 30.
  • a Ti layer is first sputtered on the polyimide layer 30, and then a Cu layer is sputtered to form a stacked metal layer Ti/Cu layer.
  • the Al layer and the Ti/Cu layer are both nanoscale metal layers, and their thickness can be set according to actual needs, and is not limited here.
  • the metal layer 40 is formed in this step to ensure that the aperture range of the etching remains unchanged during the subsequent small-size longitudinal etching.
  • the metal layer 40 is mixed between the polyimide layer 30 and the preset layer 60 The metal layer 40 is used to prevent adhesion to the polyimide layer 30 when the preset layer 60 is removed, thereby facilitating removal.
  • step S4 is then performed to form a predetermined layer 60 on the metal layer 40 and form a first pre-via hole 71 on the predetermined layer 60 .
  • a pre-via hole is located vertically directly above the metal pad 20 , and the aperture size of the first pre-via hole 71 is less than or equal to 2 ⁇ m.
  • the method of forming the preset layer 60 includes one of plastic sealing process, compression molding, transfer molding, liquid sealing molding, vacuum lamination molding, spin coating molding and electroplating molding.
  • the preset layer 60 The material is one of epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass and electroplated metal.
  • the specific thickness of the preset layer 60 is set according to actual needs and is not limited here.
  • the first pre-via hole 71 is located vertically directly above the metal pad 20. When preparing the first pre-via hole 71, it is necessary to preset the position directly above the metal pad 20 vertically.
  • the pore diameter of the first pre-via hole 71 is the same as the pore diameter of the finally formed polyimide via hole 74 , and the pore diameter size is less than or equal to 2 ⁇ m.
  • step S5 is then performed to form a second pre-via hole 72 in the metal layer 40 based on the first pre-via hole 71 .
  • the pore diameter of the second pre-via hole 72 is the same as the pore diameter of the first pre-via hole 71 , that is, the pore diameter is the same as the finally formed polyimide via hole 74 , and the pore size is less than or equal to 2 ⁇ m.
  • the metal layer 40 has a single-layer structure of an Al layer or a stacked structure of a Ti layer and a Cu layer. When the metal layer 40 has a single-layer structure of an Al layer, the second layer can be formed by dry etching. Pre-via hole 72; when the metal layer 40 is a stacked structure of a Ti layer and a Cu layer, the second pre-via hole 72 can be formed by wet etching.
  • Dry etching includes all gas types, such as O 2 , N 2 , AR, CF 4 , N 2 H 2 , etc.
  • the etching gas is mainly selected based on the substrate to be etched;
  • the solution for wet process etching includes solutions containing Glue remover containing methyl sulfoxide, ethylene glycol, N-methyl-2-pyrrolidone and tetramethylammonium hydroxide. Both preparation methods can be used to form the second pre-via hole 72 , but different formation methods are used for different materials of the metal layer 40 .
  • the specific formation method can be set according to actual needs and is not limited here.
  • step S6 is then performed, and the polyimide layer 30 is etched to form the third pre-via hole 73 based on the second pre-via hole 72 .
  • Three pre-vias 73 are located vertically directly above the metal pad 20 and are in direct contact with the metal pad 20 .
  • the first pre-via hole 71 , the second pre-via hole 72 and the third pre-via hole 73 are all on the same vertical line, the apertures of the three are also the same, and the size of the apertures is less than or equal to 2 ⁇ m. .
  • the preparation method of polyimide vias in this embodiment is mainly aimed at the small-sized polyimide vias 74, making the product design more complex and detailed, greatly improving the chip performance, and in the prior art,
  • the pore diameter of polyimide vias is mostly larger than 2 ⁇ m.
  • a method of forming the polyimide via 74 is dry etching the polyimide layer 30 , and the dry etching includes all gas types, such as O 2 , N 2 , AR, CF 4 , N 2 H 2 , etc.
  • the etching gas is mainly selected according to the substrate to be etched. The specific settings can be set according to actual needs and are not limited here.
  • the dry etching process can reduce the generation of waste water, reduce environmental pollution, and is more environmentally friendly.
  • step S7 is finally performed to remove all the components on the polyimide layer 30 .
  • step S7 is finally performed to remove all the components on the polyimide layer 30 .
  • the structure on the polyimide layer 30 includes the metal layer 40 and the preset layer 60.
  • the preset layer 60 can be peeled off first, or the preset layer 60 can be etched using a dry etching process.
  • Layer 60 is provided, and then the metal layer 40 is etched through a dry etching or wet etching process. Removal methods include but are not limited to the above-mentioned methods, as long as they can meet the removal requirements, and can be set according to actual needs, and are not limited here.
  • the step of forming the preset layer 60 includes: forming a patterned preset photoresist layer 50 on the metal layer 40 , and the preset layer 60 is formed on the metal layer 40 .
  • the photoresist layer 50 is located vertically directly above the metal pad 20, and the diameter of the preset photoresist layer 50 is less than or equal to 2 ⁇ m (as shown in Figure 12); metal is electroplated on the metal layer 40 to form the The preset layer 60 fills the gaps between the preset photoresist layers 50, and the preset layer 60 is flush with the top of the preset photoresist layer 50 (as shown in Figure 13 ); Etch away all of the preset photoresist layer 50 to form the first pre-via hole 71 at the position of the preset photoresist layer 50 . It should be noted here that the position of the patterned preset photoresist layer 50 is also the position where the first pre-via hole 71 is subsequently formed.
  • the patterned preset photoresist layer 50 should be cylindrical. , the diameter of which is exactly the same as the first pre-via hole 71 .
  • the material of the preset photoresist layer 50 is one or a combination of two or more of epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and can be etched away using dry etching.
  • the preset photoresist layer 50 .
  • the steps of forming the preset photoresist layer 50 include coating, exposure and development to form the preset photoresist layer 50 with the same preset shape as the first pre-via hole 71 .
  • the subsequent process methods and material types are the same as those in the above steps and have been introduced in detail and will not be described again here.
  • the preset layer 60 is a photoresist layer.
  • the steps of forming the photoresist layer include coating, exposure and development, and etching on the photoresist layer.
  • the first pre-via hole 71 is formed by etching.
  • the first pre-via hole 71 is located vertically directly above the metal pad 20.
  • the aperture size of the first pre-via hole 71 is less than or equal to 2 ⁇ m.
  • step S5 After forming the second pre-via hole 72 , a step of removing the preset layer 60 is also included.
  • the steps of forming the photoresist layer include coating, exposure and development. At this time, the photoresist layer is formed first, and then the first pre-via hole 71 is etched on the photoresist layer. Based on the The first pre-via hole 71 is etched into the metal layer 40 to form the second pre-via hole 72, and then the photoresist layer is removed.
  • the material of the photoresist layer is epoxy resin, silica gel, PBO, BCB, oxidation One or a combination of two or more of silicon, phosphosilicate glass and fluorine-containing glass can be etched away by dry etching. At this time, removing the photoresist layer alleviates the problem.
  • preparation The burden of the polyimide via hole 74 prevents the preparation of the polyimide via hole 74 from being insufficiently precise due to too many structures above the polyimide layer 30 .
  • the material of the preset layer 60 is polyimide, and the steps of forming the preset layer 60 include coating, exposure, development and curing, so that The first pre-via hole 71 is formed on the preset layer 60 (as shown in FIG. 15 ).
  • the first pre-via hole 71 is located vertically directly above the metal pad 20 .
  • the aperture size of 71 is less than or equal to 2 ⁇ m.
  • step S5 after forming the second pre-via hole 72 (as shown in FIG. 16), the step of removing the preset layer 60 is also included.
  • the steps of forming the preset layer 60 include coating, exposure, development and curing. Since the material of the preset layer 60 is polyimide, the preset layer 60 formed here has already formed the first A pre-via hole 71, the substrate and the first pre-via hole 71 formed by this method will cause residues at the bottom to a certain extent, so that the lower profile of the first pre-via hole 71 is smaller than the upper profile . It should be noted here that the metal layer 40 should be etched to form the second pre-via hole 72 based on the aperture of the lower contour of the first pre-via hole 71 . The aperture of the lower contour of the first pre-via hole 71 is The diameter of the second pre-via hole 72 is the same, and the preset layer 60 is removed by dry etching.
  • the removal of the preset layer 60 eases the process of preparing the polyimide in step S6.
  • the burden of via holes 74 is to avoid the problem caused by too many structures above the polyimide layer 30 As a result, the preparation of the polyimide via hole 74 is not precise enough.
  • This embodiment provides a specific example of a method for preparing a polyimide via.
  • the method for preparing a polyimide via includes the following steps:
  • the substrate 10 with the metal pad 20 attached to the surface.
  • the substrate 10 preferably uses a glass layer, which has lower cost and is used to reduce the difficulty of the subsequent stripping process.
  • the material of the metal pad 20 is due to cost
  • the problem and conductivity of copper are preferred to become copper pads.
  • the polyimide layer 30 is formed on the glass layer through processes such as coating, full exposure and curing.
  • the top of the polyimide layer 30 is higher than the copper pad. At this time, the polyimide layer 30 is The imine layer 30 is solid.
  • a Ti layer is first sputtered on the polyimide layer 30 by a sputtering method, and then a Cu layer is sputtered to form a stacked structure of Ti/Cu layers.
  • the preset photoresist layer 50 is formed on the Ti/Cu layer through processes such as coating, exposure and development.
  • the preset photoresist layer 50 is located vertically directly above the Ti/Cu layer.
  • the diameter of the photoresist layer 50 is 1.8 ⁇ m.
  • the position of the preset photoresist layer 50 is also the position of the first pre-via hole 71 described later.
  • the shape and height are the same as the first pre-via hole 71.
  • Metal Cu is then electroplated on the Ti/Cu layer to form an electroplated metal Cu layer.
  • the electroplated metal Cu layer fills the gaps between the preset photoresist layers 50.
  • the electroplated metal Cu layer and the preset photoresist layer 50 are Assume that the top of the photoresist layer 50 is flush, wrap the preset photoresist layer 50 , and then peel or etch away the preset photoresist layer 50 to form a photoresist layer 50 at the position of the preset photoresist layer 50
  • the first pre-via hole 71 has a hole diameter of 1.8 ⁇ m.
  • a wet etching process is used to etch the Ti/Cu layer to form a second pre-via hole 72.
  • the aperture of the second pre-via hole 72 is the same as that of the first pre-via hole 71.
  • the size is the same, 1.8 ⁇ m.
  • a dry etching process is used to etch the polyimide layer 30 to form a third pre-via hole 73.
  • the third pre-via hole 73 is located vertically to the Cu pad. Above and in direct contact with the Cu pad, the third pre-via hole 73 and the second pre-via hole 72 also have the same aperture size, which is 1.8 ⁇ m.
  • This embodiment provides a specific example of a method for preparing a polyimide via.
  • the method for preparing a polyimide via includes the following steps:
  • Embodiment 2 lies in the formation of the metal layer and subsequent steps. The previous steps have been described in Embodiment 2 and will not be described again.
  • An Al layer is sputtered on the polyimide layer 30 by a sputtering method to form a single-layer structure of the Al layer.
  • a photoresist layer is first formed on the Al layer through processes such as coating, exposure and development.
  • the material of the photoresist layer is epoxy resin.
  • the photoresist layer is etched using a dry etching process to form the third photoresist layer.
  • a pre-via hole 71, the aperture size of the first pre-via hole 71 is 1.8 ⁇ m, and the first pre-via hole 71 is located vertically directly above the Cu pad.
  • a dry etching process is used to etch the Al layer to form a second pre-via hole 72, and then a dry etching process is used to etch the remaining photoresist layer. Removing the remaining photoresist layer at this time reduces the burden of preparing the polyimide via 74 and avoids the excessive thickness of the polyimide layer 30 due to the structure above the polyimide layer 30 being too thick. Hole 74 is not fine enough.
  • the second pre-via hole 72 and the first pre-via hole 71 have the same hole diameter, which is 1.8 ⁇ m.
  • a dry etching process is used to etch the polyimide layer 30 to form a third pre-via hole 72 .
  • Hole 73, the third pre-via hole 73 is located vertically directly above the Cu pad and is in direct contact with the Cu pad.
  • the third pre-via hole 73 and the second pre-via hole 72 also have the same hole diameter, which is 1.8 ⁇ m.
  • All etching processes in this embodiment adopt dry etching, which can reduce the generation of waste water, reduce environmental pollution, and is more environmentally friendly.
  • This embodiment provides a specific example of a method for preparing a polyimide via.
  • the method for preparing a polyimide via includes the following steps:
  • Embodiment 2 lies in the steps after forming the metal layer. The previous steps have been described in Embodiment 2 and will not be described again.
  • the preset layer 60 is formed on the Ti/Cu layer through processes such as coating, exposure, development and curing.
  • the material of the preset layer 60 is polyimide.
  • the preset layer 60 The first pre-via hole 71 has been formed.
  • the substrate and the first pre-via hole 71 formed by this method will cause residues to exist at the bottom to a certain extent, so that the first pre-via hole 71
  • the lower profile is smaller than the upper profile
  • the aperture size of the lower profile of the first pre-via hole 71 is 1.8 ⁇ m
  • the first pre-via hole 71 is located vertically directly above the Cu pad.
  • a wet etching process is used to etch the Ti/Cu layer to form the second pre-via hole 72; and then a dry etching process is used to etch the material into polyethylene.
  • the remaining preset layer 60 of imide reduces the burden of preparing the polyimide via 74 and avoids the problem of preparing the polyimide due to the structure above the polyimide layer 30 being too thick.
  • the imine vias 74 are not fine enough.
  • the diameter of the second pre-via hole 72 is the same as the diameter of the lower profile of the first pre-via hole 71 , both being 1.8 ⁇ m.
  • a dry etching process is used to etch the polyimide layer 30 to form the third pre-via hole 73.
  • the third pre-via hole 73 is located on the Cu pad. Vertically above and in direct contact with the Cu pad.
  • the third pre-via hole 73 and the second pre-via hole 72 also have the same hole diameter, which is 1.8 ⁇ m.
  • This embodiment provides a method for preparing a wafer-level semiconductor packaging structure.
  • the method for preparing a wafer-level semiconductor packaging structure includes the method for preparing polyimide vias described in Embodiment 1.
  • the present invention provides a method for preparing polyimide vias.
  • the method for preparing polyimide vias includes the following steps: S1: Provide a substrate with a metal pad attached to the surface; S2: A polyimide layer is formed on the substrate, and the top of the polyimide layer is higher than the metal pad; S3: forming a metal layer on the polyimide layer; S4: forming a metal layer on the metal layer Form a preset layer, and form a first pre-via hole on the preset layer.
  • the first pre-via hole is located vertically directly above the metal pad.
  • the aperture size of the first pre-via hole is less than or equal to 2 ⁇ m.
  • S5 Based on the first pre-via hole, etching the metal layer to form a second pre-via hole;
  • S6 Based on the second pre-via hole, etching the polyimide layer to form a third pre-via hole hole, the third pre-via hole is located vertically directly above the metal pad and is in direct contact with the metal pad;
  • S7 Remove all structures on the polyimide layer to remove the polyimide layer. Polyimide vias are formed on the imide layer.
  • the present invention avoids the problem of residues at the bottom of small-sized polyimide via holes, makes the upper and lower contours of the polyimide via holes basically consistent, and refines the preparation process, thereby improving the yield of the product; the present invention is effective at the wafer level In semiconductor packaging, smaller polyimides Vias can make product design more complex and detailed, greatly improving chip performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

本发明提供一种聚酰亚胺过孔及晶圆级半导体封装结构的制备方法，聚酰亚胺过孔的制备方法包括：S1：提供表面附有金属焊盘的基板；S2：于基板上形成聚酰亚胺层；S3：于聚酰亚胺层上形成金属层；S4：于金属层上形成预设层，并于预设层上形成第一预过孔；S5：刻蚀金属层形成第二预过孔；S6：刻蚀聚酰亚胺层形成第三预过孔；S7：去除聚酰亚胺层之上的所有结构，以于聚酰亚胺层上形成聚酰亚胺过孔。本发明避免了小尺寸聚酰亚胺过孔底部存在残留物的问题，使得聚酰亚胺过孔上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率；本发明在晶圆级半导体封装中，较小的聚酰亚胺过孔可以使产品设计更加复杂和细致，大大提高了芯片性能。

Description

聚酰亚胺过孔及晶圆级半导体封装结构的制备方法 技术领域
本发明涉及半导体先进封装技术领域，特别是涉及一种聚酰亚胺过孔及晶圆级半导体封装结构的制备方法。
背景技术
随着电子科学技术的迅猛发展，微电子技术向小型化的趋势发展，对晶圆级封装材料的研究不断深化。早期的晶圆级封装材料选用苯并环丁烯(Benzocyclobutene，BCB)，但受制于其断裂伸长率低、拉伸强度低、工艺成本高等缺点而被逐渐淘汰。现如今因聚酰亚胺(Polyimide，PI)具有优异的热稳定性、机械性能、化学稳定性、介电性能、绝缘性、附着力和耐水性，是一种高分子材料，已广泛应用于航空航天、微电子等领域。特别是在晶圆级封装等先进的半导体封装工艺中，聚酰亚胺是作为最重要的层间介电材料之一。如1图至图3所示，在常规的现有技术中，通常通过涂布、曝光、显影及固化等方式制备聚酰亚胺过孔，将上下重分布层(Redistribution Layer，RDL)连接起来，但是聚酰亚胺过孔轮廓从上到下变化很大，工艺不精，过孔底部会有残留物。先进的半导体封装技术需要更小尺寸的聚酰亚胺过孔来提高芯片性能，因此需要工艺优化和改进。
鉴于以上，有必要提供一种聚酰亚胺过孔及半导体封装结构的制备方法，避免了小尺寸聚酰亚胺过孔底部存在残留物的问题，使得聚酰亚胺过孔上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率，也大大提高了芯片的性能。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种聚酰亚胺过孔及晶圆级半导体封装结构的制备方法，用于避免小尺寸聚酰亚胺过孔底部存在残留物的问题，使得聚酰亚胺过孔上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率，也大大提高了芯片的性能。
为实现上述目的，本发明提供一种聚酰亚胺过孔的制备方法，所述制备方法包括：
S1：提供表面附有金属焊盘的基板；
S2：于所述基板上形成聚酰亚胺层，所述聚酰亚胺层顶部高于所述金属焊盘；
S3：于所述聚酰亚胺层上形成金属层；
S4：于所述金属层上形成预设层，并于所述预设层上形成第一预过孔，所述第一预过孔位于所述金属焊盘垂直正上方，所述第一预过孔的孔径尺寸小于等于2μm；
S5：基于所述第一预过孔，刻蚀所述金属层形成第二预过孔；
S6：基于所述第二预过孔，刻蚀所述聚酰亚胺层形成第三预过孔，所述第三预过孔位于所述金属焊盘垂直正上方，并与所述金属焊盘直接接触；
S7：去除所述聚酰亚胺层之上的所有结构，以于所述聚酰亚胺层上形成聚酰亚胺过孔。
可选地，所述第一预过孔、所述第二预过孔及所述第三预过孔的孔径尺寸相同。
可选地，形成所述聚酰亚胺层的步骤包括：涂布、全部曝光及固化。
可选地，在步骤S4中，形成所述预设层的步骤包括：先于所述金属层上形成图形化的预设光阻层，所述预设光阻层位于所述金属焊盘垂直正上方，所述预设光阻层的直径尺寸小于等于2μm；于所述金属层上电镀金属，形成所述预设层，所述预设层填充满所述预设光阻层之间的间隙，所述预设层与所述预设光阻层顶部齐平；刻蚀掉全部所述预设光阻层，从而在所述预设光阻层的位置形成所述第一预过孔。可选地，在步骤S4中，所述预设层为光阻层，形成所述预设层的步骤包括涂布、曝光及显影，并于所述预设层上刻蚀形成所述第一预过孔，所述第一预过孔位于所述金属焊盘垂直正上方，所述第一预过孔的孔径尺寸小于等于2μm，在步骤S5中，形成所述第二预过孔后还包括去除所述预设层的步骤。
可选地，在步骤S4中，所述预设层的材料为聚酰亚胺，形成所述预设层的步骤包括涂布、曝光、显影及固化，从而所述预设层上形成所述第一预过孔，所述第一预过孔位于所述金属焊盘垂直正上方，所述第一预过孔的孔径尺寸小于等于2μm，在步骤S5中，形成所述第二预过孔后还包括去除所述预设层的步骤。
可选地，所述金属焊盘的材料为铝、铜及金中的一种或两种以上的组合。
可选地，所述金属层为Al层的单层结构或Ti层与Cu层的叠层结构。
可选地，形成所述聚酰亚胺过孔的方法为干法蚀刻所述聚酰亚胺层。
本发明还提供一种晶圆级半导体封装结构的制备方法，所述制备方法包括：上述任意一项所述的聚酰亚胺过孔的制备方法。
如上所述，本发明的聚酰亚胺过孔及晶圆级半导体封装结构的制备方法，具有以下有益效果：本发明避免了小尺寸聚酰亚胺过孔底部存在残留物的问题，使得聚酰亚胺过孔上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率；本发明在晶圆级半导体封装中，较小的聚酰亚胺过孔可以使产品设计更加复杂和细致，大大提高了芯片性能。
附图说明
图1显示为现有技术的聚酰亚胺过孔的制备方法涂布所呈现的结构示意图。
图2显示为现有技术的聚酰亚胺过孔的制备方法曝光所呈现的结构示意图。
图3显示为现有技术的聚酰亚胺过孔的制备方法显影及固化所呈现的结构示意图。
图4显示为本发明的聚酰亚胺过孔的制备方法流程示意图。
图5显示为本发明的聚酰亚胺过孔的制备方法的步骤S1所呈现的结构示意图。
图6显示为本发明的聚酰亚胺过孔的制备方法的步骤S2所呈现的结构示意图。
图7显示为本发明的聚酰亚胺过孔的制备方法的步骤S3所呈现的结构示意图。
图8显示为本发明的聚酰亚胺过孔的制备方法的步骤S4所呈现的结构示意图。
图9显示为本发明的聚酰亚胺过孔的制备方法的步骤S5所呈现的结构示意图。
图10显示为本发明的聚酰亚胺过孔的制备方法的步骤S6所呈现的结构示意图。
图11显示为本发明的聚酰亚胺过孔的制备方法的步骤S7所呈现的结构示意图。
图12显示为本发明的聚酰亚胺过孔的制备方法的步骤S4具体实施例中形成预设光阻层所呈现的结构示意图。
图13显示为本发明的聚酰亚胺过孔的制备方法的步骤S4具体实施例中形成预设 层所呈现的结构示意图。
图14显示为本发明的聚酰亚胺过孔的制备方法的步骤S5具体实施例中去除第一预过孔所在的预设层所呈现的结构示意图。
图15为本发明的聚酰亚胺过孔的制备方法的步骤S4具体实施例中在材料为聚酰亚胺的预设层中形成第一预过孔所呈现的结构示意图。
图16显示为基于图15中的第一预过孔形成第二预过孔所呈现的结构示意图。
元件标号说明
10，基板；20，金属焊盘；30，聚酰亚胺层；40，金属层；50，预设光阻层；60，预设层；
71，第一预过孔；72，第二预过孔；73，第三预过孔；74，聚酰亚胺过孔。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个结构或特征与其他结构或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。本文使用的“介于……之间”表示包括两端点值。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
请参阅图1至图16。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
聚酰亚胺在半导体封装领域最重要的层间介电材料之一。如图1至图3所示，为现有技术制备聚酰亚胺过孔的方法，通常主要通过涂布(如图1所示)、曝光(如图2所示)、显影及固化(如图3所示)的步骤来制备聚酰亚胺过孔，将上下的重分布层连接起来，但是通过现有技术制备的聚酰亚胺过孔轮廓从上到下变化很大(如图3所示)，特别是在过孔底部会存在残留物，使得聚酰亚胺过孔上下轮廓尺寸不一致，使得产品的良率不高。
发明人基于以上发现并经过研究分析，提出一种聚酰亚胺过孔的制备方法，以解决聚酰亚胺过孔底部存在残留物的问题，使得聚酰亚胺过孔上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率，也大大提高了芯片的性能。下面结合附图详细描述本实施例的聚酰亚胺过孔的制备方法。
实施例一
如图4至图11所示，本实施例提供一种聚酰亚胺过孔的制备方法，所述聚酰亚胺过孔的制备方法包括如下步骤：
S1：提供表面附有金属焊盘20的基板10；
S2：于所述基板10上形成聚酰亚胺层30，所述聚酰亚胺层30顶部高于所述金属焊盘20；
S3：于所述聚酰亚胺层30上形成金属层40；
S4：于所述金属层40上形成预设层60，并于所述预设层形成第一预过孔71，所述第一预过孔71位于所述金属焊盘20垂直正上方，所述第一预过孔71的孔径尺寸小于等于2μm；
S5：基于所述第一预过孔71，刻蚀所述金属层40形成第二预过孔72；
S6：基于所述第二预过孔72，刻蚀所述聚酰亚胺层30形成第三预过孔73，所述第三预过孔73位于所述金属焊盘20垂直正上方，并与所述金属焊盘20直接接触；
S7：去除所述聚酰亚胺层30之上的所有结构，以于所述聚酰亚胺层30上形成聚酰亚胺过孔74。
本实施例避免了小尺寸所述聚酰亚胺过孔74底部存在残留物的问题，使得所述聚酰亚胺过孔74上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率；本实施例在晶圆级半导体封装中，较小的所述聚酰亚胺过孔74可以使产品设计更加复杂和细致，大大提高了芯片性能。
参阅图4至图16，以下结合附图对本实施例进行进一步的介绍。
如图4及图5所示，作为示例，首先进行步骤S1，提供表面附有金属焊盘20的基板10。
作为示例，所述基板10为玻璃基板、金属基板、半导体基板、聚合物基板以及陶瓷基板中的一种，在本实施例中优选采用玻璃层，所述玻璃层成本较低，且能降低后续的剥离工艺的难度。作为示例，所述金属焊盘20的材料为铝、铜及金中的一种或两种以上的组合。本实施例对所述基板10和所述金属焊盘20的厚度不做任何限制，可根据实际需要进行设置，只要符合以上要求即可。
如图4及图6所示，作为示例，接着进行步骤S2，于所述基板10上形成聚酰亚胺层30，所述聚酰亚胺层30顶部高于所述金属焊盘20。
作为示例，形成所述聚酰亚胺层30的步骤包括：涂布、全部曝光及固化。这里需要说明的是，本实施例形成所述聚酰亚胺层30的步骤与现有技术中不同，在现有技术中通常主要通过涂布、曝光、显影及固化的步骤来制备聚酰亚胺过孔，也就是说说在形成聚酰亚胺层的同时将聚酰亚胺过孔一起制备，在曝光这一步骤中就已经图形化，形成聚酰亚胺过孔雏形，再经过显影及固化，形成带有聚酰亚胺过孔的聚酰亚胺层。在本实施例中，于所述基板10上涂布聚酰亚胺，全部曝光涂布聚酰亚胺，并固化成形，形成所述聚酰亚胺层30，此时的所述聚酰亚胺层30是实体的，并不包含所述聚酰亚胺过孔74。
如图4及图7所示，作为示例，接着进行步骤S3，于所述聚酰亚胺层30上形成金属层40。
作为示例，所述金属层40为Al层的单层结构或Ti层与Cu层的叠层结构，图7中仅示出Ti层与Cu层的叠层结构。在本实施例中，形成所述金属层40的方法为溅射工艺法，当所述 金属层40为Al层的单层结构时，即在所述聚酰亚胺层30上溅射一层Al层；当所述金属层40为Ti层与Cu层的叠层结构时，即在所述聚酰亚胺层30上先溅射一层Ti层，再溅射一层Cu层，形成叠层金属层Ti/Cu层。所述Al层及所述Ti/Cu层都是纳米级金属层，其厚度可根据实际需要进行设置，在此不做限制。在此步骤中形成金属层40，是为了在后续的小尺寸纵向刻蚀时，保证刻蚀的孔径范围不变，同时，在所述聚酰亚胺层30与所述预设层60中间夹杂所述金属层40，是为了在去除所述预设层60时，不与所述聚酰亚胺层30发生粘连，便于去除。
如图4及图8所示，作为示例，接着进行步骤S4，于所述金属层40上形成预设层60，并于所述预设层60上形成第一预过孔71，所述第一预过孔位于所述金属焊盘20垂直正上方，所述第一预过孔71的孔径尺寸小于等于2μm。
形成所述预设层60的方法包括塑封工艺、压缩成型、传递模塑成型、液封成型、真空层压成型、旋涂成型及电镀成型中的一种，此时所述预设层60的材料为环氧树脂、硅胶、PBO、BCB、氧化硅、磷硅玻璃、含氟玻璃及电镀金属中一种，所述预设层60的具体厚度根据实际需要进行设置，在此不作限制。所述第一预过孔71的位置位于所述金属焊盘20的垂直正上方，在制备所述第一预过孔71时需要事先预设出所述金属焊盘20垂直正上方为位置，所述第一预过孔71的孔径与最终形成的所述聚酰亚胺过孔74的孔径相同，孔径尺寸小于等于2μm。
如图4及图9所示，作为示例，接着进行步骤S5，基于所述第一预过孔71，于所述金属层40形成第二预过孔72。
所述第二预过孔72孔径与所述第一预过孔71的孔径相同，也即与最终形成的所述聚酰亚胺过孔74的孔径相同，孔径尺寸小于等于2μm。所述金属层40为Al层的单层结构或Ti层与Cu层的叠层结构，当所述金属层40为Al层的单层结构时，可以用干法工艺刻蚀形成所述第二预过孔72；当所述金属层40为Ti层与Cu层的叠层结构时，可以用湿法工艺刻蚀形成所述第二预过孔72。干法蚀刻包括所有气体类型，例如，O2、N2、AR、CF4、N2H2等，主要根据要刻蚀的基底来选择刻蚀气体；湿法工艺刻蚀的溶液包括含有二甲亚砜、乙二醇、N-甲基-2-吡咯烷酮及四甲基氢氧化铵成分的去胶液。两种制备方法都可以用于形成所述第二预过孔72，只是针对不同的所述金属层40材料采用不同的形成方法，具体形成方法可根据实际需要设置，在此不做限制。
如图4及图10所示，作为示例，接着进行步骤S6，基于所述第二预过孔72，刻蚀所述聚酰亚胺层30形成所述第三预过孔73，所述第三预过孔73位于所述金属焊盘20垂直正上方，并与所述金属焊盘20直接接触。作为示例，所述第一预过孔71、所述第二预过孔72及所述第三预过孔73都在同一垂直线上，三者孔径也都相同，孔径的尺寸都小于等于2μm。本实施例的聚酰亚胺过孔的制备方法主要针对的也是小尺寸的所述聚酰亚胺过孔74，使产品设计更加复杂和细致，大大提高了芯片性能，而现有技术中的聚酰亚胺过孔的孔径大多大于2μm。
作为示例，形成所述聚酰亚胺过孔74的方法为干法蚀刻所述聚酰亚胺层30，所述干法蚀刻包括所有气体类型，例如，O2、N2、AR、CF4、N2H2等，主要根据要刻蚀的基底来选择刻蚀气体，具体可根据实际需要进行设置，在此不做限制。干法蚀刻工艺可减少废水的产生，减轻环境污染，更为绿色环保。
如图4及图11所示，作为示例，最后进行步骤S7，去除所述聚酰亚胺层30之上的所 有结构，以于所述聚酰亚胺层30上形成聚酰亚胺过孔74。
此时所述聚酰亚胺层30之上的结构包括所述金属层40及所述预设层60，可以先剥离所述预设层60，或用干法刻蚀工艺刻蚀所述预设层60，再通过干法刻蚀或湿法刻蚀工艺刻蚀所述金属层40。去除方法包括并不限于以上所述方法，只要能满足去除要求即可，具体可根据实际需要进行设置，在此不做限制。
如图12至图13所示，作为示例，在步骤S4中，形成所述预设层60的步骤包括：先于所述金属层40上形成图形化的预设光阻层50，所述预设光阻层50位于所述金属焊盘20垂直正上方，所述预设光阻层50直径尺寸小于等于2μm(如图12所示)；于所述金属层40上电镀金属，形成所述预设层60，所述预设层60填充满所述预设光阻层50之间的间隙，所述预设层60与所述预设光阻层50顶部齐平(如图13所示)；刻蚀掉全部所述预设光阻层50，从而在所述预设光阻层50的位置形成所述第一预过孔71。这里需要说明的是，图形化的所述预设光阻层50所在的位置也即后续形成所述第一预过孔71的位置，图形化的所述预设光阻层50应为圆柱型，其直径尺寸与所述第一预过孔71完全相同。所述预设光阻层50的材料为环氧树脂、硅胶、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃中的一种或两种以上的组合，可以使用干法刻蚀刻蚀掉所述预设光阻层50。形成所述预设光阻层50的步骤包括涂布、曝光及显影，以形成与所述第一预过孔71预设形状相同的所述预设光阻层50。后续的工艺方法及材料种类与上述步骤中相同，已详细介绍，此处不再进行赘述。
如图14所示，作为示例，在步骤S4中，所述预设层60为光阻层，形成所述光阻层的步骤包括涂布、曝光及显影，并于所述光阻层上刻蚀形成所述第一预过孔71，所述第一预过孔71位于所述金属焊盘20垂直正上方，所述第一预过孔71的孔径尺寸小于等于2μm，在步骤S5中，形成所述第二预过孔72后还包括去除所述预设层60的步骤。
形成所述光阻层的步骤包括涂布、曝光及显影，此时这里先形成的所述光阻层，再于所述光阻层上刻蚀形成所述第一预过孔71；基于所述第一预过孔71，刻蚀所述金属层40形成第二预过孔72，再去除所述光阻层，所述光阻层的材料为环氧树脂、硅胶、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃中的一种或两种以上的组合，可以使用干法刻蚀刻蚀掉所述光阻层，此时去除所述光阻层减轻了在步骤S6中，制备所述聚酰亚胺过孔74的负担，避免因所述聚酰亚胺层30上方结构太多而导致制备所述聚酰亚胺过孔74不够精细。
如图15至图16所示，作为示例，在步骤S4中，所述预设层的材料为聚酰亚胺，形成所述预设层60的步骤包括涂布、曝光、显影及固化，从而所述预设层60上形成所述第一预过孔71(如图15所示)，所述第一预过孔71位于所述金属焊盘20垂直正上方，所述第一预过孔71的孔径尺寸小于等于2μm，在步骤S5中，形成所述第二预过孔72(如图16所示)后还包括去除所述预设层60的步骤。
形成所述预设层60的步骤包括涂布、曝光、显影及固化，因所述预设层60的材料为聚酰亚胺，此时这里形成的所述预设层60已经形成所述第一预过孔71，在此基底及通过此种方法形成的所述第一预过孔71会在一定程度上造成底部存在残留物，使得所述第一预过孔71的下轮廓小于上轮廓。这里需要说明的是，应该基于所述第一预过孔71下轮廓的孔径，刻蚀所述金属层40形成所述第二预过孔72，所述第一预过孔71下轮廓的孔径与所述第二预过孔72的孔径相同，再通过干法刻蚀除去所述预设层60，此时去除所述预设层60减轻了在步骤S6中，制备所述聚酰亚胺过孔74的负担，避免因所述聚酰亚胺层30上方结构太多而导 致制备所述聚酰亚胺过孔74不够精细。
实施例二
本实施例提供一种聚酰亚胺过孔的制备方法的具体实施例，所述聚酰亚胺过孔的制备方法包括以下步骤：
提供表面附有所述金属焊盘20的所述基板10，所述基板10优选采用玻璃层，成本较低，且用于降低后续的剥离工艺的难度，所述金属焊盘20的材料因成本问题和导电性优选采用为铜，成为铜焊盘。
于所述玻璃层上通过涂布、全部曝光及固化等工艺形成所述聚酰亚胺层30，所述聚酰亚胺层30顶部高于所述铜焊盘，此时的所述聚酰亚胺层30是实体的。
于所述聚酰亚胺层30上通过溅射法先溅射一层Ti层，再溅射一层Cu层，形成Ti/Cu层的叠层结构。
于所述Ti/Cu层上通过涂布、曝光及显影等工艺形成所述预设光阻层50，所述预设光阻层50位于所述Ti/Cu层垂直正上方，所述预设光阻层50直径尺寸为1.8μm，所述预设光阻层50的位置也即为后面所述第一预过孔71的位置，形状和高度都与所述第一预过孔71相同，再于所述Ti/Cu层上电镀金属Cu，形成电镀金属Cu层，所述电镀金属Cu层填充满所述预设光阻层50之间的间隙，所述电镀金属Cu层与所述预设光阻层50顶部齐平，将所述预设光阻层50包裹起来，再将所述预设光阻层50剥离或刻蚀掉，从而在所述预设光阻层50的位置形成第一预过孔71，所述第一预过孔71的孔径大小为1.8μm。
基于所述第一预过孔71，采用湿法刻蚀工艺刻蚀所述Ti/Cu层形成第二预过孔72，所述第二预过孔72与所述第一预过孔71孔径大小相同，均为1.8μm。
基于所述第二预过孔72，采用干法刻蚀工艺刻蚀所述聚酰亚胺层30形成第三预过孔73，所述第三预过孔73位于所述Cu焊盘垂直正上方，并与所述Cu焊盘直接接触，所述第三预过孔73与所述第二预过孔72孔径大小也相同，均为1.8μm。
先采用干法刻蚀工艺，去除剩余所述电镀金属Cu层，再采用湿法刻蚀工艺去除剩余所述Ti/Cu层，最终获得所述聚酰亚胺层30上的所述聚酰亚胺过孔74。
实施例三
本实施例提供一种聚酰亚胺过孔的制备方法的具体实施例，所述聚酰亚胺过孔的制备方法包括以下步骤：
本实施例与实施例二中不同之处在于形成金属层及其后面的步骤，之前的步骤实施例二中已有说明，在此不做赘述。
于所述聚酰亚胺层30上通过溅射法溅射一层Al层，形成Al层的单层结构。
于所述Al层上通过涂布、曝光及显影等工艺先形成光阻层，所述光阻层的材料为环氧树脂，采用干法刻蚀工艺刻蚀所述光阻层形成所述第一预过孔71，所述第一预过孔71的孔径大小为1.8μm，所述第一预过孔71位于所述Cu焊盘垂直正上方。
基于所述第一预过孔71，采用干法刻蚀工艺刻蚀所述Al层形成第二预过孔72，再采用干法刻蚀工艺刻蚀剩余所述光阻层。此时去除剩余的所述光阻层减轻了在制备所述聚酰亚胺过孔74的负担，避免因所述聚酰亚胺层30上方结构太厚而导致制备所述聚酰亚胺过孔74不够精细。所述第二预过孔72与所述第一预过孔71孔径大小相同，均为1.8μm。
基于所述第二预过孔72，采用干法刻蚀工艺刻蚀所述聚酰亚胺层30形成第三预过 孔73，所述第三预过孔73位于所述Cu焊盘垂直正上方，且与所述Cu焊盘直接接触。所述第三预过孔73与所述第二预过孔72孔径大小也相同，均为1.8μm。
最后，采用干法刻蚀工艺刻蚀剩余所述Al层，最终获得所述聚酰亚胺层30上的所述聚酰亚胺过孔74。
本实施例中所有的刻蚀工艺都采用干法刻蚀，可减少废水的产生，减轻环境污染，更为绿色环保。
实施例四
本实施例提供一种聚酰亚胺过孔的制备方法的具体实施例，所述聚酰亚胺过孔的制备方法包括以下步骤：
本实施例与实施例二中不同之处在于形成金属层后面的步骤，之前的步骤实施例二中已有说明，在此不做赘述。
于所述Ti/Cu层上通过涂布、曝光、显影及固化等工艺形成所述预设层60，所述预设层60的材料为聚酰亚胺，此时所述预设层60上已经形成所述第一预过孔71，在此基底及通过此种方法形成的所述第一预过孔71会在一定程度上造成底部存在残留物，使得所述第一预过孔71的下轮廓小于上轮廓，所述第一预过孔71下轮廓的孔径大小为1.8μm，所述第一预过孔71位于所述Cu焊盘垂直正上方。
基于所述第一预过孔71下轮廓的孔径，采用湿法刻蚀工艺刻蚀所述Ti/Cu层形成所述第二预过孔72；再采用干法刻蚀工艺刻蚀材料为聚酰亚胺的剩余所述预设层60，则减轻了在制备所述聚酰亚胺过孔74的负担，避免因所述聚酰亚胺层30上方结构太厚而导致制备所述聚酰亚胺过孔74不够精细。所述第二预过孔72的孔径相同与所述第一预过孔71下轮廓的孔径，均为1.8μm。
基于所述第二预过孔72，采用干法刻蚀工艺刻蚀所述聚酰亚胺层30形成所述第三预过孔73，所述第三预过孔73位于所述Cu焊盘垂直上方，且与所述Cu焊盘直接接触。所述第三预过孔73与所述第二预过孔72孔径大小也相同，均为1.8μm。
最后，采用湿法刻蚀工艺刻蚀剩余所述Ti/Cu层，最终获得所述聚酰亚胺层30上的所述聚酰亚胺过孔74。
实施例五
本实施例提供一种晶圆级半导体封装结构的制备方法，所述晶圆级半导体封装结构的制备方法包括实施例一中所述的聚酰亚胺过孔的制备方法。
综上所述，本发明提供一种聚酰亚胺过孔的制备方法，所述聚酰亚胺过孔的制备方法包括如下步骤：S1：提供表面附有金属焊盘的基板；S2：于所述基板上形成聚酰亚胺层，所述聚酰亚胺层顶部高于所述金属焊盘；S3：于所述聚酰亚胺层上形成金属层；S4：于所述金属层上形成预设层，并于所述预设层上形成第一预过孔，所述第一预过孔位于所述金属焊盘垂直正上方，所述第一预过孔的孔径尺寸小于等于2μm；S5：基于所述第一预过孔，刻蚀所述金属层形成第二预过孔；S6：基于所述第二预过孔，刻蚀所述聚酰亚胺层形成第三预过孔，所述第三预过孔位于所述金属焊盘垂直正上方，并与所述金属焊盘直接接触；S7：去除所述聚酰亚胺层之上的所有结构，以于所述聚酰亚胺层上形成聚酰亚胺过孔。本发明避免了小尺寸聚酰亚胺过孔底部存在残留物的问题，使得聚酰亚胺过孔上下轮廓基本一致，制备工艺精细化，从而提高了产品的良率；本发明在晶圆级半导体封装中，较小的聚酰亚胺 过孔可以使产品设计更加复杂和细致，大大提高了芯片性能。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种聚酰亚胺过孔的制备方法，其特征在于，所述聚酰亚胺过孔的制备方法包括如下步骤：
    S1：提供表面附有金属焊盘的基板；
    S2：于所述基板上形成聚酰亚胺层，所述聚酰亚胺层顶部高于所述金属焊盘；
    S3：于所述聚酰亚胺层上形成金属层；
    S4：于所述金属层上形成预设层，并于所述预设层形成第一预过孔，所述第一预过孔位于所述金属焊盘垂直正上方，所述第一预过孔的孔径尺寸小于等于2μm；
    S5：基于所述第一预过孔，刻蚀所述金属层形成第二预过孔；
    S6：基于所述第二预过孔，刻蚀所述聚酰亚胺层形成第三预过孔，所述第三预过孔位于所述金属焊盘垂直正上方，并与所述金属焊盘直接接触；
    S7：去除所述聚酰亚胺层之上的所有结构，以于所述聚酰亚胺层上形成聚酰亚胺过孔。
  2. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：所述第一预过孔、所述第二预过孔及所述第三预过孔的孔径尺寸相同。
  3. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于，形成所述聚酰亚胺层的步骤包括：涂布、全部曝光及固化。
  4. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：在步骤S4中，形成所述预设层的步骤包括：先于所述金属层上形成图形化的预设光阻层，所述预设光阻层位于所述金属焊盘垂直正上方，所述预设光阻层的直径尺寸小于等于2μm；于所述金属层上电镀金属，形成所述预设层，所述预设层填充满所述预设光阻层之间的间隙，所述预设层与所述预设光阻层顶部齐平；刻蚀掉全部所述预设光阻层，从而在所述预设光阻层的位置形成所述第一预过孔。
  5. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：在步骤S4中，所述预设层为光阻层，形成所述预设层的步骤包括涂布、曝光及显影，并于所述预设层上刻蚀形成所述第一预过孔，在步骤S5中，形成所述第二预过孔后还包括去除所述预设层的步骤。
  6. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：在步骤S4中，所述预设层的材料为聚酰亚胺，形成所述预设层的步骤包括涂布、曝光、显影及固化，从而所述预设层上形成所述第一预过孔，在步骤S5中，形成所述第二预过孔后还包括去除所述预设层的步骤。
  7. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：所述金属焊盘的材料为铝、铜及金中的一种或两种以上的组合。
  8. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：所述金属层为Al层的单层结构或Ti层与Cu层的叠层结构。
  9. 根据权利要求1所述的聚酰亚胺过孔的制备方法，其特征在于：形成所述聚酰亚胺过孔的方法为干法蚀刻所述聚酰亚胺层。
  10. 一种晶圆级半导体封装结构的制备方法，其特征在于：包括如权利要求1～9中任意一项所述的聚酰亚胺过孔的制备方法。
PCT/CN2023/097808 2022-09-02 2023-06-01 聚酰亚胺过孔及晶圆级半导体封装结构的制备方法 WO2024045732A1 (zh)

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