WO2024045261A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024045261A1
WO2024045261A1 PCT/CN2022/123931 CN2022123931W WO2024045261A1 WO 2024045261 A1 WO2024045261 A1 WO 2024045261A1 CN 2022123931 W CN2022123931 W CN 2022123931W WO 2024045261 A1 WO2024045261 A1 WO 2024045261A1
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layer
substrate
gate trench
barrier layer
semiconductor structure
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English (en)
French (fr)
Inventor
赵春蕾
陆勇
徐亚超
张瑞奇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a preparation method thereof.
  • the feature size of devices is also continuously reduced in proportion.
  • the operating voltage of the device does not scale down, causing the electric field intensity in the gate trench to continue to strengthen, and the HCI (hot carrier injection) effect to become more and more serious.
  • the present disclosure provides a semiconductor structure, including:
  • the gate dielectric layer includes a first oxide layer, a barrier layer and a second oxide layer, the second oxide layer covers the sidewalls and bottom of the gate trench, the barrier layer covers all The first oxide layer covers the sidewalls of the second oxide layer, and covers the surface of the barrier layer and the surface of the second oxide layer located at the bottom of the gate trench.
  • the thickness of the second oxide layer located on the bottom sidewall of the gate trench is smaller than the thickness of the second oxide layer located on the top sidewall of the gate trench.
  • the barrier layer includes a doped polysilicon layer.
  • the barrier layer has a thickness of 0.5 nm to 1 nm.
  • the doping type of the barrier layer is N-type, and the doping concentration of doping ions in the barrier layer is 10E20cm-3 ⁇ 20E20cm-3.
  • the semiconductor structure further includes a conductive layer located in the gate trench, the conductive layer covering a surface of the first oxide layer.
  • the substrate further includes a shallow trench isolation structure, and the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate.
  • the present disclosure also provides a method for preparing a semiconductor structure, including:
  • the initial barrier layer and the substrate are thermally oxidized to form a second oxide layer covering the sidewalls and bottom of the gate trench and a barrier layer covering the sidewalls of the second oxide layer.
  • forming the initial barrier layer on the sidewall of the gate trench includes:
  • a low-step covering process is used to deposit a doped polysilicon layer on the sidewalls of the gate trench, the bottom of the gate trench and the substrate to form the barrier material layer.
  • the thickness of the barrier material layer is 2 nm to 8 nm
  • the thickness of the initial barrier layer is 1 nm to 3 nm
  • the thickness of the barrier layer is 0.5 nm to 1 nm.
  • the doping concentration of doping ions in the barrier layer ranges from 10E20cm-3 to 20E20cm-3.
  • the thermal oxidation treatment of the initial barrier layer and the substrate includes: using an in-situ water vapor generation process to oxidize a portion of the initial barrier layer and a portion of the initial barrier layer covered by the initial barrier layer. base.
  • the method further includes: after forming the second oxide layer and the barrier layer, forming a conductive layer on the surface of the first oxide layer.
  • the method further includes: forming a shallow trench isolation structure in the substrate, and the shallow trench isolation structure is A plurality of active areas arranged at intervals are isolated in the substrate.
  • the gate dielectric layer includes a first oxide layer, a barrier layer and a second oxide layer.
  • the second oxide layer covers the sidewalls and bottom of the gate trench
  • the barrier layer covers the sidewalls of the second oxide layer.
  • the first oxide layer covers the surface of the barrier layer and the surface of the second oxide layer located at the bottom of the gate trench.
  • the method for preparing a semiconductor structure of the present disclosure forms a first oxide layer, a second oxide layer and a barrier layer in a gate trench.
  • the second oxide layer covers the sidewalls and bottom of the gate trench, and the barrier layer covers the second oxide layer.
  • the sidewalls of the oxide layer form a gate dielectric layer structure with multiple oxide layers.
  • the gate dielectric layer of the present disclosure can better protect the device, reduce the occurrence of abnormal gate leakage, and reduce the hot carrier injection effect. .
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment
  • Figure 2 is a schematic cross-sectional view of the structure obtained in step S11 of the method for preparing a semiconductor structure provided in an embodiment
  • FIG. 3 is a cross-section of the structure obtained by forming a shallow trench isolation structure in a substrate in a method for manufacturing a semiconductor structure provided in an embodiment, and the shallow trench isolation structure isolates a plurality of spaced-apart active regions in the substrate.
  • FIG. 4 is a schematic cross-sectional view of the structure obtained by forming an isolation material layer on the upper surface of the substrate in the method for preparing a semiconductor structure provided in one embodiment
  • Figure 5 is a schematic top view of the structure obtained in step S12 of the method for preparing a semiconductor structure provided in an embodiment
  • Figure 6 is a schematic cross-sectional view of the structure taken at A-A’ in Figure 5;
  • Figure 7 is a step flow chart of step S13 in a method for manufacturing a semiconductor structure provided in an embodiment
  • Figure 8 is a schematic cross-sectional view of the structure obtained in step S131 of the method for preparing a semiconductor structure provided in an embodiment
  • Figure 9 is a schematic cross-sectional view of the structure obtained in step S132 of the method for preparing a semiconductor structure provided in an embodiment
  • Figure 10 is a schematic cross-sectional view of the structure obtained in step S14 of the method for preparing a semiconductor structure provided in an embodiment
  • Figure 11 is a schematic cross-sectional view of the structure obtained in step S15 of the method for preparing a semiconductor structure provided in an embodiment
  • FIG. 12 is a schematic cross-sectional view of the structure obtained by forming a conductive layer on the surface of the first oxide layer in a method for preparing a semiconductor structure provided in an embodiment.
  • Substrate 11. Shallow trench isolation structure; 12. Active area; 2. Isolation material layer; 31. Gate trench; 32. Barrier material layer; 33. Initial barrier layer; 34. First oxide layer; 35. Barrier layer; 36. Second oxide layer; 37. Conductive layer.
  • first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure; for example, a first element, component, region, layer, doping type or section could be termed
  • the first doping type becomes the second doping type, and similarly, the second doping type can become the first doping type; the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “under”, “under”, “under”, “on”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Inventive embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown are contemplated due, for example, to manufacturing techniques and/or tolerances.
  • embodiments of the present disclosure should not be limited to the specific shapes of regions shown herein but are to include deviations in shapes due, for example, to manufacturing techniques.
  • an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not indicative of the actual shapes of the regions of the device and do not limit the scope of the present disclosure.
  • the feature size of devices is also continuously reduced in proportion.
  • the operating voltage of the device does not scale down, causing the electric field intensity in the gate trench to continue to strengthen, and the HCI (hot carrier injection) effect to become more and more serious.
  • the present disclosure provides a method for preparing a semiconductor structure, including:
  • S15 Perform thermal oxidation treatment on the initial barrier layer and the substrate to form a second oxide layer covering the sidewalls and bottom of the gate trench and a barrier layer covering the sidewalls of the second oxide layer.
  • the preparation method of the semiconductor structure in the above embodiment is by forming a first oxide layer, a second oxide layer and a barrier layer in the gate trench.
  • the second oxide layer covers the sidewalls and bottom of the gate trench, and the barrier layer covers The sidewalls of the second oxide layer form a gate dielectric layer structure with multiple oxide layers.
  • the gate dielectric layer of the present disclosure can better protect the device, reduce the occurrence of abnormal gate leakage, and reduce hot carriers. injection effect.
  • step S11 please refer to step S11 in Figure 1 and Figure 2, a substrate 1 is provided.
  • the substrate 1 may include but is not limited to at least one of a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate; specifically, the substrate 1 may be a silicon substrate, a germanium substrate , any one of silicon germanium substrate, gallium arsenide substrate, gallium nitride substrate and silicon carbide substrate, or a composite substrate composed of two or more of them.
  • the method before forming the gate trench in the substrate 1 , the method further includes: forming a shallow trench isolation structure 11 in the substrate 1 , and the shallow trench isolation structure 11 isolates a plurality of spaced-apart structures in the substrate 1 .
  • the steps for active area 12 and the resulting structure are shown in Figure 3.
  • a first ion implantation may be performed on the active region 12 to form a well region in the active region 12; a second ion implantation may be performed on the active region 12 to form a lightly doped region in the well region.
  • the second ion is a P-type ion; if the first ion is a P-type ion, the second ion is an N-type ion; the N-type ion may include a phosphorus ion, arsenic ion or At least one of antimony ions; the P-type ions may include at least one of boron ions, indium ions or gallium ions.
  • the depth of the lightly doped region is smaller than the depth of the well region. That is, for example, the upper surface of the well region is flush with the upper surface of the lightly doped region, and the bottom of the well region is lower than the bottom of the lightly doped region.
  • the lightly doped region may include a source region and a drain region.
  • forming the shallow trench isolation structure 11 in the substrate 1 may include:
  • the trench dielectric layer is filled in the shallow trench to form a shallow trench isolation structure 11 .
  • dry etching may be used to form shallow trenches in the substrate 1; deposition may be used to fill the trench dielectric layer in the shallow trenches; the trench dielectric layer may be, but is not limited to, a silicon dioxide layer.
  • forming shallow trenches in the substrate 1 may include:
  • a photoresist layer is formed on the upper surface of the substrate 1; the method of forming the photoresist layer may be spin coating among the coating methods;
  • the substrate 1 is etched based on the patterned photoresist layer to form shallow trenches in the substrate 1 .
  • the photoresist layer may include a positive photoresist layer or a negative photoresist layer.
  • the method of forming the isolation material layer 2 on the upper surface of the substrate 1 may include but is not limited to atomic layer deposition, epitaxy, chemical vapor deposition, etc.
  • the isolation material layer 2 may be made of the same material as the trench dielectric layer in the shallow trench isolation structure 11; for example, the isolation material layer 2 may be but is not limited to a silicon dioxide layer.
  • step S12 please refer to step S12 in FIG. 1 and FIGS. 5 to 6 , a gate trench 31 is formed in the substrate 1 .
  • FIG. 5 is a schematic top view of the structure formed by forming the gate trench 31 in the substrate 1;
  • FIG. 6 is a schematic cross-sectional view of the structure taken at A-A’ in FIG. 5.
  • forming the gate trench 31 in the substrate 1 may include:
  • the mask layer may be at least one of a silicon nitride layer, a silicon carbide layer, and a silicon oxynitride layer;
  • the etching method can adopt but is not limited to dry etching process.
  • the depth of the gate trench 31 can be 30-400nm; for example, the depth of the gate trench 31 can be 30nm, 50nm, 100nm, 200nm, 300nm or 400nm, or it can be other depths between 30-400nm. , are not limited by the illustrated embodiments.
  • step S13 please refer to step S13 in FIG. 1 and FIGS. 7 to 9 , an initial barrier layer 33 is formed on the sidewall of the gate trench 31 .
  • forming the initial barrier layer 33 on the sidewall of the gate trench 31 may include:
  • S132 Remove the barrier material layer 32 located at the bottom of the gate trench 31 and on the substrate 1, leaving the barrier material layer 32 located on the side walls of the gate trench 31 to form an initial barrier layer 33, as shown in FIG. 9.
  • the barrier material layer 32 may be a leakage current barrier material layer; the initial barrier layer 33 may be an initial leakage current barrier layer.
  • the thickness of the barrier material layer 32 may be 2 nm ⁇ 8 nm; specifically, the thickness of the barrier material layer 32 may be 2 nm, 4 nm, 6 nm or 8 nm, or it may be any other thickness between 2 nm ⁇ 8 nm, regardless of Limitations to the examples illustrated.
  • an initial barrier layer 33 is formed on the sidewalls of the gate trench 31 , that is, the initial barrier layer 33 is formed in the gate trench 31 in the active area 12 and the gate trench 31 in the shallow trench isolation structure 11 at the same time.
  • the barrier material layer 32 at the bottom of the gate trench 31 can be removed through an Etching Back process; wherein the depth of the etching back is less than the sum of the thicknesses of the shallow trench isolation structure 11 and the isolation material layer 2 ;
  • the method of etching back can be dry etching.
  • the etching gas used to remove the barrier material layer 32 at the bottom of the gate trench 31 may include at least one of sulfur hexafluoride, chlorine, methane, silicon chloride, and argon.
  • a low-step covering process can be used to deposit a doped polysilicon layer on the sidewalls of the gate trench 31 , the bottom of the gate trench 31 and the substrate 1 to form the barrier material layer 32 .
  • both the barrier material layer 32 and the initial barrier layer 33 may be made of doped polysilicon material, and the doped ions may include but are not limited to at least one of phosphorus ions, arsenic ions, or antimony ions.
  • the doping concentration of the doping ions in the doped polysilicon material can be 10E20cm -3 ⁇ 20E20cm -3 .
  • the doping concentration can be 10E20cm -3 , 12E20cm -3 , 15E20cm -3 , 18E20cm -3 or 20E20cm - 3 , it can also be other concentrations between 10E20cm -3 and 20E20cm -3 , and is not limited by the illustrated embodiment.
  • the doping concentration of the barrier material layer 32 may be 15E20 cm -3 .
  • the thickness of the initial barrier layer 33 may be 1 nm to 3 nm; specifically, the thickness of the initial barrier layer 33 may be 1 nm, 2 nm, 2.5 nm or 3 nm, or any other thickness between 1 nm and 3 nm. The thickness is not limited by the illustrated embodiment.
  • a low-step covering process can be used to form an N-type doped polysilicon layer as the barrier material layer 32 on the sidewalls of the gate trench 31 , the bottom of the gate trench 31 and the substrate 1 . That is, the material of the barrier material layer 32 and the initial barrier layer 33 can both be N-type doped polysilicon material.
  • the low-step covering process can improve the film uniformity of the barrier material layer 32.
  • the process has the characteristics of extremely low spatter amount and high deposition rate, which can reduce material spatter during the process and increase the stability of the arc, thereby obtaining quality.
  • the N-type doped polysilicon material is deposited through a low-step covering process, and the process is simple. Compared with the traditional process of forming N-type doping, doped ions are easily consumed by the etching process.
  • the low-step covering process of the present disclosure can deposit N-type doped polysilicon materials to replenish the doped ions, and the doped N Type ions can better prevent leakage and increase leakage current, improve device performance, and the process is simple, which can save costs.
  • the thickness of the barrier material layer 32 located on the bottom sidewall of the gate trench 31 is smaller than that located on the sidewall of the gate trench 31 The thickness of the barrier material layer 32 of the top sidewalls.
  • step S14 please refer to step S14 in FIG. 1 and FIG. 10 , a first oxide layer 34 is formed on the surface of the initial barrier layer 33 and the bottom of the gate trench 31 .
  • atomic layer deposition may be used to form the first oxide layer 34 on the surface of the initial barrier layer 33 and the bottom of the gate trench 31; the first oxide layer 34 may include a silicon oxide layer, a silicon oxynitride layer, and a carbon oxide layer. at least one of the silicon layers.
  • step S15 please refer to step S15 in Figure 1 and Figure 11, the initial barrier layer 33 and the substrate 1 are thermally oxidized to form a second oxide layer 36 covering the sidewalls and bottom of the gate trench 31 and Barrier layer 35 covering the sidewalls of the second oxide layer.
  • the thickness of the barrier material layer 32 located on the bottom sidewall of the gate trench 31 is smaller than the thickness of the barrier material layer 32 located on the top sidewall of the gate trench 31 , so that the thickness of the barrier material layer 32 located on the bottom side of the gate trench 31
  • the thickness of the second oxide layer 36 of the wall is smaller than the thickness of the second oxide layer 36 located on the top sidewall of the gate trench 31 .
  • thermally oxidizing the initial barrier layer 33 and the substrate 1 includes: using an in-situ water vapor generation process to oxidize part of the initial barrier layer 33 and part of the substrate 1 covered by the initial barrier layer 33 .
  • an In-Situ Steam Generation (ISSG) process is used to perform thermal oxidation treatment on the initial barrier layer 33 and the substrate 1 to consume part of the initial barrier layer 33 and part of the substrate 1, thereby obtaining the second oxide layer 36 and the barrier layer 35. Therefore, the thickness of the barrier layer 35 is smaller than the thickness of the initial barrier layer 33.
  • ISSG In-Situ Steam Generation
  • in-situ water vapor generation technology is a new low-pressure rapid oxidation thermal annealing technology (RTP, Rapid Thermal Process), which is currently mainly used for the growth of ultra-thin oxide films, sacrificial oxide layers, and the preparation of nitrogen-oxygen films.
  • RTP Rapid oxidation thermal annealing technology
  • the in-situ water vapor generation technology grows the oxide layer through a high-temperature water vapor atmosphere, which grows the oxide layer faster.
  • the gate oxide film grown by the in-situ water vapor generation method is better than the gate oxide film obtained by the furnace tube wet oxidation.
  • the gate oxide film has more outstanding electrical properties.
  • the material of the initial barrier layer 33 can be a doped polysilicon material, during the thermal oxidation process of the initial barrier layer 33 and the substrate 1 using an in-situ water vapor generation process, the doped ions can be partially diffused into the first oxidation layer.
  • the layer 34 and the second oxide layer 36 can help reduce the risk of leakage of the gate structure.
  • the second oxide layer 36 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon oxycarbide layer.
  • the material of the barrier layer 35 can be doped polysilicon material, and the doping concentration of the doping ions in the doped polysilicon material can be 10E20cm -3 ⁇ 20E20cm -3 .
  • the doping concentration can be 10E20cm -3 or 12E20cm -3 , 15E20cm -3 , 18E20cm -3 or 20E20cm -3 , or other concentrations between 10E20cm -3 and 20E20cm -3 , which are not limited by the illustrated embodiments.
  • the thickness of the barrier layer 35 may be 0.5nm ⁇ 1nm; specifically, the thickness of the barrier layer 35 may be 0.5nm, 0.6nm, 0.8nm or 1nm, or it may be any other thickness between 0.5nm ⁇ 1nm, regardless of the thickness. Limitations to the examples illustrated.
  • the method for preparing a semiconductor structure further includes the step of forming a conductive layer 37 on the surface of the first oxide layer 34 after forming the second oxide layer 36 and the barrier layer 35.
  • the resulting structure is as shown in FIG. 12.
  • the upper surface of the conductive layer 37 may be lower than the upper surface of the gate trench 31; the material of the conductive layer 37 may include silicon, silicon germanium, tungsten, tantalum, titanium, molybdenum, aluminum, hafnium, ruthenium and metal silicide. at least one of them.
  • forming the conductive layer 37 on the surface of the first oxide layer 34 may include:
  • a conductive material layer is formed on the surface of the first oxide layer 34 and the isolation material layer 2; the conductive material layer is etched back to form a conductive layer 37 in the gate trench 31.
  • the conductive layer 37 covers the bottom and part of the first oxide layer 34. side walls.
  • the etching gas used to etch back the conductive material layer may include at least one of sulfur hexafluoride, chlorine, methane, silicon chloride, and argon.
  • the conductive layer 37 after forming the conductive layer 37 on the surface of the first oxide layer 34 , it may also include the step of forming an insulating isolation layer on the upper surface of the conductive layer 37 and filling the gate trench with the insulating isolation layer.
  • the method of forming the insulating isolation layer on the upper surface of the conductive layer 37 may include but is not limited to atomic layer deposition, epitaxy, chemical vapor deposition, etc.
  • the insulating isolation layer may include, but is not limited to, at least one of a silicon nitride layer, a silicon carbide layer, and a silicon oxynitride layer.
  • the semiconductor structure may include: a substrate 1, and a gate trench 31 located in the substrate 1; a gate dielectric layer, and the gate dielectric layer includes a first oxide layer. 34. Barrier layer 35 and second oxide layer 36.
  • the second oxide layer 36 covers the sidewalls and bottom of the gate trench 31.
  • the barrier layer 35 covers the sidewalls of the second oxide layer 36.
  • the first oxide layer 34 covers the barrier layer. 35 and the surface covering the second oxide layer 36 located at the bottom of the gate trench 31 .
  • the gate dielectric layer includes a first oxide layer 34, a barrier layer 35 and a second oxide layer 36.
  • the second oxide layer 36 covers the sidewalls and bottom of the gate trench 31, and the barrier layer 35 Covering the sidewalls of the second oxide layer 36, the first oxide layer 34 covers the surface of the barrier layer 35 and the surface of the second oxide layer 36 at the bottom of the gate trench 31.
  • the gate dielectric layer of the present disclosure can better protect the device, reduce the occurrence of abnormal gate leakage, reduce the hot carrier injection effect, and improve device performance.
  • the substrate 1 may include but is not limited to at least one of a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate; the substrate 1 may be a silicon substrate, a germanium substrate , any one of silicon germanium substrate, gallium arsenide substrate, gallium nitride substrate and silicon carbide substrate, or a composite substrate composed of two or more of them.
  • the first oxide layer 34 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon oxycarbide layer.
  • the second oxide layer 36 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon oxycarbide layer.
  • barrier layer 35 may include a doped polysilicon layer.
  • the doping elements in the doped polysilicon layer may include, but are not limited to, at least one of phosphorus ions, arsenic ions or antimony ions.
  • the doped ions in the barrier layer 35 can partially diffuse into the first oxide layer 34 and the second oxide layer 36, which can help reduce the risk of leakage of the gate structure.
  • the doping type of the barrier layer is N-type
  • the doping concentration of the doping ions in the barrier layer can be 10E20cm -3 ⁇ 20E20cm -3 .
  • the doping concentration can be 10E20cm -3 , 12E20cm -3 , 15E20cm -3 , 18E20cm -3 or 20E20cm -3 can also be other concentrations between 10E20cm -3 and 20E20cm -3 and are not limited by the illustrated embodiments.
  • the thickness of the barrier layer 35 may be 0.5nm ⁇ 1nm.
  • the thickness of the barrier layer 35 can be 0.5nm, 0.6nm, 0.8nm or 1nm, or can be any other thickness between 0.5nm and 1nm, and is not limited by the illustrated embodiment.
  • the thickness of the first oxide layer 34 located on the bottom sidewall of the gate trench 31 may be smaller than the thickness of the first oxide layer 34 located on the top sidewall of the gate trench 31 .
  • the semiconductor structure may further include a conductive layer 37 located in the gate trench, and the conductive layer 37 covers the surface of the first oxide layer 34 .
  • the upper surface of the conductive layer 37 may be lower than the upper surface of the gate trench 31; the material of the conductive layer 37 may include silicon, silicon germanium, tungsten, tantalum, titanium, molybdenum, aluminum, hafnium, ruthenium and metal silicide. at least one of them.
  • the substrate 1 further includes a shallow trench isolation structure 11 .
  • the shallow trench isolation structure 11 isolates a plurality of active regions 12 arranged at intervals in the substrate 1 .
  • the shallow trench isolation structure 11 may be a structure in which a shallow trench is filled with a trench dielectric layer; the trench dielectric layer may be a silicon dioxide layer.
  • a well region is formed in the active region 12 , and first ions are implanted in the well region; a lightly doped region is formed in the well region, and second ions are implanted in the lightly doped region.
  • the second ion is a P-type ion; if the first ion is a P-type ion, the second ion is an N-type ion; the N-type ion may include a phosphorus ion, arsenic ion or At least one of antimony ions; the P-type ions may include at least one of boron ions, indium ions or gallium ions.
  • the depth of the lightly doped region is smaller than the depth of the well region. That is, for example, the upper surface of the well region is flush with the upper surface of the lightly doped region, and the bottom of the well region is lower than the bottom of the lightly doped region.
  • the lightly doped region may include a source region and a drain region.
  • the semiconductor structure further includes an isolation material layer 2 , and the isolation material layer 2 is located on the upper surface of the substrate 1 .
  • the isolation material layer 2 may be the same material layer as the trench dielectric layer in the shallow trench isolation structure 11; for example, the isolation material layer 2 may be a silicon dioxide layer.
  • the semiconductor structure further includes an insulating isolation layer (not shown) located on the upper surface of the conductive layer 37 .
  • the insulating isolation layer may include, but is not limited to, at least one of a silicon nitride layer, a silicon carbide layer, and a silicon oxynitride layer.
  • the semiconductor structure of the present disclosure can be used in various semiconductor components, such as in dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the gate dielectric layer of the semiconductor structure of the present disclosure can be used in dynamic random access memory. Provide better protection, reduce the occurrence of abnormal gate leakage, reduce hot carrier injection effects, and improve device stability.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

本公开涉及一种半导体结构及其制备方法。半导体结构包括：基底(1)，以及位于所述基底(1)内的栅极沟槽(31)；栅极介质层，所述栅极介质层包括第一氧化层(34)、阻挡层(35)和第二氧化层(36)，所述第二氧化层(36)覆盖所述栅极沟槽(31)的侧壁及底部，所述阻挡层(35)覆盖所述第二氧化层(36)的侧壁，所述第一氧化层(34)覆盖所述阻挡层(35)的表面以及覆盖位于所述栅极沟槽(31)底部的所述第二氧化层(36)的表面。

Description

半导体结构及其制备方法
相关申请的交叉引用：
本申请要求于2022年9月02日提交中国专利局、申请号为2022110760424、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
这里的陈述仅提供与本公开有关的背景信息，而不必然地构成现有技术。
随着半导体工艺技术的不断改进，器件的特征尺寸也不断按比例缩小。但器件的工作电压并不是按比例缩小的，使得栅极沟槽的电场强度不断加强，HCI(hot carrier injection，热载流子注入)效应也变得越来越严重。
然而在字线结构中，字线导电层与基底之间只有一层常规栅氧化层，不能起到较好的保护作用，容易导致漏电情况的发生，HCI效应也变得越来越严重。
发明内容
基于此，有必要针对现有技术中的字线导电层与基底之间只有一层常规栅氧化层，起不到较好的保护作用，容易导致漏电的问题提供一种半导体结构及其制备方法。
为了实现上述目的，一方面，本公开提供了一种半导体结构，包括：
基底，以及位于所述基底内的栅极沟槽；
栅极介质层，所述栅极介质层包括第一氧化层、阻挡层和第二氧化层，所述第二氧化层覆盖所述栅极沟槽的侧壁及底部，所述阻挡层覆盖所述第二氧化层的侧壁，所述第一氧化层覆盖所述阻挡层的表面以及覆盖位于所述栅极沟槽底部的所述第二氧化层的表面。
在其中一个实施例中，位于所述栅极沟槽底部侧壁的所述第二氧化层的厚度，小于位于所述栅极沟槽顶部侧壁的所述第二氧化层的厚度。
在其中一个实施例中，所述阻挡层包括掺杂多晶硅层。
在其中一个实施例中，所述阻挡层的厚度为0.5nm～1nm。
在其中一个实施例中，所述阻挡层的掺杂类型为N型，所述阻挡层中掺杂离子的掺杂浓度为10E20cm-3～20E20cm-3。
在其中一个实施例中，所述半导体结构还包括位于所述栅极沟槽中的导电层，所述导电层覆盖所述第一氧化层的表面。
在其中一个实施例中，所述基底还包括浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出多个间隔排布的有源区。
本公开还提供一种半导体结构的制备方法，包括：
提供基底；
于所述基底内形成栅极沟槽；
于所述栅极沟槽的侧壁形成初始阻挡层；
于所述初始阻挡层的表面及所述栅极沟槽的底部形成第一氧化层；
对所述初始阻挡层及所述基底进行热氧化处理，以形成覆盖所述栅极沟槽的侧壁及底部的第二氧化层及覆盖所述第二氧化层的侧壁的阻挡层。
在其中一个实施例中，于所述栅极沟槽的侧壁形成所述初始阻挡层，包括：
于所述栅极沟槽的侧壁、所述栅极沟槽的底部及所述基底上形成阻挡材料层；去除位于所述栅极沟槽底部及位于所述基底上的所述阻挡材料层，保留位于所述栅极沟槽侧壁的所述阻挡材料层，形成所述初始阻挡层。
在其中一个实施例中，采用低台阶覆盖工艺于所述栅极沟槽的侧壁、所述栅极沟槽的底部及所述基底上沉积掺杂多晶硅层，形成所述阻挡材料层。
在其中一个实施例中，所述阻挡材料层的厚度为2nm～8nm，所述初始阻挡层的厚度为1nm～3nm，所述阻挡层的厚度为0.5nm～1nm。
在其中一个实施例中，所述阻挡层中掺杂离子的掺杂浓度为10E20cm-3～20E20cm-3。
在其中一个实施例中，所述对所述初始阻挡层及所述基底进行热氧化处理包括：采用原位水汽生成工艺氧化部分所述初始阻挡层以及被所述初始阻挡层覆盖的部分所述基底。
在其中一个实施例中，所述方法还包括：形成所述第二氧化层及所述阻挡层之后，于所述第一氧化层的表面形成导电层。
在其中一个实施例中，所述提供基底之后，所述于所述基底内形成栅极沟槽之前，还包括：于所述基底内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出多个间隔排布的有源区。
本公开的半导体结构及其制备方法具有如下有益效果：
本公开的半导体结构中，栅极介质层包括第一氧化层、阻挡层和第二氧化层，第二氧化层覆盖栅极沟槽的侧壁及底部，阻挡层覆盖第二氧化层的侧壁，第一氧化层覆盖阻挡层的表面以及覆盖位于栅极沟槽底部的第二氧化层的表面，相较于只有一层氧化层的栅极介质层结构，本公开的栅极介质层可以对器件进行更好地保护，降低栅极异常漏电的发生，降低热载流子注入效应。
本公开的半导体结构的制备方法，通过在栅极沟槽内形成第一氧化层、第二氧化层及阻挡层，第二氧化层覆盖栅极沟槽的侧壁及底部，阻挡层覆盖第二氧化层的侧壁，形成具有多层氧化层的栅极介质层结构，本公开的栅极介质层可以对器件进行更好地保护，降低栅极异常漏电的发生，降低热载流子注入效应。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的半导体结构的制备方法的流程图；
图2为一实施例中提供的半导体结构的制备方法中步骤S11所得结构的截面结构示意图；
图3为一实施例中提供的半导体结构的制备方法中于基底内形成浅沟槽隔离结构，浅沟槽隔离结构于基底内隔离出多个间隔排布的有源区的步骤所得结构的截面结构示意图；
图4为一实施例中提供的半导体结构的制备方法中于基底的上表面形成隔离材料层的步骤所得结构的截面结构示意图；
图5为一实施例中提供的半导体结构的制备方法中步骤S12所得结构的俯视结构示意图；
图6为图5中A-A’处所截取的结构的截面结构示意图；
图7为一实施例中提供的半导体结构的制备方法中步骤S13的步骤流程图；
图8为一实施例中提供的半导体结构的制备方法中步骤S131所得结构的截面结构示意图；
图9为一实施例中提供的半导体结构的制备方法中步骤S132所得结构的截面结构示意图；
图10为一实施例中提供的半导体结构的制备方法中步骤S14所得结构的截面结构示意图；
图11为一实施例中提供的半导体结构的制备方法中步骤S15所得结构的截面结构示意图；
图12为一实施例中提供的半导体结构的制备方法中于第一氧化层的表面形成导电层所得结构的截面结构示意图。
附图标记说明：
1、基底；11、浅沟槽隔离结构；12、有源区；2、隔离材料层；31、栅极沟槽；32、阻挡材料层；33、初始阻挡层；34、第一氧化层；35、阻挡层；36、第二氧化层；37、导电层。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描 述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形 状并不表示器件的区的实际形状，且并不限定本公开的范围。
随着半导体工艺技术的不断改进，器件的特征尺寸也不断按比例缩小。但器件的工作电压并不是按比例缩小的，使得栅极沟槽的电场强度不断加强，HCI(hot carrier injection，热载流子注入)效应也变得越来越严重。
然而在字线结构中，字线导电层与基底之间只有一层常规栅氧化层，不能起到较好的保护作用，容易导致漏电情况的发生，HCI效应也变得越来越严重。
基于此，有必要针对现有技术中的字线导电层与基底之间只有一层常规栅氧化层，起不到较好的保护作用，容易导致漏电的问题提供一种半导体结构及其制备方法。
为了实现上述目的，如图1所示，本公开提供一种半导体结构的制备方法，包括：
S11：提供基底；
S12：于基底内形成栅极沟槽；
S13：于栅极沟槽的侧壁形成初始阻挡层；
S14：于初始阻挡层的表面及栅极沟槽的底部形成第一氧化层；
S15：对初始阻挡层及基底进行热氧化处理，以形成覆盖栅极沟槽的侧壁及底部的第二氧化层及覆盖第二氧化层的侧壁的阻挡层。
上述实施例中的半导体结构的制备方法，通过在栅极沟槽内形成第一氧化层、第二氧化层及阻挡层，第二氧化层覆盖栅极沟槽的侧壁及底部，阻挡层覆盖第二氧化层的侧壁，形成具有多层氧化层的栅极介质层结构，本公开的栅极介质层可以对器件进行更好地保护，降低栅极异常漏电的发生，降低热载流子注入效应。
在步骤S11中，请参阅图1中的S11步骤及图2，提供基底1。
其中，基底1可以包括但不仅限于硅基底、锗基底、硅锗基底、砷化镓基底、氮化镓基底和碳化硅基底中的至少一种；具体地，基底1可以是硅基底、锗基底、硅锗基底、砷化镓基底、氮化镓基底和碳化硅基底中的任意一种，也可以是其中两种或两种以上组合而成的复合基底。
在一个实施例中，于基底1内形成栅极沟槽之前，还包括：于基底1内形成浅沟槽隔离结构11，浅沟槽隔离结构11于基底1内隔离出多个间隔排布的有源区12的步骤，所得结构如图3所示。
在一些示例中，可以对有源区12进行第一离子注入，以于有源区12内形成阱区；对有源区12进行第二离子注入，以于阱区内形成轻掺杂区。
具体地，若第一离子为N型离子，则第二离子为P型离子；若第一离子为P型离子，则第二离子为N型离子；N型离子可以包括磷离子、砷离子或锑离子中的至少一种；P型离子可以包括硼离子、铟离子或镓离子中的至少一种。
其中，轻掺杂区的深度小于阱区的深度，即以阱区的上表面与轻掺杂区的上表面相平齐为例，阱区的底部低于轻掺杂区的底部。其中，轻掺杂区可以包括源区及漏区。
在一个实施例中，于基底1内形成浅沟槽隔离结构11可以包括：
于基底1内形成浅沟槽；
于浅沟槽内填充沟槽介质层，以形成浅沟槽隔离结构11。
具体地，于基底1内形成浅沟槽可以采用干法刻蚀的方式；于浅沟槽内填充沟槽介质层可以采用沉积的方式；沟槽介质层可以是但不仅限于二氧化硅层。
进一步地，于基底1内形成浅沟槽可以包括：
于基底1的上表面形成光阻层；形成光阻层的方法可以是涂布法中的旋涂法；
基于第一图形化光罩对光阻层进行曝光；
对曝光后的光阻层进行显影，以得到图形化光阻层；
基于图形化光阻层刻蚀基底1，以于基底1内形成浅沟槽。
在一些示例中，光阻层可以包括正性光阻层，也可以包括负性光阻层。
在一个实施例中，于基底1内形成浅沟槽隔离结构11之后，于基底1内形成栅极沟槽之前，还包括：于基底1的上表面形成隔离材料层2的步骤，所得结构如图4所示。其中，于基底1的上表面形成隔离材料层2的方法可以包括但不仅限于原子层沉积法、外延法、化学气相沉积法等。隔离材料层2可以与浅沟槽隔离结构11内的沟槽介质层为相同材料；示例性的，隔离材料层2可以是但不仅限于二氧化硅层。
在步骤S12中，请参阅图1中的S12步骤及图5至图6，于基底1内形成栅极沟槽31。其中，图5为于基底1内形成栅极沟槽31所得结构的俯视示意图；图6为图5中A-A’处所截取的结构的截面示意图。
具体地，于基底1内形成栅极沟槽31可以包括：
S121：于隔离材料层2的上表面形成掩膜层；掩膜层可以是氮化硅层、碳化硅层和氮氧化硅层中的至少一种；
S122：基于第二图形化光罩对掩膜层进行曝光；
S123：对曝光后的掩膜层进行显影，以得到图形化掩膜层；
S124：基于图形化掩膜层，沿厚度方向依次刻蚀隔离材料层2和基底1，以于有源区12内和浅沟槽隔离结构11内形成栅极沟槽31。
其中，刻蚀的方式可以采用但不仅限于干法刻蚀工艺。栅极沟槽31的深度可以为30～400nm；示例性的，栅极沟槽31的深度可以为30nm、50nm、100nm、200nm、300nm或400nm，也可以是其他位于30～400nm之间的深度，不受所例举的实施例限制。
在步骤S13中，请参阅图1中的S13步骤及图7至图9，于栅极沟槽31的侧壁形成初始阻挡层33。
在一个实施例中，如图7所示，于栅极沟槽31的侧壁形成初始阻挡层33，可以包括：
S131：于栅极沟槽31的侧壁、栅极沟槽31的底部及基底1上形成阻挡材料层32，如图8所示；
S132：去除位于栅极沟槽31底部及位于基底1上的阻挡材料层32，保留位于栅极沟槽31侧壁的阻挡材料层32，形成初始阻挡层33，如图9所示。
其中，阻挡材料层32可以是漏电流阻挡材料层；初始阻挡层33可以是初始漏电流阻挡层。
具体地，阻挡材料层32的厚度可以为2nm～8nm；具体地，阻挡材料层32的厚度可以为2nm、4nm、6nm或8nm，也可以是其他位于2nm～8nm之间的任意厚度，不受所例举的实施例限制。
需要说明的是，参阅图5、图6和图9，因栅极沟槽31横穿有源区12和浅沟槽隔离结构11，所以于栅极沟槽31的侧壁形成初始阻挡层33，便是同时在有源区12里的栅极沟槽31内和浅沟槽隔离结构11里的栅极沟槽31内形成初始阻挡层33。
在一个示例中，可以通过回刻(Etching Back)工艺去除位于栅极沟槽31底部的阻挡材料层32；其中，回刻的深度小于浅沟槽隔离结构11和隔离材料层2的厚度之和；回刻的方式可以是干法蚀刻。
具体地，回刻去除位于栅极沟槽31底部的阻挡材料层32所采用的刻蚀气体可以包括六氟化硫、氯气、甲烷、氯化硅及氩气中的至少一种。
在一个实施例中，可以采用低台阶覆盖工艺于栅极沟槽31的侧壁、栅极沟槽31的底部及基底1上沉积掺杂多晶硅层，形成阻挡材料层32。
具体地，阻挡材料层32及初始阻挡层33的材料均可以是掺杂多晶硅材料，掺杂离子可以包括但不仅限于磷离子、砷离子或锑离子中的至少一种。掺杂多晶硅材料中掺杂离子的掺杂浓度均可以为10E20cm -3～20E20cm -3，具体地，掺杂浓度均可以为10E20cm -3、12E20cm -3、15E20cm -3、18E20cm -3或20E20cm -3，也可以是其他位于10E20cm -3～20E20cm -3之间的浓度，不受所例举的实施例限制。示例性的，本实施例中，阻挡材料层32的掺杂浓度可以是15E20cm -3。
在一个实施例中，初始阻挡层33的厚度可以为1nm～3nm；具体地，初始阻挡层33的厚度可以为1nm、2nm、2.5nm或3nm，也可以是其他位于1nm～3nm之间的任意厚度，不受所例举的实施例限制。
进一步地，可以采用低台阶覆盖工艺于栅极沟槽31的侧壁、栅极沟槽31的底部及基底1上形成N型掺杂多晶硅层作为阻挡材料层32。即阻挡材料层32及初始阻挡层33的材料均可以是N型掺杂多晶硅材料。
具体地，低台阶覆盖工艺可提高阻挡材料层32的膜均匀性，工艺上具有极低飞溅量和高沉积速率的特点，能减少工艺过程中的材料飞溅和增加电弧的稳定性，进而获得质量较高的阻挡材料层32。通过低台阶覆盖工艺沉积N型掺杂多晶硅材料，过程中工艺简单。相较于传统的形成N型掺杂的工艺中掺杂的离子容易被蚀刻过程所消耗，本公开的低台阶覆盖工艺沉积N型掺杂多晶硅材料的方案可以补充掺杂离子，掺杂的N型离子可以起到较好防止漏电和提高漏电流的作用，提升器件性能，且工艺简单，可节约成本。
需要说明的是，采用低台阶覆盖工艺于栅极沟槽31的侧壁形成阻挡材料层32后，位于栅极沟槽31的底部侧壁的阻挡材料层32的厚度小于位于栅极沟槽31的顶部侧壁的阻挡材料层32的厚度。
在步骤S14中，请参阅图1中的S14步骤及图10，于初始阻挡层33的表面及栅极沟槽31的底部形成第一氧化层34。
具体地，可以采用原子层沉积的方式于初始阻挡层33的表面及栅极沟槽31的底部形成第一氧化层34；第一氧化层34可以包括氧化硅层、氮氧化硅层和碳 氧化硅层中的至少一种。
在步骤S15中，请参阅图1中的S15步骤及图11，对初始阻挡层33及基底1进行热氧化处理，以形成覆盖栅极沟槽31的侧壁及底部的第二氧化层36及覆盖第二氧化层的侧壁的阻挡层35。
需要说明的是，位于栅极沟槽31的底部侧壁的阻挡材料层32的厚度小于位于栅极沟槽31的顶部侧壁的阻挡材料层32的厚度，使得位于栅极沟槽31底部侧壁的第二氧化层36的厚度小于位于栅极沟槽31顶部侧壁的第二氧化层36的厚度。
在一个实施例中，对初始阻挡层33及基底1进行热氧化处理包括：采用原位水汽生成工艺氧化部分初始阻挡层33以及被初始阻挡层33覆盖的部分基底1。
具体地，采用原位水汽生成(In-Situ Steam Generation，ISSG)工艺对初始阻挡层33及基底1进行热氧化处理，以消耗部分初始阻挡层33及部分基底1，从而得到第二氧化层36及阻挡层35，因此，阻挡层35的厚度是小于初始阻挡层33的厚度的。
其中，原位水汽生成技术是一种新型低压快速氧化热退火技术(RTP，Rapid Thermal Process)，目前主要用于超薄氧化薄膜生长、牺牲氧化层以及氮氧薄膜的制备。原位水汽生成技术通过高温水汽氛围来生长氧化层，其生长氧化层的速度较快，并且，采用原位水汽生成方法所生长出的栅氧化膜，相对于采用炉管湿法氧化而获得的栅氧化膜，有着更为突出的电学性能。
进一步地，因为初始阻挡层33的材料可以采用掺杂多晶硅材料，在采用原位水汽生成工艺对初始阻挡层33及基底1进行热氧化处理的过程中，掺杂离子可以部分扩散至第一氧化层34及第二氧化层36中，可以帮助降低栅极结构的漏电风险。
在一些示例中，第二氧化层36可以包括氧化硅层、氮氧化硅层和碳氧化硅层中的至少一种。阻挡层35的材料均可以是掺杂多晶硅材料，掺杂多晶硅材料中掺杂离子的掺杂浓度均可以为10E20cm -3～20E20cm -3，具体地，掺杂浓度均可以为10E20cm -3、12E20cm -3、15E20cm -3、18E20cm -3或20E20cm -3，也可以是其他位于10E20cm -3～20E20cm -3之间的浓度，不受所例举的实施例限制。阻挡层35的厚度可以为0.5nm～1nm；具体地，阻挡层35的厚度可以为0.5nm、0.6nm、 0.8nm或1nm，也可以是其他位于0.5nm～1nm之间的任意厚度，不受所例举的实施例限制。
在一个实施例中，半导体结构的制备方法还包括：形成第二氧化层36及阻挡层35之后，于第一氧化层34的表面形成导电层37的步骤，所得结构如图12所示。
具体地，导电层37的上表面可以低于栅极沟槽31的上表面；导电层37的材料可以包括硅、锗硅和钨、钽、钛、钼、铝、铪、钌和金属硅化物中的至少一种。
在一个示例中，于第一氧化层34的表面形成导电层37可以包括：
于第一氧化层34及隔离材料层2的表面形成导电材料层；回刻导电材料层，以于栅极沟槽31内形成导电层37，导电层37覆盖第一氧化层34的底部及部分侧壁。
具体地，回刻导电材料层所采用的刻蚀气体可以包括六氟化硫、氯气、甲烷、氯化硅及氩气中的至少一种。
在一些示例中，于第一氧化层34的表面形成导电层37之后，还可以包括：于导电层37的上表面形成绝缘隔离层，绝缘隔离层填满栅极沟槽的步骤。
具体地，于导电层37的上表面形成绝缘隔离层的方法可以包括但不仅限于原子层沉积法、外延法、化学气相沉积法等。绝缘隔离层可以包括但不仅限于氮化硅层、碳化硅层和氮氧化硅层中的至少一种。
应该理解的是，虽然上述各实施例的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，各流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
本公开还提供了一种半导体结构，如图11所示，半导体结构可以包括：基底1，以及位于基底1内的栅极沟槽31；栅极介质层，栅极介质层包括第一氧化层34、阻挡层35和第二氧化层36，第二氧化层36覆盖栅极沟槽31的侧壁及底部，阻挡层35覆盖第二氧化层36的侧壁，第一氧化层34覆盖阻挡层35 的表面以及覆盖位于栅极沟槽31底部的第二氧化层36的表面。
上述实施例中的半导体结构中，栅极介质层包括第一氧化层34、阻挡层35和第二氧化层36，第二氧化层36覆盖栅极沟槽31的侧壁及底部，阻挡层35覆盖第二氧化层36的侧壁，第一氧化层34覆盖阻挡层35的表面以及覆盖位于栅极沟槽31底部的第二氧化层36的表面，相较于只有一层氧化层的栅极介质层结构，本公开的栅极介质层可以对器件进行更好地保护，降低栅极异常漏电的发生，降低热载流子注入效应，提升器件性能。
在一些示例中，基底1可以包括但不仅限于硅基底、锗基底、硅锗基底、砷化镓基底、氮化镓基底和碳化硅基底中的至少一种；基底1可以是硅基底、锗基底、硅锗基底、砷化镓基底、氮化镓基底和碳化硅基底中的任意一种，也可以是其中两种或两种以上组合而成的复合基底。第一氧化层34可以包括氧化硅层、氮氧化硅层和碳氧化硅层中的至少一种。第二氧化层36可以包括氧化硅层、氮氧化硅层和碳氧化硅层中的至少一种。
在一个实施例中，阻挡层35可以包括掺杂多晶硅层。
进一步地，掺杂多晶硅层中的掺杂元素可以包括但不仅限于磷离子、砷离子或锑离子中的至少一种。阻挡层35的掺杂离子可以部分扩散至第一氧化层34及第二氧化层36中，可以帮助降低栅极结构的漏电风险。
在一个实施例中，阻挡层的掺杂类型为N型，阻挡层中掺杂离子的掺杂浓度可以是10E20cm -3～20E20cm -3，示例性的，掺杂浓度均可以为10E20cm -3、12E20cm -3、15E20cm -3、18E20cm -3或20E20cm -3，也可以是其他位于10E20cm -3～20E20cm -3之间的浓度，不受所例举的实施例限制。
在一个实施例中，阻挡层35的厚度可以为0.5nm～1nm。
具体地，阻挡层35的厚度可以为0.5nm、0.6nm、0.8nm或1nm，也可以是其他位于0.5nm～1nm之间的任意厚度，不受所例举的实施例限制。
在一个实施例中，位于栅极沟槽31底部侧壁的第一氧化层34的厚度可以小于位于栅极沟槽31顶部侧壁的第一氧化层34的厚度。
在一个实施例中，如图12所示，半导体结构还可以包括位于栅极沟槽中的导电层37，导电层37覆盖第一氧化层34的表面。
具体地，导电层37的上表面可以低于栅极沟槽31的上表面；导电层37的材料可以包括硅、锗硅和钨、钽、钛、钼、铝、铪、钌和金属硅化物中的至少 一种。
在一个实施例中，参阅图3，基底1还包括浅沟槽隔离结构11，浅沟槽隔离结构11于基底1内隔离出多个间隔排布的有源区12。
具体地，浅沟槽隔离结构11可以是浅沟槽内填充有沟槽介质层的结构；沟槽介质层可以是二氧化硅层。
在一些示例中，有源区12内形成有阱区，阱区内注入有第一离子；阱区内形成有轻掺杂区，轻掺杂区内注入有第二离子。
具体地，若第一离子为N型离子，则第二离子为P型离子；若第一离子为P型离子，则第二离子为N型离子；N型离子可以包括磷离子、砷离子或锑离子中的至少一种；P型离子可以包括硼离子、铟离子或镓离子中的至少一种。
其中，轻掺杂区的深度小于阱区的深度，即以阱区的上表面与轻掺杂区的上表面相平齐为例，阱区的底部低于轻掺杂区的底部。其中，轻掺杂区可以包括源区及漏区。
在一个实施例中，参阅图4，半导体结构还包括隔离材料层2，隔离材料层2位于基底1的上表面。
具体地，隔离材料层2可以与浅沟槽隔离结构11内的沟槽介质层为相同材料层；示例性地，隔离材料层2可以是二氧化硅层。
在一个实施例中，半导体结构还包括绝缘隔离层(图未示出)，绝缘隔离层位于导电层37的上表面。
具体地，绝缘隔离层可以包括但不仅限于氮化硅层、碳化硅层和氮氧化硅层中的至少一种。
本公开的半导体结构可应用于各种半导体元器件中，如用在动态随机存取存储器(dynamic random access memory，DRAM)中，本公开的半导体结构的栅极介质层可以对动态随机存取存储器进行更好地保护，降低栅极异常漏电的发生，降低热载流子注入效应，提升器件稳定性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的 普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体结构，包括：
    基底，以及位于所述基底内的栅极沟槽；
    栅极介质层，所述栅极介质层包括第一氧化层、阻挡层和第二氧化层，所述第二氧化层覆盖所述栅极沟槽的侧壁及底部，所述阻挡层覆盖所述第二氧化层的侧壁，所述第一氧化层覆盖所述阻挡层的表面以及覆盖位于所述栅极沟槽底部的所述第二氧化层的表面。
  2. 根据权利要求1所述的半导体结构，其中，位于所述栅极沟槽底部侧壁的所述第二氧化层的厚度，小于位于所述栅极沟槽顶部侧壁的所述第二氧化层的厚度。
  3. 根据权利要求1所述的半导体结构，其中，所述阻挡层包括掺杂多晶硅层。
  4. 根据权利要求1所述的半导体结构，其中，所述阻挡层的厚度为0.5nm～1nm。
  5. 根据权利要求1所述的半导体结构，其中，所述阻挡层的掺杂类型为N型，所述阻挡层中掺杂离子的掺杂浓度为10E20cm -3～20E20cm -3。
  6. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括位于所述栅极沟槽中的导电层，所述导电层覆盖所述第一氧化层的表面。
  7. 根据权利要求1至6中任一项所述的半导体结构，其中，所述基底还包括浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出多个间隔排布的有源区。
  8. 一种半导体结构的制备方法，包括：
    提供基底；
    于所述基底内形成栅极沟槽；
    于所述栅极沟槽的侧壁形成初始阻挡层；
    于所述初始阻挡层的表面及所述栅极沟槽的底部形成第一氧化层；
    对所述初始阻挡层及所述基底进行热氧化处理，以形成覆盖所述栅极沟槽的侧壁及底部的第二氧化层及覆盖所述第二氧化层的侧壁的阻挡层。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，于所述栅极沟槽的侧壁形成所述初始阻挡层，包括：
    于所述栅极沟槽的侧壁、所述栅极沟槽的底部及所述基底上形成阻挡材料层；去除位于所述栅极沟槽底部及位于所述基底上的所述阻挡材料层，保留位于所述栅极沟槽侧壁的所述阻挡材料层，形成所述初始阻挡层。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，采用低台阶覆盖工艺于所述栅极沟槽的侧壁、所述栅极沟槽的底部及所述基底上沉积掺杂多晶硅层，形成所述阻挡材料层。
  11. 根据权利要求9所述的半导体结构的制备方法，其中，所述阻挡材料层的厚度为2nm～8nm，所述初始阻挡层的厚度为1nm～3nm，所述阻挡层的厚度为0.5nm～1nm。
  12. 根据权利要求10所述的半导体结构的制备方法，其中，所述阻挡层中掺杂离子的掺杂浓度为10E20cm -3～20E20cm -3。
  13. 根据权利要求8所述的半导体结构的制备方法，其中，所述对所述初始阻挡层及所述基底进行热氧化处理包括：采用原位水汽生成工艺氧化部分所述初始阻挡层以及被所述初始阻挡层覆盖的部分所述基底。
  14. 根据权利要求8所述的半导体结构的制备方法，其中，所述方法还包括：形成所述第二氧化层及所述阻挡层之后，于所述第一氧化层的表面形成导电层。
  15. 根据权利要求8至14中任一项所述的半导体结构的制备方法，其中，所述提供基底之后，所述于所述基底内形成栅极沟槽之前，还包括：于所述基底内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出多个间隔排布的有源区。
PCT/CN2022/123931 2022-09-02 2022-10-09 半导体结构及其制备方法 Ceased WO2024045261A1 (zh)

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