WO2024045219A1 - 监测电路、刷新方法及存储器 - Google Patents

监测电路、刷新方法及存储器 Download PDF

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Publication number
WO2024045219A1
WO2024045219A1 PCT/CN2022/118567 CN2022118567W WO2024045219A1 WO 2024045219 A1 WO2024045219 A1 WO 2024045219A1 CN 2022118567 W CN2022118567 W CN 2022118567W WO 2024045219 A1 WO2024045219 A1 WO 2024045219A1
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Prior art keywords
refresh
address
signal
monitoring
statistical
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PCT/CN2022/118567
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English (en)
French (fr)
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周润发
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a refresh method and a memory.
  • DRAM Dynamic Random Access Memory stores data through a transistor connected to a storage area (1T1C).
  • the transistor is controlled by a word line (WL). When WL is turned on, the The charge is shared with the charge of the bit line (BL) to read data from the target storage area or write data to the target storage area.
  • WL word line
  • BL bit line
  • An embodiment of the present disclosure provides a monitoring circuit, including: a sampling module configured to sample an initial address to obtain a monitoring address, where the initial address is an opened word line address in a memory where the monitoring circuit is located; a counting module connected to the sampling The module is configured such that if the same monitoring address exists in the counting module, the counting value of the counter corresponding to the same monitoring address will be incremented by 1. If the same monitoring address does not exist in the counting module, a new counter corresponding to the monitoring address will be added.
  • the processing module connected to the counting module, is configured to compare the count value of the counter corresponding to each monitoring address in the counting module based on the statistical signal to obtain the target address, and compare the target address based on the refresh signal
  • the adjacent rows perform a refresh operation; the statistical signal is provided during the interval between two adjacent refresh signals.
  • the processing module includes: a comparison unit, connected to the counting module, and is configured to compare the counting values of the counters corresponding to each monitoring address in the counting module based on the statistical signal, and use the monitoring addresses corresponding to the k counters with the largest counting values as The target address is latched and transmitted to the pre-storage unit, k is a positive integer; the pre-storage unit is configured to store the target address transmitted by the comparison unit, and perform refresh operations on adjacent rows of the target address based on the refresh signal; reset unit, connection count The module is configured to provide a reset signal based on the refresh signal, and the reset signal is used to instruct the counting module to reset the counter corresponding to the target address of the refresh operation.
  • the comparison unit is also configured to compare the count values of counters corresponding to each monitoring address in the counting module based on the refresh signal, and latch the monitoring addresses corresponding to the m counters with the largest count values as target addresses and transfer them to the pre-memory unit , m is a positive integer.
  • the refresh operation is performed on the adjacent rows of the target address, including: comparing the count value corresponding to the target address in the counting module, and performing the refresh operation on the adjacent rows of the n target addresses with the largest count value, n is less than or equal to ( m+k) positive integer.
  • the number of statistical signals provided during the interval between two adjacent refresh signals is multiple.
  • the monitoring circuit also includes: a signal generation module configured to generate a statistical signal at any time node in each refresh cycle, where the refresh cycle is the interval between adjacent refresh signals.
  • the signal generation module includes: a random generation unit configured to generate a random number located in the preset value interval based on the preset value interval defined by the preset minimum value and the preset maximum value, and based on the random number and the preset value interval. Set the difference of the minimum value to obtain the proportion of the difference in the preset value interval; the time processing unit is connected to the random generation unit and is configured to determine and output the random delay time based on the proportion value and the refresh cycle; the signal generation unit, Connect the time processing unit to provide statistical signals after a random delay time based on the time node of the refresh signal.
  • the random generation unit generates a generated random number for each statistical signal based on the refresh signal.
  • the sampling module samples based on a preset interval to obtain the monitoring address, where the preset interval is set to sample the monitoring address once every x initial addresses appear, and x is a positive integer.
  • x is a positive integer equal to or less than 16.
  • Another embodiment of the present disclosure provides a refresh method, which is applied to the monitoring circuit provided in the above embodiment, including: sampling monitoring addresses in each refresh cycle, and counting the number of monitoring addresses; based on the statistical signal, obtaining the statistical
  • the target address in the monitoring address is the monitoring address corresponding to the k counters with the largest count value; the target address is stored and latched, and a refresh operation is performed on the adjacent rows of the target address based on the refresh signal.
  • the target address before storing and latching the target address, it also includes: based on the refresh signal, obtaining the target address in the statistical monitoring address.
  • the refresh signal after performing a refresh operation on adjacent rows of the target address based on the refresh signal, it also includes: providing a reset signal based on the refresh signal, and the reset signal is used to indicate resetting the counter corresponding to the target address.
  • a random number located in the preset numerical interval is generated, and based on the difference between the random number and the preset minimum value, the difference value in the preset numerical interval is obtained
  • determine and output the random delay time based on the time node of the refresh signal, provide statistical signals after delaying the random delay time.
  • Yet another embodiment of the present disclosure also provides a memory that obtains a target word line address based on the monitoring circuit provided in the above embodiment.
  • Figure 1 is a schematic structural diagram of a monitoring circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a processing module provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a signal generation module provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of the working principle of a time processing unit provided by an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the principle of monitoring address counting based on different statistical signals provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic flowchart corresponding to each step in a refresh method provided by another embodiment of the present disclosure.
  • the refresh cycle is usually used as the time unit, and the data stored in a refresh cycle is The storage area adjacent to the word line address that has been opened the most times is supplementally refreshed, so as to avoid errors in stored data; however, in the supplementary refresh of the storage area using this method, the time for counting the number of times the word line address is opened is fixed, and it is impossible to Accurately obtain the address of the word line that is turned on more times in the early or middle period of the refresh cycle. The address of the word line that is turned on more times in the early or middle stage of the refresh cycle may also cause data errors in adjacent storage areas in the memory.
  • An embodiment of the present disclosure provides a monitoring circuit that adjusts the statistical time of word line addresses in each refresh cycle, so that in some refresh cycles, statistics and supplementary refresh are enabled more times in the early or mid-term of the refresh cycle.
  • the word line address prevents the word line address that has been turned on more times in the early or mid-term from being masked, thereby improving the memory's flexibility in word line address monitoring and the accuracy of the supplementary refresh function.
  • Figure 1 is a schematic structural diagram of the monitoring circuit provided in this embodiment.
  • Figure 2 is a schematic structural diagram of the processing module provided in this embodiment.
  • Figure 3 is a schematic structural diagram of the signal generation module provided in this embodiment.
  • Figure 4 is a schematic structural diagram of the signal generation module provided in this embodiment.
  • Figure 5 is a schematic diagram of the working principle of the time processing unit.
  • Figure 5 is a schematic diagram of the principle of monitoring address counting based on different statistical signals provided by this embodiment.
  • the monitoring circuit provided by this embodiment is described in detail below with reference to the accompanying drawings, as follows:
  • the monitoring circuit includes:
  • the sampling module 101 is configured to sample an initial address to obtain a monitoring address, where the initial address is an enabled word line address in the memory where the monitoring circuit is located.
  • the counting module 102 is connected to the sampling module 101 and is configured to add 1 to the count value of the counter corresponding to the same monitoring address if the same monitoring address exists in the counting module 102. If the same monitoring address does not exist in the counting module 102 , then add a counter corresponding to the monitoring address and set the counter value to 1.
  • the processing module 103 and the connection counting module 102 are configured to compare the count value of the counter corresponding to each monitoring address in the counting module 102 based on the statistical signal to obtain the target address, and perform a refresh operation on the adjacent rows of the target address based on the refresh signal. , where the statistical signal is provided within the interval between two adjacent refresh signals.
  • the processing module 103 compares the count value corresponding to each monitoring address in the counting module 102 based on the statistical signal, thereby obtaining and storing the target address, where the adjacent behavior memory of the target address needs to perform supplementary refresh. address, and then perform a refresh operation on adjacent rows of the stored target address based on the refresh signal; in addition, by setting the statistical signal to be provided within the interval between adjacent refresh signals, the refresh cycle can be adjusted by adjusting the supply time of the statistical signal Count the time of enabled word line addresses, so that in some refresh cycles, the word line addresses that are enabled more often in the early or mid-term of the refresh cycle can be counted and refreshed to prevent the word line addresses that are enabled more often in the early or mid-term of the refresh cycle.
  • the word line address is masked, improving the memory's flexibility in word line address monitoring and the accuracy of the supplementary refresh function.
  • the memory can directly perform a refresh operation on the adjacent rows of the stored address, or the processing module 103 can output the stored target address. to a certain register of the memory, and the memory uniformly performs refresh operations on adjacent rows of the target address stored in the register. Specifically, adjacent rows of stored multiple target addresses are refreshed in sequence, that is, the +1 and -1 row addresses of a target address are supplementally refreshed, and then based on the count value corresponding to the target address, it is judged whether to Adjacent rows such as +2 and -2 are supplementally refreshed. After refreshing the adjacent rows of one target address, the adjacent rows of another target address are refreshed, and the refresh operation is completed in one go.
  • the sampling module 101 samples based on a preset interval to obtain the monitoring address, where the preset interval is set to perform a sampling of the monitoring address every time x initial addresses appear, x is a positive integer, that is, every time x word line addresses are opened in the memory, the sampling module 101 performs a sampling of the monitoring address.
  • x is a positive integer less than or equal to 16; in a specific example, x can be set to a positive integer such as 14, 12, 10, 8, 6, 4 or 2.
  • the capacity of the counter is b, it must be ensured that 2b>161, that is, b is at least 8. In this case, the capacity of the counter is set to 8 bits; it should be noted that the numerical examples in this example are only for those skilled in the art to understand the capacity setting method of the counter in the counting module 102, and do not constitute a limitation to this embodiment.
  • the processing module 103 includes: a comparison unit 201 and a connection counting module 102, which are configured to compare each monitoring address in the counting module 102 based on statistical signals.
  • the count values of the corresponding counters, and the monitoring addresses corresponding to the k counters with the largest count values are latched as target addresses and transmitted to the pre-storage unit 202, where k is a positive integer;
  • the pre-storage unit 202 is configured to store the comparison unit 201 and transmit The target address, and based on the refresh signal, performs a refresh operation on adjacent rows of the target address;
  • the reset unit 203 connected to the counting module 102, is configured to provide a reset signal based on the refresh signal, and the reset signal is used to instruct the counting module 102 to perform a refresh
  • the counter corresponding to the target address of the operation is reset. Since the reset signal only resets the target address that performs the refresh operation, other monitored addresses can continue to be counted in the next refresh cycle
  • the reset unit 203 provides a reset signal based on a refresh signal as an example.
  • the reset unit can also be configured to provide a reset signal based on statistical signals.
  • the reset signal can also be set to instruct the counting module 102 to reset all counters. At this time, if the reset signal is provided based on the refresh signal, the word line address statistics time of the monitoring circuit is within the time interval from the refresh signal to the statistics signal; if The reset signal is provided based on the refresh signal, and the word line address statistics time of the monitoring circuit is within the time interval of adjacent statistical signals.
  • the comparison unit 201 is further configured to compare the count values of the counters corresponding to each monitoring address in the counting module 102 based on the refresh signal, and use the monitoring addresses corresponding to the m counters with the largest count values as the target address lock.
  • m is a positive integer.
  • the target address is obtained by comparing the refresh signal and the statistical signal twice, thereby obtaining the word line address that is turned on more times in the entire refresh cycle, and the word line address that is turned on more times in the early or middle period of the refresh cycle, further improving the memory Added refresh function accuracy.
  • m and k can be set to the same integer, that is, the number of monitoring addresses obtained by the memory based on the refresh signal and the statistical signal is the same; in other embodiments, m and k can be set to different integers, That is, the number of monitoring addresses obtained by the memory based on the refresh signal and the statistical signal is different.
  • the number of statistical signals provided during the interval between two adjacent refresh signals is multiple, that is, by setting multiple statistical signals and comparing multiple times to obtain the target address, thereby obtaining different time nodes of the refresh cycle.
  • the word line addresses that are turned on more times further improve the accuracy of the memory supplementary refresh function.
  • the pre-storage unit 202 is further configured to compare the count values corresponding to the target addresses in the counting module 102, and perform refresh operations on adjacent rows of the n target addresses with the largest count values, where n is less than or equal to (m + k); based on the aforementioned various implementations, the number of target addresses stored in the pre-storage unit 202 is multiple, and the count value is calculated by performing a secondary comparison on the count value corresponding to the target address in the pre-storage unit 202 The largest n target addresses perform refresh operations to reduce the driving power consumption of the monitoring circuit.
  • n is set to 1, that is, the processing module 103 only performs the refresh operation on the adjacent row of the target address with the largest count value, and the memory pair monitoring circuit obtains the target multiple times based on the statistical signal and/or the refresh signal.
  • the adjacent rows of the target address that has been opened the most times are supplementally refreshed to reduce the power consumption of the monitoring circuit.
  • an identifier can be set for the target address. The identifiers corresponding to the target address obtained based on the refresh signal and the statistical signal are different. By setting a corresponding priority for the identifier, the target address obtained based on the statistical signal is refreshed first, or Prioritize refreshing the target address obtained based on the refresh signal.
  • the target address obtained by the statistics signal and the target address obtained by the refresh signal can realize the refresh operation of adjacent rows through different refresh commands.
  • the target address obtained by the refresh signal is based on the current The refresh command implements the refresh operation of adjacent rows, counts the target address obtained by the signal, and implements the refresh operation of adjacent rows based on the next refresh command.
  • the monitoring circuit further includes: a signal generation module 104 configured to generate a statistical signal at any time node in each refresh cycle, where the refresh cycle is the interval between adjacent refresh signals.
  • the signal generation module 104 includes: a random generation unit 301 configured to generate a signal located in the preset value interval based on the preset value interval defined by the preset minimum value and the preset maximum value. random number, and based on the difference between the random number and the preset minimum value, obtain the proportion of the difference in the preset value interval; the time processing unit 302, connected to the random generation unit 301, is configured to, based on the proportion value and refresh period, determine and output a random delay time; the signal sending unit 303, connected to the time processing unit 302, provides a statistical signal after delaying the random delay time based on the time node of the refresh signal.
  • the generated preset numerical interval is: the preset numerical interval (0,10) defined based on the preset minimum value 0 and the preset maximum value 10 (the preset minimum value 0 corresponds to The random number and the random number corresponding to the preset maximum value 10 respectively correspond to the two refresh signals of the refresh interval. Since the provision time of the statistical signal does not coincide with the refresh signal, the preset value interval is set to an open interval). At this time, the random number The random numbers that can be generated by the generating unit 301 are 1, 2, 3, 4, 5, 6, 7, 8 and 9.
  • the random delay time obtained by the time processing unit 302 is 1/10 times the refresh cycle.
  • the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 1 shown in Figure 4; when the random number generated by the random generation unit 301 is 2, the difference between the preset minimum value and the random number is 2 , the length ratio of the difference in the preset value interval is 2/10. At this time, the random delay time obtained by the time processing unit 302 is 2/10 times the refresh period.
  • the statistical signal provided by the signal generation unit 303 is shown in Figure 4
  • the position of the dashed line 2 on the coordinate axis shown is provided; when the random number generated by the random generation unit 301 is 3, the difference between the preset minimum value and the random number is 3, and the difference accounts for the length of the preset value interval. is 3/10.
  • the random delay time obtained by the time processing unit 302 is 3/10 times the refresh cycle.
  • the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 3 shown in Figure 4; when randomly generated When the random number generated by unit 301 is 4, the difference between the preset minimum value and the random number is 4, and the length ratio of the difference in the preset value interval is 1/10.
  • the time processing unit 302 obtains The random delay time is 4/10 times the refresh period.
  • the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 4 shown in Figure 4; when the random number generated by the random generation unit 301 is 5, the preset minimum The difference between the value and the random number is 5, and the length ratio of the difference in the preset value interval is 1/10.
  • the random delay time obtained by the time processing unit 302 is 5/10 times the refresh period, and the signal The statistical signal provided by the generating unit 303 is provided at the position of the coordinate axis dotted line 5 shown in Figure 4; when the random number generated by the random generating unit 301 is 6, the difference between the preset minimum value and the random number is 6, and the difference The length ratio of the value in the preset value interval is 1/10. At this time, the random delay time obtained by the time processing unit 302 is 6/10 times the refresh period.
  • the statistical signal provided by the signal generation unit 303 is as shown in Figure 4
  • the position of the coordinate axis dotted line 6 is provided; when the random number generated by the random generation unit 301 is 7, the difference between the preset minimum value and the random number is 7, and the length ratio of the difference in the preset value interval is 1 /10, at this time, the random delay time obtained by the time processing unit 302 is 7/10 times the refresh period, and the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 7 shown in Figure 4; when the random generation unit 301 When the generated random number is 8, the difference between the preset minimum value and the random number is 8, and the length ratio of the difference in the preset value interval is 1/10.
  • the random delay obtained by the time processing unit 302 The time is 8/10 times the refresh period, and the statistical signal provided by the signal generating unit 303 is provided at the position of the coordinate axis dotted line 8 shown in Figure 4; when the random number generated by the random generating unit 301 is 9, the preset minimum value and The difference between the random numbers is 9, and the length ratio of the difference in the preset value interval is 1/10.
  • the random delay time obtained by the time processing unit 302 is 9/10 times the refresh period, and the signal generation unit The statistical signal provided by 303 is provided at the position of the coordinate axis dotted line 9 shown in Figure 4.
  • Figure 5 shows the counting module 102 for monitoring address A, monitoring address B, monitoring address C, monitoring address D and monitoring address E. If the statistical time is provided at the dotted line position shown at t1, each monitoring address The size relationship of the corresponding count values is: B>C>A>D>E; if the statistical time is provided at the dotted line position shown in t2, the size relationship of the count values corresponding to each monitoring address is: C>B>A>D> E; If the statistical time is provided at the dotted line position shown in t3, the relationship between the count values corresponding to each monitoring address is: B>A>C>D>E; If the statistical time is provided at the dotted line position shown at t4, the corresponding counting values of each monitoring address The relationship between the count values is: A>B>C>D>E; that is, by adjusting the statistical time provided, the word line address that has been turned on the most times in different time periods in the refresh cycle can be obtained.
  • the processing module 103 only obtains the monitoring address with the largest count value as the target address based on the count value comparison of the counting module 102.
  • the target addresses stored in the processing unit 103 at this time are B and C; if the statistical signal is provided based on t1 and t3, the target address stored in the processing unit 103 at this time is B; if the statistical signal is based on t1 and t4 are provided, and the target addresses stored in the processing unit 103 are A and B at this time; if the statistical signal is provided based on t2 and t3, the target addresses stored in the processing unit 103 are B and C at this time; if the statistical signal is provided based on t2 and t3 If the statistical signal is provided based on t3 and t4, the target addresses stored in the processing unit 103 are A and B.
  • the random generation unit 301 generates a random number for each statistical signal based on the refresh signal, that is, the random generation unit 301 regenerates a random number based on each refresh signal, and regenerates the random number through the refresh signal, that is, adjusts
  • the time nodes provided by the statistical signals in different refresh cycles make the time nodes provided by the statistical signals in different refresh cycles different.
  • the processing module 103 compares the count value corresponding to each monitoring address in the counting module 102 based on the statistical signal, thereby obtaining and storing the target address, where the target address is the address where the memory needs to perform supplementary refresh, and then Perform a refresh operation on the stored target address based on the refresh signal; in addition, by setting the statistical signal to be provided within the interval between adjacent refresh signals, the word lines whose statistics are turned on within the refresh cycle can be adjusted by adjusting the supply time of the statistical signal.
  • the word line addresses that are turned on more times in the early or mid-term of the refresh cycle are counted and refreshed to prevent the word line addresses that are turned on more often in the early or mid-term of the refresh cycle from being covered up, improving The flexibility of the memory's word line address monitoring and the accuracy of the supplementary refresh function.
  • Another embodiment of the present disclosure provides a refresh method, applied to the monitoring circuit provided in the above embodiment, by adjusting the statistical time of word line addresses in each refresh cycle, so that in some refresh cycles, statistics and supplementary refresh are performed during the refresh period.
  • the word line addresses that are turned on more times in the early or mid-term of the cycle prevent the word line addresses that are turned on more often in the early or mid-cycle from being masked, thereby improving the memory's flexibility in word line address monitoring and the accuracy of the supplementary refresh function.
  • FIG. 6 is a schematic flowchart corresponding to each step in the refresh method provided by this embodiment.
  • the refresh method provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:
  • refresh methods include:
  • Step 401 In each refresh cycle, sample monitoring addresses and count the number of monitoring addresses.
  • the monitoring address is obtained based on the initial address sampling, and the initial address is the address of the opened word line in the memory.
  • the monitoring address is obtained by sampling based on a preset interval, where the preset interval is set to sample the monitoring address every time x initial addresses appear, and x is a positive integer, that is, every time x word lines are opened in the memory Address, the sampling module 101 performs a sampling of the monitoring address, and sets the sampling probability for the sampling module 101 to reduce the word line address that the sampling module 101 needs to obtain, that is, the power consumption of the monitoring circuit is reduced through sampling detection.
  • x is a positive integer less than or equal to 16; in a specific example, x can be set to a positive integer such as 14, 12, 10, 8, 6, 4 or 2.
  • Step 402 Based on the statistical signal, obtain the target address among the statistical monitoring addresses.
  • the target address is the monitoring address corresponding to the k counters with the largest count value.
  • the capacity of the counter is b, it must be ensured that 2b>161, that is, b is at least 8.
  • the capacity of the counter is set to 8 bits; it should be noted that the numerical examples in this example are only used for those skilled in the art to understand the capacity setting method of the counter in the counting module 102, and do not constitute a limitation to this embodiment.
  • the statistical signal is generated at any time node in each refresh period, and the refresh period is the interval between adjacent refresh signals.
  • the method of obtaining a statistical signal includes: based on a preset numerical interval defined by a preset minimum value and a preset maximum value, generating a random number located in the preset numerical interval, and based on the random number and The difference of the preset minimum value is obtained, and the proportion of the difference in the preset value interval is obtained. Based on the proportion and the refresh period, the random delay time is determined and output. Based on the time node of the refresh signal, statistics are provided after delaying the random delay time. Signal.
  • the generated preset numerical interval is: the preset numerical interval (0,10) defined based on the preset minimum value 0 and the preset maximum value 10 (the preset minimum value 0 corresponds to The random number and the random number corresponding to the preset maximum value 10 respectively correspond to the two refresh signals of the refresh interval. Since the provision time of the statistical signal does not coincide with the refresh signal, the preset value interval is set to an open interval). At this time, the random number The random numbers that can be generated by the generating unit 301 are 1, 2, 3, 4, 5, 6, 7, 8 and 9.
  • the random delay time obtained by the time processing unit 302 is 1/10 times the refresh cycle.
  • the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 1 shown in Figure 4; when the random number generated by the random generation unit 301 is 2, the difference between the preset minimum value and the random number is 2 , the length ratio of the difference in the preset value interval is 2/10. At this time, the random delay time obtained by the time processing unit 302 is 2/10 times the refresh period.
  • the statistical signal provided by the signal generation unit 303 is shown in Figure 4
  • the position of the dashed line 2 on the coordinate axis shown is provided; when the random number generated by the random generation unit 301 is 3, the difference between the preset minimum value and the random number is 3, and the difference accounts for the length of the preset value interval. is 3/10.
  • the random delay time obtained by the time processing unit 302 is 3/10 times the refresh cycle.
  • the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 3 shown in Figure 4; when randomly generated When the random number generated by unit 301 is 4, the difference between the preset minimum value and the random number is 4, and the length ratio of the difference in the preset value interval is 1/10.
  • the time processing unit 302 obtains The random delay time is 4/10 times the refresh period.
  • the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 4 shown in Figure 4; when the random number generated by the random generation unit 301 is 5, the preset minimum The difference between the value and the random number is 5, and the length ratio of the difference in the preset value interval is 1/10.
  • the random delay time obtained by the time processing unit 302 is 5/10 times the refresh period, and the signal The statistical signal provided by the generating unit 303 is provided at the position of the coordinate axis dotted line 5 shown in Figure 4; when the random number generated by the random generating unit 301 is 6, the difference between the preset minimum value and the random number is 6, and the difference The length ratio of the value in the preset value interval is 1/10. At this time, the random delay time obtained by the time processing unit 302 is 6/10 times the refresh period.
  • the statistical signal provided by the signal generation unit 303 is as shown in Figure 4
  • the position of the coordinate axis dotted line 6 is provided; when the random number generated by the random generation unit 301 is 7, the difference between the preset minimum value and the random number is 7, and the length ratio of the difference in the preset value interval is 1 /10, at this time, the random delay time obtained by the time processing unit 302 is 7/10 times the refresh period, and the statistical signal provided by the signal generation unit 303 is provided at the position of the coordinate axis dotted line 7 shown in Figure 4; when the random generation unit 301 When the generated random number is 8, the difference between the preset minimum value and the random number is 8, and the length ratio of the difference in the preset value interval is 1/10.
  • the random delay obtained by the time processing unit 302 The time is 8/10 times the refresh period, and the statistical signal provided by the signal generating unit 303 is provided at the position of the coordinate axis dotted line 8 shown in Figure 4; when the random number generated by the random generating unit 301 is 9, the preset minimum value and The difference between the random numbers is 9, and the length ratio of the difference in the preset value interval is 1/10.
  • the random delay time obtained by the time processing unit 302 is 9/10 times the refresh period, and the signal generation unit The statistical signal provided by 303 is provided at the position of the coordinate axis dotted line 9 shown in Figure 4.
  • Figure 5 shows the counting module 102 for monitoring address A, monitoring address B, monitoring address C, monitoring address D and monitoring address E. If the statistical time is provided at the dotted line position shown at t1, each monitoring address The size relationship of the corresponding count values is: B>C>A>D>E; if the statistical time is provided at the dotted line position shown in t2, the size relationship of the count values corresponding to each monitoring address is: C>B>A>D> E; If the statistical time is provided at the dotted line position shown in t3, the relationship between the count values corresponding to each monitoring address is: B>A>C>D>E; If the statistical time is provided at the dotted line position shown at t4, the corresponding counting values of each monitoring address The relationship between the count values is: A>B>C>D>E; that is, by adjusting the statistical time provided, the word line address that has been turned on the most times in different time periods in the refresh cycle can be obtained.
  • a random number is generated for each statistical signal based on the refresh signal, that is, the random number is regenerated based on each refresh signal, and the random number is regenerated through the refresh signal, that is, the random number provided by the statistical signal in different refresh periods is adjusted.
  • Time nodes make the time nodes provided by statistical signals in different refresh cycles different, further improving the accuracy of the memory supplementary refresh function.
  • the number of statistical signals provided is multiple, that is, by setting multiple statistical signals and comparing multiple times to obtain the target address, thereby obtaining the number of times the node is turned on at different times in the refresh cycle. More word line addresses further improve the accuracy of the memory supplementary refresh function.
  • Step 404 Store and latch the target address, and perform a refresh operation on the target address based on the refresh signal.
  • the memory can directly perform a refresh operation on the adjacent rows of the stored address, or the processing module 103 can output the stored target address. to a certain register of the memory, and the memory uniformly performs refresh operations on adjacent rows of the target address stored in the register. Specifically, adjacent rows of stored multiple target addresses are refreshed in sequence, that is, the +1 and -1 row addresses of a target address are supplementally refreshed, and then based on the count value corresponding to the target address, it is judged whether to Adjacent rows such as +2 and -2 are supplementally refreshed. After refreshing the adjacent rows of one target address, the adjacent rows of another target address are refreshed, and the refresh operation is completed in sequence.
  • Step 405 Provide a reset signal based on the refresh signal.
  • the reset signal is used to instruct the counter corresponding to the target address of the refresh operation to be reset. Since the reset signal only resets the target address that performs the refresh operation, other monitored addresses can continue to be counted in the next refresh cycle, thereby monitoring the word line addresses whose number of turns is continuously and slowly increasing, further improving the accuracy of the memory supplementary refresh function.
  • the method before executing step 404, the method further includes: step 403, obtaining the target address among the statistical monitoring addresses based on the refresh signal.
  • the count values of the counters corresponding to each monitoring address are compared, and the monitoring addresses corresponding to the m counters with the largest count values are used as the target address.
  • the target address is obtained through two comparisons of the refresh signal and the statistical signal, thereby Obtain the word line addresses that are turned on more times in the entire refresh cycle, as well as the word line addresses that are turned on more times in the early or mid-term of the refresh cycle, to further improve the accuracy of the memory supplementary refresh function.
  • m and k can be set to the same integer, that is, the number of monitoring addresses obtained by the memory based on the refresh signal and the statistical signal is the same; in other embodiments, m and k can be set to different integers, that is, the memory is based on The number of monitoring addresses obtained by refresh signals and statistical signals is different.
  • step 404 also includes: comparing the count values corresponding to the target addresses, and performing a refresh operation on the n target addresses with the largest count values, where n is a positive integer less than or equal to (m+k); Based on the various implementations mentioned above, the number of stored target addresses is multiple. By performing a secondary comparison on the count values corresponding to the target addresses, the refresh operation is performed on the n target addresses with the largest count values to reduce the cost of the monitoring circuit. Driver power consumption.
  • n is set to 1, that is, the refresh operation is only performed on adjacent rows of the target address with the largest count value, and the memory pair monitoring circuit is turned on among the target addresses obtained multiple times based on statistical signals and/or refresh signals.
  • the adjacent rows of the most frequent target addresses are supplementally refreshed to reduce the power consumption of the monitoring circuit.
  • an identifier can be set for the target address.
  • the identifiers corresponding to the target address obtained based on the refresh signal and the statistical signal are different. By setting a corresponding priority for the identifier, the target address obtained based on the statistical signal is refreshed first, or Prioritize refreshing the target address obtained based on the refresh signal.
  • the target address obtained by the statistics signal and the target address obtained by the refresh signal can realize the refresh operation of adjacent rows through different refresh commands.
  • the target address obtained by the refresh signal is based on the current The refresh command implements the refresh operation of adjacent rows, counts the target address obtained by the signal, and implements the refresh operation of adjacent rows based on the next refresh command.
  • the refresh method provided in this embodiment compares the count values corresponding to each monitoring address based on statistical signals, thereby obtaining and storing the target address.
  • the adjacent behavioral memory of the target address needs to perform supplementary refresh of the address, and then stores the address based on the refresh signal.
  • the adjacent rows of the target address perform a refresh operation; in addition, by setting the statistical signal to be provided within the interval between adjacent refresh signals, the statistics of words turned on in the refresh cycle can be adjusted by adjusting the supply time of the statistical signal. line address time, so that in some refresh cycles, the word line addresses that are turned on more times in the early or mid-term of the refresh cycle are counted and refreshed to prevent the word line addresses that are turned on more often in the early or mid-term of the refresh cycle from being covered up. Improve the memory's flexibility in word line address monitoring and the accuracy of the supplementary refresh function.
  • Another embodiment of the present disclosure provides a memory that obtains a target word line address based on the monitoring circuit provided in the above embodiment, and adjusts the statistical time of the word line address in each refresh cycle, so that in some refresh cycles, statistics and supplementation Refresh the word line addresses that have been turned on more times in the early or mid-term of the refresh cycle to prevent the word line addresses that have been turned on more often in the early or mid-term of the refresh cycle from being masked, thereby improving the memory's flexibility in word line address monitoring and supplementing the refresh function. accuracy.
  • the processing module compares the count value corresponding to each monitoring address in the counting module based on the statistical signal, thereby obtaining and storing the target address, where the adjacent behavioral memory of the target address needs to perform supplementary refresh of the address, and then based on The refresh signal performs a refresh operation on the adjacent rows of the stored target address; in addition, by setting the statistical signal to be provided within the interval between adjacent refresh signals, the statistics can be turned on within the refresh cycle by adjusting the supply time of the statistical signal.
  • the memory may be a memory unit or device based on a semiconductor device or component.
  • the memory device may be a volatile memory such as dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory Access memory LPDDR SDRAM, graphics double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2SDRAM, double data rate type triple synchronous dynamic random access memory DDR3SDRAM, double data Rate fourth generation synchronous dynamic random access memory DDR4SDRAM, thyristor random access memory TRAM, etc.; or it can be non-volatile memory, such as phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory RRAM etc.

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Abstract

本公开涉及半导体电路设计领域，特别涉及一种监测电路、刷新方法及存储器，监测电路包括：采样模块，对初始地址采样以获取监测地址，初始地址为监测电路所在存储器中被开启的字线地址；计数模块，连接采样模块，若计数模块中存在相同的监测地址，则将相同的监测地址对应的计数器的计数值加1，若计数模块中不存在相同的监测地址，则新增监测地址对应的计数器，并将计数器的计数值置1；处理模块，连接计数模块，基于统计信号比较计数模块中各监测地址对应的计数器的计数值，以获取目标地址，并基于刷新信号对目标地址的相邻行执行刷新操作；其中，统计信号于相邻的两个刷新信号的间隔时间内提供，以提高存储器对字线地址监测的灵活性。

Description

监测电路、刷新方法及存储器
交叉引用
本公开要求于2022年08月30日递交的名称为“监测电路、刷新方法及存储器”、申请号为202211049623.9的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开涉及半导体电路设计领域，特别涉及一种监测电路、刷新方法及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)通过一个晶体管连接一存储区的结构(1T1C)存储数据，其中晶体管通过字线(word line，WL)控制，WL导通时，存储区内的电荷与位线(bit line，BL)的电荷共享，以将目标存储区中的数据读出，或向目标存储区中写入数据。
字线频繁开启会导致相邻存储区内的电荷丢失，可能导致存储区内存储的数据发生错误；对于上述问题，目前通常基于刷新周期为时间单位，对一个刷新周期内被开启次数最多的字线地址相邻的存储区进行补充刷新，从而避免存储的数据发生错误；然而，采用这种方式进行存储区的补充刷新中，统计字线地址被开启次数的时间固定，无法准确获取在刷新周期前期或中期被开启次数较多的字线地址，而在刷新周期的前期或中期被开启次数较多的字线地址也可能导致存储器内相邻存储区的数据发生错误。
如何提供一种对字线地址的统计更为准确的补充刷新方式，是当前亟待解决的技术问题。
发明内容
本公开一实施例提供了一种监测电路，包括：采样模块，被配置为，对初始地址采样以获取监测地址，初始地址为监测电路所在存储器中被开启的字线地址；计数模块，连接采样模块，被配置为，若计数模块中存在相同的监测地址，则将相同的监测地址对应的计数器的计数值加1，若计数模块中不存在相同的监测地址，则新增监测地址对应的计数器，并将计数器的计数值置1；处理模块，连接计数模块，被配置为，基于统计信号比较计数模块中各监测地址对应的计数器的计数值，以获取目标地址，并基于刷新信号对目标地址的相邻行执行刷新操作；其中，统计信号于相邻的两个刷新信号的间隔时间内提供。
另外，处理模块，包括：比较单元，连接计数模块，被配置为，基于统计信号比较计数模块中各监测地址对应的计数器的计数值，并将计数值最大的k个计数器所对应的监测地址作为目标地址锁存并传输至预存单元，k为正整数；预存单元被配置为，存储比较单元传输的目标地址，并基于刷新信号，对目标地址的相邻行执行刷新操作；复位单元，连接计数模块，被配置为，基于刷新信号提供复位信号，复位信号用于指示计数模块对执行刷新操作的目标地址对应的计数器进行复位。
另外，比较单元还被配置为，基于刷新信号比较计数模块中各监测地址对应的计数器的计数值，并将计数值最大的m个计数器所对应的监测地址作为目标地址锁存并传输至预存单元，m为正整数。
另外，对目标地址的相邻行执行刷新操作，包括：比较计数模块中目标地址对应的计数值，并对计数值最大的n个的目标地址的相邻行执行刷新操作，n为小于等于(m+k)正整数。
另外，于相邻的两个刷新信号的间隔时间内提供的统计信号的数量为多个。
另外，监测电路还包括：信号产生模块，被配置为，于每一刷新周期中的任意时间节点生成统计信号，刷新周期为相邻刷新信号的间隔时间。
另外，信号产生模块，包括：随机产生单元，被配置为，基于预设最小值和预设最大值定义的预设数值区间，生成位于预设数值区间中的随机数，并基于随机数和预设最小值的差值获取差值在 预设数值区间中的占比值；时间处理单元，连接随机产生单元，被配置为，基于占比值和刷新周期，确定并输出随机延迟时间；信号产生单元，连接时间处理单元，基于刷新信号的时间节点，延时随机延迟时间后提供统计信号。
另外，随机产生单元基于刷新信号为每个统计信号产生一个产生的随机数。
另外，采样模块基于预设间隔采样以获取监测地址，其中，预设间隔设置为每出现x个初始地址，进行一次监测地址的采样，x为正整数。
另外，x为小于等于16的正整数。
本公开又一实施例提供了一种刷新方法，应用于上述实施例提供的监测电路，包括：于每一刷新周期内，采样监测地址，并统计监测地址的数量；基于统计信号，获取统计的监测地址中的目标地址，目标地址为计数值最大的k个计数器所对应的监测地址；存储并锁存目标地址，并基于刷新信号对目标地址的相邻行执行刷新操作。
另外，存储并锁存目标地址之前，还包括：基于刷新信号，获取统计的监测地址中的目标地址。
另外，在基于刷新信号对目标地址的相邻行执行刷新操作之后，还包括：基于刷新信号提供复位信号，复位信号用于指示对目标地址对应的计数器进行复位
另外，于每一刷新周期内，提供的统计信号的数量为多个。
另外，基于预设最小值和预设最大值定义的预设数值区间，生成位于预设数值区间中的随机数，并基于随机数和预设最小值的差值获取差值在预设数值区间中的占比值；基于占比值和刷新周期，确定并输出随机延迟时间；基于刷新信号的时间节点，延时随机延迟时间后提供统计信号。
本公开又一实施例还提供了一种存储器，基于上述实施例提供的监测电路获取目标字线地址。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的监测电路的结构示意图；
图2为本公开一实施例提供的处理模块的结构示意图；
图3为本公开一实施例提供的信号产生模块的结构示意图；
图4为本公开一实施例提供的时间处理单元的工作原理示意图；
图5为本公开一实施例提供的基于不同的统计信号进行监测地址计数的原理示意图；
图6为本公开另一实施例提供的刷新方法中各步骤对应的流程示意图。
具体实施方式
由背景技术可知，字线频繁开启会导致相邻存储区内的电荷丢失，可能导致存储区内存储的数据发生错误；对于上述问题，目前通常基于刷新周期为时间单位，对一个刷新周期内被开启次数最多的字线地址相邻的存储区进行补充刷新，从而避免存储的数据发生错误；然而，采用这种方式进行存储区的补充刷新中，统计字线地址被开启次数的时间固定，无法准确获取在刷新周期前期或中期被开启次数较多的字线地址，而在刷新周期的前期或中期被开启次数较多的字线地址也可能导致存储器内相邻存储区的数据发生错误。
本公开一实施例提供了一种监测电路，通过调节每个刷新周期内对字线地址的统计时间，使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前 期或中期被开启次数较多的字线地址被掩盖，从而提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的监测电路的结构示意图，图2为本实施例提供的处理模块的结构示意图，图3为本实施例提供的信号产生模块的结构示意图，图4为本实施例提供的时间处理单元的工作原理示意图，图5为本实施例提供的基于不同的统计信号进行监测地址计数的原理示意图，以下结合附图对本实施例提供的监测电路进行详细说明，具体如下：
参考图1，监测电路，包括：
采样模块101，被配置为，对初始地址采样以获取监测地址，初始地址为监测电路所在存储器中被开启的字线地址。
计数模块102，连接采样模块101，被配置为，若计数模块102中存在相同的监测地址，则将相同的监测地址对应的计数器的计数值加1，若计数模块102中不存在相同的监测地址，则新增监测地址对应的计数器，并将计数器的计数值置1。
处理模块103，连接计数模块102，被配置为，基于统计信号比较计数模块102中各监测地址对应的计数器的计数值，以获取目标地址，并基于刷新信号对目标地址的相邻行执行刷新操作，其中，统计信号于相邻的两个刷新信号的间隔时间内提供。
本实施例提供的监测电路中，处理模块103基于统计信号比较计数模块102中各监测地址所对应的计数值，从而获取并存储目标地址，其中，目标地址的相邻行为存储器需要执行补充刷新的地址，然后基于刷新信号对存储的目标地址的相邻行执行刷新操作；另外，通过将统计信号设置为于相邻刷新信号的间隔时间内提供，使得通过调节统计信号的提供时间可以调节刷新周期内统计被开启的字线地址的时间，从而使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前期或中期被开启次数较多的字线地址被掩盖，提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
需要说明的是，对于上述提及的“对存储的目标地址的相邻行执行刷新操作”，存储器可以直接对存储的地址的相邻行执行刷新操作，或处理模块103将存储的目标地址输出到存储器的某一寄存器中，存储器对于寄存器中存储的目标地址的相邻行统一执行刷新操作。具体地，对存储的多个目标地址的相邻行依次进行刷新，即先对一个目标地址的+1和-1行地址进行补充刷新，再根据目标地址对应的计数值的情况，判断是否对+2和-2等相邻行进行补充刷新，刷新完一个目标地址的相邻行，再对另外一个目标地址的相邻行进行刷新，一次完成刷新操作。
对于本实施例提供的采样模块101，在一些实施例中，采样模块101基于预设间隔采样以获取监测地址，其中，预设间隔设置为每出现x个初始地址，进行一次监测地址的采样，x为正整数，即存储器每开启x个字线地址，采样模块101进行一次监测地址的采样，通过为采样模块101设置采样概率，以降低采样模块101所需获取的字线地址，即通过抽样检测的方式降低监测电路的功耗。在一些实施例中，x为小于等于16的正整数；在一个具体的例子中，x可以设置为14、12、10、8、6、4或2等正整数。
对于本实施例提供的计数模块102中的计数器，计数器的容量基于刷新命令的接收间隔时间、采样的预设间隔和存储器中字线开启间隔时间设置；具体地，在DDR4的标准中，正常工作温度下，16G容量的存储器在1X刷新模式下，字线开启间隔时间tRC＝45ns，采样的预设间隔tREFC＝550ns，刷新命令的接收间隔时间tREFI＝7.8us；此时，在存储器的突发传输模式下9*tREFI下存储器可开启的字线地址的数量为9*(tREFI-tREFC)/tRC＝161，若计数器的容量为b，需保证2b＞161，即b最少为8，在这种示例下，计数器的容量设置为8比特；需要说明的是，本示例的数值举例，仅用于本领域技术人员理解计数模块102中计数器的容量设置方式，并不构成对本实施例的限定。
对于本实施例提供的处理模块103，参考图2，在一些实施例中，处理模块103，包括：比较单元201，连接计数模块102，被配置为，基于统计信号比较计数模块102中各监测地址对应的计数器的计数值，并将计数值最大的k个计数器所对应的监测地址作为目标地址锁存并传输至预存单元202，k为正整数；预存单元202被配置为，存储比较单元201传输的目标地址，并基于刷新信号，对目标地址的相邻行执行刷新操作；复位单元203，连接计数模块102，被配置为基于刷新信号提供复位信号，复位信号用于指示计数模块102对执行刷新操作的目标地址对应的计数器进行复位。由于复位信号仅复位执行刷新操作的目标地址，使得其他监测地址在下一刷新周期中可以持续被计数，从而监测持续且缓慢被开启的字线地址，进一步提高存储器补充刷新功能的准确性。
需要说明的是，本实施例中复位单元203以根据刷新信号提供复位信号为例进行举例说明，在其他实施例中，复位单元还可以被配置为基于统计信号提供复位信号，另外，在其他实施例中，复位信号还可以设置为，用于指示计数模块102复位所有计数器，此时若复位信号基于刷新信号提供，监测电路的字线地址统计时间为刷新信号至统计信号的时间间隔内；若复位信号基于刷新信号提供，监测电路的字线地址统计时间为相邻统计信号的时间间隔内。
在一些实施例中，比较单元201还被配置为，基于刷新信号比较计数模块102中各监测地址对应的计数器的计数值，并将计数值最大的m个计数器所对应的监测地址作为目标地址锁存并传输至预存单元202，m为正整数。通过刷新信号和统计信号的两次比较获取目标地址，从而获取整个刷新周期中被开启次数较多的字线地址，以及刷新周期的前期或中期被开启次数较多的字线地址，进一步提高存储器补充刷新功能的准确性。
具体地，在一些实施例中，m和k可以设置为相同整数，即存储器基于刷新信号和统计信号获取的监测地址的数量相同；在另一些实施例中，m和k可以设置为不通整数，即存储器基于刷新信号和统计信号获取的监测地址的数量不同。
在一些实施例中，于相邻的两个刷新信号的间隔时间内提供的统计信号的数量为多个，即通过设置多个统计信号，多次比较获取目标地址，从而获取刷新周期不同时间节点被开启次数较多的字线地址，进一步提高存储器补充刷新功能的准确性。
在一些实施例中，预存单元202还被配置为，比较计数模块102中目标地址对应的计数值，并对计数值最大的n个目标地址的相邻行执行刷新操作，n为小于等于(m+k)的正整数；基于前述的多种实施方案，预存单元202中存储的目标地址的数量为多个，通过对预存单元202中目标地址对应的计数值进行二次比较，以对计数值最大的n个目标地址执行刷新操作，以降低监测电路的驱动功耗。
另外，在一些实施例中，n设置为1，即处理模块103仅对计数值最大的目标地址的相邻行执行刷新操作，存储器对监测电路基于统计信号和/或刷新信号多次获取的目标地址中，被开启次数最多的目标地址的相邻行进行补充刷新，以降低监测电路的功耗。在一些实施例中，可以为目标地址设置标识符，基于刷新信号和统计信号获取的目标地址对应的标识符不同，通过为标识符设置相应优先级，优先刷新基于统计信号获取的目标地址，或者优先刷新基于刷新信号获取的目标地址。在一些实施例中，统计信号获取的目标地址与刷新信号获取的目标地址可以通过不同的刷新命令实现相邻行的刷新操作，在一个具体的例子中，刷新信号获取的目标地址，基于本次刷新命令实现相邻行的刷新操作，统计信号获取的目标地址，基于下一次刷新命令实现相邻行的刷新操作。
继续参考图1，在一些实施例中，监测电路还包括：信号产生模块104，被配置为，于每一刷新周期中的任意时间节点生成统计信号，刷新周期为相邻刷新信号的间隔时间。
在一些实施例中，参考图3，信号生成模块104，包括：随机产生单元301，被配置为，基于预设最小值和预设最大值定义的预设数值区间，生成位于预设数值区间中的随机数，并基于随机数和预设最小值的差值，获取差值在预设数值区间中的占比值；时间处理单元302，连接随机产生单元301，被配置为，基于占比值和刷新周期，确定并输出随机延迟时间；信号发送单元303，连接时间处理单元302，基于刷新信号的时间节点，延时随机延迟时间后提供统计信号。
在一个具体的例子中，参考图4，假设生成的预设数值区间为：基于预设最小值0和预设最大值10定义的预设数值区间(0,10)(预设最小值0对应的随机数和预设最大值10对应的随机数分别 对应于刷新间隔的两个刷新信号，由于统计信号的提供时间不与刷新信号重合，因此预设数值区间设置为开区间)，此时随机产生单元301可产生的随机数为1、2、3、4、5、6、7、8和9，当随机产生单元301产生的随机数为1时，预设最小值和随机数之间的差值为1，预设数值区间的长度为10，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即1/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线1的位置提供；当随机产生单元301产生的随机数为2时，预设最小值和随机数之间的差值为2，差值在预设数值区间中的长度占比为2/10，此时时间处理单元302获取的随机延迟时间即2/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线2的位置提供；当随机产生单元301产生的随机数为3时，预设最小值和随机数之间的差值为3，差值在预设数值区间中的长度占比为3/10，此时时间处理单元302获取的随机延迟时间即3/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线3的位置提供；当随机产生单元301产生的随机数为4时，预设最小值和随机数之间的差值为4，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即4/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线4的位置提供；当随机产生单元301产生的随机数为5时，预设最小值和随机数之间的差值为5，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即5/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线5的位置提供；当随机产生单元301产生的随机数为6时，预设最小值和随机数之间的差值为6，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即6/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线6的位置提供；当随机产生单元301产生的随机数为7时，预设最小值和随机数之间的差值为7，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即7/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线7的位置提供；当随机产生单元301产生的随机数为8时，预设最小值和随机数之间的差值为8，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即8/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线8的位置提供；当随机产生单元301产生的随机数为9时，预设最小值和随机数之间的差值为9，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即9/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线9的位置提供。
需要说明的是，上述举例说明，仅用于本领域计数人员理解信号生成模块104生成统计信号的工作原理，具体预设数值区间的数值设置并不构成对本实施例的限定；在具体的应用中，本领域计数人员可以通过设置预设数值区间的大小，调节统计信号所提供的时间节点，其中，预设数值区间越大，相邻统计信号可提供的时间节点越密集；预设数值区间越小，驱动信号生成模块104所需的功耗越小。
参考图5，图5所示即计数模块102对监测地址A、监测地址B、监测地址C、监测地址D和监测地址E的计数示意，若统计时间于t1所示虚线位置提供，各监测地址对应的计数值的大小关系为：B＞C＞A＞D＞E；若统计时间于t2所示虚线位置提供，各监测地址对应的计数值的大小关系为：C＞B＞A＞D＞E；若统计时间于t3所示虚线位置提供，各监测地址对应的计数值的大小关系为：B＞A＞C＞D＞E；若统计时间于t4所示虚线位置提供，各监测地址对应的计数值的大小关系为：A＞B＞C＞D＞E；即调节统计时间的提供时间，可以获取刷新周期中不同时间段内被开启次数最多的字线地址。
继续参考图5，假设于两个刷新信号的间隔时间内提供的统计信号为2个，且处理模块103基于计数模块102的计数值比较仅获取计数值最大的监测地址作为目标地址，此时，若统计信号基于t1和t2提供，此时处理单元103中存储的目标地址为B和C；若统计信号基于t1和t3提供，此时处理单元103中存储的目标地址为B；若统计信号基于t1和t4提供，此时处理单元103中存储的目标地址为A和B；若统计信号基于t2和t3提供，此时处理单元103中存储的目标地址为B和C；若统计信号基于t2和t4提供，此时处理单元103中存储的目标地址为A和C；若统计信号基于t3和t4提供，此时处理单元103中存储的目标地址为A和B。
需要说明的是，本领域技术人员可以基于图5的示例以及上述论述，合理推导出刷新信号的间隔时间内提供多个统计信号时，处理模块103所存储的不同的目标地址的方案，皆属于本公开的保护范围。
另外，在一些实施例中，随机产生单元301基于刷新信号为每个统计信号产生一个随机数，即随机产生单元301基于每个刷新信号重新产生随机数，通过刷新信号重新产生随机数，即调节不同刷新周期内统计信号提供的时间节点，使得不同刷新周期中统计信号提供的时间节点不同，通过增强目标地址获取的随机性，从而进一步提高存储器补充刷新功能的准确性。
本实施例提供的监测电路中，处理模块103基于统计信号比较计数模块102中各监测地址所对应的计数值，从而获取并存储目标地址，其中，目标地址为存储器需要执行补充刷新的地址，然后基于刷新信号对存储的目标地址执行刷新操作；另外，通过将统计信号设置为于相邻刷新信号的间隔时间内提供，使得通过调节统计信号的提供时间可以调节刷新周期内统计被开启的字线地址的时间，从而使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前期或中期被开启次数较多的字线地址被掩盖，提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
需要说明的是，上述实施例所提供的监测电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的监测电路实施例。
本公开另一实施例提供一种刷新方法，应用于上述实施例提供的监测电路，通过调节每个刷新周期内对字线地址的统计时间，使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前期或中期被开启次数较多的字线地址被掩盖，从而提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
图6为本实施例提供的刷新方法中各步骤对应的流程示意图，以下结合附图对本实施例提供的刷新方法进行详细说明，具体如下：
参考图6，刷新方法，包括：
步骤401，于每一刷新周期内，采样监测地址，并统计监测地址的数量。
具体地，基于初始地址采样获取监测地址，初始地址为存储器中开启的字线地址。
在一些实施例中，基于预设间隔采样以获取监测地址，其中，预设间隔设置为每出现x个初始地址，进行一次监测地址的采样，x为正整数，即存储器每开启x个字线地址，采样模块101进行一次监测地址的采样，通过为采样模块101设置采样概率，以降低采样模块101所需获取的字线地址，即通过抽样检测的方式降低监测电路的功耗。在一些实施例中，x为小于等于16的正整数；在一个具体的例子中，x可以设置为14、12、10、8、6、4或2等正整数。
步骤402，基于统计信号，获取统计的监测地址中的目标地址，目标地址为计数值最大的k个计数器所述对应的监测地址。
对于的计数器，计数器的容量基于刷新命令的接收间隔时间、采样的预设间隔和存储器中字线开启间隔时间设置；具体地，在DDR4的标准中，正常工作温度下，16G容量的存储器在1X刷新模式下，字线开启间隔时间tRC＝45ns，采样的预设间隔tREFC＝550ns，刷新命令的接收间隔时间tREFI＝7.8us；此时，在存储器的突发传输模式下9*tREFI下存储器可开启的字线地址的数量为9*(tREFI-tREFC)/tRC＝161，若计数器的容量为b，需保证2b＞161，即b最少为8，在这种示例下，计数器的容量设置为8比特；需要说明的是，本示例的数值举例，仅用于本领域技术人员理解计数模块102中计数器的容量设置方式，并不构成对本实施例的限定。
对于统计信号，具体地，于每一刷新周期中的任意时间节点生成统计信号，刷新周期为相邻刷新信号的间隔时间。
更具体地，在一些实施例中，获取统计信号的方法包括：基于预设最小值和预设最大值定义的预设数值区间，生成位于预设数值区间中的随机数，并基于随机数和预设最小值的差值，获取差值在预设数值区间中的占比值，基于占比值和刷新周期，确定并输出随机延迟时间，基于刷新信号的时间节点，延时随机延迟时间后提供统计信号。
在一个具体的例子中，参考图4，假设生成的预设数值区间为：基于预设最小值0和预设最大值10定义的预设数值区间(0,10)(预设最小值0对应的随机数和预设最大值10对应的随机数分别 对应于刷新间隔的两个刷新信号，由于统计信号的提供时间不与刷新信号重合，因此预设数值区间设置为开区间)，此时随机产生单元301可产生的随机数为1、2、3、4、5、6、7、8和9，当随机产生单元301产生的随机数为1时，预设最小值和随机数之间的差值为1，预设数值区间的长度为10，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即1/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线1的位置提供；当随机产生单元301产生的随机数为2时，预设最小值和随机数之间的差值为2，差值在预设数值区间中的长度占比为2/10，此时时间处理单元302获取的随机延迟时间即2/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线2的位置提供；当随机产生单元301产生的随机数为3时，预设最小值和随机数之间的差值为3，差值在预设数值区间中的长度占比为3/10，此时时间处理单元302获取的随机延迟时间即3/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线3的位置提供；当随机产生单元301产生的随机数为4时，预设最小值和随机数之间的差值为4，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即4/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线4的位置提供；当随机产生单元301产生的随机数为5时，预设最小值和随机数之间的差值为5，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即5/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线5的位置提供；当随机产生单元301产生的随机数为6时，预设最小值和随机数之间的差值为6，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即6/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线6的位置提供；当随机产生单元301产生的随机数为7时，预设最小值和随机数之间的差值为7，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即7/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线7的位置提供；当随机产生单元301产生的随机数为8时，预设最小值和随机数之间的差值为8，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即8/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线8的位置提供；当随机产生单元301产生的随机数为9时，预设最小值和随机数之间的差值为9，差值在预设数值区间中的长度占比为1/10，此时时间处理单元302获取的随机延迟时间即9/10倍的刷新周期，信号发生单元303提供的统计信号于图4所示的坐标轴虚线9的位置提供。
参考图5，图5所示即计数模块102对监测地址A、监测地址B、监测地址C、监测地址D和监测地址E的计数示意，若统计时间于t1所示虚线位置提供，各监测地址对应的计数值的大小关系为：B＞C＞A＞D＞E；若统计时间于t2所示虚线位置提供，各监测地址对应的计数值的大小关系为：C＞B＞A＞D＞E；若统计时间于t3所示虚线位置提供，各监测地址对应的计数值的大小关系为：B＞A＞C＞D＞E；若统计时间于t4所示虚线位置提供，各监测地址对应的计数值的大小关系为：A＞B＞C＞D＞E；即调节统计时间的提供时间，可以获取刷新周期中不同时间段内被开启次数最多的字线地址。
另外，在一些实施例中，基于刷新信号为每个统计信号产生一个随机数，即基于每个刷新信号重新产生随机数，通过刷新信号重新产生随机数，即调节不同刷新周期内统计信号提供的时间节点，使得不同刷新周期中统计信号提供的时间节点不同，进一步提高存储器补充刷新功能的准确性。
另外，在一些实施例中，于每一刷新周期内，提供的统计信号的数量为多个，即通过设置多个统计信号，多次比较获取目标地址，从而获取刷新周期不同时间节点被开启次数较多的字线地址，进一步提高存储器补充刷新功能的准确性。
步骤404，存储并锁存目标地址，并基于刷新信号对目标地址执行刷新操作。
需要说明的是，对于上述提及的“对存储的目标地址的相邻行执行刷新操作”，存储器可以直接对存储的地址的相邻行执行刷新操作，或处理模块103将存储的目标地址输出到存储器的某一寄存器中，存储器对于寄存器中存储的目标地址的相邻行统一执行刷新操作。具体地，对存储的多个目标地址的相邻行依次进行刷新，即先对一个目标地址的+1和-1行地址进行补充刷新，再根据目标地址对应的计数值的情况，判断是否对+2和-2等相邻行进行补充刷新，刷新完一个目标地址的相邻行，再对另外一个目标地址的相邻行进行刷新，依次完成刷新操作。
步骤405，基于刷新信号提供复位信号，复位信号用于指示对执行刷新操作的目标地址对应 的计数器进行复位。由于复位信号仅复位执行刷新操作的目标地址，使得其他监测地址在下一刷新周期中可以持续被计数，从而监测被开启次数持续且缓慢增长的字线地址，进一步提高存储器补充刷新功能的准确性。
在一些实施例中，在执行步骤404之前，还包括：步骤403，基于刷新信号，获取统计的监测地址中的目标地址。
具体地，基于刷新信号比较各监测地址对应的计数器的计数值，并将计数值最大的m个计数器所对应的监测地址作为目标地址，通过刷新信号和统计信号的两次比较获取目标地址，从而获取整个刷新周期中被开启次数较多的字线地址，以及刷新周期的前期或中期被开启次数较多的字线地址，进一步提高存储器补充刷新功能的准确性。
在一些实施例中，m和k可以设置为相同整数，即存储器基于刷新信号和统计信号获取的监测地址的数量相同；在另一些实施例中，m和k可以设置为不同整数，即存储器基于刷新信号和统计信号获取的监测地址的数量不同。
对于步骤404，在一些实施例中，步骤404还包括：比较目标地址对应的计数值，并对计数值最大的n个目标地址执行刷新操作，n为小于等于(m+k)的正整数；基于前述的多种实施方案，存储的目标地址的数量为多个，通过对目标地址对应的计数值进行二次比较，以对计数值最大的n个目标地址执行刷新操作，以降低监测电路的驱动功耗。
在一些实施例中，n设置为1，即仅对计数值最大的目标地址的相邻行执行刷新操作，存储器对监测电路基于统计信号和/或刷新信号多次获取的目标地址中，被开启次数最多的目标地址的相邻行进行补充刷新，以降低监测电路的功耗。
在一些实施例中，可以为目标地址设置标识符，基于刷新信号和统计信号获取的目标地址对应的标识符不同，通过为标识符设置相应优先级，优先刷新基于统计信号获取的目标地址，或者优先刷新基于刷新信号获取的目标地址。
在一些实施例中，统计信号获取的目标地址与刷新信号获取的目标地址可以通过不同的刷新命令实现相邻行的刷新操作，在一个具体的例子中，刷新信号获取的目标地址，基于本次刷新命令实现相邻行的刷新操作，统计信号获取的目标地址，基于下一次刷新命令实现相邻行的刷新操作。
本实施例提供的刷新方法，基于统计信号比较各监测地址所对应的计数值，从而获取并存储目标地址，其中，目标地址的相邻行为存储器需要执行补充刷新的地址，然后基于刷新信号对存储的目标地址的相邻行执行刷新操作；另外，通过将统计信号设置为于相邻所述刷新信号的间隔时间内提供，使得通过调节统计信号的提供时间可以调节刷新周期内统计被开启的字线地址的时间，从而使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前期或中期被开启次数较多的字线地址被掩盖，提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
需要说明的是，上述实施例所提供的刷新方法中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的刷新方法实施例。
本公开又一实施例提供一种存储器，基于上述实施例提供的监测电路获取目标字线地址，通过调节每个刷新周期内对字线地址的统计时间，使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前期或中期被开启次数较多的字线地址被掩盖，从而提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
具体地，对于监测电路，处理模块基于统计信号比较计数模块中各监测地址所对应的计数值，从而获取并存储目标地址，其中，目标地址的相邻行为存储器需要执行补充刷新的地址，然后基于刷新信号对存储的目标地址的相邻行执行刷新操作；另外，通过将统计信号设置为于相邻刷新信号的间隔时间内提供，使得通过调节统计信号的提供时间可以调节刷新周期内统计被开启的字线地址的时间，从而使得在一些刷新周期中，统计并补充刷新在刷新周期的前期或中期被开启次数较多的字线地址，防止前期或中期被开启次数较多的字线地址被掩盖，提高存储器对字线地址监测的灵活性和补充刷新功能的准确性。
在一些实施例中，存储器可以是基于半导体装置或组件的存储单元或装置。例如，存储器装置可以是易失性存储器，例如动态随机存取存储器DRAM、同步动态随机存取存储器SDRAM、双倍数据速率同步动态随机存取存储器DDR SDRAM、低功率双倍数据速率同步动态随机存取存储器LPDDR SDRAM、图形双倍数据速率同步动态随机存取存储器GDDR SDRAM、双倍数据速率类型双同步动态随机存取存储器DDR2SDRAM、双倍数据速率类型三同步动态随机存取存储器DDR3SDRAM、双倍数据速率第四代同步动态随机存取存储器DDR4SDRAM、晶闸管随机存取存储器TRAM等；或者可以是非易失性存储器，例如相变随机存取存储器PRAM、磁性随机存取存储器MRAM、电阻式随机存取存储器RRAM等。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (16)

  1. 一种监测电路，包括：
    采样模块，被配置为，对初始地址采样以获取监测地址，所述初始地址为所述监测电路所在存储器中被开启的字线地址；
    计数模块，连接所述采样模块，被配置为，若所述计数模块中存在相同的所述监测地址，则将相同的所述监测地址对应的计数器的计数值加1，若所述计数模块中不存在相同的所述监测地址，则新增所述监测地址对应的计数器，并将所述计数器的计数值置1；
    处理模块，连接所述计数模块，被配置为，基于统计信号比较所述计数模块中各所述监测地址对应的计数器的计数值，以获取目标地址，并基于刷新信号对所述目标地址的相邻行执行刷新操作；
    其中，所述统计信号于相邻的两个所述刷新信号的间隔时间内提供。
  2. 根据权利要求1所述的监测电路，其中，所述处理模块，包括：
    比较单元，连接所述计数模块，被配置为，基于所述统计信号比较所述计数模块中各所述监测地址对应的计数器的计数值，并将计数值最大的k个计数器所对应的所述监测地址作为所述目标地址锁存并传输至预存单元，所述k为正整数；
    所述预存单元被配置为，存储所述比较单元传输的所述目标地址，并基于所述刷新信号，对所述目标地址的相邻行执行刷新操作；
    复位单元，连接所述计数模块，被配置为，基于所述刷新信号提供复位信号，所述复位信号用于指示所述计数模块对执行刷新操作的所述目标地址对应的所述计数器进行复位。
  3. 根据权利要求2所述的监测电路，其中，所述比较单元还被配置为，基于所述刷新信号比较所述计数模块中各所述监测地址对应的计数器的计数值，并将计数值最大的m个计数器所对应的所述监测地址作为所述目标地址锁存并传输至所述预存单元，所述m为正整数。
  4. 根据权利要求2或3所述的监测电路，其中，所述对所述目标地址的相邻行执行刷新操作，包括：比较所述计数模块中所述目标地址对应的计数值，并对计数值最大的n个的所述目标地址的相邻行执行刷新操作，所述n为小于等于(m+k)的正整数。
  5. 根据权利要求1所述的监测电路，其中，于相邻的两个所述刷新信号的间隔时间内提供的所述统计信号的数量为多个。
  6. 根据权利要求1或5所述的监测电路，其中，还包括：信号产生模块，被配置为，于每一刷新周期中的任意时间节点生成所述统计信号，所述刷新周期为相邻所述刷新信号的间隔时间。
  7. 根据权利要求6所述的监测电路，其中，所述信号产生模块，包括：
    随机产生单元，被配置为，基于预设最小值和预设最大值定义的预设数值区间，生成位于所述预设数值区间中的随机数，并基于所述随机数和所述预设最小值的差值获取所述差值在所述预设数值区间中的占比值；
    时间处理单元，连接所述随机产生单元，被配置为，基于所述占比值和所述刷新周期，确定并输出随机延迟时间；
    信号产生单元，连接所述时间处理单元，基于所述刷新信号的时间节点，延时所述随机延迟时间后提供所述统计信号。
  8. 根据权利要求7所述的监测电路，其中，所述随机产生单元基于所述刷新信号为每个所述统计信号产生一个所述随机数。
  9. 根据权利要求1所述的监测电路，其中，所述采样模块基于预设间隔采样以获取所述监测地址，其中，所述预设间隔设置为每出现x个初始地址，进行一次所述监测地址的采样，所述x为正整数。
  10. 根据权利要求9所述的监测电路，其中，所述x为小于等于16的正整数。
  11. 一种刷新方法，应用于权利要求1～10任一项所述的监测电路，包括：
    于每一刷新周期内，采样监测地址，并统计所述监测地址的数量；
    基于统计信号，获取统计的所述监测地址中的目标地址，所述目标地址为计数值最大的k个计数器所对应的所述监测地址；
    存储并锁存所述目标地址，并基于刷新信号对所述目标地址的相邻行执行刷新操作。
  12. 根据权利要求11所述的刷新方法，其中，所述存储并锁存所述目标地址之前，还包括：基于所述刷新信号，获取统计的所述监测地址中的所述目标地址。
  13. 根据权利要求11所述的刷新方法，其中，在所述基于刷新信号对所述目标地址的相邻行执行刷新操作之后，还包括：基于所述刷新信号提供复位信号，所述复位信号用于指示对所述目标地址对应的所述计数器进行复位。
  14. 根据权利要求11所述的刷新方法，其中，于每一刷新周期内，提供的所述统计信号的数量为多个。
  15. 根据权利要求11所述的刷新方法，其中，包括：
    基于预设最小值和预设最大值定义的预设数值区间，生成位于所述预设数值区间中的随机数，并基于所述随机数和所述预设最小值的差值获取所述差值在所述预设数值区间中的占比值；
    基于所述占比值和所述刷新周期，确定并输出随机延迟时间；
    基于所述刷新信号的时间节点，延时所述随机延迟时间后提供所述统计信号。
  16. 一种存储器，基于权利要求1～10任一项所述的监测电路获取目标字线地址。
PCT/CN2022/118567 2022-08-30 2022-09-13 监测电路、刷新方法及存储器 WO2024045219A1 (zh)

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CN114627940A (zh) * 2020-12-14 2022-06-14 爱思开海力士有限公司 包括执行目标刷新的存储器件的存储系统
CN114627922A (zh) * 2020-12-10 2022-06-14 爱思开海力士有限公司 半导体存储器装置和包括其的存储器系统

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