WO2024041437A1 - 一种差分锁存器电路、开关驱动器以及数模转换电路 - Google Patents

一种差分锁存器电路、开关驱动器以及数模转换电路 Download PDF

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Publication number
WO2024041437A1
WO2024041437A1 PCT/CN2023/113430 CN2023113430W WO2024041437A1 WO 2024041437 A1 WO2024041437 A1 WO 2024041437A1 CN 2023113430 W CN2023113430 W CN 2023113430W WO 2024041437 A1 WO2024041437 A1 WO 2024041437A1
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Prior art keywords
differential
circuit
pmos
pmos tube
switch driver
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PCT/CN2023/113430
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English (en)
French (fr)
Inventor
罗豪
朱文涛
刁玉梅
朱海鹏
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深圳市中兴微电子技术有限公司
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Publication of WO2024041437A1 publication Critical patent/WO2024041437A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit design. Specifically, they relate to a differential latch circuit, a switch driver and a digital-to-analog conversion circuit.
  • FIG. 1 is a system block diagram of a Digital to Analog Converter (DAC) in related technology.
  • the DAC includes a data link (Data Path), a clock link (CLK Path) and a digital-to-analog converter core circuit (DAC Core).
  • the data link includes interface circuit (Interface), digital data link (Digital Data Path), decoder (Decoder), serializer (Serializer) and switch driver (Switch Driver).
  • the clock link includes a clock receiver (Clock Receiver), a delay locked loop (Delay Locked Loop, DLL), a frequency divider (Divider) and some clock drivers, etc.
  • the core circuit of the digital-to-analog converter includes multiple digital-to-analog converters Core unit (DAC Core Slices).
  • DAC Core Slices the design of the switch driver in the data link is crucial, affecting multiple indicators such as linearity, power consumption, and noise.
  • the input digital signal is first received and processed through the interface circuit and digital data link.
  • the main function of the decoder is to complete the DAC segmentation encoding. Specifically, the high bits of the DAC generally use the thermometer code, and the low bits generally use the thermometer code. Binary encoding, in addition, the decoder can apply some algorithms to the data, such as: Dynamic Element Matching (DEM), dither and rotation, etc. Since the digital data link and decoder are digital P&R modules, it is impossible to achieve high data rates, so each bit of DAC data in these digital modules is generally divided into multi-phase transmission.
  • the main function of the serializer is to convert multi-phase data into single-phase or less-phase data.
  • the main function of the switch driver is to synchronize each bit of data, increase driving capability, reduce inter-code interference, etc.
  • the switch driver may also need to adjust the data cross point (that is, the crossing position of the rising edge and falling edge of the differential output data) and adjust the data high and low levels, etc. These adjustments will have a great impact Linearity, noise and other performance of digital-to-analog converters using this switch driver.
  • Figure 2 is a traditional switch driver structure in the related art. It uses the rising edge of the clock for data sampling. In order to achieve better data synchronization, a three-level latch (Latch) is used for step-by-step synchronization. The upper two channels are used for real signal transmission, and the lower two channels are added to transfer Dummy data. This is to reduce the impact of signal-related current on DAC performance [1]. At each data sampling point, if the real data is not flipped, the Dummy data is flipped; if the real data is flipped, the Dummy data is not flipped.
  • Latch three-level latch
  • 2.Latch can also be replaced by a flip-flop (DFF), or by a multiplexer (MUX) with both data combining and synchronization functions, or some other sequential logic.
  • DFF flip-flop
  • MUX multiplexer
  • the design may also include some combinational logic.
  • MUX can be combinational logic MUX, OR/NOR or AND/NAND, combinational logic MUX plus clock-triggered Latch or DFF, or other types of clock-triggered MUX. Data combining and synchronization are completed at the same time.
  • the input data can be conventional data as shown in Figure 2, or Return-to-Zero data or Return-to-One data.
  • the data types are different, and the corresponding sequential logic circuits such as Latch, DFF, and MUX may be different, and the combinational logic may also be different.
  • Figure 3 is a traditional multi-mode compatible switch driver structure. It features compatibility between regular mode and mixed mode. In the mixing mode, data changes occur on both the rising and falling edges of the clock. The data corresponding to the falling edge is the inversion of the data corresponding to the rising edge, which is equivalent to the mixing effect of the real signal and the clock signal. Finally, a DAC output with Fclk is the band-pass transfer function centered at the center, while the normal mode is a low-pass transfer function, which is helpful for applications with lower bandwidth in high, medium and high frequencies.
  • FIG. 4 is a schematic diagram of a traditional differential latch structure in the related art. It adopts a CMOS architecture. The output high and low levels are rail-to-rail. The front stage is a clock level triggered Latch, and the rear stage is a Inverter (Inverter), used to increase Add Latch driving capabilities.
  • Inverter Inverter
  • the inverter of the subsequent stage can also be a buffer.
  • the PMOS source end of the inverter in the subsequent stage can be connected not to the power supply but to the output of a level shift circuit. In this way, the high level output by the inverter is not the power supply but a specially designed voltage.
  • the NMOS source end of the inverter can be connected not to ground but to the output of a level shift circuit, so that the low level output by the inverter is not ground but a specially designed voltage.
  • the power ground of the pre-stage Latch can also be connected to the output of the level shift circuit.
  • the width-to-length ratio of the post-stage inverter PMOS and NMOS can be deliberately designed to be asymmetrical to adjust the intersection point of the inverter output data.
  • the width-to-length ratio of the front-end Latch PMOS and NMOS can also be deliberately designed to be asymmetrical.
  • DFF and MUX with synchronization function also has the above variations
  • the design of other sequential logic circuits also has the above variations
  • the design of combinational logic circuits also has the above variations.
  • Embodiments of the present disclosure provide a differential latch circuit, a switch driver and a digital-to-analog conversion circuit.
  • a differential latch circuit including a first-stage differential latch circuit, a second-stage differential inverter circuit and a low-level shift circuit connected in sequence, wherein the first-stage differential latch circuit
  • the pull-up end of the differential positive terminal of the two-stage differential inverter circuit includes a first PMOS tube and a second PMOS tube.
  • the gate of the first PMOS tube is connected to the gate of the second PMOS tube; the first PMOS tube
  • the source of the first PMOS transistor is connected to the power supply voltage; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the gate of the first PMOS transistor and the gate of the second PMOS transistor are also connected to each other respectively.
  • the data input terminal of the differential positive terminal of the second-stage differential inverter circuit; the pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit includes a third PMOS tube and a first NMOS tube, and the drain of the third PMOS tube
  • the gate electrode of the third PMOS transistor is connected to the source electrode of the first NMOS transistor and the output terminal of a level shift circuit; the gate electrode of the third PMOS transistor is connected to the differential positive terminal of the second stage differential inverter circuit.
  • Data input terminal, the source of the third PMOS tube is connected to the output terminal of the pull-down terminal of the differential negative terminal of the second stage differential inverter circuit; the drain of the first NMOS tube is connected to the drain of the second PMOS tube.
  • the gate of the first NMOS tube is connected to the data input terminal of the differential positive terminal of the second-stage differential inverter circuit; the differential negative terminal of the first-stage differential latch circuit is connected to the first-stage differential
  • the circuit structure of the differential positive terminal of the latch circuit is relatively symmetrical.
  • a switch driver includes a plurality of switch driver units, wherein each switch driver unit includes: multiple data transmission links, and each data transmission link includes the above-mentioned Differential latch circuit in embodiment.
  • a digital-to-analog conversion circuit including the switch driver in the above embodiment and a digital-to-analog conversion core circuit connected to the output end of the switch driver.
  • Figure 1 is a system structural block diagram of a digital-to-analog converter in related technology
  • Figure 2 is a schematic diagram of a traditional switch driver structure in the related art
  • Figure 3 is a schematic diagram of a traditional multi-mode compatible switch driver structure
  • Figure 4 is a schematic diagram of a traditional differential latch structure in the related art
  • Figure 5(a) is a schematic diagram of a differential latch circuit structure according to an embodiment of the present disclosure
  • Figure 5(b) is a schematic diagram of another connection method of the fourth PMOS transistor in the second-stage differential inverter circuit according to an embodiment of the present disclosure
  • Figure 5(c) shows the fourth PMOS transistor in the second-stage differential inverter circuit according to an embodiment of the present disclosure. Another schematic diagram of connection method
  • Figure 6 is a schematic structural diagram of a differential latch circuit according to another embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of a switch driver according to an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of a switch driver according to another embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of a multi-mode resistive digital-to-analog conversion circuit according to an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of a multi-mode resistive digital-to-analog conversion circuit according to another embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of a multi-mode current steering type digital-to-analog conversion circuit according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a multi-mode current steering type digital-to-analog conversion circuit according to another embodiment of the present disclosure.
  • FIG. 5(a) is a schematic structural diagram of a differential latch circuit according to an embodiment of the present disclosure.
  • the differential latch circuit includes a first-stage differential latch circuit I, a second-stage differential inverter circuit II and a low-level shift circuit.
  • the pull-up end of the differential positive terminal of the second-stage differential inverter circuit II includes a first PMOS transistor M9 and a second PMOS transistor M10.
  • the gate of the first PMOS transistor M9 is connected to the gate of the second PMOS transistor M10.
  • the source of the first PMOS transistor M9 is connected to the power supply voltage;
  • the drain of the first PMOS transistor M9 is connected to the source of the second PMOS transistor M10;
  • the gates of the second PMOS tube M10 are also respectively connected to the data input terminals of the differential positive terminals of the second-stage differential inverter circuit;
  • the pull-down terminals of the differential positive terminals of the second-stage differential inverter circuit include a third PMOS tube M15 and the first NMOS transistor M11, the drain of the third PMOS transistor M15 is connected to the source of the first NMOS transistor M11, and are connected together to the output end of a level shift circuit;
  • the drain of the first NMOS transistor M11 is connected to the drain of the second PMOS transistor M10, and the gate of the first NMOS transistor M11 is connected to the data input end of the differential positive end of the second-stage differential inverter circuit. ;
  • the circuit structures of the differential negative terminal of the first-stage differential latch circuit and the differential positive terminal of the first-stage differential latch circuit are symmetrical.
  • the differential positive terminal of the second stage differential inverter circuit also includes: a fourth PMOS transistor M17, the source of the fourth PMOS transistor M17 is connected to the power supply voltage, so The gate of the fourth PMOS transistor M17 is connected to the data input terminal of the differential negative terminal of the second stage differential inverter circuit, and the drain of the fourth PMOS transistor M17 is connected to the first PMOS transistor M9 and the second stage differential inverter circuit.
  • the first series node between the PMOS transistors M10 is used to adjust the voltage of the series node.
  • the fourth PMOS transistor may be connected to the second-stage differential inverter circuit in other ways.
  • the source of the fourth PMOS transistor M17 is connected to the fifth PMOS transistor located at the differential negative terminal of the second-stage differential inverter circuit and corresponding to the fourth PMOS transistor M17.
  • the source of M18; the gate of the fourth PMOS tube M17 is connected to the data input terminal of the differential negative terminal of the second stage differential inverter circuit, and the drain of the fourth PMOS tube M17 is connected to the first PMOS tube.
  • the fourth PMOS transistor may be connected to the second-stage differential inverter circuit in other ways. As shown in Figure 5(c), the source of the fourth PMOS transistor M17 is connected to the power supply voltage, and the gate of the fourth PMOS transistor M17 is connected to the data of the differential positive terminal of the second stage differential inverter circuit. At the output end, the drain of the fourth PMOS transistor M17 is connected to the first series node between the first PMOS transistor M9 and the second PMOS transistor M10.
  • the first series node is located between the drain of the first PMOS transistor M9 and the source of the second PMOS transistor M10.
  • FIG. 6 is a schematic structural diagram of a differential latch circuit according to another embodiment of the present disclosure.
  • the pull-up end of the differential positive terminal of the second-stage differential inverter circuit II includes a first PMOS transistor M9 and a second PMOS transistor M10.
  • the gate of the first PMOS transistor M9 is connected to the third PMOS transistor M9.
  • the gate of M9 and the gate of the second PMOS tube M10 are also respectively connected to the data input terminal of the differential positive terminal of the second stage differential inverter circuit; the pull-down terminal of the differential positive terminal of the second stage differential inverter circuit It includes a third PMOS transistor M15 and a first NMOS transistor M11.
  • the drain of the third PMOS transistor M15 is connected to the source of the first NMOS transistor M11 and together is connected to the output end of a level shift circuit;
  • the gate of the third PMOS transistor M15 is connected to the data input terminal of the differential positive terminal of the second-stage differential inverter circuit, and the source of the third PMOS transistor M15 is connected to the differential terminal of the second-stage differential inverter circuit.
  • the output end of the negative pull-down end; the drain of the first NMOS transistor M11 is connected to the drain of the second PMOS transistor M10, and the gate of the first NMOS transistor M11 is connected to the second-stage differential inverter circuit.
  • the data input terminal of the differential positive terminal in this embodiment, in the differential positive terminal of the second-stage differential inverter circuit, the first series node between the first PMOS tube M9 and the second PMOS tube M10 and The second series node located in the differential negative terminal of the second stage differential inverter circuit and corresponding to the first series node is short-circuited; the first stage The circuit structure of the differential negative terminal of the differential latch circuit is symmetrical to the differential positive terminal of the first-stage differential latch circuit.
  • the width-to-length ratio of the PMOS tube terminal and the NMOS tube terminal in the first-stage differential latch circuit is set to mismatch, and the intersection point of the differential latch circuit output is not located at the Between the PMOS tube end and the NMOS tube end.
  • the channel length of the equivalent PMOS tube can be increased and the width-to-length ratio of the equivalent PMOS tube can be reduced.
  • the pull-down end uses a PMOS tube and an NMOS tube. Structure, lowering the output cross point of the second-stage differential inverter can improve the linearity problem caused by the slow rising edge of the inverter output, and solve the reliability problem and the problem of inter-code interference. Ability to increase flexibility in adjusting output data intersection points.
  • FIG. 7 is a schematic structural diagram of a switch driver according to an embodiment of the present disclosure.
  • the switch driver includes multiple switch driver units, where each switch driver unit includes: multiple data transmission links, and each data transmission link includes the differential latch circuit in the above embodiment.
  • the multi-channel data transmission link includes a real data transmission link used to transmit real data and a Dummy data transmission link used to transmit Dummy data.
  • FIG. 8 is a schematic structural diagram of a switch driver according to another embodiment of the present disclosure.
  • the switch driver also includes: a plurality of XOR logic units, and the first input end of each XOR logic unit is connected to each data transmission link.
  • the output end of the differential latch circuit, the second input end of the XOR logic unit is connected to the clock input end; a plurality of data selectors, the first input end of each of the data selectors is connected to each of the The second input terminal of each data selector is respectively connected to the output terminal of the XOR logic unit.
  • FIG. 9 is a schematic structural diagram of a multi-mode resistive digital-to-analog conversion circuit according to an embodiment of the present disclosure.
  • the multi-mode resistive digital-to-analog conversion circuit includes the switch driver of Figure 7 and a digital-to-analog conversion core circuit connected to the output end of the switch driver.
  • the digital-to-analog conversion core circuit includes a plurality of digital-to-analog converter core units, each of the digital-to-analog converter core units includes: an inverter INV, an input terminal of the inverter an output end of the real data transmission link connected to the switch driver unit; a unit resistor with a first end connected to the output end of the inverter and a second end of the unit resistor connected to a load resistor connected; a first Dummy load, the first Dummy load is connected to the output end of the Dummy data transmission link of the switch driver unit.
  • the switch driver in the multi-mode resistive digital-to-analog conversion circuit is the switch driver shown in FIG. 8 .
  • FIG. 11 is a schematic structural diagram of a multi-mode current steering type digital-to-analog conversion circuit according to an embodiment of the present disclosure.
  • the multi-mode current steering type digital-to-analog conversion circuit includes the switch driver of Figure 7 and a digital-to-analog conversion core circuit connected to the output end of the switch driver, wherein the digital-to-analog conversion core circuit includes A plurality of digital-to-analog converter core units, each of which includes: a sixth PMOS transistor, the gate of the sixth PMOS transistor is connected to the output of the real data transmission link of the driver unit terminal, the drain of the sixth PMOS tube is connected to the load resistor and the output terminal of the digital-to-analog conversion core circuit, the source of the sixth PMOS tube is connected to the output terminal of the current source; the second Dummy load, the second Dummy A load is connected to the output of the Dummy data transmission link of the switch driver unit.
  • the switch driver in the multi-mode resistive digital-to-analog conversion circuit is the switch driver shown in FIG. 8 .
  • the embodiments of the present disclosure provide a A Latch circuit with flexible output data cross point adjustment and high level shift circuit compatibility (in this embodiment, the DFF and MUX circuits can also be designed similarly) and a high linearity switch driver circuit using the Latch circuit, and High linearity digital-to-analog converter circuit using this switch driver circuit.
  • the operations of the embodiments of the present disclosure include:
  • the width-to-length ratio of the PMOS terminal and the NMOS terminal of the first stage differential latch circuit of the Latch is deliberately designed to mismatch, causing the cross point of the Latch output to be higher and the inverter output cross point to be lower;
  • the two PMOS at the pull-up end of the second-stage differential inverter circuit of the Latch are connected in series to increase the equivalent PMOS channel length and reduce the equivalent PMOS width-to-length ratio, while the pull-down end adopts a CMOS structure to connect the inverter output cross point Turn it down to improve the linearity problem caused by the slow rising edge of the inverter output.
  • an additional PMOS tube is added to the upper pull-end series node to adjust the series node voltage to solve reliability problems and inter-code interference problems.
  • the Latch circuit structure in the embodiment of the present disclosure includes the following modules: a first-stage differential latch circuit I and a second-stage differential inverter circuit II.
  • the first-stage differential latch circuit I the circuits of the differential positive terminal and the negative terminal are the same, with the differential positive terminal as
  • the pull-up end of the latch is composed of two PMOS M1 and M2, whose gates are connected to the input data din and the input clock clkp respectively.
  • the pull-down end of the latch is composed of two NMOS M3 and M4, and their gates are connected respectively. Connect input data din and input clock clkn.
  • the capabilities of the pull-up end and the pull-down end can be designed to match, that is, the width-to-length ratio of the PMOS end and the NMOS end is designed to make the pull-up and pull-down current capabilities similar, so that the cross point of the Latch output is in the middle.
  • the width-to-length ratio of the PMOS terminal and the NMOS terminal can also be deliberately designed to be mismatched, so that the intersection point of the Latch output is not in the middle. For example: If the PMOS and NMOS width-to-length ratios are equal and the pull-up and pull-down capabilities are the same, we can design the PMOS width-to-length ratio to be twice the NMOS width-to-length ratio, making the intersection point of the Latch output higher.
  • the second stage differential inverter circuit II the circuits of the differential positive terminal and the negative terminal are the same.
  • the pull-up terminal of the inverter is a structure of two PMOS M9 and M10 connected in series, that is, two PMOS gates terminals are short-circuited, the source terminal of one PMOS is connected to the power supply voltage, the drain terminal is connected to the source terminal of the other PMOS, and the drain terminal of the other PMOS is pulled out to connect to the pull-down terminal of the inverter.
  • An additional PMOS M17 is added to the series node of the two PMOSs.
  • the source terminal of the PMOS is connected to the power supply voltage, the drain terminal is connected to the series node, and the gate terminal is connected to the input of the inverter at the other end of the differential.
  • the additional PMOS can be better controlled
  • the voltage of the series node; the pull-down end of the second-stage differential inverter circuit is a CMOS structure, including PMOS M15 and NMOS M11.
  • the PMOS drain stage is connected to the NMOS source stage and is connected to the output of a level shift circuit, so that the inverter The output low level is not ground, but a value that needs to meet design requirements.
  • the differential latch includes at least the following modifications:
  • PMOS series connection at the pull-up end of the inverter.
  • the number of PMOS series connections can be multiple. Depending on the design requirements, it can also be changed to NMOS series connection, CMOS series connection, or various series connections. Combinations, etc., are applied at the pull-up end or the pull-down end.
  • MOS series connection method can be applied in the post-stage inverter, or in the front-stage latch, or both stages are used, or neither stage is used.
  • the CMOS structure is used at the pull-down end of the inverter to ensure its pull-down capability under different process angles. There are many variations. According to different design requirements, it can also be changed to a combination of multiple CMOS series or parallel connections, etc., applied in the above Pull end or pull-down end. In addition, this CMOS structure can be used in the post-stage inverter or in the pre-stage Latch, or both stages can be used, or neither stage can be used.
  • the level shift circuit can be added to the pull-up or pull-down end of the inverter according to the design requirements.
  • the output voltage of the level shift circuit can be higher or lower than the ground voltage, or higher or lower than the power supply voltage.
  • the level shift circuit can be applied in the post-stage inverter, or in the pre-stage Latch, or both stages, or neither stage.
  • the above one to four points can be extended to the various traditional Latch variants mentioned above, and can also be similarly extended to the design of DFF, MUX and other circuits with synchronization functions and their variants, and can also be extended to other timings. In the design of logic circuits, it can also be promoted in the design of combinational logic circuits.
  • Figure 5(a) assumes that the design requirement is that the inverter differential output is a low crossover point.
  • the present disclosure is implemented in the following manner:
  • the series connection of two PMOS M9 and M10 at the pull-up end of the inverter can effectively increase the channel length of the equivalent PMOS and reduce the width-to-length ratio of the equivalent PMOS, which is beneficial to lowering the inverter output cross point.
  • the pull-down end of the inverter is a CMOS structure, including PMOS M15 and NMOS M11.
  • the CMOS structure can better guarantee the pull-down capability of the inverter under different process angles, especially the extreme process conditions of SNFP and FNSP, which is beneficial to converting the inverter
  • the phase converter output cross point is lowered.
  • Figure 5(a) assumes that the design requires that the inverter output low level is not ground potential, so the pull-down end is The output of a level shift circuit is input. If the output of the level shift circuit is higher than the ground potential, this will reduce the current capability of the pull-down end of the inverter, which is not conducive to lowering the inverter output cross point. The above three requirements are required. way to compensate for this adverse effect. Conversely, if the output of the level-shift circuit is below ground, it is advantageous to adjust the inverter output crossover point lower.
  • the differential latch (Latch) circuit in the above embodiment of the present disclosure can be used to implement the switch driver circuit of the embodiment of the present disclosure.
  • the first switch driver structure of the embodiment of the present disclosure adopts a conventional data format. Data is sampled on the rising edge of the clock. Among them, the upper two channels transmit real signals, and the lower two channels transmit Dummy data. At each data sampling point, if the real data is not flipped, the Dummy data is flipped; if the real data is flipped, the Dummy data is not flipped.
  • the third level Latch adopts the latch (Latch) shown in any one of Figure 5(a), Figure 5(b), Figure 5(c) or Figure 6 of the present disclosure.
  • the real data Din and Db_in of the upper two channels pass through the latches of the first two levels, are photographed step by step by Fclk, and then sent to the disclosed latch, and are finally output to the next level.
  • the next two Dummy data Dum_in and Dumb_in are output to the next level through the same path.
  • FIG. 8 is a schematic diagram of a second switch driver structure according to an embodiment of the present disclosure, which is characterized by being compatible with the normal mode and the mixing mode.
  • the mixing mode data changes occur on both the rising and falling edges of the clock.
  • the data corresponding to the falling edge is the inversion of the data corresponding to the rising edge, which is equivalent to the mixing effect of the real signal and the clock signal.
  • a DAC output with Fclk is the bandpass transfer function centered (the normal mode is a low-pass transfer function), which is very helpful for applications with lower bandwidth in high, medium and high frequencies.
  • Latch, XOR, and MUX may adopt the technology of the embodiments of the present disclosure, or a combination of the technologies of the embodiments of the present disclosure may be adopted.
  • the above-mentioned first and second switch drivers include at least the following modifications:
  • the technology involved in the Latch in the embodiment of the present disclosure can be extended to the various traditional Latch variants mentioned above, it can also be similarly extended to the design of DFF, MUX and other circuits with synchronization functions and their variants, as well. It can be extended to the design of other sequential logic circuits, and can also be extended to the design of combinational logic circuits. Therefore, as long as the switch driver applies the technology involved in the Latch of the present disclosure, it falls within the scope of protection of the embodiments of the present disclosure, including all the above-mentioned ones. Variations of traditional switch drivers, including various variations of traditional switch drivers not mentioned above.
  • the differential latch (Latch) circuit in the above embodiments of the present disclosure can also be used to implement two multi-mode, low power consumption and high linearity digital-to-analog converter (DAC) circuits.
  • the difference between the two DAC circuits lies in the structure of the DAC core slice, which are the multi-mode current steering DAC circuit of the present disclosure and the multi-mode resistive DAC of the present disclosure. These two DACs will be introduced in detail in specific implementations below.
  • Figure 9 is a schematic diagram of the first multi-mode resistive DAC circuit structure according to an embodiment of the present disclosure.
  • Figure 9 only includes the first switch driver (Switch Driver) and DAC core circuit (DAC Core) of the present disclosure. Others Parts are not included, wherein the switch driver of the present disclosure includes the latch of the present disclosure.
  • the switch driver needs to be divided into multiple units (Slices) for multi-bit data output (N in Figure 9).
  • the switch driver unit adopts the switch driver structure of the present disclosure to achieve high speed and high linearity. Spend.
  • the DAC core circuit will be divided into multiple units (Slices) for data reception.
  • the real data D ⁇ N:0> and Db ⁇ N:0> output by the switch driver are respectively connected to the inputs of the inverter circuits INV1 and INV2 in the DAC core circuit for selecting the power supply potential or
  • the ground potential to the left ports of unit resistors Ru1 and Ru2 can be connected together and connected to the load resistor as the positive terminal of the differential output, and the right ports of all Ru2 are connected together as The negative terminal of the differential output forms a resistor network as a whole.
  • the number of Ru1 and Ru2 connected to the power supply/ground potential in the resistor network is different, realizing the linear conversion relationship between the output differential voltage Vout and the input data.
  • the Dummy data Dum ⁇ N:0> and Dumb ⁇ N:0> output by the switch driver enter the core circuit unit and are connected to the Dummy load.
  • the load is close to the real data D ⁇ N:0> and Db ⁇ N:0>. The load is consistent.
  • FIG. 10 is a schematic diagram of the second multi-mode resistive DAC circuit structure according to an embodiment of the present disclosure.
  • the figure only includes the second switch driver (Switch Driver) and DAC core circuit (DAC Core) of the present disclosure, and other parts Not included. Except for the switch driver, other parts are consistent with Figure 9.
  • the first and second multi-mode resistive DACs in the present disclosure include at least the following variations:
  • the switch driver of the DAC can be any variation of the switch driver described above.
  • the DAC core circuit shown in Figures 9 and 10 is a basic resistive DAC structure.
  • the present disclosure can be extended to other variant structures of resistive DACs.
  • the power supply potential and ground potential can be replaced by positive and negative reference potentials, and Ru1 and Ru2 can be set to different resistance values in different DAC core circuit units to achieve different weights.
  • a Dummy load is added to the DAC core circuit. Dummy loads can be simplified or removed based on actual needs.
  • FIG 11 is the first multi-mode current steering DAC circuit structure of the present disclosure.
  • the figure only includes the first switch driver (Switch Driver) and DAC core circuit (DAC Core) of the present disclosure.
  • the other parts Not included, wherein the switch driver of the present disclosure includes the latch of the present disclosure.
  • the switch driver needs to be divided into multiple units (Slices) for multi-bit data output (N units are shown in Figure 11).
  • the switch driver unit can adopt the switch driver structure of the present disclosure to achieve high speed and high performance. linearity.
  • the DAC core circuit will be divided into multiple units (Slices) for data reception.
  • the real data D ⁇ N:0> and Db ⁇ N:0> output by the switch driver are connected to the gates of the switch circuits Switch1 and Switch2 in the DAC core circuit respectively, which are used to select the current source.
  • Output current to the upper port of the load resistor RL1 or RL2 that is, the positive or negative terminal of the DAC differential output.
  • the drains of Switch1 of all DAC core circuit units are connected together, and the drains of all Switch2 are connected together.
  • the total current flowing to RL1 and the total current flowing to RL2 are different, and the corresponding differential output voltage Vout is also Differently, the linear conversion relationship between the output differential voltage Vout and the input data is finally achieved.
  • the Dummy data Dum ⁇ N:0> and Dumb ⁇ N:0> output by the switch driver enter the core circuit unit and are connected to the Dummy load.
  • the load is close to the real data D ⁇ N:0> and Db ⁇ N:0>. The load is consistent.
  • Figure 12 is the second multi-mode current steering DAC circuit structure of the present disclosure.
  • the figure only includes the second switch driver (Switch Driver) and DAC core circuit (DAC Core) of the present disclosure, and other parts are not included. Except for the switch driver, other parts are consistent with Figure 11.
  • the first and second multi-mode current steering DACs in the present disclosure include at least the following modifications:
  • the switch driver of the DAC can be any variation of the switch driver described above.
  • the DAC core circuit shown in Figure 11 and Figure 12 is a basic current steering DAC structure.
  • the present disclosure can be extended to other variant structures of current steering DACs.
  • a Dummy load is added to the DAC core circuit. Dummy payloads can be simplified or removed based on actual needs.
  • the series connection of two PMOS M9 and M10 at the pull-up end of the inverter can effectively increase the channel length of the equivalent PMOS, reduce the width-to-length ratio of the equivalent PMOS, and together with the pull-down end, realize the control of the inverter. Control of output cross points.
  • connecting two PMOS in series can increase the effective area of the equivalent PMOS tube and improve the mismatch problem caused by the small size of the MOS tube at the pull-up end, as well as the problem caused by the small size of the MOS tube.
  • the additional PMOS M17 can better control the voltage of the series node. If two PMOS series nodes are not processed, the series node will be in a high-impedance state when the inverter input is high. At this time, the series node voltage is easily disturbed, causing many problems in high-speed designs. For example, when the voltage at the input terminal of the inverter changes rapidly from low level to high level, the voltage of the series node will rise rapidly or even be higher than the power supply voltage, causing design reliability problems.
  • the series node The voltage is in a high-resistance state, and it takes a long time to recover from a state higher than the power supply voltage to a normal state (close to the power supply voltage).
  • the first situation is that the inverter during this recovery process The input terminal voltage quickly switches from high level to low level.
  • the PMOS series node will first discharge from a state higher than the power supply voltage.
  • the PMOS series node voltage decreases, pulling the inverter output node high.
  • the PMOS series node and The output of the inverter is close to the power supply voltage.
  • modules or steps of the present disclosure can be implemented using general-purpose computing devices, and they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices. They may be implemented in program code executable by a computing device, such that they may be stored in a storage device for execution by the computing device, and in some cases may be executed in a sequence different from that shown herein. Or the described steps can be implemented by making them into individual integrated circuit modules respectively, or by making multiple modules or steps among them into a single integrated circuit module. As such, the present disclosure is not limited to any specific combination of hardware and software.

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Abstract

一种差分锁存器电路、开关驱动器以及数模转换电路，该差分锁存器电路包括：第一级差分锁存器电路(I)、第二级差分反相电路(II)以及低电平移位电路，第二级差分反相电路(II)的差分正端的上拉端包括第一PMOS管(M9)和第二PMOS管(M10)，第二级差分反相电路(II)的差分正端的下拉端包括第三PMOS管(M15)和第一NMOS管(M11)，第一级差分锁存器电路(I)的差分负端与第一级差分锁存器电路(I)的差分正端的电路结构相对称。

Description

一种差分锁存器电路、开关驱动器以及数模转换电路
相关公开的交叉引用
本公开要求在2022年8月26日提交国家知识产权局、公开号为CN202211043550.2、发明名称为“一种差分锁存器电路、开关驱动器以及数模转换电路”的中国专利申请的优先权，该申请的全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及但不限于集成电路设计领域，具体而言，涉及一种差分锁存器电路、开关驱动器以及数模转换电路。
背景技术
图1是相关技术中数模转换器(Digital to Analog Converter，DAC)的系统框图。如图1所示，该DAC包括数据链路(Data Path)、时钟链路(CLK Path)和数模转换器核心电路(DAC Core)。其中数据链路包括接口电路(Interface)、数字数据链路(Digital Data Path)、译码器(Decoder)、串行化器(Serializer)和开关驱动器(Switch Driver)。时钟链路包括时钟接收器(Clock Receiver)、延迟锁相环(Delay Locked Loop，DLL)、分频器(Divider)和一些时钟驱动器等，而数模转换器核心电路包括多个数模转换器核心单元(DAC Core Slices)。对于DAC而言，数据链路中的开关驱动器的设计至关重要，影响到线性度、功耗、噪声等多个指标。
在数据链路中，输入数字信号首先通过接口电路和数字数据链路进行数据接收和处理，译码器的主要功能是完成DAC分段编码，具体地，DAC高位一般用温度计码，低位一般用二进制编码，此外，译码器中可以对数据施加一些算法，例如：动态元素匹配(Dynamic Element Matching，DEM)、dither以及rotation等。由于数字数据链路和译码器是数字P&R模块，不可能达到很高的数据率，所以在这些数字模块中DAC的每一位数据一般都会分为多相位传输。串行化器的主要功能是将多相位数据转变为单相位或较少相位的数据。而开关驱动器的主要功能是对每一位数据进行同步，并增加驱动能力，减小码间干扰等。根据数模 转换器核心单元的具体架构和需求，开关驱动器可能还需要进行数据交叉点(即差分输出的数据上升沿和下降沿的交叉位置)调整和数据高低电平的调整等，这些调整都会较大地影响应用该开关驱动器的数模转换器的线性度、噪声等性能。
图2是相关技术中一种传统的开关驱动器结构。它采用时钟上升沿进行数据采样，为了实现较好的数据同步，使用了三级锁存器(Latch)进行逐级同步，其中上两路进行真实信号传递，另外增加下两路传递Dummy数据，这是为了减小信号相关的电流对DAC性能的影响[1]。在每个数据采样点，如果真实数据不翻转，则Dummy数据翻转；如果真实数据翻转，则Dummy数据不翻转。
传统的开关驱动器有较多变型，比如：
1.Latch级数可以不一样。
2.Latch也可以被替换为触发器(DFF)，或者替换为同时带有数据合路和同步功能的多路选择器(MUX)，或者其它一些时序逻辑。设计中也可能包括一些组合逻辑。
3.MUX实现方式也有很多种，可以是组合逻辑的MUX、OR/NOR或AND/NAND，也可以是组合逻辑MUX加上时钟触发的Latch或DFF，也可以是其它一些类型的时钟触发的MUX同时完成数据合路和同步。
4.输入数据可以采用如图2的常规数据，或者Return-to-Zero数据或Return-to-One数据。数据类型不一样，对应Latch、DFF、MUX等时序逻辑电路可能有所不同，组合逻辑也可能有所不同。
5.Dummy数据路径也有不同的实现方式甚至删除。
6.另外，在开关驱动器上还可以实现多模兼容。图3是一种传统的多模兼容开关驱动器结构。它的特点是将常规模式和混频模式兼容起来。在混频模式下，时钟上升沿和下降沿都会发生数据变化，下降沿对应的数据是上升沿对应数据的取反，相当于真实信号和时钟信号的混频效果，最终在DAC输出实现一个以Fclk为中心的带通传递函数，而常规模式是低通传递函数，这对高中频较低带宽的应用很有帮助。
尽管开关驱动器存在很多变型，带同步功能的Latch、DFF、MUX等时序逻辑电路和一些组合逻辑电路是属于其中比较基础的单元。图4是相关技术中一种传统的差分锁存器结构的示意图，它采用CMOS架构，输出高低电平是rail-to-rail的，前级是一个时钟电平触发的Latch，后级是一个反相器(Inverter)，用于增 加Latch的驱动能力。
如图4所示，它的左右两侧是对称的。以左侧为例，当clkp为低电平，clkn为高电平时，din被第一级Latch采到，并通过第二级的反相器传给输出dout；当clkp为高电平，clkn为低电平时，din通路被断开，dout保持不变。
传统的Latch也有较多变型，比如：
1.后级的反相器也可以是缓冲器(Buffer)。
2.后级的反相器PMOS源端可以不接电源而是接一个电平移位电路的输出，这样反相器输出的高电平就不是电源而是一个特别设计的电压。同样地，反相器NMOS源端可以不接地而是接一个电平移位电路的输出，这样反相器输出的低电平就不是地而是一个特别设计的电压。另外，前级Latch的电源地同样可以接电平移位电路的输出。
3.后级的反相器PMOS和NMOS的宽长比可以故意设计成不对称的，用于调整反相器输出数据的交叉点。同样地，前级Latch PMOS和NMOS的宽长比也可以故意设计成不对称的。
4.带同步功能的DFF、MUX的设计同样存在以上的变型，其它时序逻辑电路的设计同样存在以上的变型，组合逻辑电路的设计同样存在以上的变型。
传统Latch存在以下缺点：
1.单纯通过PMOS和NMOS的宽长比来调整反相器输出数据的交叉点是有局限性的。如果PMOS和NMOS的宽长比差异过大，大尺寸的MOS管会造成前级负载过重，而且尺寸很大会导致大电流。MOS管源漏连接在版图实现上会产生较大的IR drop，影响MOS管的电流能力，进而影响输出数据交叉点的调整效果，影响DAC线性度。小尺寸的MOS管会导致输出数据沿过缓，而且小尺寸MOS管的失配较大，会导致DAC不同bit的输出数据沿偏差较大，影响DAC线性度。
2.如果在传统Latch的基础上增加电平移位电路，输出数据交叉点的调整可能会进一步受到影响，因为电平移位电路可能会使得PMOS端和NMOS端不匹配，进而影响到输出数据交叉点。如果这个交叉点的偏差和我们的需求是相反的，很难通过单纯调整PMOS和NMOS的宽长比来达成目标。
发明内容
本公开实施例提供了一种差分锁存器电路、开关驱动器以及数模转换电路。
根据本公开的一个实施例，提供了一种差分锁存器电路，包括依次连接的第一级差分锁存器电路、第二级差分反相电路和低电平移位电路，其中，所述第二级差分反相电路的差分正端的上拉端包括第一PMOS管和第二PMOS管，所述第一PMOS管的栅极连接所述第二PMOS管的栅极；所述第一PMOS管的源极连接电源电压；所述第一PMOS管的漏极连接所述第二PMOS管的源极；所述第一PMOS管的栅极和所述第二PMOS管的栅极还分别连接所述第二级差分反相电路的差分正端的数据输入端；所述第二级差分反相电路的差分正端的下拉端包括第三PMOS管和第一NMOS管，所述第三PMOS管的漏极与所述第一NMOS管的源极相连接，并一同连接在一电平移位电路的输出端；所述第三PMOS管的栅极连接所述第二级差分反相电路的差分正端的数据输入端，所述第三PMOS管的源极连接所述第二级差分反相电路的差分负端的下拉端的输出端；所述第一NMOS管的漏极连接所述第二PMOS管的漏极，所述第一NMOS管的栅极连接所述第二级差分反相电路的差分正端的数据输入端；所述第一级差分锁存器电路的差分负端与所述第一级差分锁存器电路的差分正端的电路结构相对称。
根据本公开的另一实施例，提供了一种开关驱动器，所述开关驱动器包括多个开关驱动器单元，其中每个开关驱动器单元包括：多路数据传输链路，每路数据传输链路包括上述实施例中的差分锁存器电路。
根据本公开的又一实施例，还提供一种数模转换电路，包括上述实施例中的开关驱动器以及与所述开关驱动器的输出端连接的数模转换核心电路。
附图说明
图1是相关技术中数模转换器的系统结构框图；
图2是相关技术中一种传统的开关驱动器结构的示意图；
图3是一种传统的多模兼容开关驱动器结构的示意图；
图4是相关技术中一种传统的差分锁存器结构的示意图；
图5(a)是根据本公开实施例的差分锁存器电路结构的示意图；
图5(b)是根据本公开实施例的第四PMOS管在第二级差分反相电路中的另一连接方式示意图；
图5(c)是根据本公开实施例的第四PMOS管在第二级差分反相电路中的 又一连接方式示意图；
图6是根据本公开另一实施例的差分锁存器电路的结构示意图；
图7是根据本公开实施例的一种开关驱动器的结构示意图；
图8是根据本公开另一实施例的开关驱动器的结构示意图；
图9是根据本公开实施例的多模电阻型数模转换电路的结构示意图；
图10是根据本公开另一实施例的多模电阻型数模转换电路的结构示意图；
图11是根据本公开实施例的多模电流舵型数模转换电路的结构示意图；
图12是根据本公开另一实施例的多模电流舵型数模转换电路的结构示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开的实施例。
图5(a)是根据本公开实施例的差分锁存器电路的结构示意图。如图5(a)所示，该差分锁存器电路包括第一级差分锁存器电路Ⅰ、第二级差分反相电路Ⅱ以及低电平移位电路。
所述第二级差分反相电路Ⅱ的差分正端的上拉端包括第一PMOS管M9和第二PMOS管M10，所述第一PMOS管M9的栅极连接所述第二PMOS管M10的栅极；所述第一PMOS管M9的源极连接电源电压；所述第一PMOS管M9的漏极连接所述第二PMOS管M10的源极；所述第一PMOS管M9的栅极和所述第二PMOS管M10的栅极还分别连接所述第二级差分反相电路的差分正端的数据输入端；所述第二级差分反相电路的差分正端的下拉端包括第三PMOS管M15和第一NMOS管M11，所述第三PMOS管M15的漏极与所述第一NMOS管M11的源极相连接，并一同连接在一电平移位电路的输出端；所述第三PMOS管M15的栅极连接所述第二级差分反相电路的差分正端的数据输入端，所述第三PMOS管M15的源极连接所述第二级差分反相电路的差分负端的下拉端的输出端；所述第一NMOS管M11的漏极连接所述第二PMOS管M10的漏极，所述第一NMOS管M11的栅极连接所述第二级差分反相电路的差分正端的数据输入端；所述第一级差分锁存器电路的差分负端与所述第一级差分锁存器电路的差分正端的电路结构相对称。
在本实施例中，如图5(a)所示，第二级差分反相电路的差分正端，还包括：第四PMOS管M17，所述第四PMOS管M17的源极连接所述电源电压，所 述第四PMOS管M17的栅极连接所述第二级差分反相电路的差分负端的数据输入端，所述第四PMOS管M17的漏极连接所述第一PMOS管M9与所述第二PMOS管M10之间的第一串联节点，以调节所述串联节点电压。
在一个示例性实施中，所述第四PMOS管还可通过其他方式连接在所述第二级差分反相电路中。如图5(b)所示，所述第四PMOS管M17的源极连接位于所述第二级差分反相电路的差分负端且与所述第四PMOS管M17相对应的第五PMOS管M18的源极；所述第四PMOS管M17的栅极连接所述第二级差分反相电路的差分负端的数据输入端，所述第四PMOS管M17的漏极连接所述第一PMOS管M9与所述第二PMOS管M10之间的第一串联节点。
在一个示例性实施中，所述第四PMOS管还可通过其他方式连接在所述第二级差分反相电路中。如图5(c)所示，所述第四PMOS管M17的源极连接所述电源电压，所述第四PMOS管M17的栅极连接所述第二级差分反相电路的差分正端的数据输出端，所述第四PMOS管M17的漏极连接所述第一PMOS管M9与所述第二PMOS管M10之间的第一串联节点。
在本实施例中，所述第一串联节点位于所述第一PMOS管M9的漏极和所述第二PMOS管M10的源极之间。
图6是根据本公开另一实施例的差分锁存器电路的结构示意图。如图6所示，所述第二级差分反相电路Ⅱ的差分正端的上拉端包括第一PMOS管M9和第二PMOS管M10，所述第一PMOS管M9的栅极连接所述第二PMOS管M10的栅极；所述第一PMOS管M9的源极连接电源电压；所述第一PMOS管M9的漏极连接所述第二PMOS管M10的源极；所述第一PMOS管M9的栅极和所述第二PMOS管M10的栅极还分别连接所述第二级差分反相电路的差分正端的数据输入端；所述第二级差分反相电路的差分正端的下拉端包括第三PMOS管M15和第一NMOS管M11，所述第三PMOS管M15的漏极与所述第一NMOS管M11的源极相连接，并一同连接在一电平移位电路的输出端；所述第三PMOS管M15的栅极连接所述第二级差分反相电路的差分正端的数据输入端，所述第三PMOS管M15的源极连接所述第二级差分反相电路的差分负端的下拉端的输出端；所述第一NMOS管M11的漏极连接所述第二PMOS管M10的漏极，所述第一NMOS管M11的栅极连接所述第二级差分反相电路的差分正端的数据输入端；在本实施例中，在所述第二级差分反相电路的差分正端中，所述第一PMOS管M9与第二PMOS管M10之间的第一串联节点与位于所述第二级差分反相电路的差分负端中且与所述第一串联节点相对应的第二串联节点短接；所述第一级 差分锁存器电路的差分负端与所述第一级差分锁存器电路的差分正端的电路结构相对称。
在一个示例性实施例中，所述第一级差分锁存器电路中的PMOS管端和NMOS管端的宽长比设置为不匹配，所述差分锁存器电路输出的交叉点不位于所述PMOS管端与NMOS管端的中间。
由于第二级差分反相器电路上拉端的两个PMOS管串联，可增加等效PMOS管的沟道长度，减小等效PMOS管宽长比，下拉端采用一个PMOS管和一个NMOS管的结构，将第二级差分反相器输出交叉点调低，能够改善反相器输出上升沿过缓导致的线性度问题，解决可靠性问题和码间干扰的问题。能够提高调整输出数据交叉点的灵活性。
图7是根据本公开实施例的一种开关驱动器的结构示意图。如图7所示，所述开关驱动器包括多个开关驱动器单元，其中每个开关驱动器单元包括：多路数据传输链路，每路数据传输链路包括上述实施例中的差分锁存器电路。
在一个示例性实施例中，所述多路数据传输链路包括用于传输真实数据的真实数据传输链路，用于传输Dummy数据的Dummy数据传输链路。
图8是根据本公开另一实施例的开关驱动器的结构示意图。如图8所示，该开关驱动器除包括图7所示的所有结构外，还包括：多个异或逻辑单元，每个所述异或逻辑单元的第一输入端连接各数据传输链路中的所述差分锁存器电路的输出端，所述异或逻辑单元的第二输入端连接时钟输入端；多个数据选择器，每个所述数据选择器的第一输入端连接所述各路数据传输链路中差分锁存器电路的输出端，每个所述数据选择器的第二输入端分别连接所述异或逻辑单元的输出端。
图9是根据本公开实施例的多模电阻型数模转换电路的结构示意图。如图9所示，该多模电阻型数模转换电路，包括图7的开关驱动器以及与所述开关驱动器的输出端连接的数模转换核心电路。
在一个示例性实施例中，所述数模转换核心电路包括多个数模转换器核心单元，每个所述数模转换器核心单元包括：反相器INV，所述反相器的输入端连接至所述开关驱动器单元的真实数据传输链路的输出端；单元电阻，所述单元电阻的第一端连接至所述反相器的输出端，所述单元电阻的第二端与负载电阻相连接；第一Dummy负载，所述第一Dummy负载连接所述开关驱动器单元的所述Dummy数据传输链路的输出端。
在一个实施例性实施例中，如图10所示，该多模电阻型数模转换电路中的开关驱动器为图8所示的开关驱动器。
图11是根据本公开实施例的多模电流舵型数模转换电路的结构示意图。如图11所示，该多模电流舵型数模转换电路，包括图7的开关驱动器以及与所述开关驱动器的输出端连接的数模转换核心电路，其中，所述数模转换核心电路包括多个数模转换器核心单元，每个所述数模转换器核心单元包括：第六PMOS管，所述第六PMOS管的栅极连接所述驱动器单元的所述真实数据传输链路的输出端，所述第六PMOS管漏极连接负载电阻以及所述数模转换核心电路的输出端，所述第六PMOS管的源极连接电流源输出端；第二Dummy负载，所述第二Dummy负载连接所述开关驱动器单元的所述Dummy数据传输链路的输出端。
在一个实施例性实施例中，如图12所示，该多模电阻型数模转换电路中的开关驱动器为图8所示的开关驱动器。
为便于对本公开所提供的技术方案的理解，下面将结合具体场景的实施例进行详细的阐述。
本公开实施例为了克服现有技术中存在的输出数据交叉点调整有局限性、在与电平移位电路配合使用时存在困难处理不好会对整体电路线性度造成较大损失等问题，提供一种输出数据交叉点调整较为灵活、电平移位电路兼容性高的Latch电路(在本实施例中，DFF和MUX电路也可以类似设计)以及应用该Latch电路的高线性度的开关驱动器电路，以及应用该开关驱动器电路的高线性度数模转换器电路。具体地，本公开实施例的操作包括：
将Latch第一级差分锁存器电路的PMOS端和NMOS端的宽长比故意设计成不匹配，使得Latch输出的交叉点偏高，反相器输出交叉点随之偏低；
将Latch第二级差分反相器电路上拉端的两个PMOS串联，增加等效PMOS的沟道长度，减小等效PMOS宽长比，而下拉端采用CMOS结构，将反相器输出交叉点调低，改善反相器输出上升沿过缓导致的线性度问题。
在Latch第二级差分反相器电路上拉端串联节点，额外增加一个PMOS管，用来调节串联节点电压，解决可靠性问题和码间干扰的问题。
如图5(a)所示，在本公开实施例中的Latch电路结构包括以下模块：第一级差分锁存器电路Ⅰ和第二级差分反相器电路Ⅱ。
第一级差分锁存器电路Ⅰ，差分正端和负端的电路是一致的，以差分正端为 例，锁存器上拉端由两个PMOS M1和M2组成，它们的栅级分别接输入数据din和输入时钟clkp，锁存器下拉端由两个NMOS M3和M4组成，它们的栅级分别接输入数据din和输入时钟clkn。上拉端和下拉端能力可以设计成匹配的，即设计PMOS端和NMOS端的宽长比使得上拉和下拉电流能力相似，使得Latch输出的交叉点在中间位置。
在本实施例中，PMOS端和NMOS端的宽长比也可以考虑故意设计为不匹配，使得Latch输出的交叉点不在中间。例如：假如PMOS和NMOS宽长比相等时上拉端和下拉端能力是一致的，我们可以设计PMOS宽长比是NMOS宽长比的2倍，使得Latch输出的交叉点偏高。
第二级差分反相器电路Ⅱ，差分正端和负端的电路是一致的，以差分正端为例，反相器上拉端是两个PMOS M9和M10串联的结构，即两个PMOS栅端短接，其中一个PMOS的源端接电源电压，漏端接另外一个PMOS的源端，另外一个PMOS的漏端拉出去接反相器的下拉端。在两个PMOS的串联节点，额外增加了一个PMOS M17，该PMOS源端接电源电压，漏端接串联节点，栅端接差分另外一端反相器的输入，额外增加的PMOS能够较好地控制串联结点的电压；第二级差分反相器电路下拉端是一个CMOS结构，包括PMOS M15和NMOS M11，PMOS漏级和NMOS源级相连并接一个电平移位电路的输出，使得反相器输出低电平不是地，而是一个需要符合设计需求的值。
在一个示例性实施例中，差分锁存器(Latch)至少包括以下变型：
一、在反相器上拉端通过PMOS串联调节差分输出交叉点可以有多种变型，PMOS串联数量可以是多个，根据设计需求的不同，也可以改成NMOS串联、CMOS串联、各种串联的组合等，应用在上拉端或者下拉端，此外，MOS串联的方式可以应用在后级反相器中，也可以前级的Latch中，或者两级都采用，或者两级都不采用。
二、控制PMOS串联点电位的方式可以有多种变型，例如图5(b)、图5(c)、图6等。图6中将第二级反相器中M9、M10的串联节点和M12、M13的串联节点直接短接；图5(b)中PMOS串连节点额外增加的两个PMOS管源端没有接电源，而是直接短接在一起；图5(c)中PMOS串连节点额外增加的两个PMOS管栅端改为由dout和doutb控制。除了这些已经提出来的变型，还有更多通过本公开所述方式很容易联想的方式，目的都是避免PMOS串联点处于高阻态所造成的不利影响。显然这些控制串联点电位的方式可以推广到多个PMOS串联、 NMOS串联、CMOS串联、各种串联的组合等，应用在上拉端或者下拉端，也可以根据实际设计情况有些串联点使用，有些不使用，另外，除了应用在后级反相器以外，也可以应用在前级Latch或者两级都采用或者两级都不采用。
三、在反相器下拉端使用CMOS结构保障其在不同工艺角下的下拉能力可以有多种变型，根据设计需求的不同，也可以改成多个CMOS串联或并联的组合等，应用在上拉端或者下拉端，此外，该CMOS结构可以应用在后级反相器中，也可以前级的Latch中，或者两级都采用，或者两级都不采用。
四、电平移位电路根据设计需求可以是加在反相器上拉端或下拉端，电平移位电路的输出电压可以是高于或低于地电压，也可以是高于或低于电源电压，此外，电平移位电路可以应用在后级反相器中，也可以前级的Latch中，或者两级都采用，或者两级都不采用。
五、上述一至四点均可以推广到前文所述的各种传统Latch的变型中，也可以类似地推广到带同步功能的DFF、MUX等电路及其变型的设计中，也可以推广到其它时序逻辑电路的设计中，也可以推广组合逻辑电路的设计中。
六、上述一至四点均可以推广到应用这些Latch、DFF、MUX、其它时序逻辑、组合逻辑等电路及其变型的开关驱动器中，也可以推广到前文所述的各种传统开关驱动器的变型中，也可以推广到应用这些开关驱动器及其变型的高速数模转换器(DAC)中。
七、上述一至四点还可以进一步推广到所有需要全部或部分用到这些技术的模拟电路和数模混合电路中。
在一个示例性实施例中，图5(a)是假设设计需求反相器差分输出是低交叉点，本公开通过以下方式来实现：
通过将锁存器PMOS端和NMOS端的宽长比故意设计成不匹配，使得Latch输出的交叉点偏高，反相器输出交叉点随之偏低；
反相器上拉端两个PMOS M9和M10串联能够有效增加等效PMOS的沟道长度，减小等效PMOS宽长比，有利于将反相器输出交叉点调低。
反相器下拉端是一个CMOS结构，包括PMOS M15和NMOS M11，CMOS结构能够在不同工艺角下更好地保障反相器的下拉能力，尤其是SNFP和FNSP的极端工艺情况，有利于将反相器输出交叉点调低。
图5(a)是假设设计需求反相器输出低电平不是地电位，所以在下拉端引 入了一个电平移位电路的输出，如果该电平移位电路的输出高于地电位，这会减小反相器下拉端的电流能力，不利于将反相器输出交叉点调低，需要上述三种方式来补偿这个不利效果。相反地，如果电平移位电路的输出低于地电位，有利于将反相器输出交叉点调低。
本公开上述实施例中的差分锁存器(Latch)电路可以用于实现本公开实施例的开关驱动器电路，如图7所示，本公开实施例的第一种开关驱动器结构采用常规数据格式，时钟上升沿进行数据采样。其中上两路进行真实信号传递，下两路传递Dummy数据。在每个数据采样点，如果真实数据不翻转，则Dummy数据翻转；如果真实数据翻转，则Dummy数据不翻转。其中第三级Latch采用本公开的图5(a)、图5(b)、图5(c)或图6中任一所示的锁存器(Latch)。
如图7所示，在本实施例中，上两路的真实数据Din和Db_in经过前两级的Latch，被Fclk逐级打拍后送到本公开Latch，最后输出给下一级。下两路的Dummy数据Dum_in和Dumb_in经过同样的路径输出到下一级。
图8是根据本公开实施例的第二种开关驱动器结构的示意图，它的特点是将常规模式和混频模式兼容起来。在混频模式下，时钟上升沿和下降沿都会发生数据变化，下降沿对应的数据是上升沿对应数据的取反，相当于真实信号和时钟信号的混频效果，最终在DAC输出实现一个以Fclk为中心的带通传递函数(常规模式是低通传递函数)，这对高中频较低带宽的应用很有帮助。其中的Latch、XOR、MUX可只有一个采用本公开实施例的技术，或者组合采用本公开实施例的技术。
在一示例性实施例中，上述的第一种和第二种开关驱动器至少包括以下变型：
由于本公开实施例中的Latch所涉及的技术可以推广到前文所述的各种传统Latch的变型中，也可以类似地推广到带同步功能的DFF、MUX等电路及其变型的设计中，也可以推广到其它时序逻辑电路的设计中，也可以推广组合逻辑电路的设计中，所以只要应用本公开Latch所涉及技术的开关驱动器，均属于本公开实施例的保护范围，包括前文所述的各种传统开关驱动器的变型，也包括前文未提及的各种传统开关驱动器的变型。
本公开上述实施例中的差分锁存器(Latch)电路还可以用于实现两种多模低功耗高线性度数模转换器(DAC)电路。两种DAC电路的不同之处在于DAC core slice的结构，分别为本公开的多模电流舵型DAC电路和本公开的多模电阻型DAC。以下将在具体实施方案中针对这两种DAC进行详细介绍。
图9是根据本公开实施例的第一种多模电阻型DAC电路结构的示意图，图9中只包含了本公开的第一种开关驱动器(Switch Driver)和DAC核心电路(DAC Core)，其它部分未包含，其中本公开的开关驱动器包括了本公开的锁存器(Latch)。根据DAC位数和分段情况，开关驱动器需要分为多个单元(Slice)进行多位数据输出(图9示意为N个)，开关驱动器单元采用本公开的开关驱动器结构，实现高速和高线性度。同样地，DAC核心电路会分多个单元(Slice)进行数据接收。
如图9所示，开关驱动器输出的真实数据D<N:0>和Db<N:0>分别接入到DAC核心电路中的反相器电路INV1和INV2的输入，用于选择电源电位或地电位到单元电阻Ru1和Ru2的左端口，所有DAC核心电路单元中Ru1的右端口可以连接在一起，并与负载电阻相连，作为差分输出的正端，所有Ru2的右端口连在一起，作为差分输出的负端，整体形成一个电阻网络。根据D<N:0>和Db<N:0>数据的不同，电阻网络中连接到电源/地电位的Ru1和Ru2的数量是不同的，实现了输出差分电压Vout与输入数据的线性转换关系。开关驱动器输出的Dummy数据Dum<N:0>和Dumb<N:0>进入核心电路单元后接到Dummy负载上，该负载近似于真实数据D<N:0>和Db<N:0>的负载一致。
图10是根据本公开实施例的第二种多模电阻型DAC电路结构的示意图，图中只包含了本公开的第二种开关驱动器(Switch Driver)和DAC核心电路(DAC Core)，其它部分未包含。除开关驱动器外，其他部分和图9一致。
在一个示例性实施例中，本公开中的第一种和第二种多模电阻型DAC至少包括以下变型：
一、DAC的开关驱动器可以是上文所述的开关驱动器的任意变形。
二、图9和10所示的DAC核心电路是一种基本的电阻型DAC结构。本公开可扩展到其它电阻型DAC的变型结构。另外，电源电位和地电位可替换为正负参考电位，Ru1和Ru2在不同的DAC核心电路单元中可设置不同的阻值，用于实现不同的权重。
三、为保证Dummy数据和真实数据在DAC核心电路输入端的负载近似一致，在DAC核心电路增加了Dummy负载。根据实际需求Dummy负载可以被简化或移除。
图11是本公开的第一种多模电流舵型DAC电路结构，图中只包含了本公开的第一种开关驱动器(Switch Driver)和DAC核心电路(DAC Core)，其它部分 未包含，其中本公开的开关驱动器包括了本公开的锁存器(Latch)。根据DAC位数和分段情况，开关驱动器需要分为多个单元(Slice)进行多位数据输出(图11示意为N个)，开关驱动器单元可采用本公开的开关驱动器结构，实现高速和高线性度。同样地，DAC核心电路会分多个单元(Slice)进行数据接收。
如图11所示，开关驱动器输出的真实数据D<N:0>和Db<N:0>分别接到DAC核心电路中的开关电路Switch1和Switch2的栅极，用于选择电流源Current Source的输出电流到负载电阻RL1或RL2的上端口(也即DAC差分输出的正端或负端)。所有DAC核心电路单元的Switch1的漏极是连在一起的，所有Switch2的漏极是连在一起的。对于整个DAC核心电路而言，根据D<N:0>和Db<N:0>数据的不同，流到RL1的总电流和流到RL2的总电流是不同的，对应的差分输出电压Vout也是不同的，最终实现了输出差分电压Vout与输入数据的线性转换关系。开关驱动器输出的Dummy数据Dum<N:0>和Dumb<N:0>进入核心电路单元后接到Dummy负载上，该负载近似于真实数据D<N:0>和Db<N:0>的负载一致。
图12是本公开的第二种多模电流舵型DAC电路结构，图中只包含了本公开的第二种开关驱动器(Switch Driver)和DAC核心电路(DAC Core)，其它部分未包含。除开关驱动器外，其他部分和图11一致。
在一个示例性实施例中，本公开中的第一种和第二种多模电流舵型DAC至少包括以下变型：
一、DAC的开关驱动器可以是上文所述的开关驱动器的任意变形。
二、图11和图12所示的DAC核心电路是一种基本的电流舵型DAC结构。本公开可扩展到其它电流舵型DAC的变型结构。
三、为保证Dummy数据和真实数据在DAC核心电路输入端的负载近似一致，在DAC核心电路增加了Dummy负载。根据实际需求，Dummy负载可以被简化或移除。
通过本公开的上述实施例，反相器上拉端两个PMOS M9和M10串联能够有效增加等效PMOS的沟道长度，减小等效PMOS宽长比，和下拉端一起实现对反相器输出交叉点的控制。相比于直接采用一个PMOS并减小其沟道宽度的做法，两个PMOS串联能够增大等效PMOS管的有效面积，改善上拉端由于MOS管尺寸小带来的失配问题，以及由此导致的线性度问题；相比于直接采用一个PMOS并增加其沟道长度的做法，在许多小尺寸工艺中，短沟长器件的性能往往 更为优化，能够改善反相器输出上升沿过缓导致的线性度问题。
在本公开实施例中，在两个PMOS M9和M10的串联节点，额外增加的PMOS M17能够较好地控制串联结点的电压。如果两个PMOS串联节点不做任何处理，该串联节点在反相器输入端为高电平时处于高阻状态，此时串联节点电压容易受到干扰，在高速设计中造成许多问题。例如，当反相器输入端电压从低电平到高电平快速变化时，该串联节点电压会跟着快速升高甚至出现高于电源电压的情况，导致设计可靠性问题，此时这个串联节点电压处于高阻状态，需要较长时间才能从高于电源电压的状态恢复到正常状态(接近于电源电压)，此时会存在两种情况，第一种情况是在这个恢复过程中反相器输入端电压又从高电平快速切换到低电平，PMOS串联节点会从一个高于电源电压的状态先放电，PMOS串联节点电压降低，把反相器输出节点拉高，最终PMOS串联节点和反相器输出都接近于电源电压，另外存在第二种情况是反相器输入端电压在高电平维持了较长时间，使得PMOS串联节点已经恢复到正常状态(接近于电源电压)，这时PMOS串联节点会从接近于电源电压的状态放电，将反相器输出节点拉高。对于这两种情况，反相器输出的上拉时间是不一样的，对于高速电路设计就存在码间干扰的问题。
在两个PMOS的串联节点上额外增加一个PMOS，上述问题可以得到解决，当差分一端的反相器输入端电压从低电平到高电平快速变化时，串联节点电压会跟着快速升高甚至短期出现高于电源电压的情况，由于额外增加的PMOS的栅级是接差分另外一端反相器的输入(从高电平到低电平)，该PMOS开启，迅速将串联节点电压拉回电源电压，避免了上述可靠性问题和码间干扰的问题，当差分一端的反相器输入端电压从高电平到低电平快速变化时，额外增加的PMOS会关断，不会影响反相器PMOS上拉端特性和交叉点控制。
显然，本领域的技术人员应该明白，上述的本公开的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作
的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种差分锁存器电路，包括依次连接的第一级差分锁存器电路、第二级差分反相电路和低电平移位电路，其中，
    所述第二级差分反相电路的差分正端的上拉端包括第一PMOS管和第二PMOS管，所述第一PMOS管的栅极连接所述第二PMOS管的栅极；所述第一PMOS管的源极连接电源电压；所述第一PMOS管的漏极连接所述第二PMOS管的源极；所述第一PMOS管的栅极和所述第二PMOS管的栅极还分别连接所述第二级差分反相电路的差分正端的数据输入端；
    所述第二级差分反相电路的差分正端的下拉端包括第三PMOS管和第一NMOS管，所述第三PMOS管的漏极与所述第一NMOS管的源极相连接，并一同连接在一电平移位电路的输出端；所述第三PMOS管的栅极连接所述第二级差分反相电路的差分正端的数据输入端，所述第三PMOS管的源极连接所述第二级差分反相电路的差分负端的下拉端的输出端；所述第一NMOS管的漏极连接所述第二PMOS管的漏极，所述第一NMOS管的栅极连接所述第二级差分反相电路的差分正端的数据输入端；所述第一级差分锁存器电路的差分负端与所述第一级差分锁存器电路的差分正端的电路结构相对称。
  2. 根据权利要求1所述的电路，其中，所述第二级差分反相电路的差分正端还包括第四PMOS管，其中，
    所述第四PMOS管的源极连接所述电源电压，所述第四PMOS管的栅极连接所述第二级差分反相电路的差分负端的数据输入端，所述第四PMOS管的漏极连接所述第一PMOS管与所述第二PMOS管之间的第一串联节点；或，
    所述第四PMOS管的源极连接位于所述第二级差分反相电路的差分负端且与所述第四PMOS管相对应的第五PMOS管的源极，所述第四PMOS管的栅极连接所述第二级差分反相电路的差分负端的数据输入端，所述第四PMOS管的漏极连接所述第一PMOS管与所述第二PMOS管之间的第一串联节点；或，
    所述第四PMOS管的源极连接所述电源电压，所述第四PMOS管的栅极连接所述第二级差分反相电路的差分正端的数据输出端，所述第四PMOS管的漏极连接所述第一PMOS管与所述第二PMOS管之间的第一串联节点。
  3. 根据权利要求1所述的电路，其中，所述第一PMOS管与第二PMOS管 之间的第一串联节点与位于所述第二级差分反相电路的差分负端中且与所述第一串联节点相对应的第二串联节点短接，其中，所述第一串联节点位于所述第一PMOS管的漏极与所述第二PMOS管的源极之间。
  4. 根据权利要求1所述的电路，其中，所述第一级差分锁存器电路中的PMOS管端和NMOS管端的宽长比设置为不匹配，所述差分锁存器电路输出的交叉点不位于所述PMOS管端与NMOS管端的中间。
  5. 一种开关驱动器，所述开关驱动器包括多个开关驱动器单元，其中每个开关驱动器单元包括多路数据传输链路，每路数据传输链路包括权利要求1-3任一项中的差分锁存器电路。
  6. 根据权利要求5所述的开关驱动器，其中，所述多路数据传输链路包括用于传输真实数据的真实数据传输链路和用于传输Dummy数据的Dummy数据传输链路。
  7. 根据权利要求5所述的开关驱动器，还包括：
    多个异或逻辑单元，每个所述异或逻辑单元的第一输入端连接各数据传输链路中的所述差分锁存器电路的输出端，所述异或逻辑单元的第二输入端连接时钟输入端；
    多个数据选择器，每个所述数据选择器的第一输入端连接所述各路数据传输链路中差分锁存器电路的输出端，每个所述数据选择器的第二输入端分别连接所述异或逻辑单元的输出端。
  8. 一种数模转换电路，包括权利要求4-6任一项中的开关驱动器以及与所述开关驱动器的输出端连接的数模转换核心电路。
  9. 根据权利要求8所述的数模转换电路，其中，所述数模转换核心电路包括多个数模转换器核心单元，每个所述数模转换器核心单元包括：
    反相器，所述反相器的输入端连接至所述开关驱动器单元的真实数据传输链路的输出端；
    第一Dummy负载，所述第一Dummy负载连接所述开关驱动器单元的所述Dummy数据传输链路的输出端。
  10. 根据权利要求8所述的数模转换电路，其中，所述数模转换核心电路包括多个数模转换器核心单元，每个所述数模转换器核心单元包括：
    第六PMOS管，所述第六PMOS管的栅极连接所述驱动器单元的所述真实数据传输链路的输出端，所述第六PMOS管漏极连接负载电阻以及所述数模转换核心电路的输出端，所述第六PMOS管的源极连接电源电压；
    第二Dummy负载，所述第二Dummy负载连接所述开关驱动器单元的所述Dummy数据传输链路的输出端。
PCT/CN2023/113430 2022-08-26 2023-08-17 一种差分锁存器电路、开关驱动器以及数模转换电路 WO2024041437A1 (zh)

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