WO2024041267A1 - 音频功放电路及其占空比调制电路和噪音抑制电路 - Google Patents

音频功放电路及其占空比调制电路和噪音抑制电路 Download PDF

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Publication number
WO2024041267A1
WO2024041267A1 PCT/CN2023/107684 CN2023107684W WO2024041267A1 WO 2024041267 A1 WO2024041267 A1 WO 2024041267A1 CN 2023107684 W CN2023107684 W CN 2023107684W WO 2024041267 A1 WO2024041267 A1 WO 2024041267A1
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Prior art keywords
signal
logic
output
duty cycle
terminal
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PCT/CN2023/107684
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English (en)
French (fr)
Inventor
刘贺
于翔
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骏盈半导体(上海)有限公司
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Publication of WO2024041267A1 publication Critical patent/WO2024041267A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit

Definitions

  • the present invention relates to the technical field of audio power amplifiers, and more specifically, to an audio power amplifier circuit and its duty cycle modulation circuit and noise suppression circuit.
  • Class D amplifier circuit is a switching type power amplifier circuit. Compared with linear power amplifier circuits, it has the characteristics of high efficiency and low heat generation. Therefore, it is often used as an audio power amplifier circuit and is widely used in consumer electronics products such as smart TVs and mobile phones.
  • Figure 1 shows a circuit schematic diagram of an existing two-stage audio power amplifier circuit.
  • the audio power amplifier circuit 100 includes an integral amplifier module 110 , a signal modulation module 120 and a drive output module 130 .
  • the integral amplifier module 110 includes a first-stage integral amplifier AMP1 and a second-stage integral amplifier AMP2.
  • a pair of differential signals INA and INB are respectively coupled to the input of the first-stage integral amplifier AMP1 through a capacitor Cin and a resistor Rin, and pass through the first
  • the first-stage integral amplifier AMP1 and the second-stage integral amplifier AMP2 perform fully differential amplification and then output signals OPA and OPB.
  • the output signals OPA and OPB are respectively modulated by the comparators CMP1 and CMP2 in the signal modulation module 120 and a modulation signal RAMP to generate pulse width modulation signals PWMA and PWMB.
  • the driving output module 130 amplifies the power of the pulse width modulation signals PWMA and PWMB through the alternate operation of the transistor half-bridges, and generates the driving signals OUTA and OUTB.
  • Feedback resistors Rfb1 and Rfb2 are used to feed back the drive signals OUTA and OUTB to the input terminals.
  • the driving signal output by the driving output module 130 can be directly transmitted to the speaker and restored to an audio signal (the speaker itself has a certain low-pass filtering capability) or restored to an audio signal through a low-pass filter circuit and transmitted to the speaker for playback.
  • the purpose of the present invention is to provide an audio power amplifier circuit and its duty cycle modulation circuit and noise suppression circuit, which can weaken the "POP" noise during the startup or shutdown process of the chip by controlling the gain of the audio power amplifier circuit, while satisfying the requirements. High linearity of the circuit while reducing costs.
  • a duty cycle modulation circuit of an audio power amplifier circuit includes an integral amplification module and an input of a second-stage integral amplifier provided in the integral amplification module.
  • a high-frequency switch between resistors, the duty cycle modulation circuit is used to adjust the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch, wherein the duty cycle modulation circuit includes: a counting module for counting pulses of a duty cycle modulated signal to obtain a first count value; a second counting module for counting pulses of a clock signal to obtain a second count value; and a logic output A module configured to perform logical operations according to the first count value, the second count value and the clock signal to obtain a switch modulation signal for controlling the high-frequency switch.
  • the logic output module is configured to determine the pulse width of the switch modulation signal based on the first count value, and determine the switching period of the switch modulation signal based on the second count value.
  • the duty cycle modulation circuit further includes: a first detection module, configured to provide a first detection signal to the logic output module when the first count value is 0, and the logic output module is based on the The first detection signal puts the switch modulation signal into an initial level state.
  • a first detection module configured to provide a first detection signal to the logic output module when the first count value is 0, and the logic output module is based on the The first detection signal puts the switch modulation signal into an initial level state.
  • the duty cycle modulation circuit further includes: a second detection module configured to provide a third value to the first counting module and the logic output module when the first count value reaches a first preset value. Two detection signals, the first counting module stops counting pulses of the duty cycle modulation signal in response to the second detection signal, and the logic output module modulates the switch in response to the second detection signal The signal is placed at its final level.
  • the duty cycle modulation circuit further includes: a third detection module for outputting a third detection signal when the second count value reaches a second preset value; and a first NOR gate for Perform a NOR logic operation on the third detection signal and the first detection signal to provide a first logic signal to the second counting module, wherein the first NOR gate is used to perform a logical operation on the first detection signal.
  • the second counting module is reset.
  • the first counting module includes: a first D flip-flop, which has a first data signal input terminal, a first clock control terminal, a first reset terminal and a first signal output terminal.
  • the first data signal The input terminal is used to receive the duty cycle modulation signal, the first clock control terminal is used to receive the clock signal, the first reset terminal is used to receive the reset signal, and the first signal output terminal is used to output a second logic signal; a second NOR gate for performing a NOR logic operation on the second detection signal, the second logic signal and the inversion of the reset signal, and outputting a third logic signal; and a first Counter, which has a second clock control terminal, a second reset terminal and a second signal output terminal, the second clock control terminal is used to receive the third logic signal, and the second reset terminal is used to receive the reset signal, and the second signal output terminal is used to output the first count value.
  • the second counting module includes: a second counter having a third clock control terminal, a third reset terminal and a third signal output terminal, the third clock control terminal being used to receive the clock signal, The third reset terminal is used to receive the first logic signal, and the third signal output terminal is used to output the second count value.
  • the logic output module includes: a logic unit having first and second counting input terminals, a fourth clock control terminal, a fourth reset terminal and a fourth signal output terminal, the first counting input terminal is used to receive The first count value, the second count input terminal is used to receive the second count value, the fourth clock control terminal is used to receive the clock signal, and the fourth reset terminal is used to receive the reset signal, so The fourth signal output terminal is used to output a fourth logic signal; a second D flip-flop has a second data signal input terminal, a fifth clock control terminal, a fifth reset terminal and a fifth signal output terminal, and the second The data signal input terminal is used to receive the power supply voltage, the fifth clock control terminal is used to receive the fourth logic signal, the fifth reset terminal is used to receive the first logic signal, and the fifth signal output terminal Used to output the fifth logic signal; the third D flip-flop has a third data signal input terminal, a sixth clock control terminal, a sixth reset terminal and a sixth signal output terminal, the third data signal input terminal is used for Receive the fifth logic signal
  • the logic unit is configured to determine whether the first count value and the second count value are equal before each falling edge of the clock signal. If they are equal, the fourth count value is The logic signal is asserted to a logic high level.
  • the first count value and the second count value are composed of multi-bit binary numbers, and the first counter and the second counter are implemented by synchronous counters.
  • the synchronous counter includes: multiple D flip-flops with the same number of digits as the multi-bit binary number, and the clock control end of the first D flip-flop among the multiple D flip-flops is used to receive a counting signal; and a plurality of signal transmission units located before the second to the last D flip-flop among the plurality of D flip-flops, wherein each signal transmission unit is configured to trigger according to the D flip-flop before the corresponding D flip-flop The signal of the clock control terminal of the corresponding D flip-flop is obtained from the output logic state of the device and the inverted signal of the counting signal.
  • each of the signal transmission units is configured to: determine whether the output logic state of all D flip-flops before its corresponding D flip-flop is a logic high level, and if it is a logic high level, control the output logic state of its corresponding D flip-flop.
  • the signal at the clock control terminal of the D flip-flop is the same as the count signal; otherwise, the signal controlling the clock control terminal of the corresponding D flip-flop is always at a logic high level.
  • the signal transmission unit includes at least one NAND gate or a combination of at least one NAND gate and an inverter.
  • the frequency of the clock signal is set by the frequency of the switch modulation signal and the linearity of duty cycle change required by the system.
  • the frequency of the duty cycle modulation signal is set by the time of chip switching or shutdown.
  • a noise suppression circuit for an audio power amplifier circuit at least includes an integral amplification module, a signal modulation module and a drive output module, wherein the noise suppression circuit It includes: a high-frequency switch arranged between the input resistors of the second-stage integrating amplifier in the integrating amplifier module; and the above-mentioned duty cycle modulation circuit, which is used to control the duty cycle of the high-frequency switch. To adjust the gain of the audio power amplifier circuit.
  • an audio power amplifier circuit including: an integral amplification module, including at least a first-stage operational amplifier and a second-stage integral amplifier, for amplifying a differential input signal through an integral operation to obtain a differential output signal; a signal modulation module for generating a first pulse width modulation signal and a second pulse width modulation signal according to the differential output signal; a driving output module for respectively amplifying the first pulse width modulation signal and the a second pulse width modulation signal to obtain a driving signal for driving the speaker; a high-frequency switch provided between the input resistors of the second-stage integral amplifier in the integral amplifier module; and the above-mentioned duty cycle modulation circuit, For adjusting the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch.
  • an integral amplification module including at least a first-stage operational amplifier and a second-stage integral amplifier, for amplifying a differential input signal through an integral operation to obtain a differential output signal
  • a signal modulation module for generating a first pulse width modulation signal
  • the audio power amplifier circuit of the embodiment of the present invention includes a high-frequency switch and a duty cycle modulation circuit arranged between the input resistors of the second-stage integration amplifier of the integration amplification module.
  • the duty cycle modulation circuit is in the process of turning on or off the chip.
  • the switching modulation signal of the high-frequency switch is generated by counting the duty cycle modulation signal and the clock signal, so that the duty cycle of the high-frequency switch can be gradually reduced or increased according to the set linearity to adjust the audio power amplifier
  • the gain of the circuit can not only weaken the "POP" noise, but also improve the linearity of the circuit and reduce the cost of the circuit.
  • the present invention also provides a synchronous counter for counting.
  • the synchronous counter can pre-judge the clock control signal of each D flip-flop in the counter before the clock control signal is input. Whether the outputs of all D flip-flops before the D flip-flop are logic high levels. If the outputs of all D flip-flops before the D flip-flop are logic high levels, then the clock control signal of the D flip-flop is controlled. It is the same as the counting signal. On the contrary, the clock control signal of the D flip-flop is set to a logic high level, so that the output delay of the counter can be only the delay of one D flip-flop, which greatly reduces the delay of the counter.
  • Figure 1 shows a circuit schematic diagram of an existing two-stage audio power amplifier circuit
  • Figure 2 shows a circuit schematic diagram of an audio power amplifier circuit with noise suppression capability according to an embodiment of the present invention
  • Figure 3 shows a circuit schematic diagram of a duty cycle modulation circuit according to an embodiment of the present invention
  • Figure 4 shows an operating timing diagram of a duty cycle modulation circuit according to an embodiment of the present invention
  • Figure 5 shows a working timing diagram of the first counting module according to an embodiment of the present invention
  • Figure 6 shows a schematic circuit diagram of a synchronous counter according to an embodiment of the present invention.
  • circuit refers to a conductive loop composed of at least one element or sub-circuit through electrical connection or electromagnetic connection.
  • FIG. 2 shows a circuit schematic diagram of an audio power amplifier circuit with noise suppression capability according to an embodiment of the present invention.
  • the audio power amplifier circuit 200 includes an integral amplifier module 210 , a signal modulation module 220 , a drive output module 230 , a high-frequency switch K1 and a duty cycle modulation circuit 300 .
  • the integral amplifier module 210 includes a first-stage operational amplifier AMP1 and a second-stage integral amplifier AMP2.
  • a pair of differential input signals INA and INB are respectively coupled to the input of the first-stage operational amplifier AMP1 through the input capacitor Cin and the input resistor Rin.
  • the differential output signals OPA and OPB are obtained.
  • the differential input signals INA and INB are converted into current signals through resistors and then input to the first-stage operational amplifier AMP1.
  • a voltage signal is output.
  • the voltage signal is converted into a current signal input through resistors R5 ⁇ R8.
  • the second-stage integrating amplifier AMP2 integrates, operates and amplifies and outputs differential output signals OPA and OPB.
  • the differential output signals OPA and OPB are voltage signals.
  • feedback resistors R3 and R4 are provided between the input terminal and the output terminal of the first-stage operational amplifier AMP1.
  • Integrating capacitors C1 and C2 are also provided between the differential input terminal and the differential output terminal of the second-stage integrating amplifier AMP2.
  • the signal modulation module 220 is configured to respectively input the modified differential output signals OPA and OPB, and generate the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB according to the differential output signals OPA and OPB.
  • the first pulse width modulation signal PWMA is modulated by the differential output signal OPA
  • the second pulse width modulation signal PWMB is modulated by the differential output signal OPB.
  • the signal modulation module 220 may include two parallel comparators CMP1 and CMP2.
  • the comparator CMP1 is used to compare the differential output signal OPA and the modulation signal RAMP, and output the first pulse width modulation signal PWMA.
  • the comparator CMP2 is used to compare the differential output signal OPB and the modulation signal RAMP, and output a second pulse width modulation signal PWMB.
  • the modulation signal RAMP is usually a waveform with periodic rising and falling edges such as a triangle wave or a sawtooth wave.
  • the two differential signals can be easily modulated into PWM signals.
  • the signal modulation module 220 can also use other circuit structures to implement PWM modulation.
  • the driving output module 230 is used to respectively amplify the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB to obtain driving signals OUTA and OUTB.
  • the driving output module 230 may be implemented using a half-bridge circuit, which includes two transistors connected in series between a power supply and ground. When the input pulse width modulation signal is high level, the transistor connected to the power supply is turned on, and the transistor connected to the ground is turned off, thereby outputting the voltage and current limited by the power supply. When the input pulse width modulation signal is low level, the transistor connected to the ground is turned on and the transistor connected to the power supply is turned off, thereby amplifying the PWM signal.
  • the integral amplifier module 210 and the signal modulation module 220 in this embodiment are usually powered by the low-voltage domain power supply VDD generated by the low-voltage linear regulator (LDO) (not shown in the figure) inside the chip.
  • VDD is usually It is about 4V ⁇ 6V
  • the power supply of the driving output module 230 usually uses the high-voltage domain power supply PVDD input from outside the chip (not shown in the figure), which can be as low as 4V and as high as 30V, usually around 20V ⁇ 30V.
  • the audio power amplifier circuit 200 of this embodiment also includes a feedback circuit connected between the differential output terminal of the driving output module 230 and the differential input terminal of the second-stage integrating amplifier AMP2.
  • the feedback circuit consists of two feedback resistors Rfb1 and Rfb2.
  • the feedback resistor Rfb1 is connected between the first output terminal of the driving output module 230 and the first input terminal of the second-stage integrating amplifier AMP2
  • the feedback resistor Rfb2 is connected between the second output terminal of the driving output module 230 and the second-stage integrating amplifier. between the second input terminals of amplifier AMP2.
  • the high-frequency switch K1 is set between the input resistors R5 ⁇ R8 of the second-stage integral amplifier AMP2 in the integral amplifier module 210, and the duty cycle modulation circuit 300 is used to generate a conductor that controls the high-frequency switch K1.
  • the on and off switch signals are controlled, and the duty cycle of the high-frequency switch K1 is controlled by controlling the duty cycle of the switch signal to adjust the gain of the audio power amplifier circuit 200, thereby weakening the "POP" noise.
  • the duty cycle of the control signal generated by the duty cycle modulation circuit 300 of the high-frequency switch K1 is 100%, that is, the high-frequency switch K1 remains in the on state.
  • the circuit The gain is 0, and then the duty cycle modulation circuit 300 gradually reduces the duty cycle of the high-frequency switch K1 according to the set linearity until the duty cycle of the switch signal is 0, at which time the gain of the circuit reaches the normal gain.
  • the duty cycle modulation circuit 300 gradually increases the duty cycle of the high-frequency switch according to the set linearity until the duty cycle of the high-frequency switch K1 reaches 100%.
  • FIG. 3 shows a circuit schematic diagram of a duty cycle modulation circuit 300 according to an embodiment of the present invention.
  • the digital duty cycle modulation circuit 300 provided in this embodiment includes a first counting module 310, a second counting module 320, a logic output module 330, a NOR gate NOR1, and first to third detection modules 340 ⁇ 360.
  • the first counting module 310 is configured to receive the duty cycle modulation signal CTRL_in, and count the pulses of the duty cycle modulation signal CTRL_in to obtain the first count value CONT1.
  • the second counting module 320 is used to count the pulses of the clock signal CLK and obtain the second count value CONT2.
  • the first count value CONT1 and the second count value CONT2 are, for example, multi-bit binary numbers.
  • the logic output module 330 is configured to perform logic operations according to the first count value CONT1, the second count value CONT2 and the clock signal CLK, and finally output switching modulation signals Fade_in and Fade_out.
  • the switch modulation signal Fade_in is used to control the duty cycle change of the high-frequency switch K1 during the chip startup process
  • the switch modulation signal Fade_out is used to control the duty cycle change of the high-frequency switch K1 during the chip shutdown process.
  • the switch modulation signals Fade_in and Fade_out are signals with opposite phases to each other.
  • the duty cycle of the switch modulation signal refers to the ratio of its high level time to the switching period
  • the logic output module 330 is configured to determine the pulses of the switch modulation signal Fade_in and Fade_out based on the first count value CONT1 width (ie, high level time), and determine the switching period of the switching modulation signal Fade_in and Fade_out based on the second count value CONT2, and finally the duty cycle of the switching modulation signal can be controlled.
  • the first detection module 340 is used to detect the first count value CONT1, and is configured to output a first detection signal T1 to the logic output module 330 when the first count value CONT1 is 0.
  • the second detection module 350 is used to detect the first count value CONT1, and is configured to output a second detection signal T2 to the logic output module 330 when the first count value CONT1 reaches a first preset value
  • the third detection module 360 is used to detect the second count value CONT2, and is configured to output a third detection signal T3 when the second count value CONT2 reaches a second preset value.
  • One input terminal of the NOR gate NOR1 is used to receive the third detection signal T3, the other input terminal is used to receive the first detection signal T1, and the output terminal is used to provide a logic signal B1 to the logic output module.
  • the first preset value is used to define the total time period of the chip startup process or the shutdown process, and the second preset value is used to define the switching period of the switch modulation signal.
  • the first counting module 310 includes a D flip-flop 301, a NOR gate NOR2, an inverter INV1 and a first counter 302.
  • the D flip-flop 301 has a data signal input terminal D, a clock control terminal Clk, a reset terminal NCLR (also called a clear terminal), and signal output terminals Q and QN.
  • the data signal input terminal D of the D flip-flop 301 is used to receive the duty cycle modulation signal CTRL_in, the clock control terminal Clk is connected to the clock signal CLK, the reset terminal NCLR is connected to the reset signal Reset, and the signal output terminal QN is used to output a logic signal.
  • CTRL_in the duty cycle modulation signal CTRL_in
  • the clock control terminal Clk is connected to the clock signal CLK
  • the reset terminal NCLR is connected to the reset signal Reset
  • the signal output terminal QN is used to output a logic signal.
  • One input terminal of the NOR gate NOR2 is used to receive the second detection signal T2, the second input terminal is connected to the signal output terminal QN of the D flip-flop 301 to receive the logic signal B2, and the third input terminal It is connected to the output of the inverter INV1 for receiving the inverted signal of the reset signal Reset.
  • the first counter 302 has a clock control terminal Clk, a reset terminal NCLR and an output terminal Out.
  • the clock control terminal is connected to the output terminal of the NOR gate NOR2 to receive the logic signal B3.
  • the reset terminal NCLR is connected to the reset signal Reset.
  • the output terminal Out is used to output the first count value CONT1.
  • the second counting module 320 includes a second counter 303 having a clock control terminal Clk, a reset terminal NCLR and an output terminal Out.
  • the clock control terminal Clk of the second counter 303 is connected to the clock signal CLK
  • the reset terminal NCLR is connected to the output terminal of the NOR gate NOR1
  • the output terminal Out is used to output the second count value CONT2.
  • Logic output module 330 includes logic unit 304, D flip-flops 305 and 306, NOR gates NOR3 and NOR4, and inverters INV2 and INV3.
  • the logic unit 304 has counting input terminals A and B, a clock control terminal Clk, a reset terminal NCLR and an output terminal Out.
  • the counting input terminal A of the logic unit 304 is used to receive the first count value CONT1
  • the counting input terminal B is used to receive the first count value CONT1.
  • the clock control terminal Clk is used to receive the clock signal CLK
  • the reset terminal NCLR is used to receive the reset signal Reset
  • the output terminal Out is used to output the logic signal B4.
  • the data signal input terminal D of the D flip-flop 305 is used to receive the power supply voltage Vdd
  • the clock control terminal Clk is connected to the output terminal of the logic unit 304 to receive the logic signal B4
  • the reset terminal NCLR is connected to the NOR gate.
  • the output terminal of NOR1 is connected, and the signal output terminal QN is used to output the logic signal B5.
  • the data signal input terminal D of the D flip-flop 306 is connected to the signal output terminal QN of the D flip-flop 305 to receive the logic signal B5, the clock control terminal Clk receives the clock signal CLK, and the reset terminal NCLR is connected to the output of the inverter INV2.
  • the signal output terminal Q is used to output the logic signal B6.
  • One input terminal of the NOR gate NOR3 is connected to the output terminal of the second detection module 350 to receive the second detection signal T2, and the other input terminal is connected to the signal output terminal Q of the D flip-flop 306 to receive the logic signal output by it. B6.
  • One input terminal of the NOR gate NOR4 is connected to the output terminal of the first detection module 340 to receive the first detection signal T1, and the other input terminal is connected to the output terminal of the NOR gate NOR3 to receive its output logic signal B7.
  • the output terminal Used to output the switch modulation signal Fade_out.
  • the input terminal of the inverter INV3 is connected to the output terminal of the NOR gate NOR4, and its output terminal is used to output the switching modulation signal Fade_in.
  • FIG. 4 shows an operating timing diagram of a duty cycle modulation circuit according to an embodiment of the present invention, which respectively shows the reset signal Reset, the duty cycle modulation signal CTRL_in, the clock signal CLK, the output signal B4 of the logic unit 304 and the switch. Timing diagram of modulated signals Fade_in and Fade_out.
  • the working principle of the duty cycle modulation circuit of the embodiment of the present invention will be described in detail below with reference to FIG. 3 and FIG. 4 , taking the chip shutdown process as an example.
  • the reset terminal NCLR of the D flip-flop, counter and logic unit in the circuit is active at low level.
  • the reset signal Reset is set to a logic low level
  • each module in the circuit is reset, and the output of the first counter 302 is reset to zero.
  • the first detection signal T1 output by the first detection module 340 flipped to a logic high level
  • the switch modulation signal Fade_out is set to the initial level state, that is, a logic low level (at this time, the duty cycle of the switch modulation signal Fade_out is 0).
  • the second counter 303, D flip-flop 305 and D flip-flop 306 are reset at the same time.
  • the reset signal Reset is set to a logic high level, and each module in the circuit exits the reset state.
  • the pulse signal CTRL_in is input through the duty cycle modulation pin, and at the same time, the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in.
  • the value of the first count value CONT1 is ⁇ 000 ⁇ 001 >.
  • Figure 5 shows a working timing diagram of the first counting module according to an embodiment of the present invention.
  • the D flip-flop 301 determines the output signal B2 according to the logic state of the duty cycle modulation signal CTRL_in of the data signal input terminal D before each rising edge of the clock signal CLK.
  • the logic state finally gets the waveform of logic signal B2. Since the outputs of the second detection signal T2 and the inverter INV1 are both low level at this time, the logic signal B3 output by the NOR gate NOR2 has completely opposite waveforms to the logic signal B2.
  • the first counter 302 is effective before each rising edge of the logic signal B3, counts the pulses of the signal B3, and outputs the first count value CONT1. Since the phase of the signal B3 is the same as the duty cycle modulation signal CTRL_in, the first counter 302 It is equivalent to counting the pulses of the duty cycle modulation signal CTRL_in.
  • the second detection signal T2 output by the second detection module 350 flips to a logic high level. At this time, the output signal B3 of the NOR gate NOR2 flips to a logic low level, and the first counter 302 stops pulse counting.
  • the output signal B7 of the NOR gate NOR3 flips to a logic low level, because after the first counting module 310 starts counting, the first count value CONT1 is no longer 0, so the first detection signal T1 is also at a logic low level at this time, and then the output of the NOR gate NOR4 is set to a logic high level, corresponding to the switch modulation signal Fade_out being set to a logic high level (at this time The duty cycle of the switch modulation signal Fade-out is 100%).
  • the second counter 303 starts to work, counts the pulses of the clock signal CLK, and outputs the second count value CONT2.
  • the D flip-flop 306 outputs the logic high level of the signal output terminal QN of the D flip-flop 305 in the reset phase to its signal output terminal Q, or the NOR gate NOR3 sets the signal B7 to a logic low level according to the logic high level signal B6, and the NOR gate NOR4 sets the switch modulation signal Fade_out to a high level according to the logic low level detection signal T1 and the signal B7.
  • the second count value CONT2 is equal to the first count value CONT1.
  • the logic unit 304 jumps the output signal B4 from a logic low level to a logic high level.
  • the D flip-flop 306 sets the switching modulation signal Fade_out to a logic low level.
  • the second counter 303 continues to count the pulses of the clock signal CLK.
  • the third detection module 360 outputs the third detection signal T3 and flips it to a high level.
  • the NOR gate NOR1 flips the signal B1 to a logic low level according to the high-level third detection signal T3, resets the D flip-flop 305 and the second counter 303, and a switching cycle of the switching modulation signal Fade_out ends, and so on. In subsequent switching cycles, the second counter 303 and the logic output module 330 continue to repeat the above process.
  • Figure 6 shows a schematic circuit diagram of a synchronous counter according to an embodiment of the present invention.
  • the key factor that limits the frequency of the clock signal CLK is the counting delay of the counter.
  • the counter is a binary counter composed of multiple D flip-flops connected in series. If the counter outputs more digits, then This delay will become a key factor that limits the frequency of the clock signal CLK.
  • this embodiment designs a new synchronous counter for the first counter 302 and the second counter 303, which greatly reduces the delay of the counter. reduce.
  • the synchronous counter 400 in this embodiment includes multiple D flip-flops DFF1 ⁇ DFF4 (this embodiment uses four D flip-flops as an example for explanation, and the present invention does not limit this) and multiple D flip-flops located in multiple D flip-flops.
  • a plurality of signal transmission units (signal transmission units 401 to 403 shown in FIG. 6 ) from the second D flip-flop DFF2 to the last D flip-flop DFF4 among the D flip-flops.
  • each signal transmission unit is configured to obtain the clock control signal of the D flip-flop connected to it based on the logic state of the signal output terminal Q of the previous D flip-flop and the inverted signal of the counting signal IN.
  • the data signal input terminals D of multiple D flip-flops DFF1 ⁇ DFF4 are connected to the signal output terminal QN, the clock control terminal Clk is used to receive the clock control signal, and the signal output terminal Q is used to output a multi-bit binary count value respectively.
  • the D flip-flop DFF1 also includes inverters INV4 and INV5 connected in sequence.
  • the input terminal of the inverter INV4 is used to receive the counting signal IN.
  • the output terminal is connected to the input terminal of the inverter INV5.
  • the output terminal of the inverter INV5 It is connected to the clock control terminal Clk of the D flip-flop DFF1, so the clock control signal of the D flip-flop DFF1 has the same waveform as the count signal IN.
  • the signal transmission unit 401 includes, for example, a NAND gate NAND1.
  • One input terminal of the NAND gate NAND1 receives the logic level of the signal output terminal Q of the D flip-flop DFF1, the other input terminal receives the inverted signal of the counting signal IN, and the output terminal is
  • the clock control terminal Clk of the D flip-flop DFF2 is connected to provide its clock control signal.
  • the signal transfer unit 402 includes, for example, a NAND gate NANB5, an inverter INV6, and a NAND gate NANB6.
  • One input terminal of the NAND gate NANB5 is connected to the signal output terminal Q of the D flip-flop DFF2, the other input terminal of the NAND gate NANB5 is connected to the signal output terminal of the D flip-flop DFF1, and the output terminal of the NAND gate NAND is connected to the inverting
  • the input terminal of the inverter INV6 is connected, the output terminal of the inverter INV6 is connected to an input terminal of the NAND gate NANB6, the other input terminal of the NAND gate NANB6 is connected to the inverted signal of the counting signal IN, and the output of the NAND gate NANB6
  • the terminal is connected to the clock control terminal of D flip-flop DFF3.
  • the signal transmission unit 402 is configured to perform a NAND logic operation on the output results of the D flip-flops DFF1 and DFF2.
  • the operation result is inverted by the inverter INV6 and then performed NAND logic with the inverted signal of the counting signal IN. operation, and finally obtain the clock control signal of D flip-flop DFF3.
  • the signal transfer unit 403 includes, for example, a NAND gate NAND4, an inverter INV7, and a NAND gate NAND5.
  • One input terminal of the NAND gate NAND4 is used to receive the AND logic operation result of the outputs of the D flip-flops DFF1 and DFF2, the other input terminal receives the output result of the D flip-flop DFF3, and the output terminal is connected to the input terminal of the inverter INV7.
  • One input terminal of the NAND gate NAND5 is connected to the output terminal of the inverter INV7, the other input terminal is connected to the inverted signal of the counting signal IN, and the output terminal is connected to the clock control terminal of the D flip-flop DFF4.
  • the NAND gate NAND4 is used to perform the AND logic operation result of the output logic of the D flip-flop DFF1 and DFF2 and the output logic of the D flip-flop DFF3.
  • the obtained result is inverted by the inverter INV7 to obtain D
  • the AND logic operation result of the output results of the flip-flops DFF1 to DFF3 is then performed a NAND logic operation with the inverted signal of the count signal IN, and finally the clock control signal of the D flip-flop DFF4 is obtained.
  • the synchronous counter provided in this embodiment can pre-determine the signal output terminals of all D flip-flops before the D flip-flop before the clock control signal of each D flip-flop in the counter is input by setting the signal transmission unit. Whether Q is a logic high level, if the signal output terminal Q of all D flip-flops before the D flip-flop is a logic high level, then the clock control signal of the D flip-flop is the same as the counting signal IN, otherwise, the clock control signal of the D flip-flop is the same as the counting signal IN. The clock control signal of the D flip-flop is always at a logic high level. Therefore, the output delay of the synchronous counter in this embodiment is only the delay of one D flip-flop, which greatly reduces the delay of the counter.
  • the audio power amplifier circuit of the embodiment of the present invention includes a high-frequency switch disposed between the input resistors of the second-stage integrating amplifier of the integrating amplifier module and a duty cycle modulation circuit.
  • the duty cycle modulation circuit is configured when the chip is turned on. Or during the shutdown process, the switching modulation signal of the high-frequency switch is generated by counting the duty cycle modulation signal and the clock signal, so that the duty cycle of the high-frequency switch can be gradually reduced or increased according to the set linearity.
  • the present invention also provides a synchronous counter for counting.
  • the synchronous counter can pre-judge the clock control signal of each D flip-flop in the counter before the clock control signal is input. Whether the outputs of all D flip-flops before the D flip-flop are logic high levels. If the outputs of all D flip-flops before the D flip-flop are logic high levels, then the clock control signal of the D flip-flop is controlled. It is the same as the counting signal. On the contrary, the clock control signal of the D flip-flop is set to a logic high level, so that the output delay of the counter can be only the delay of one D flip-flop, which greatly reduces the delay of the counter.

Abstract

本发明公开了一种音频功放电路及其占空比调制电路和噪音抑制电路，该音频功放电路包括积分放大模块以及设置在积分放大模块中的第二级积分放大器的输入电阻之间的高频开关，该占空比调制电路用于通过控制高频开关的占空比以调整音频功放电路的增益，其中，占空比调制电路包括：第一计数模块，用于对一占空比调制信号的脉冲进行计数，以获得第一计数值；第二计数模块，用于对时钟信号的脉冲进行计数，以获得第二计数值；以及逻辑输出模块，用于根据第一计数值、第二计数值以及时钟信号进行逻辑运算，以获得控制高频开关的开关调制信号，通过控制音频功放电路的增益来弱化芯片开机或关机过程中的"POP"噪音，在满足电路的高线性度的同时降低成本。

Description

音频功放电路及其占空比调制电路和噪音抑制电路
本申请要求了申请日为2022年08月24日、申请号为202211020372.1、名称为“音频功放电路及其占空比调制电路和噪音抑制电路”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本发明涉及音频功放技术领域，更具体地，涉及一种音频功放电路及其占空比调制电路和噪音抑制电路。
 背景技术
D类放大器电路是一种开关型的功放电路，其与线性功放电路相比，具有效率高、发热少的特点，因此常被作为音频功放电路广泛应用于智能电视、手机等消费电子产品领域。
图1示出了现有的两级音频功放电路的电路示意图。如图1所示，该音频功放电路100包括积分放大模块110、信号调制模块120和驱动输出模块130。
所述积分放大模块110包括第一级积分放大器AMP1和第二级积分放大器AMP2，一对差分信号INA和INB分别通过电容Cin和电阻Rin耦合至第一级积分放大器AMP1的输入，依次经过第一级积分放大器AMP1和第二级积分放大器AMP2进行全差分放大后输出信号OPA和OPB。输出信号OPA和OPB分别通过信号调制模块120中的比较器CMP1和比较器CMP2与一调制信号RAMP进行调制，产生脉宽调制信号PWMA和PWMB。驱动输出模块130通过晶体管半桥的交替工作将脉宽调制信号PWMA和PWMB进行功率放大，产生驱动信号OUTA和OUTB。反馈电阻Rfb1和Rfb2用于将驱动信号OUTA和OUTB反馈到输入端。在实际应用中，由驱动输出模块130输出的驱动信号可以直接传输至扬声器还原为音频信号（扬声器本身具有一定的低通滤波能力）或经由低通滤波电路还原为音频信号传输至扬声器播放。
现有的音频功放电路在上电或关断器件，会在输出端产生“POP”噪音，“POP”噪音会使得扬声器在功率放大器上电或关断时产生爆破音。小的“POP”噪音可能会让用户有不悦耳的感觉，而大的“POP”噪音更可能损坏扬声器。因此，如何抑制音频功放电路的“POP”噪音是非常重要的。
 发明内容
鉴于上述问题，本发明的目的在于提供一种音频功放电路及其占空比调制电路和噪音抑制电路，通过控制音频功放电路的增益来弱化芯片开机或关机过程中的“POP”噪音，在满足电路的高线性度的同时降低成本。
根据本发明实施例的第一方面，提供了一种音频功放电路的占空比调制电路，所述音频功放电路包括积分放大模块以及设置在所述积分放大模块中的第二级积分放大器的输入电阻之间的高频开关，所述占空比调制电路用于通过控制所述高频开关的占空比以调整所述音频功放电路的增益，其中，所述占空比调制电路包括：第一计数模块，用于对一占空比调制信号的脉冲进行计数，以获得第一计数值；第二计数模块，用于对时钟信号的脉冲进行计数，以获得第二计数值；以及逻辑输出模块，用于根据所述第一计数值、所述第二计数值以及所述时钟信号进行逻辑运算，以获得控制所述高频开关的开关调制信号。
可选的，所述逻辑输出模块配置为基于所述第一计数值确定所述开关调制信号的脉冲宽度，并基于所述第二计数值确定所述开关调制信号的开关周期。
可选的，所述占空比调制电路还包括：第一检测模块，用于在所述第一计数值为0时向所述逻辑输出模块提供第一检测信号，所述逻辑输出模块基于所述第一检测信号将所述开关调制信号置于初始电平状态。
可选的，所述占空比调制电路还包括：第二检测模块，用于在所述第一计数值达到第一预设数值时向所述第一计数模块和所述逻辑输出模块提供第二检测信号，所述第一计数模块响应于所述第二检测信号停止对所述占空比调制信号的脉冲进行计数，所述逻辑输出模块响应于所述第二检测信号将所述开关调制信号置于最终电平状态。
可选的，所述占空比调制电路还包括：第三检测模块，用于在所述第二计数值达到第二预设数值时输出第三检测信号；以及第一或非门，用于将所述第三检测信号与所述第一检测信号进行或非逻辑运算，向所述第二计数模块提供第一逻辑信号，其中，所述第一或非门用于在所述第一检测信号和所述第三检测信号之一有效时，将所述第二计数模块复位。
可选的，所述第一计数模块包括：第一D触发器，其具有第一数据信号输入端、第一时钟控制端、第一复位端以及第一信号输出端，所述第一数据信号输入端用于接收所述占空比调制信号，所述第一时钟控制端用于接收所述时钟信号，所述第一复位端用于接收复位信号，所述第一信号输出端用于输出第二逻辑信号；第二或非门，用于将所述第二检测信号、所述第二逻辑信号以及所述复位信号的反相进行或非逻辑运算，输出第三逻辑信号；以及第一计数器，其具有第二时钟控制端、第二复位端和第二信号输出端，所述第二时钟控制端用于接收所述第三逻辑信号，所述第二复位端用于接收所述复位信号，所述第二信号输出端用于输出所述第一计数值。
可选的，所述第二计数模块包括：第二计数器，其具有第三时钟控制端、第三复位端和第三信号输出端，所述第三时钟控制端用于接收所述时钟信号，所述第三复位端用于接收所述第一逻辑信号，所述第三信号输出端用于输出所述第二计数值。
可选的，所述逻辑输出模块包括：逻辑单元，其具有第一和第二计数输入端、第四时钟控制端、第四复位端和第四信号输出端，第一计数输入端用于接收所述第一计数值，第二计数输入端用于接收所述第二计数值，所述第四时钟控制端用于接收所述时钟信号，所述第四复位端用于接收复位信号，所述第四信号输出端用于输出第四逻辑信号；第二D触发器，其具有第二数据信号输入端、第五时钟控制端、第五复位端和第五信号输出端，所述第二数据信号输入端用于接收电源电压，所述第五时钟控制端用于接收所述第四逻辑信号，所述第五复位端用于接收所述第一逻辑信号，所述第五信号输出端用于输出第五逻辑信号；第三D触发器，其具有第三数据信号输入端、第六时钟控制端、第六复位端和第六信号输出端，所述第三数据信号输入端用于接收所述第五逻辑信号，所述第六时钟控制端用于接收所述时钟信号，所述第六复位端用于接收所述第一检测信号的反相信号，所述第六信号输出端用于输出第六逻辑信号；第三或非门，用于将所述第二检测信号与所述第六逻辑信号进行或非逻辑运算，输出第七逻辑信号；以及第四或非门，用于将所述第一检测信号与所述第七逻辑信号进行或非逻辑运算，输出所述开关调制信号。
可选的，所述逻辑单元配置为在所述时钟信号的每个下降沿来临之前判断所述第一计数值与所述第二计数值是否相等，若二者相等，则将所述第四逻辑信号置位为逻辑高电平。
可选的，所述第一计数值和所述第二计数值通过多位二进制数构成，所述第一计数器和所述第二计数器通过同步计数器实现。
可选的，所述同步计数器包括：与所述多位二进制数的位数相同的多个D触发器，所述多个D触发器中的第一个D触发器的时钟控制端用于接收计数信号；以及位于所述多个D触发器中的第二个至最后一个D触发器之前的多个信号传递单元，其中，每个信号传递单元用于根据对应的D触发器之前的D触发器的输出逻辑状态和所述计数信号的反相信号获得该对应的D触发器的时钟控制端的信号。
可选的，每个所述信号传递单元配置为：判断与其对应的D触发器之前的所有D触发器的输出逻辑状态是否为逻辑高电平，若为逻辑高电平，则控制与其对应的D触发器的时钟控制端的信号与所述计数信号相同；否则，则控制与其对应的D触发器的时钟控制端的信号恒为逻辑高电平。
可选的，所述信号传递单元包括至少一个与非门或者至少一个与非门和反相器的组合。
可选的，所述时钟信号的频率通过所述开关调制信号的频率和系统要求的占空比变化线性度来设置。
可选的，所述占空比调制信号的频率通过芯片开关或关机的时间来设置。
根据本发明实施例的第二方面，提供了一种用于音频功放电路的噪音抑制电路，所述音频功放电路至少包括积分放大模块、信号调制模块和驱动输出模块，其中，所述噪音抑制电路包括：设置在所述积分放大模块中的第二级积分放大器的输入电阻之间的高频开关；以及上述的占空比调制电路，所述用于通过控制所述高频开关的占空比以调整所述音频功放电路的增益。
根据本发明实施例的第三方面，提供了一种音频功放电路，包括：积分放大模块，至少包括第一级运算放大器和第二级积分放大器，用于将差分输入信号经过积分运算放大后得到差分输出信号；信号调制模块，用于根据所述差分输出信号生成第一脉宽调制信号和第二脉宽调制信号；驱动输出模块，用于分别放大所述第一脉宽调制信号和所述第二脉宽调制信号，以得到驱动扬声器的驱动信号；设置在所述积分放大模块中的第二级积分放大器的输入电阻之间的高频开关；以及上述的占空比调制电路，所述用于通过控制所述高频开关的占空比以调整所述音频功放电路的增益。
本发明实施例的音频功放电路包括设置在积分放大模块的第二级积分放大器的输入电阻之间的高频开关和占空比调制电路，该占空比调制电路在芯片开机或关机过程中，通过对占空比调制信号和时钟信号进行计数来产生该高频开关的开关调制信号，从而可以按照设定的线性度逐渐降低或增大该高频开关的占空比，以调整该音频功放电路的增益，不仅可以实现对“POP”噪音的弱化，而且可以提高电路的线性度，同时降低了电路的成本。
在进一步的实施例中，本发明还提供了一种用于计数的同步计数器，该同步计数器通过设置信号传递单元，可以在计数器中的每一个D触发器的时钟控制信号输入之前，预先判断该D触发器之前的所有的D触发器的输出是否为逻辑高电平，若该D触发器之前的所有的D触发器的输出均为逻辑高电平，则控制该D触发器的时钟控制信号与计数信号相同，反之，将该D触发器的时钟控制信号设置为逻辑高电平，从而可以将计数器的输出延时仅为一个D触发器的延时，大大降低了计数器的延时。
 附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了现有的两级音频功放电路的电路示意图；
图2示出了根据本发明实施例的具有噪音抑制能力的音频功放电路的电路示意图；
图3示出了根据本发明实施例的占空比调制电路的电路示意图；
图4示出了根据本发明实施例的占空比调制电路的工作时序图；
图5示出了根据本发明实施例的第一计数模块的工作时序图；
图6示出了根据本发明实施例的一种同步计数器的电路示意图。
 具体实施方式
以下基于实施例对本发明进行描述，但是本发明并不仅仅限于这些实施例。在下文对本发明的细节描述中，详尽描述了一些特定的细节部分。对本领域技术来说没有这些细节部分的描述也可以完全理解本发明。为了避免混淆本发明的实质，公知的方法、过程、流程、元件和电路并没有详细描述。
此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且这些附图不一定是按比例绘制的。
同时，应当理解，在以下的描述中，“电路”是指由至少一个元件或子电路通过电气连接或电磁连接构成的导电回路。当称元件或电路“连接到”另一元件或称元件/电路“连接在”两个节点之间时，它可以是直接耦接或连接到另一元件或者可以存在中间元件，元件之间的连接可以是物理上的、逻辑上的、或者其结合。相反，当称元件“直接耦接到”或“直接连接到”另一元件上时，意味着两者不存在中间元件。
下面结合附图和实施例对本发明进一步说明。
图2示出了根据本发明实施例的具有噪音抑制能力的音频功放电路的电路示意图。如图2所示，所述音频功放电路200包括积分放大模块210、信号调制模块220、驱动输出模块230、高频开关K1以及占空比调制电路300。
其中，积分放大模块210包括第一级运算放大器AMP1和第二级积分放大器AMP2，一对差分输入信号INA和INB分别通过输入电容Cin和输入电阻Rin耦合至第一级运算放大器AMP1的输入，依次经过第一级运算放大器AMP1和第二级积分放大器AMP2进行全差分放大后得到差分输出信号OPA和OPB。所述差分输入信号INA和INB经过电阻转换为电流信号后输入至第一级运算放大器AMP1，经过第一级运算放大器AMP1放大后输出电压信号，该电压信号经过电阻R5~R8转换为电流信号输入至第二级积分放大器AMP2，由第二级积分放大器AMP2积分运算放大后输出差分输出信号OPA和OPB，差分输出信号OPA和OPB为电压信号。进一步的，第一级运算放大器AMP1的输入端和输出端之间还设置有反馈电阻R3和R4。第二级积分放大器AMP2的差分输入端和差分输出端之间还设置有积分电容C1和C2。信号调制模块220用于分别输入修正后的差分输出信号OPA和OPB，并根据差分输出信号OPA和OPB生成第一脉宽调制信号PWMA和第二脉宽调制信号PWMB。其中，第一脉宽调制信号PWMA由差分输出信号OPA调制得到，第二脉宽调制信号PWMB由差分输出信号OPB调制得到。具体的，信号调制模块220可以包括两个并列的比较器CMP1和CMP2，比较器CMP1用于比较差分输出信号OPA和调制信号RAMP，输出第一脉宽调制信号PWMA。比较器CMP2用于比较差分输出信号OPB和调制信号RAMP，输出第二脉宽调制信号PWMB，所述调制信号RAMP通常为三角波或锯齿波等具有周期性的倾斜上升和倾斜下降边沿的波形。由此，可以方便地将两路差分信号调制为PWM信号。当然，信号调制模块220也可以采用其他电路结构来实现PWM调制。
驱动输出模块230用于分别放大第一脉宽调制信号PWMA和第二脉宽调制信号PWMB，得到驱动信号OUTA和OUTB。驱动输出模块230可以采用半桥电路实现，该半桥电路包括串联在电源和地之间的两个晶体管。在输入的脉宽调制信号为高电平时，与电源连接的晶体管导通，与地连接的晶体管关断，从而输出电源限定的电压和电流。在输入的脉宽调制信号为低电平时，与地连接的晶体管导通，与电源连接的晶体管关断，由此，可以将PWM信号放大。需要说明的是，本实施例的积分放大模块210和信号调制模块220通常采用芯片内部的低压差线性稳压器（LDO）（图中未示出）产生的低压域电源VDD进行供电，VDD通常为4V~6V左右，而所述驱动输出模块230的电源通常采用芯片外部输入的高压域电源PVDD（图中未示出），最低可到4V，最高可达30V，通常为20V~30V左右。
进一步的，本实施例的音频功放电路200还包括连接在驱动输出模块230的差分输出端和第二级积分放大器AMP2的差分输入端之间的反馈电路。具体的，反馈电路由两路反馈电阻Rfb1和Rfb2组成。其中，反馈电阻Rfb1连接在驱动输出模块230的第一输出端和第二级积分放大器AMP2的第一输入端之间，反馈电阻Rfb2连接在驱动输出模块230的第二输出端和第二级积分放大器AMP2的第二输入端之间。
本实施例中，高频开关K1设置在积分放大模块210中的第二级积分放大器AMP2的输入电阻R5~R8之间，占空比调制电路300用于生成控制所述高频开关K1的导通和关断的开关信号，并通过控制开关信号的占空比来控制高频开关K1的占空比，以调整所述音频功放电路200的增益，继而实现对“POP”噪音的弱化。
该实施例中，在芯片开机前，所述占空比调制电路300生成所述高频开关K1的控制信号的占空比为100%，即高频开关K1保持导通状态，此时电路的增益为0，继而占空比调制电路300按照设定的线性度逐渐降低所述高频开关K1的占空比，直到所述开关信号的占空比为0，此时电路的增益达到正常增益，当芯片关机时，所述占空比调制电路300按照设定的线性度逐渐增大所述高频开关的占空比，直到所述高频开关K1的占空比达到100%。
图3示出了根据本发明实施例的占空比调制电路300的电路示意图。如图3所示，本实施例提供的数字占空比调制电路300包括第一计数模块310、第二计数模块320、逻辑输出模块330、或非门NOR1以及第一至第三检测模块340~360。
第一计数模块310用于接收占空比调制信号CTRL_in，并对所述占空比调制信号CTRL_in的脉冲进行计数，获得第一计数值CONT1。第二计数模块320用于对时钟信号CLK的脉冲进行计数，并获得第二计数值CONT2。其中，第一计数值CONT1和第二计数值CONT2例如为多位二进制数。逻辑输出模块330用于根据所述第一计数值CONT1、第二计数值CONT2以及所述时钟信号CLK进行逻辑运算，最终输出开关调制信号Fade_in和Fade_out。其中，开关调制信号Fade_in用于控制所述高频开关K1在芯片开机过程中的占空比变化，开关调制信号Fade_out用于控制所述高频开关K1在芯片关机过程中的占空比变化。在该实施例中，开关调制信号Fade_in和Fade_out为相互反相的信号。
其中，开关调制信号的占空比指的是其高电平时间与开关周期的比值，所述逻辑输出模块330配置为基于所述第一计数值CONT1确定所述开关调制信号Fade_in和Fade_out的脉冲宽度（即高电平时间），并基于所述第二计数值CONT2确定所述开关调制信号Fade_in和Fade_out的开关周期，最终可以控制所述开关调制信号的占空比。
第一检测模块340用于对所述第一计数值CONT1进行检测，其配置为当所述第一计数值CONT1为0时向所述逻辑输出模块330输出第一检测信号T1。第二检测模块350用于对所述第一计数值CONT1进行检测，其配置为当所述第一计数值CONT1达到第一预设数值时向所述逻辑输出模块330输出第二检测信号T2，第三检测模块360用于对所述第二计数值CONT2进行检测，其配置为当所述第二计数值CONT2达到第二预设数值时输出第三检测信号T3。所述或非门NOR1的一个输入端用于接收所述第三检测信号T3，另一个输入端用于接收所述第一检测信号T1，输出端用于向所述逻辑输出模块提供逻辑信号B1。其中，所述第一预设数值用于限定所述芯片开机过程或关机过程的总的时间周期，所述第二预设数值用于限定所述开关调制信号的开关周期。
具体的，第一计数模块310包括D触发器301、或非门NOR2、反相器INV1以及第一计数器302。
其中，D触发器301具有数据信号输入端D、时钟控制端Clk、复位端NCLR（也称为清零端）以及信号输出端Q和QN。D触发器301的数据信号输入端D用于接收所述占空比调制信号CTRL_in，时钟控制端Clk与时钟信号CLK连接，复位端NCLR与复位信号Reset连接，信号输出端QN用于输出逻辑信号B2。或非门NOR2的一个输入端用于接收所述第二检测信号T2，第二个输入端与所述D触发器301的信号输出端QN连接以接收所述逻辑信号B2，第三个输入端与反相器INV1的输出连接，用于接收所述复位信号Reset的反相信号。第一计数器302具有时钟控制端Clk、复位端NCLR和输出端Out，其时钟控制端与所述或非门NOR2的输出端连接以接收逻辑信号B3，复位端NCLR与复位信号Reset连接，输出端Out用于输出所述第一计数值CONT1。
第二计数模块320包括第二计数器303，所述第二计数器303具有时钟控制端Clk、复位端NCLR和输出端Out。其中，所述第二计数器303的时钟控制端Clk与时钟信号CLK连接，复位端NCLR与所述或非门NOR1的输出端连接，输出端Out用于输出所述第二计数值CONT2。
逻辑输出模块330包括逻辑单元304、D触发器305和306、或非门NOR3和NOR4以及反相器INV2和INV3。其中，逻辑单元304具有计数输入端A和B、时钟控制端Clk、复位端NCLR和输出端Out，其计数输入端A用于接收所述第一计数值CONT1，计数输入端B用于接收所述第二计数值CONT2，时钟控制端Clk用于接收所述时钟信号CLK，复位端NCLR用于接收所述复位信号Reset，输出端Out用于输出逻辑信号B4。所述D触发器305的数据信号输入端D用于接收电源电压Vdd，时钟控制端Clk与所述逻辑单元304的输出端连接以接收所述逻辑信号B4，复位端NCLR与所述或非门NOR1的输出端连接，信号输出端QN用于输出逻辑信号B5。所述D触发器306的数据信号输入端D与D触发器305的信号输出端QN连接以接收逻辑信号B5，时钟控制端Clk接收所述时钟信号CLK，复位端NCLR与反相器INV2的输出连接以接收所述第一检测信号T1的反相信号，信号输出端Q用于输出逻辑信号B6。或非门NOR3的一个输入端与第二检测模块350的输出端连接以接收所述第二检测信号T2，另一个输入端与D触发器306的信号输出端Q连接以接收其输出的逻辑信号B6。或非门NOR4的一个输入端与第一检测模块340的输出端连接以接收第一检测信号T1，另一个输入端与或非门NOR3的输出端连接以接收其输出的逻辑信号B7，输出端用于输出开关调制信号Fade_out。反相器INV3的输入端与或非门NOR4的输出端连接，其输出端用于输出所述开关调制信号Fade_in。
图4示出了根据本发明实施例的占空比调制电路的工作时序图，其中分别示出了复位信号Reset、占空比调制信号CTRL_in、时钟信号CLK、逻辑单元304的输出信号B4以及开关调制信号Fade_in和Fade_out的时序图。以下结合图3和图4以芯片关机过程为例对本发明实施例的占空比调制电路的工作原理进行详细说明。
首先根据开关调制信号Fade_out的频率以及系统要求的占空比变化的线性度来设计输入时钟信号CLK的频率，假设开关调制信号Fade_out的输出频率为1M，要求的占空比变化的线性度为1%，则输入的时钟信号CLK的频率为：1M/1%=100M。接着根据开关调制信号Fade_out的时间要求来设计占空比调制信号CTRL_in的频率，假设芯片关机过程的时间为10ms，则占空比调制信号CTRL_in的周期为：10ms/100=0.1ms。
在本实施例中，电路中的D触发器、计数器以及逻辑单元的复位端NCLR为低电平有效。在时刻t0之前，复位信号Reset被置位为逻辑低电平，电路中的各个模块被复位，第一计数器302的输出被复位为零，此时第一检测模块340输出的第一检测信号T1翻转为逻辑高电平，将开关调制信号Fade_out置位为初始电平状态，即逻辑低电平（此时开关调制信号Fade_out的占空比为0）。同时将第二计数器303、D触发器305和D触发器306复位。在时刻t0之后，复位信号Reset被置位为逻辑高电平，电路中的各个模块退出复位状态。在时刻t1，通过占空比调制引脚输入脉冲信号CTRL_in，同时第一计数模块310对占空比调制信号CTRL_in的脉冲进行计数，此时第一计数值CONT1的数值为<000···001>。
图5示出了根据本发明实施例的第一计数模块的工作时序图。如图5所示，当复位信号Reset为逻辑高电平时，D触发器301在时钟信号CLK的每个上升沿之前根据数据信号输入端D的占空比调制信号CTRL_in的逻辑状态确定输出信号B2的逻辑状态，最终得到逻辑信号B2的波形。由于此时第二检测信号T2和反相器INV1的输出均为低电平，因此或非门NOR2输出的逻辑信号B3与逻辑信号B2的波形完全相反。第一计数器302在逻辑信号B3的每个上升沿之前有效，对信号B3的脉冲进行计数，输出第一计数值CONT1，由于信号B3与占空比调制信号CTRL_in的相位相同，因此第一计数器302相当于对占空比调制信号CTRL_in的脉冲进行计数。当第一计数值CONT1的数值达到第一预设数值m时（例如m=100，占空比调制信号CTRL_in的100个脉冲对应于开关调制信号的占空比变化的线性度要求为1%），第二检测模块350输出的第二检测信号T2翻转为逻辑高电平，此时或非门NOR2的输出信号B3翻转为逻辑低电平，第一计数器302停止脉冲计数。
继续参照图4，当第二检测信号T2为逻辑高电平时，或非门NOR3的输出信号B7翻转为逻辑低电平，由于在第一计数模块310开始计数之后第一计数值CONT1不再为0，因此此时第一检测信号T1也为逻辑低电平，继而或非门NOR4的输出被置位为逻辑高电平，对应于开关调制信号Fade_out被置位为逻辑高电平（此时开关调制信号Fade-out的占空比为100%）。当第一计数值CONT1的数值大于0且小于所述第一预设数值时，第二计数器303开始工作，对时钟信号CLK的脉冲进行计数，输出第二计数值CONT2。在时刻t2，D触发器306在时钟信号CLK每个周期的上升沿到来时，将在复位阶段D触发器305的信号输出端QN的逻辑高电平输出至其信号输出端Q，或非门NOR3根据逻辑高电平的信号B6将信号B7置位为逻辑低电平，或非门NOR4根据逻辑低电平的检测信号T1和信号B7将开关调制信号Fade_out置位为高电平。在时刻t3，第二计数值CONT2和第一计数值CONT1相等，逻辑单元304在时钟信号CLK的下降沿到来时，将输出信号B4由逻辑低电平跳变为逻辑高电平，当时钟信号CLK的下一个上升沿到来时，D触发器306将开关调制信号Fade_out置位为逻辑低电平。第二计数器303继续对时钟信号CLK的脉冲进行计数，当第二计数值CONT2达到第二预设数值（例如等于100）时，第三检测模块360输出第三检测信号T3翻转为高电平，或非门NOR1根据高电平的第三检测信号T3将信号B1翻转为逻辑低电平，将D触发器305和第二计数器303复位，开关调制信号Fade_out的一个开关周期结束，依次类推，在之后的开关周期中第二计数器303和逻辑输出模块330继续重复上述的过程。
图6示出了根据本发明实施例的一种同步计数器的电路示意图。在本实施例中，限制时钟信号CLK频率的关键因素是计数器的计数延时，在传统的设计中，计数器为多个D触发器串联构成的二进制计数器，如果计数器输出的位数较多，那么这个延时将成为限制时钟信号CLK频率的关键因素，为了将延时降到最低，本实施例为第一计数器302和第二计数器303设计了一种新的同步计数器，将计数器的延时大大降低。
如图6所示，本实施例的同步计数器400包括多个D触发器DFF1~DFF4（本实施例中以4个D触发器为例进行说明，本发明对此不做限制）以及位于多个D触发器中的第二个D触发器DFF2至最后一个D触发器DFF4之前的多个信号传递单元（如图6中示出的信号传递单元401~403）。其中，每个信号传递单元配置为根据之前的D触发器的信号输出端Q的逻辑状态以及计数信号IN的反相信号得到与之相连的D触发器的时钟控制信号。
具体的，多个D触发器DFF1~DFF4的数据信号输入端D与信号输出端QN相连，时钟控制端Clk用于接收时钟控制信号，信号输出端Q分别用于输出多位二进制的计数值的每一位<Q0Q1Q2Q3>。
D触发器DFF1之前还包括依次连接的反相器INV4和INV5，反相器INV4的输入端用于接收计数信号IN，输出端与反相器INV5的输入端连接，反相器INV5的输出端与D触发器DFF1的时钟控制端Clk连接，因此D触发器DFF1的时钟控制信号与计数信号IN的波形相同。
信号传递单元401例如包括与非门NAND1，与非门NAND1的一个输入端接收D触发器DFF1的信号输出端Q的逻辑电平，另一个输入端接收计数信号IN的反相信号，输出端与D触发器DFF2的时钟控制端Clk连接以提供其的时钟控制信号。
信号传递单元402例如包括与非门NANB5、反相器INV6和与非门NANB6。与非门NANB5的一个输入端与D触发器DFF2的信号输出端Q连接，与非门NANB5的另一个输入端与D触发器DFF1的信号输出端连接，与非门NAND的输出端与反相器INV6的输入端连接，反相器INV6的输出端和与非门NANB6的一个输入端连接，与非门NANB6的另一个输入端与计数信号IN的反相信号连接，与非门NANB6的输出端与D触发器DFF3的时钟控制端连接。其中，信号传递单元402被配置为将D触发器DFF1和DFF2的输出结果进行与非逻辑运算，该运算结果经过反相器INV6的反相之后再与计数信号IN的反相信号进行与非逻辑运算，最终得到D触发器DFF3的时钟控制信号。
信号传递单元403例如包括与非门NAND4、反相器INV7和与非门NAND5。与非门NAND4的一个输入端用于接收D触发器DFF1和DFF2的输出的与逻辑运算结果，另一个输入端接收D触发器DFF3的输出结果，输出端与反相器INV7的输入端连接。与非门NAND5的一个输入端与反相器INV7的输出端连接，另一个输入端与计数信号IN的反相信号连接，输出端与D触发器DFF4的时钟控制端连接。其中，与非门NAND4用于将D触发器DFF1和DFF2的输出逻辑的与逻辑运算结果和D触发器DFF3的输出逻辑进行与非逻辑运算，得到的结果经过反相器INV7的反相得到D触发器DFF1至DFF3的输出结果的与逻辑运算结果，该结果再与计数信号IN的反相信号进行与非逻辑运算，最终得到D触发器DFF4的时钟控制信号。
综上，本实施例提供的同步计数器通过设置信号传递单元，可以在计数器中的每一个D触发器的时钟控制信号输入之前，预先判断该D触发器之前的所有的D触发器的信号输出端Q是否为逻辑高电平，若该D触发器之前的所有的D触发器的信号输出端Q均为逻辑高电平，则该D触发器的时钟控制信号与计数信号IN相同，反之，该D触发器的时钟控制信号恒为逻辑高电平，因此本实施例的同步计数器的输出延时仅为一个D触发器的延时，将计数器的延时大大地降低了。
综上所述，本发明实施例的音频功放电路包括设置在积分放大模块的第二级积分放大器的输入电阻之间的高频开关和占空比调制电路，该占空比调制电路在芯片开机或关机过程中，通过对占空比调制信号和时钟信号进行计数来产生该高频开关的开关调制信号，从而可以按照设定的线性度逐渐降低或增大该高频开关的占空比，以调整该音频功放电路的增益，不仅可以实现对“POP”噪音的弱化，而且可以提高电路的线性度，同时降低了电路的成本。
在进一步的实施例中，本发明还提供了一种用于计数的同步计数器，该同步计数器通过设置信号传递单元，可以在计数器中的每一个D触发器的时钟控制信号输入之前，预先判断该D触发器之前的所有的D触发器的输出是否为逻辑高电平，若该D触发器之前的所有的D触发器的输出均为逻辑高电平，则控制该D触发器的时钟控制信号与计数信号相同，反之，将该D触发器的时钟控制信号设置为逻辑高电平，从而可以将计数器的输出延时仅为一个D触发器的延时，大大降低了计数器的延时。
本领域普通技术人员可以理解，本文中使用的与电路运行相关的词语“期间”、“当”和“当……时”不是表示在启动动作开始时立即发生的动作的严格术语，而是在其与启动动作所发起的反应动作（reaction）之间可能存在一些小的但是合理的一个或多个延迟，例如各种传输延迟等。本文中使用词语“大约”或者“基本上”意指要素值（element）具有预期接近所声明的值或位置的参数。然而，如本领域所周知的，总是存在微小的偏差使得该值或位置难以严格为所声明的值。本领域已恰当的确定了，至少百分之十（10%）（对于半导体掺杂浓度，至少百分之二十（20%））的偏差是偏离所描述的准确的理想目标的合理偏差。当结合信号状态使用时，信号的实际电压值或逻辑状态（例如“1”或“0”）取决于使用正逻辑还是负逻辑。
此外，还需要说明，在本文中的诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
依照本发明的实施例如上文，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims (17)

  1. 一种音频功放电路的占空比调制电路，所述音频功放电路包括积分放大模块以及设置在所述积分放大模块中的第二级积分放大器的输入电阻之间的高频开关，所述占空比调制电路用于通过控制所述高频开关的占空比以调整所述音频功放电路的增益，
    其中，所述占空比调制电路包括：
    第一计数模块，用于对一占空比调制信号的脉冲进行计数，以获得第一计数值；
    第二计数模块，用于对时钟信号的脉冲进行计数，以获得第二计数值；以及
    逻辑输出模块，用于根据所述第一计数值、所述第二计数值以及所述时钟信号进行逻辑运算，以获得控制所述高频开关的开关调制信号。
  2. 根据权利要求1所述的占空比调制电路，其中，所述逻辑输出模块配置为基于所述第一计数值确定所述开关调制信号的脉冲宽度，并基于所述第二计数值确定所述开关调制信号的开关周期。
  3. 根据权利要求1所述的占空比调制电路，还包括：
    第一检测模块，用于在所述第一计数值为0时向所述逻辑输出模块提供第一检测信号，
    所述逻辑输出模块基于所述第一检测信号将所述开关调制信号置于初始电平状态。
  4. 根据权利要求3所述的占空比调制电路，还包括：
    第二检测模块，用于在所述第一计数值达到第一预设数值时向所述第一计数模块和所述逻辑输出模块提供第二检测信号，
    所述第一计数模块响应于所述第二检测信号停止对所述占空比调制信号的脉冲进行计数，所述逻辑输出模块响应于所述第二检测信号将所述开关调制信号置于最终电平状态。
  5. 根据权利要求4所述的占空比调制电路，还包括：
    第三检测模块，用于在所述第二计数值达到第二预设数值时输出第三检测信号；以及
    第一或非门，用于将所述第三检测信号与所述第一检测信号进行或非逻辑运算，向所述第二计数模块提供第一逻辑信号，
    其中，所述第一或非门用于在所述第一检测信号和所述第三检测信号之一有效时，将所述第二计数模块复位。
  6. 根据权利要求5所述的占空比调制电路，其中，所述第一计数模块包括：
    第一D触发器，其具有第一数据信号输入端、第一时钟控制端、第一复位端以及第一信号输出端，所述第一数据信号输入端用于接收所述占空比调制信号，所述第一时钟控制端用于接收所述时钟信号，所述第一复位端用于接收复位信号，所述第一信号输出端用于输出第二逻辑信号；
    第二或非门，用于将所述第二检测信号、所述第二逻辑信号以及所述复位信号的反相进行或非逻辑运算，输出第三逻辑信号；以及
    第一计数器，其具有第二时钟控制端、第二复位端和第二信号输出端，所述第二时钟控制端用于接收所述第三逻辑信号，所述第二复位端用于接收所述复位信号，所述第二信号输出端用于输出所述第一计数值。
  7. 根据权利要求6所述的占空比调制电路，其中，所述第二计数模块包括：
    第二计数器，其具有第三时钟控制端、第三复位端和第三信号输出端，所述第三时钟控制端用于接收所述时钟信号，所述第三复位端用于接收所述第一逻辑信号，所述第三信号输出端用于输出所述第二计数值。
  8. 根据权利要求5所述的占空比调制电路，其中，所述逻辑输出模块包括：
    逻辑单元，其具有第一和第二计数输入端、第四时钟控制端、第四复位端和第四信号输出端，第一计数输入端用于接收所述第一计数值，第二计数输入端用于接收所述第二计数值，所述第四时钟控制端用于接收所述时钟信号，所述第四复位端用于接收复位信号，所述第四信号输出端用于输出第四逻辑信号；
    第二D触发器，其具有第二数据信号输入端、第五时钟控制端、第五复位端和第五信号输出端，所述第二数据信号输入端用于接收电源电压，所述第五时钟控制端用于接收所述第四逻辑信号，所述第五复位端用于接收所述第一逻辑信号，所述第五信号输出端用于输出第五逻辑信号；
    第三D触发器，其具有第三数据信号输入端、第六时钟控制端、第六复位端和第六信号输出端，所述第三数据信号输入端用于接收所述第五逻辑信号，所述第六时钟控制端用于接收所述时钟信号，所述第六复位端用于接收所述第一检测信号的反相信号，所述第六信号输出端用于输出第六逻辑信号；
    第三或非门，用于将所述第二检测信号与所述第六逻辑信号进行或非逻辑运算，输出第七逻辑信号；以及
    第四或非门，用于将所述第一检测信号与所述第七逻辑信号进行或非逻辑运算，输出所述开关调制信号。
  9. 根据权利要求8所述的占空比调制电路，其中，所述逻辑单元配置为在所述时钟信号的每个下降沿来临之前判断所述第一计数值与所述第二计数值是否相等，若二者相等，则将所述第四逻辑信号置位为逻辑高电平。
  10. 根据权利要求7所述的占空比调制电路，其中，所述第一计数值和所述第二计数值通过多位二进制数构成，所述第一计数器和所述第二计数器通过同步计数器实现。
  11. 根据权利要求10所述的占空比调制电路，其中，所述同步计数器包括：
    与所述多位二进制数的位数相同的多个D触发器，所述多个D触发器中的第一个D触发器的时钟控制端用于接收计数信号；以及
    位于所述多个D触发器中的第二个至最后一个D触发器之前的多个信号传递单元，
    其中，每个信号传递单元用于根据对应的D触发器之前的D触发器的输出逻辑状态和所述计数信号的反相信号获得该对应的D触发器的时钟控制端的信号。
  12. 根据权利要求11所述的占空比调制电路，其中，每个所述信号传递单元配置为：
    判断与其对应的D触发器之前的所有D触发器的输出逻辑状态是否为逻辑高电平，若为逻辑高电平，则控制与其对应的D触发器的时钟控制端的信号与所述计数信号相同；否则，则控制与其对应的D触发器的时钟控制端的信号恒为逻辑高电平。
  13. 根据权利要求12所述的占空比调制电路，其中，所述信号传递单元包括至少一个与非门或者至少一个与非门和反相器的组合。
  14. 根据权利要求1所述的占空比调制电路，其中，所述时钟信号的频率通过所述开关调制信号的频率和系统要求的占空比变化线性度来设置。
  15. 根据权利要求1所述的占空比调制电路，其中，所述占空比调制信号的频率通过芯片开关或关机的时间来设置。
  16. 一种用于音频功放电路的噪音抑制电路，所述音频功放电路至少包括积分放大模块、信号调制模块和驱动输出模块，其中，所述噪音抑制电路包括：
    设置在所述积分放大模块中的第二级积分放大器的输入电阻之间的高频开关；以及
    权利要求1-15任一项所述的占空比调制电路，所述用于通过控制所述高频开关的占空比以调整所述音频功放电路的增益。
  17. 一种音频功放电路，其中，包括：
    积分放大模块，至少包括第一级运算放大器和第二级积分放大器，用于将差分输入信号经过积分运算放大后得到差分输出信号；
    信号调制模块，用于根据所述差分输出信号生成第一脉宽调制信号和第二脉宽调制信号；
    驱动输出模块，用于分别放大所述第一脉宽调制信号和所述第二脉宽调制信号，以得到驱动扬声器的驱动信号；
    设置在所述积分放大模块中的第二级积分放大器的输入电阻之间的高频开关；以及
    权利要求1-15任一项所述的占空比调制电路，用于通过控制所述高频开关的占空比以调整所述音频功放电路的增益。
PCT/CN2023/107684 2022-08-24 2023-07-17 音频功放电路及其占空比调制电路和噪音抑制电路 WO2024041267A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100109773A1 (en) * 2008-10-20 2010-05-06 Rohm Co., Ltd. Class-D Amplifier
CN201781459U (zh) * 2010-06-30 2011-03-30 比亚迪股份有限公司 一种防破音的d类音频功率放大器
CN109995329A (zh) * 2018-01-03 2019-07-09 无锡华润矽科微电子有限公司 D类功放中实现静态噪音消除功能的电路及相应驱动电路
CN112910427A (zh) * 2021-01-13 2021-06-04 上海艾为电子技术股份有限公司 D类音频放大器及其自适应脉宽调整方法、电子设备
CN113852362A (zh) * 2021-12-01 2021-12-28 广东芯炽集成电路技术有限公司 一种用于高速模数转换器的占空比可调电路
CN115459720A (zh) * 2022-08-24 2022-12-09 骏盈半导体(上海)有限公司 音频功放电路及其占空比调制电路和噪音抑制电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100109773A1 (en) * 2008-10-20 2010-05-06 Rohm Co., Ltd. Class-D Amplifier
CN201781459U (zh) * 2010-06-30 2011-03-30 比亚迪股份有限公司 一种防破音的d类音频功率放大器
CN109995329A (zh) * 2018-01-03 2019-07-09 无锡华润矽科微电子有限公司 D类功放中实现静态噪音消除功能的电路及相应驱动电路
CN112910427A (zh) * 2021-01-13 2021-06-04 上海艾为电子技术股份有限公司 D类音频放大器及其自适应脉宽调整方法、电子设备
CN113852362A (zh) * 2021-12-01 2021-12-28 广东芯炽集成电路技术有限公司 一种用于高速模数转换器的占空比可调电路
CN115459720A (zh) * 2022-08-24 2022-12-09 骏盈半导体(上海)有限公司 音频功放电路及其占空比调制电路和噪音抑制电路

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