WO2024041122A1 - 高电子迁移率晶体管及其制备方法 - Google Patents

高电子迁移率晶体管及其制备方法 Download PDF

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WO2024041122A1
WO2024041122A1 PCT/CN2023/100463 CN2023100463W WO2024041122A1 WO 2024041122 A1 WO2024041122 A1 WO 2024041122A1 CN 2023100463 W CN2023100463 W CN 2023100463W WO 2024041122 A1 WO2024041122 A1 WO 2024041122A1
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layer
semiconductor layer
stress compensation
gate electrode
substrate
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PCT/CN2023/100463
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English (en)
French (fr)
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房育涛
刘浪
叶念慈
张洁
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湖南三安半导体有限责任公司
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Publication of WO2024041122A1 publication Critical patent/WO2024041122A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Definitions

  • the invention relates to the field of semiconductor devices, and in particular to a high electron mobility transistor and a preparation method thereof.
  • Gallium nitride-based compound semiconductor materials are widely used in high-voltage and high-frequency electronic devices and devices due to their advantages such as large bandgap, good thermal stability, radiation resistance, acid and alkali resistance, direct band gap, and easy formation of heterojunction device structures. Fabrication of light-emitting devices.
  • Gallium nitride-based high electron mobility transistor (HEMT) as an important gallium nitride electronic device, is widely used in high-power radio frequency applications and high-efficiency power conversion applications.
  • HEMT high electron mobility transistor
  • epitaxial device structure design and device manufacturing processes continue to improve, the radio frequency and power performance of gallium nitride HEMT devices have also continued to improve.
  • the biggest feature of gallium nitride power devices is that they can achieve higher withstand voltage and power density by optimizing materials and device processes.
  • the technical problem mainly solved by this disclosure is how to improve the operating voltage of gallium nitride-based compound semiconductor devices.
  • the first technical solution adopted by this disclosure is to provide a high electron mobility transistor.
  • the high electron mobility transistor includes:
  • the epitaxial layer is arranged on the surface of the substrate.
  • the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer are heterostructures.
  • the source electrode, the drain electrode and the gate electrode are spaced apart from each other on the epitaxial layer, and the gate electrode is provided between the source electrode and the drain electrode; wherein the gate electrode has sidewalls facing the drain electrode.
  • the stress compensation layer is disposed on the second semiconductor layer and contacts the sidewall of the gate; the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer.
  • the second technical solution adopted by the present disclosure is to provide a method for preparing a high electron mobility transistor.
  • the method for preparing a high electron mobility transistor includes:
  • a substrate is provided.
  • An epitaxial layer is formed on the surface of the substrate.
  • the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer are heterostructures.
  • a stress compensation layer is formed on the epitaxial layer, and the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer.
  • a source electrode, a drain electrode and a gate electrode are provided on the epitaxial layer, and the source electrode, drain electrode and gate electrode are spaced apart from each other; the gate electrode has a side wall facing the drain electrode, and the stress compensation layer is in contact with the side wall.
  • the embodiments of the present disclosure provide a high electron mobility transistor and a preparation method thereof.
  • the high electron mobility transistor includes a substrate, an epitaxial layer, a source electrode, a drain electrode, Gate and stress compensation layer: the epitaxial layer is arranged on the surface of the substrate.
  • the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer are different
  • the source electrode, the drain electrode and the gate electrode are spaced apart from each other on the epitaxial layer and the gate electrode is provided between the source electrode and the drain electrode; wherein, the gate electrode has sidewalls facing the drain electrode; the stress compensation layer is provided on the third on the second semiconductor layer and in contact with the sidewall of the gate; the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer.
  • the stress deformation under high voltage increases the breakdown electric field strength of the second semiconductor layer; at the same time, it can also reduce the two-dimensional electron gas concentration at the gate edge to adjust the electric field strength at the gate edge, thereby improving the voltage resistance of the device and reducing the risk of multiple level field plate requirements, thereby simplifying the device preparation process.
  • Figure 1 is a schematic structural diagram of an embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional structural diagram at A-A in Figure 1;
  • Figure 3 is a schematic structural diagram of another embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic flow chart of an embodiment of a method for manufacturing a high electron mobility transistor provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram corresponding to steps S1 to S5 in Figure 4;
  • Figure 6 is a schematic flow chart of an embodiment of step S3 in Figure 4;
  • Figure 7 is a schematic structural diagram corresponding to steps S311 to S313 in Figure 6;
  • FIG 8 is a schematic flow chart of another embodiment of step S3 in Figure 4;
  • FIG. 9 is a schematic structural diagram corresponding to steps S321 to S322 in FIG. 8 .
  • first”, “second” and “third” in the embodiments of the present disclosure are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined as “first”, “second”, and “third” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise clearly and specifically limited. All directional indications (such as up, down, left, right, front, back%) in the embodiments of the present disclosure are only used to explain the relative positional relationship between components in a specific posture (as shown in the accompanying drawings).
  • an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosed embodiments.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • FIG. 1 is a schematic structural diagram of an embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional structural diagram of A-A in FIG. 1 .
  • the high electron mobility transistor 100 includes a substrate 10 and an epitaxial layer 20, which is disposed on the surface of the substrate 10.
  • the epitaxial layer 20 at least includes: a first semiconductor layer 13 and a second semiconductor layer 14 disposed on the first semiconductor layer 13,
  • the first semiconductor layer 13 and the second semiconductor layer 14 are heterostructures.
  • the source electrode 17 , the drain electrode 18 and the gate electrode 16 are spaced apart from each other on the epitaxial layer 20 and the gate electrode 16 is provided between the source electrode 17 and the drain electrode 18 ; wherein, the gate electrode 16 has sidewalls facing the drain electrode 18 .
  • the stress compensation layer 15 is disposed on the second semiconductor layer 14 and is in contact with the sidewall of the gate electrode 16; the piezoelectric coefficient of the stress compensation layer 15 is opposite to the piezoelectric coefficient of the second semiconductor layer 14.
  • the epitaxial layer 20 includes a first semiconductor layer 13 and a second semiconductor layer 14, and the substrate 10 Can be gallium nitride.
  • the first semiconductor layer 13 is directly disposed on one side of the substrate 10 .
  • gallium nitride is gallium surface gallium nitride or nitrogen surface gallium nitride, it refers to gallium surface gallium nitride.
  • the epitaxial layer 20 includes a nucleation layer 11 , a buffer layer 12 , a first semiconductor layer 13 and a second semiconductor layer 14 that are sequentially stacked on the substrate 10 .
  • the substrate 10 may be at least one of silicon, silicon carbide, sapphire, or aluminum oxide.
  • the high electron mobility transistor 100 includes a substrate 10, a nucleation layer 11, a buffer layer 12, a first semiconductor layer 13 and a second semiconductor layer 14, and a stress compensation layer 15 stacked in sequence from bottom to top; It also includes: a source electrode 17 , a gate electrode 16 and a drain electrode 18 disposed on the second semiconductor layer 14 and spaced apart from each other, wherein the stress compensation layer 15 is disposed on a side of the gate electrode 16 facing the drain electrode 18 .
  • the high electron mobility transistor 100 further includes a passivation layer 19 , which is disposed on a side of the epitaxial layer 20 away from the substrate 10 and covers the epitaxial layer 20 and the stress compensation layer 15 .
  • the nucleation layer 11 may be a GaN layer or an AlN layer.
  • the main function of the nucleation layer 11 is to provide necessary nucleation centers for high-temperature GaN growth, reduce the interface free energy between high-temperature GaN and the substrate 10, and The adsorption of reactant atoms on the substrate 10 and the lateral growth of GaN are promoted.
  • the buffer layer 12 is a GaN layer or an AlGaN layer.
  • the buffer layer 12 may have a single-layer structure or a multi-layer structure, which is not limited here.
  • the content of the Al component in each AlGaN layer may be the same or different.
  • the first semiconductor layer 13 and the second semiconductor layer 14 are heterostructures, and a two-dimensional electron gas is formed at the interface between the first semiconductor layer 13 and the second semiconductor layer 14 .
  • the first semiconductor layer 13 is a high-temperature GaN layer
  • the first semiconductor layer 13 is a conductive layer along the length direction of the high electron mobility transistor 100 due to an external electric field. That is, the first semiconductor layer 13 is a channel layer.
  • the second semiconductor layer 14 may have a single-layer structure or a multi-layer structure. When the second semiconductor layer 14 has a single-layer structure, the second semiconductor layer 14 includes a gallium plane AlGaN layer.
  • the second semiconductor layer 14 When the second semiconductor layer 14 has a multi-layer structure, that is, when the second semiconductor layer 14 is a composite second semiconductor layer, the second semiconductor layer 14 includes an AlN intercalation layer, a gallium surface AlGaN layer and a GaN cap layer.
  • the AlN intercalation layer, the gallium plane AlGaN layer and the GaN cap layer are sequentially stacked on the first semiconductor layer 13 along the direction from the substrate 10 to the epitaxial layer 20 .
  • the electrons in the second semiconductor layer 14 generated by the piezoelectric effect fall into the first semiconductor layer 13 , thereby generating a two-dimensional electron gas of high mobility conductive electrons in the first semiconductor layer 13 , thereby forming a carrier channel 131 .
  • An interface is defined between the second semiconductor layer 14 and the first semiconductor layer 13, and the carrier channel 131 of the two-dimensional electron gas is located at this interface.
  • the source electrode 17, the drain electrode 18, and the gate electrode 16 are disposed on the surface of the second semiconductor layer 14 away from the substrate 10.
  • the gate electrode 16 is located between the source electrode 17 and the drain electrode 18, and is spaced apart from the drain electrode 18 and the source electrode 17 respectively. .
  • the gate electrode 16 forms a Schottky contact with the second semiconductor layer 14 .
  • the source electrode 17 and the drain electrode 18 respectively form ohmic contacts with the second semiconductor layer 14 .
  • Source 17 and drain 18 are each configured for electrical connection to carrier channel 131 .
  • Source 17 and drain The poles 18 may respectively be at least one of Ti, Al, Ni and Au.
  • the gate electrode 16 can be made of metal materials such as nickel, nickel-manganese alloy, nickel-chromium alloy, nickel-molybdenum iron alloy, etc. The materials of the gate electrode 16, the source electrode 17 and the drain electrode 18 are not limited here and can be selected according to actual needs.
  • the stress compensation layer 15 is disposed on the surface of the second semiconductor layer 14 away from the substrate 10 , and the stress compensation layer 15 is disposed between the gate electrode 16 and the drain electrode 18 and is spaced apart from the drain electrode 18 .
  • the stress compensation layer 15 is in contact with the surface of the side of the gate electrode 16 close to the drain electrode 18 .
  • the piezoelectric coefficient of the stress compensation layer 15 is opposite to the piezoelectric coefficient of the second semiconductor layer 14.
  • the stress compensation layer 15 can generate an inverse piezoelectric deformation stress opposite to the second semiconductor layer 14, reducing the pressure of the second semiconductor layer 14 under high pressure.
  • the stress deformation can increase the breakdown voltage of the second semiconductor layer 14 and improve the stress state of the high electron mobility transistor 100 under high voltage and high power, thereby improving the reliability of the high electron mobility transistor 100 .
  • the passivation layer 19 between the gate electrode 16 and the drain electrode 18 is placed on the side away from the substrate 10 or on the side of the gate electrode 16 away from the substrate 10
  • a multi-level metal field plate is set up on one side.
  • the stress compensation layer 15 is provided to adjust the distribution of the two-dimensional electron gas and the electric field distribution, thereby reducing the peak electric field intensity near the gate 16 and thereby improving the withstand voltage performance of the high electron mobility transistor 100.
  • Multi-level metal field plates can better increase the breakdown voltage and improve the electric field withstand capability near the gate 16, thereby reducing the need for multi-level field plates, thereby simplifying the device preparation process.
  • the following description of the width is described in a direction parallel to the substrate 10 and perpendicular to the extension direction of the gate electrode 16
  • the description of the thickness is described in a direction perpendicular to the substrate 10
  • the description of the length is The description is in the extending direction of the gate electrode 16.
  • the thickness of the stress compensation layer 15 is 20 nm to 1000 nm, and the thickness of the stress compensation layer 15 is smaller than the thickness of the gate 16 ; it should be noted that the thickness direction is the direction from the substrate 10 to the epitaxial layer 20 .
  • the stress compensation layer 15 requires a certain thickness.
  • the stress compensation layer 15 is too thin.
  • the thickness of the stress compensation layer 15 is less than 20 nm.
  • the reverse piezoelectric deformation stress generated by the stress compensation layer 15 and opposite to the second semiconductor layer 14 is small, which is detrimental to the reduction.
  • the stress compensation layer 15 is too thick, for example, the thickness of the stress compensation layer 15 is greater than 1000 nm, which will affect the subsequent production of the passivation layer 19 and the field plate. It should be understood that the thickness of the stress compensation layer 15 is related to the piezoelectric coefficient of the stress compensation layer 15 and the stress requirement of the stress compensation layer 15 , and the optimal thickness range of the stress compensation layer 15 can be obtained through testing.
  • the ratio of the width of the stress compensation layer 15 to the width of the area between the gate electrode 16 and the drain electrode 18 is 2% to 20%.
  • the width of the stress compensation layer 15 along the arrangement direction from the gate electrode 16 to the drain electrode 18 is 0.5 ⁇ m to 10 ⁇ m.
  • the width of the stress compensation layer 15 and the thickness of the stress compensation layer 15 will also affect the compensation effect of the stress compensation layer 15 .
  • the material of the stress compensation layer 15 is nitrogen-surface nitride or oxygen-surface zinc oxide.
  • the stress compensation layer 15 formed of nitrogen-surface nitride or oxygen-surface zinc oxide has the same properties as the second layer in the epitaxial layer 20 .
  • the semiconductor layer 14 has an opposite pressure coefficient.
  • the nitrogen surface nitride may be nitrogen surface gallium nitride.
  • the stress compensation layer 15 can also be made of other piezoelectric materials, as long as the piezoelectric coefficient is opposite to the piezoelectric coefficient of the second semiconductor layer 14. There are no excessive restrictions here, and the selection can be made according to actual needs.
  • the cross-sectional area of the stress compensation layer 15 in a direction parallel to the substrate 10 is rectangular.
  • the length of the stress compensation layer 15 is consistent with the length of the gate electrode 16 , where the length direction refers to a direction parallel to the surface of the substrate 10 and perpendicular to the direction from the gate electrode 16 to the drain electrode 18 , or may be the extending direction of the sidewalls of the gate 16 .
  • the cross-sectional area of the stress compensation layer 15 in the direction parallel to the substrate 10 may be a fan shape, a parallelogram, or other shapes, as long as the thickness and width requirements of the stress compensation layer 15 are met.
  • FIG. 3 is a schematic structural diagram of another embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure.
  • the stress compensation layer 15 includes a plurality of sub-stress compensation layers 151.
  • the plurality of sub-stress compensation layers 151 are spaced apart on the sidewalls of the gate electrode 16, or along the length direction (the extension of the sidewalls of the gate electrode 16). direction) interval setting.
  • the shapes and/or sizes of the different sub-stress compensation layers 151 may be the same, or the shapes and sizes of the different sub-stress compensation layers 151 may be different, and there are no excessive restrictions here.
  • each sub-stress compensation layer 151 has the same shape and size, and the cross-sectional area of the sub-stress compensation layer 151 in a direction parallel to the substrate 10 is rectangular.
  • the spacing between any two adjacent sub-stress compensation layers 151 is the same.
  • the high electron mobility transistor 100 further includes: a passivation layer 19 disposed on the second semiconductor layer 14 , the passivation layer 19 being located between the source electrode 17 and the gate electrode 16 and between the gate electrode 16 and the drain electrode 18 , and the passivation layer 19 covers the stress compensation layer 15 .
  • the thickness of the passivation layer 19 is greater than or equal to the thickness of the stress compensation layer 15 .
  • the passivation layer 19 may be a dielectric material such as silicon dioxide, silicon nitride, or aluminum nitride.
  • Embodiments of the present disclosure provide a high electron mobility transistor 100.
  • the high electron mobility transistor 100 includes a substrate 10, an epitaxial layer 20, a source electrode 17, a drain electrode 18, a gate electrode 16 and a stress compensation layer 15: the epitaxial layer 20 is provided on the surface of the substrate 10, and the epitaxial layer 20 at least includes: A semiconductor layer 13 and a second semiconductor layer 14 disposed on the first semiconductor layer 13.
  • the first semiconductor layer 13 and the second semiconductor layer 14 are heterostructures; the source electrode 17, the drain electrode 18 and the gate electrode 16 are spaced apart from each other.
  • the gate electrode 16 is disposed on the epitaxial layer and the gate electrode 16 is disposed between the source electrode 17 and the drain electrode 18; wherein the gate electrode 16 has a sidewall facing the drain electrode 18; the stress compensation layer 15 is disposed on the second semiconductor layer 14 and is connected with the second semiconductor layer 14. The sidewalls of the gate 16 are in contact; the piezoelectric coefficient of the stress compensation layer 15 is opposite to the piezoelectric coefficient of the second semiconductor layer 14 .
  • the electrical stress reduces the stress deformation of the second semiconductor layer 14 under high voltage to increase the breakdown electric field strength of the second semiconductor layer 14. It can also reduce the two-dimensional electron gas concentration at the edge of the gate electrode 16 to adjust the electric field strength at the edge of the gate electrode 16, thereby Improve the voltage resistance of the device and reduce the need for multi-level field plates, thereby simplifying the device preparation process.
  • the embodiment of the present disclosure provides a method for preparing a high electron mobility transistor 100, which is used to prepare the above-mentioned high electron mobility transistor 100.
  • the specific steps of the preparation method of the high electron mobility transistor 100 are as follows:
  • FIG. 4 is a schematic flow diagram of an embodiment of a method for preparing a high electron mobility transistor provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram corresponding to steps S1 to S5 in FIG. 4 .
  • the substrate 10 is at least one of silicon, silicon carbide, sapphire, aluminum oxide, or gallium nitride.
  • the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer are heterostructures.
  • the epitaxial layer 20 at least includes a first semiconductor layer 13 and a second semiconductor layer 14, and the first semiconductor layer 13 and the second semiconductor layer 14 are heterostructures.
  • the epitaxial layer 20 includes a nucleation layer 11 , a buffer layer 12 , a first semiconductor layer 13 and a second semiconductor layer 14 which are sequentially stacked on the substrate 10 .
  • the substrate 10 may be at least one of silicon, silicon carbide, sapphire, or aluminum oxide.
  • the nucleation layer 11 and the buffer layer 12 are sequentially grown on the substrate 10 using the MOCVD (Metal-organic Chemical Vapor Deposition) method.
  • the nucleation layer 11 may be a GaN layer or an AlN layer.
  • the growth temperature of the nucleation layer 11 is 600°C to 1200°C, and the thickness is 10nm to 500nm.
  • the buffer layer 12 is a GaN layer or an AlGaN layer.
  • the growth temperature of the buffer layer 12 is 900°C to 1200°C; the thickness of the buffer layer 12 is 100nm to 10 ⁇ m.
  • the buffer layer 12 may have a single-layer structure or a multi-layer structure, which is not limited here. When the buffer layer 12 includes multiple AlGaN layers, the content of the Al component in each AlGaN layer may be the same or different.
  • the nucleation layer 11 and the buffer layer 12 can also be prepared by other methods without excessive restrictions here.
  • the epitaxial layer 20 only includes the first semiconductor layer 13 and the second semiconductor layer 14, and the substrate 10 may be gallium nitride.
  • the first semiconductor layer 13 is directly disposed on one side of the substrate 10 .
  • the first semiconductor layer 13 and the second semiconductor layer 14 may be produced by first using the MOCVD method to grow a high-temperature GaN layer.
  • the high-temperature GaN layer is the first semiconductor layer 13 .
  • the MOCVD method is used to grow the second semiconductor layer 14 on the side of the first semiconductor layer 13 away from the substrate 10 .
  • the growth temperature of the first semiconductor layer 13 is 1000°C to 1200°C, and the thickness of the first semiconductor layer 13 is 100 nm to 1 ⁇ m.
  • the growth temperature of the second semiconductor layer 14 is 1000°C to 1200°C, and the thickness of the second semiconductor layer 14 is 5nm to 50nm.
  • the second semiconductor layer 14 may have a single-layer structure or a multi-layer structure.
  • the second semiconductor layer 14 has a single-layer structure, and the second semiconductor layer 14 includes a gallium-plane AlGaN layer.
  • the second semiconductor layer 14 is a multi-layer structure, and the second semiconductor layer 14 includes an AlN intercalation layer, a gallium plane AlGaN layer and a GaN cap layer.
  • the AlN intercalation layer, the gallium surface AlGaN layer and the GaN cap layer are sequentially stacked and grown on the first semiconductor layer 13 .
  • forming the stress compensation layer 15 on the epitaxial layer 20 means: using the MBE (Molecular beam epitaxy) method to grow the stress compensation layer 15 on the side of the second semiconductor layer 14 away from the substrate 10.
  • the stress compensation layer The piezoelectric coefficient of 15 is opposite to the piezoelectric coefficient of the second semiconductor layer 14 .
  • the growth temperature of the stress compensation layer 15 is 300°C to 1000°C, and the thickness of the stress compensation layer 15 is 20nm to 1000nm.
  • forming the stress compensation layer 15 on the epitaxial layer 20 specifically includes the following steps:
  • Figure 6 is a schematic flowchart of an embodiment of step S3 in Figure 4
  • Figure 7 is a schematic structural diagram corresponding to steps S311 to S313 in Figure 6.
  • S311 Prepare a patterned mask layer on the side of the second semiconductor layer away from the substrate, wherein the patterned mask layer is configured to be hollowed out within a preset range of sidewall contact of the gate electrode.
  • a patterned mask layer 141 is prepared on the side of the second semiconductor layer 14 away from the substrate 10 .
  • the patterned mask layer 141 may be made of high-temperature resistant materials such as silicon dioxide and silicon nitride.
  • the patterned mask layer 141 covers part of the second semiconductor layer 14, and an opening structure 142 is formed in the area that does not cover the second semiconductor layer 14.
  • the size of the opening structure 142 is a preset range of sidewall contact of the gate electrode 16, that is, the patterned mask layer 141 covers a portion of the second semiconductor layer 14.
  • the film layer 141 is configured to be hollowed out within a preset range of the sidewall contact of the gate electrode 16 .
  • S312 Grow a stress compensation layer on the patterned mask layer and the second semiconductor layer.
  • the MBE method is used to grow the stress compensation layer 15 on the side of the patterned mask layer 141 away from the substrate 10 and the stress compensation layer 15 is grown at the opening structure 142.
  • the stress compensation layer 15 covers the patterned mask layer 141 and part of second semiconductor layer 14.
  • the stress compensation layer 15 has the same thickness everywhere.
  • the step S312, that is, growing the stress compensation layer 15 on the patterned mask layer 141 and the second semiconductor layer 14, includes: growing a stress compensation layer on the patterned mask layer 141 and the second semiconductor layer 14.
  • a nitride layer is layered to form the stress compensation layer 15 .
  • the nitrogen-side nitride layer may be composed of nitrogen-side gallium nitride.
  • the step S312, that is, growing the stress compensation layer 15 on the patterned mask layer 141 and the second semiconductor layer 14, includes: growing on the patterned mask layer 141 and the second semiconductor layer 14. A layer of zinc oxide on the oxygen surface is formed to form the stress compensation layer 15 .
  • a chemical etching method is used to remove the patterned mask layer 141 and the stress compensation layer 15 on the surface of the patterned mask layer 141 away from the substrate 10 , leaving the stress compensation layer 15 in the opening structure 142 .
  • forming the stress compensation layer 15 on the epitaxial layer 20 specifically includes the following steps:
  • Figure 8 is a schematic flowchart of another embodiment of step S3 in Figure 4
  • Figure 9 is a schematic structural diagram corresponding to steps S321 to S322 in Figure 8.
  • S321 Prepare a first stress compensation layer on the side of the second semiconductor layer away from the substrate.
  • the MBE method is used to prepare the first stress compensation layer 152 on the side of the second semiconductor layer 14 away from the substrate 10 , and the first stress compensation layer 152 completely covers the second semiconductor layer 14 .
  • the first stress compensation layer 152 has the same thickness everywhere.
  • S321 that is, preparing the first stress compensation layer 152 on the side of the second semiconductor layer 14 away from the substrate 10 , includes: growing a layer on the side of the second semiconductor layer 14 away from the substrate 10 Nitrogen surface nitride structure to prepare the first stress compensation layer 152 .
  • the nitride-faced oxide structure may be composed of nitride-faced gallium nitride.
  • step 321 that is, preparing the first stress compensation layer 152 on the side of the second semiconductor layer 14 away from the substrate 10 , includes: growing on the side of the second semiconductor layer 14 away from the substrate 10 A layer of oxygen-surface zinc oxide structure is used to prepare the first stress compensation layer 152 .
  • S322 Etch the first stress compensation layer and retain the second stress compensation layer within a preset range in contact with the sidewall of the gate to obtain a stress compensation layer.
  • the first stress compensation layer 152 is etched, and the second stress compensation layer 153 within the contact range of the sidewall of the gate electrode 16 is retained to obtain the patterned stress compensation layer 15 . That is, the second stress compensation layer 153 is the patterned stress compensation layer 15 .
  • a passivation layer 19 is prepared on the side of the second semiconductor layer 14 away from the substrate 10 , and the passivation layer 19 covers the second semiconductor layer 14 and the stress compensation layer 15 .
  • the thickness of the passivation layer 19 is greater than or equal to the thickness of the stress compensation layer 15 .
  • the passivation layer 19 may be a dielectric material such as silicon dioxide, silicon nitride, or aluminum nitride.
  • the source, drain and gate are set on the epitaxial layer, and the source, drain and gate are spaced apart from each other; the gate has a sidewall facing the drain, and the stress compensation layer is in contact with the sidewall.
  • the passivation layer 19 is etched to form openings to expose part of the second semiconductor layer 14 , and the source electrode 17 , the drain electrode 18 , and the gate electrode 16 are prepared at the openings, that is, the source electrode 17 and the drain electrode 18
  • the gate electrode 16 is disposed on the surface of the second semiconductor layer 14 away from the substrate 10 .
  • the gate electrode 16 is located between the source electrode 17 and the stress compensation layer 15 and is spaced apart from the drain electrode 18 and the source electrode 17 respectively.
  • the stress compensation layer 15 is in contact with the sidewall of the gate electrode 16 facing the drain electrode 18 .
  • first, part of the passivation layer 19 is removed to partially expose the second semiconductor layer 14 to form the first exposed portions 191 .
  • Only one source electrode 17 is prepared on a first exposed portion 191
  • only one drain electrode 18 is prepared on a first exposed portion 191 .
  • the source electrode 17 and the drain electrode 18 are spaced apart.
  • the source electrode 17 and the drain electrode 18 can respectively be made of at least one of Ti, Al, Ni, and Au.
  • the source electrode 17 and the drain electrode 18 can also be made of other materials, which are not limited here and can be selected according to actual needs.
  • the metal material can be evaporated first, and then peeled off and then processed in an annealing furnace. Tempering is performed so that the source electrode 17 and the drain electrode 18 form ohmic contacts with the second semiconductor layer 14 at the first exposed portion 191 respectively.
  • the tempering temperature of the source electrode 17 and the drain electrode 18 is 500°C to 800°C.
  • the source electrode 17 and the drain electrode 18 are prepared by evaporation. In other optional embodiments, the source electrode 17 and the drain electrode 18 can be prepared by other methods such as sputtering, which is not limited here.
  • the gate electrode 16 is located between the stress compensation layer 15 and the source electrode 17. And in contact with the side surface of the stress compensation layer 15 close to the source electrode 17 . Gate 16 is also located between source 17 and drain 18 .
  • the gate 16 can be made of metal materials such as nickel, nickel-manganese alloy, nickel-chromium alloy, nickel-molybdenum iron alloy, etc. The material of the gate 16 is not limited here and can be selected according to actual needs.
  • the metal material can be evaporated first, stripped and then tempered in an annealing furnace, so that the gate electrode 16 forms Schottky contact with the second semiconductor layer 14 at the second exposed portion 192 .
  • the tempering temperature of the gate 16 is 300°C to 600°C.
  • the gate electrode 16 is prepared by evaporation. In other optional embodiments, the gate electrode 16 can be prepared by other methods such as sputtering, which is not limited here.
  • the following mainly prepares high electron mobility transistors, including the following implementation modes.
  • TMAl trimethylaluminum
  • the ammonia gas flow rate is 5000 sccm and the TMAl flow rate is 400 sccm
  • the time is 50 min
  • an AlN nucleation layer with a thickness of 200 nm is obtained.
  • the high-resistance buffer layer includes a three-layer AlGaN structure.
  • the Al composition of each layer of AlGaN structure is different; the three-layer AlGaN structure
  • the Al components are 75%, 50% and 25% respectively.
  • MO high-purity metal organic compounds
  • the ammonia gas flow rate is 1500 sccm; the surface temperature is 1050°C, the growth time is 15 minutes, and the thickness of the AlGaN structure with an Al composition of 75% is 400nm; 2
  • the growth conditions for growing an AlGaN structure with an Al composition of 50% are: MO flow, Among them, the TMGa flow rate is 58 sccm, the TMAl flow rate is 450 sccm, and the ammonia flow rate is 2000 sccm; the surface temperature is 1050°C, the growth time is 50 min, and the thickness of the AlGaN structure with 50% Al composition is 900 nm;
  • the growth Al composition is The growth conditions of the 25% AlGaN structure are: MO flow, where the TMGa flow is 180 sccm, the TMAl flow is 450 sccm, and the ammonia flow is 2000 sccm; the surface temperature is 1050°C, the growth time is 45 min, and the Al component is 25%.
  • the high-resistance GaN layer is also a buffer layer.
  • the high-resistance GaN layer is a GaN layer grown under low temperature and low pressure conditions.
  • TMGa flow is 200 sccm, while the ammonia flow rate is 12000 sccm, the surface temperature is 980°C, the growth rate is 2.5um/h, the growth time is 50min, and the thickness of the high-resistance GaN layer is 3000nm.
  • step (3) Use MOCVD equipment to continue growing the high-temperature GaN first semiconductor layer on the high-resistance GaN layer in step (3); the growth conditions of the high-temperature GaN first semiconductor layer are: TMGa flow rate is 200 sccm, and ammonia flow rate is 30,000 sccm.
  • the temperature is 1080°C, the growth rate is 2 ⁇ m/h, the growth time is 6min, and the thickness of the high-temperature GaN first semiconductor layer is 200nm.
  • the growth conditions of the second semiconductor layer are: the surface temperature is 1080°C, the ammonia gas flow is 8000 sccm; the growth conditions of the AlN intercalation layer are: the flow rate into TMAl is 400 sccm, the growth time is 16 s, and the thickness of the AlN intercalation layer is 1 nm; The growth conditions of the AlGaN second semiconductor layer are: TMAl flow rate is 400 sccm, and TMGa flow rate is 180 sccm.
  • the corresponding growth time of the AlGaN second semiconductor layer with an Al composition of 25% is 80s, and the thickness of the AlGaN second semiconductor layer is 20nm; the growth conditions of the GaN cap layer: the flow rate of TMGa is 150sccm, the growth time is 15s, The thickness of the GaN cap layer is 2nm.
  • step (6) Grow a 300nm silicon dioxide layer patterned mask layer on the surface of the second semiconductor layer in step (5), and use photolithography and etching methods to open holes in the silicon dioxide layer patterned mask layer. Expose the gap structure that requires the growth of a stress compensation layer.
  • silicon dioxide passivation layer on the oxygen surface zinc oxide stress compensation layer, and the silicon dioxide passivation layer covers the second semiconductor layer and the oxygen surface zinc oxide stress compensation layer.
  • the thickness of the silicon dioxide passivation layer is 1000nm.
  • Etch part of the silicon dioxide passivation layer open the source region and the drain region, expose part of the second semiconductor layer, and form the first exposed part. Evaporate the Ti/Al/Ni/Au composite metal layer, peel it off and put it into a rapid annealing furnace. After tempering at 650°C, let the source and drain electrodes form ohmic contacts with the second semiconductor layer at the first exposed part. .
  • Etch part of the silicon dioxide passivation layer open the gate area, expose part of the second semiconductor layer, form a second exposed part, photoetch the gate in the second exposed part, and then evaporate the Ni/Au metal layer , put it into a rapid annealing furnace after peeling off, and temper it at 400°C to form Schottky contact with the second semiconductor layer.
  • the TMAl flow rate is 400 sccm
  • the growth time is 50 min
  • an AlN nucleation layer with a thickness of 200 nm is obtained.
  • the high-resistance GaN layer is a buffer layer.
  • the high-resistance GaN layer is a GaN layer grown under low-temperature and low-pressure conditions.
  • the TMGa flow rate is 200 sccm, and the ammonia flow rate is 12,000 sccm.
  • the surface temperature is 980°C, the growth rate is 2.5 ⁇ m/h, and the growth time is 50 minutes.
  • the high-resistance GaN layer The thickness is 3000nm.
  • step (3) Use MOCVD equipment to continue to grow the high-temperature GaN first semiconductor layer on the high-resistance GaN layer in step (2); the growth conditions of the high-temperature GaN first semiconductor layer are: TMGa flow rate is 200 sccm, and ammonia flow rate is 30,000 sccm.
  • TMGa flow rate is 200 sccm
  • ammonia flow rate is 30,000 sccm.
  • the temperature is 1080°C
  • the growth rate is 2um/h
  • the growth time is 6min
  • the thickness of the high-temperature GaN first semiconductor layer is 200nm.
  • the growth conditions of the second semiconductor layer are: the surface temperature is 1080°C, the ammonia flow rate is 8000 sccm; the growth conditions of the AlN intercalation layer: the flow rate into TMAl is 400 sccm, the growth time is 16 s, and the thickness of the AlN intercalation layer is 1 nm; AlGaN The growth conditions of the second semiconductor layer are: TMAl flow rate is 400 sccm, TMGa flow rate is 180 sccm, the corresponding growth time of the AlGaN second semiconductor layer with an Al composition of 25% is 80 s, and the thickness of the AlGaN second semiconductor layer is 20 nm; GaN The growth conditions of the cap layer: the flow rate into TMGa is 150sccm, the growth time is 15s, and the thickness of the GaN cap layer is 2nm.
  • step (4) Grow a stress compensation layer on the surface of the second semiconductor layer in step (4), use MBE to grow a nitrogen-surface GaN layer with a thickness of 100nm, and use photolithography and etching to remove the stress in other areas except near the gate. Stress compensation layer to obtain a patterned nitrogen surface GaN layer stress compensation layer.
  • step (6) Grow a silicon dioxide passivation layer on the stress compensation layer in step (5).
  • the silicon dioxide passivation layer covers the second semiconductor layer and the nitrogen surface GaN layer stress compensation layer.
  • the thickness of the passivation layer is 1000 nm.
  • Etch part of the silicon dioxide passivation layer open the source region and the drain region, expose part of the second semiconductor layer, and form the first exposed part. Evaporate the Ti/Al/Ni/Au composite metal layer, peel it off and put it into a rapid annealing furnace. After tempering at 650°C, let the source and drain electrodes form ohmic contacts with the second semiconductor layer at the first exposed part. .
  • Etch part of the silicon dioxide passivation layer open the gate area, expose part of the second semiconductor layer, form a second exposed part, photoetch the gate in the second exposed part, and then evaporate the Ni/Au metal layer , put it into a rapid annealing furnace after peeling off, and temper it at 400°C to form Schottky contact with the second semiconductor layer.
  • Embodiments of the present disclosure provide a method for preparing a high electron mobility transistor.
  • the preparation method includes: providing a substrate; forming an epitaxial layer on the surface of the substrate.
  • the epitaxial layer at least includes: a first semiconductor layer and a first semiconductor layer disposed on the first semiconductor layer.
  • the second semiconductor layer on the epitaxial layer, the first semiconductor layer and the second semiconductor layer are heterostructures; a stress compensation layer is formed on the epitaxial layer, and the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer; in A source electrode, a drain electrode and a gate electrode are provided on the epitaxial layer, and the source electrode, drain electrode and gate electrode are spaced apart from each other; the gate electrode has a side wall facing the drain electrode, and the stress compensation layer is in contact with the side wall.
  • a reverse piezoelectric stress opposite to the second semiconductor layer can be generated under high pressure, reducing the pressure of the second semiconductor layer. Stress deformation under high pressure thereby increasing the breakdown of the second semiconductor layer
  • the electric field strength can also reduce the two-dimensional electron gas concentration at the gate edge to adjust the electric field strength at the gate edge, thereby reducing the need for multi-level field plates and simplifying the device preparation process.

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Abstract

本公开提供一种高电子迁移率晶体管及其制备方法。高电子迁移率晶体管包括衬底、外延层、源极、漏极、栅极和应力补偿层：外延层至少包括：第一半导体层和设置在第一半导体层上的第二半导体层，第一半导体层和第二半导体层为异质结构；源极、漏极和栅极彼此间隔地设置于外延层上且栅极设置于源极与漏极之间。通过在栅极面向漏极的侧壁设置与第二半导体层的压电系数相反的应力补偿层，可以在高压下产生与第二半导体层相反的逆压电应力减小第二半导体层在高压下的应力形变从而提高第二半导体层的击穿电场强度，还可以降低栅极边缘的二维电子气浓度调节栅极边缘电场强度，从而提高器件的耐压性以及减小对多级场板的需求，进而简化器件的制备工艺。

Description

高电子迁移率晶体管及其制备方法
相关申请的交叉引用
本申请要求2022年08月22日提交的中国专利申请2022110095040的优先权，其全部内容通过引用并入本文。
技术领域
本发明涉及半导体器件领域，尤其涉及一种高电子迁移率晶体管及其制备方法。
背景技术
氮化镓基化合物半导体材料由于其具有禁带宽度大、热稳定性好、抗辐射、耐酸碱、直接带隙、容易形成异质结器件结构等优点被广泛用于高压高频电子器件和发光器件的制作。氮化镓基高电子迁移率场效应晶体管(High electron mobility transistor，HEMT)作为一种重要的氮化镓电子器件在高功率射频领用和高效电能转换领用有着广泛的应用。随着氮化镓材料质量，外延器件结构设计和器件制作工艺的不断提高，氮化镓HEMT器件的射频和功率性能也不断改善。相较于第一代硅器件和第二代砷化镓器件，氮化镓功率器件最大特点是通过优化材料和器件工艺可以实现更高的耐压和功率密度。
然而现有技术中制作GaN HEMT的击穿电压实际值与其理论耐压极限相比仍然有着较大的差异。基于此，为了实现高功率高耐压器件，如何提高氮化镓基化合物半导体器件的工作电压成为了亟待解决的技术问题。
发明内容
本公开主要解决的技术问题是如何提高氮化镓基化合物半导体器件的工作电压。
为解决上述技术问题，本公开采用的第一个技术方案是：提供一种高电子迁移率晶体管，高电子迁移率晶体管包括：
衬底。
外延层，设置在衬底的表面，外延层至少包括：第一半导体层和设置在第一半导体层上的第二半导体层，第一半导体层和第二半导体层为异质结构。
源极、漏极和栅极，彼此间隔地设置于外延层上且栅极设置于源极与漏极之间；其中，栅极具有面向漏极的侧壁。
应力补偿层，设置于第二半导体层上，且与栅极的侧壁接触；应力补偿层的压电系数与第二半导体层的压电系数相反。
为解决上述技术问题，本公开采用的第二个技术方案是：提供一种高电子迁移晶体管的制备方法，高电子迁移晶体管的制备方法包括：
提供一衬底。
在衬底的表面形成外延层，外延层至少包括：第一半导体层和设置在第一半导体层上的第二半导体层，第一半导体层和第二半导体层为异质结构。
在外延层上形成应力补偿层，且应力补偿层的压电系数与第二半导体层的压电系数相反。
在外延层上设置源极、漏极和栅极，源极、漏极和栅极彼此之间间隔设置；栅极具有面向漏极的侧壁，应力补偿层与侧壁接触。
本公开实施例的有益效果：区别于现有技术，本公开实施例提供一种高电子迁移率晶体管及其制备方法，该高电子迁移率晶体管包括衬底、外延层、源极、漏极、栅极和应力补偿层：外延层设置在衬底的表面，外延层至少包括：第一半导体层和设置在第一半导体层上的第二半导体层，第一半导体层和第二半导体层为异质结构；源极、漏极和栅极彼此间隔地设置于外延层上且栅极设置于源极与漏极之间；其中，栅极具有面向漏极的侧壁；应力补偿层设置于第二半导体层上，且与栅极的侧壁接触；应力补偿层的压电系数与第二半导体层的压电系数相反。如此，通过在栅极面向漏极的侧壁设置与第二半导体层的压电系数相反的应力补偿层，可以在高压下产生与第二半导体层相反的逆压电应力减小第二半导体层在高压下的应力形变从而提高第二半导体层的击穿电场强度；同时还可以降低栅极边缘的二维电子气浓度调节栅极边缘电场强度，从而提高器件的耐压性以及减小对多级场板的需求，进而简化器件的制备工艺。
附图说明
图1是本公开实施例提供的高电子迁移率晶体管一实施例的结构示意图；
图2是图1中A-A处的剖面结构示意图；
图3是本公开实施例提供的高电子迁移率晶体管另一实施例的结构示意图；
图4是本公开实施例提供的高电子迁移率晶体管的制备方法一实施例的流程示意图；
图5是图4中步骤S1至S5对应的结构示意图；
图6是图4中步骤S3一实施例的流程示意图；
图7是图6中步骤S311至S313对应的结构示意图；
图8是图4中步骤S3另一实施例的流程示意图；
图9是图8中步骤S321至S322对应的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本公开实施例的一部分实施例，而不是全部的实施例。基于本公开实施例中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开实施例保护的范围。
本公开实施例中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本公开实施例的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本公开实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本公开实施例的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
下面结合附图和实施例对本公开实施例进行详细的说明。
请参阅图1和图2，图1是本公开实施例提供的高电子迁移率晶体管一实施例的结构示意图，图2是图1中A-A处的剖面结构示意图。
高电子迁移率晶体管100包括衬底10、外延层20，设置在衬底10的表面，外延层20至少包括：第一半导体层13和设置在第一半导体层13上的第二半导体层14，第一半导体层13和第二半导体14为异质结构。
源极17、漏极18和栅极16彼此间隔地设置于外延层20上且栅极16设置于源极17与漏极18之间；其中，栅极16具有面向漏极18的侧壁。
应力补偿层15设置于第二半导体层14上，且与栅极16的侧壁接触；应力补偿层15的压电系数与第二半导体层14的压电系数相反。
在一些实施例中，外延层20包括第一半导体层13和第二半导体层14，衬底10 可以为氮化镓。第一半导体层13直接设置于衬底10的一侧。
需要说明的是，在下面的描述中，未强调氮化镓是镓面氮化镓或氮面氮化镓的都是指镓面氮化镓。
在一些实施例中，外延层20包括依次层叠设置于衬底10上的成核层11、缓冲层12、第一半导体层13和第二半导体层14。衬底10可以为硅、碳化硅、蓝宝石或氧化铝中的至少一种。
在一些实施例中，高电子迁移率晶体管100包括由下至上依次叠设的衬底10、成核层11、缓冲层12、第一半导体层13和第二半导体层14以及应力补偿层15；还包括：设置在于第二半导体层14上且彼此间隔的源极17、栅极16和漏极18，其中，应力补偿层15设置栅极16面向漏极18的一侧。
在一些实施例中，高电子迁移率晶体管100还包括钝化层19，该钝化层19设置于外延层20远离衬底10的一侧，且覆盖外延层20和应力补偿层15。
示例性地，成核层11可以是GaN层或AlN层，成核层11的主要作用是给高温的GaN生长提供必要的成核中心、降低高温的GaN与衬底10间的界面自由能以促进反应物原子在衬底10上的吸附和GaN的横向生长。
示例性地，缓冲层12为GaN层或者AlGaN层。缓冲层12可以是单层结构，也可以是多层结构，此处不作限制。缓冲层12包括多层的AlGaN层时，每层的AlGaN层中的Al组分的含量可以一样，也可以不一样。
第一半导体层13和第二半导体层14为异质结构，第一半导体层13和第二半导体层14之间的界面形成有二维电子气。示例性地，第一半导体层13为高温的GaN层，第一半导体层13是高电子迁移率晶体管100中由于外加电场引起的沿长度方向的导电层。即，第一半导体层13为沟道层。第二半导体层14可以是单层结构，也可以是多层结构，第二半导体层14是单层结构时，第二半导体层14包括镓面AlGaN层。第二半导体层14是多层结构时，也就是说，第二半导体层14是复合第二半导体层时，第二半导体层14包括AlN插层、镓面AlGaN层和GaN帽层。AlN插层、镓面AlGaN层和GaN帽层依次沿衬底10到外延层20方向层叠设置于第一半导体层13上。在第一半导体层13和第二半导体层14之间存在带隙不连续性。由于压电效应产生的第二半导体层14中电子落入第一半导体层13，从而在第一半导体层13中产生高迁移率导电电子的二维电子气，进而形成载流子沟道131。第二半导体层14与第一半导体层13之间限定界面，二维电子气的载流子沟道131位于此界面处。
源极17、漏极18、栅极16设置于第二半导体层14远离衬底10的表面，栅极16位于源极17和漏极18之间，分别与漏极18和源极17间隔设置。栅极16与第二半导体层14形成肖特基接触。源极17和漏极18分别与第二半导体层14形成欧姆接触。源极17和漏极18分别被配置用于电连接至载流子沟道131。源极17和漏 极18分别可以为Ti、Al、Ni和Au中的至少一种。栅极16可以为镍、镍锰合金、镍铬合金以及镍钼铁合金等金属材料，栅极16、源极17和漏极18的材料，此处不作限制，根据实际需求进行选择。
应力补偿层15设置于第二半导体层14远离衬底10的表面，且应力补偿层15设置于栅极16与漏极18之间，且与漏极18间隔设置。应力补偿层15与栅极16靠近漏极18的一侧的表面接触。应力补偿层15的压电系数与第二半导体层14的压电系数相反，应力补偿层15可以产生与第二半导体层14相反的逆压电形变应力，减小第二半导体层14在高压下的应力形变，从而可以提高第二半导体层14的击穿电压以及改善高电子迁移率晶体管100在高压高功率下的应力状态，提高高电子迁移率晶体管100的可靠性。
进一步地，在现有技术中，为了提高器件的击穿电压，会在栅极16和漏极18之间的钝化层19远离衬底10的一侧或在栅极16远离衬底10的一侧设置多级金属场板，然而通过多级金属场板提高器件的击穿电压的方式，其击穿电压实际值与其理论耐压极限相比仍然有着较大的差异。但本公开实施例通过设置应力补偿层15，调节二维电子气的分布和电场分布，从而减小栅极16附近的峰值电场强度进而提高高电子迁移率晶体管100的耐压性能，相比于多级金属场板可以更好地提高击穿电压和提高栅极16附近电场的承受能力，进而减小对多级场板的需求，从而简化器件的制备工艺。
需要说明的是，下面对宽度的描述均是在平行于衬底10且垂直栅极16的延伸方向上进行描述，对厚度的描述是在垂直于衬底10的方向上进行描述，对长度的描述是在栅极16的延伸方向上进行描述。
在一些实施例方式中，应力补偿层15的厚度为20nm～1000nm，且应力补偿层15的厚度小于栅极16的厚度；需要说明的是，厚度方向为衬底10到外延层20的方向。应力补偿层15需要一定的厚度，应力补偿层15过薄，例如应力补偿层15的厚度小于20nm，应力补偿层15产生的与第二半导体层14相反的逆压电形变应力较小，对减小第二半导体层14在高压下的应力形变的效果不明显；应力补偿层15过厚，例如应力补偿层15的厚度大于1000nm，会影响后续钝化层19和场板的制作。需要理解的是，应力补偿层15的厚度与应力补偿层15的压电系数以及应力补偿层15的应力需求相关，通过测试可得到应力补偿层15的最佳厚度范围。
在另一些实施例方式中，沿栅极16至漏极18的排布方向，应力补偿层15的宽度与栅极16和漏极18之间区域的宽度的比值为2％～20％。示例性的，应力补偿层15沿栅极16至漏极18的排布方向的宽度为0.5μm～10μm。
需要理解的是，应力补偿层15的宽度同应力补偿层15的厚度一样也会影响应力补偿层15的补偿效果。
在一些实施例中，应力补偿层15的材料为氮面氮化物或氧面氧化锌，如此可以利用氮面氮化物或氧面氧化锌形成的应力补偿层15具有与外延层20中的第二半导体层14相反的压力系数。
在一些实施例中，应力补偿层15的材料为氮面氮化物时，氮面氮化物可以为氮面氮化镓。应力补偿层15还可以是其他压电材料，只要压电系数与第二半导体层14的压电系数相反即可，此处不作过多限制，根据实际需求进行选择。
在一些实施例中，应力补偿层15在平行于衬底10的方向上的横截面积为矩形。
在一些实施例中，例如图2中，应力补偿层15的长度与栅极16的长度一致，其中，长度方向是指平行于衬底10的表面且垂直于栅极16到漏极18的方向，或者可以是栅极16的侧壁的延伸方向。
在另一些实施例中，应力补偿层15在平行于衬底10的方向上的横截面积可以为扇形、平行四边形等图形，只要满足应力补偿层15的厚度要求以及宽度要求即可。
请参阅图1和图3，图3是本公开实施例提供的高电子迁移率晶体管另一实施例的结构示意图。
在本实施例中，应力补偿层15包括多个子应力补偿层151，多个子应力补偿层151间隔地设置于栅极16的侧壁，或者说沿着长度方向(栅极16的侧壁的延伸方向)间隔设置。不同子应力补偿层151的形状和/或尺寸可以相同，或不同子应力补偿层151的形状和尺寸也可以不相同，此处不作过多限制。如图3所示，在一些实施例中，每个子应力补偿层151的形状和大小均相同，子应力补偿层151在平行于衬底10的方向上的横截面积为矩形。
在一些实施例中，任意相邻的两个子应力补偿层151之间的间隔相同。
在一些实施例中，请参阅图1，高电子迁移率晶体管100还包括：设置在第二半导体层14上的钝化层19，该钝化层19位于源极17与栅极16之间以及栅极16与漏极18之间，且钝化层19覆盖应力补偿层15。钝化层19的厚度大于或等于应力补偿层15的厚度。钝化层19可以为二氧化硅、氮化硅或氮化铝等介电材料。
本公开实施例提供一种高电子迁移率晶体管100。高电子迁移率晶体管100包括衬底10、外延层20、源极17、漏极18、栅极16和应力补偿层15：外延层20设置在衬底10的表面，外延层20至少包括：第一半导体层13和设置在第一半导体层13上的第二半导体层14，第一半导体层13和第二半导体层14为异质结构；源极17、漏极18和栅极16彼此间隔地设置于外延层上且栅极16设置于源极17与漏极18之间；其中，栅极16具有面向漏极18的侧壁；应力补偿层15设置于第二半导体层14上，且与栅极16的侧壁接触；应力补偿层15的压电系数与第二半导体层14的压电系数相反。通过在栅极16面向漏极18的侧壁设置与第二半导体层14的压电系数相反的应力补偿层15，可以在高压下产生与第二半导体层14相反的逆压 电应力减小第二半导体层14在高压下的应力形变从而提高第二半导体层14的击穿电场强度，还可以降低栅极16边缘的二维电子气浓度调节栅极16边缘电场强度，从而提高器件的耐压性以及减小对多级场板的需求，进而简化器件的制备工艺。
本公开实施例提供一种高电子迁移率晶体管100的制备方法，用于制备上述的高电子迁移率晶体管100，高电子迁移率晶体管100的制备方法的具体步骤如下所示：
请参阅图4和图5，图4是本公开实施例提供的高电子迁移率晶体管的制备方法一实施例的流程示意图，图5是图4中步骤S1至S5对应的结构示意图。
S1：提供一衬底。
具体地，衬底10为硅、碳化硅、蓝宝石、氧化铝或氮化镓中的至少一种。
S2：在衬底的表面形成外延层，外延层至少包括：第一半导体层和设置在第一半导体层上的第二半导体层，第一半导体层和第二半导体层为异质结构。
具体地，外延层20至少包括第一半导体层13和第二半导体层14，且第一半导体层13和第二半导体层14为异质结构。
在本实施方式中，外延层20包括依次层叠设置于衬底10上的成核层11、缓冲层12、第一半导体层13和第二半导体层14。衬底10可以为硅、碳化硅、蓝宝石或氧化铝中的至少一种。具体地，在衬底10上采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉淀)的方法依次生长成核层11和缓冲层12。成核层11可以是GaN层或AlN层，成核层11的生长温度为600℃～1200℃，厚度为10nm～500nm。缓冲层12为GaN层或者AlGaN层。缓冲层12的生长温度为900℃～1200℃；缓冲层12的厚度为100nm～10μm。缓冲层12可以是单层结构，也可以是多层结构，此处不作限制。缓冲层12包括多层的AlGaN层时，每层的AlGaN层中的Al组分的含量可以一样，也可以不一样。成核层11和缓冲层12也可以采用其他方法制备，此处不作过多限制。
在一些实施方式中，外延层20仅包括第一半导体层13和第二半导体层14，衬底10可以为氮化镓。第一半导体层13直接设置于衬底10的一侧。
第一半导体层13和第二半导体层14的制作可以是：先采用MOCVD法生长高温的GaN层。高温的GaN层即为第一半导体层13。然后，采用MOCVD法在第一半导体层13远离衬底10的一侧生长第二半导体层14。
第一半导体层13的生长温度为1000℃～1200℃，第一半导体层13的厚度为100nm～1μm。第二半导体层14的生长温度为1000℃～1200℃，第二半导体层14的厚度为5nm～50nm。第二半导体层14可以是单层结构，也可以是多层结构。
在一实施例方式中，第二半导体层14是单层结构，第二半导体层14包括镓面AlGaN层。
在另一实施方式中，第二半导体层14是多层结构，第二半导体层14包括AlN插层、镓面AlGaN层和GaN帽层。AlN插层、镓面AlGaN层和GaN帽层依次层叠生长于第一半导体层13上。
S3：在外延层上形成应力补偿层，且应力补偿层的压电系数与第二半导体层的压电系数相反。
具体地，在外延层20上形成应力补偿层15是指：采用MBE(Molecular beam epitaxy，分子束外延)法在第二半导体层14远离衬底10的一侧生长应力补偿层15，应力补偿层15的压电系数与第二半导体层14的压电系数相反。应力补偿层15的生长温度为300℃～1000℃，应力补偿层15的厚度为20nm～1000nm。
在一实施方式中，对在外延层20上形成应力补偿层15具体包括如下步骤：
请参阅图6和图7，图6是图4中步骤S3一实施例的流程示意图，图7是图6中步骤S311至S313对应的结构示意图。
S311：在第二半导体层远离衬底的一侧制备图形化掩膜层，其中，图形化掩膜层被配置为在栅极的侧壁接触的预设范围内镂空。
具体地，在第二半导体层14远离衬底10的一侧制备图形化掩膜层141，图形化掩膜层141可以为二氧化硅和氮化硅等耐高温材料。图形化掩膜层141覆盖部分第二半导体层14，未覆盖第二半导体层14的地方形成开口结构142，开口结构142的大小为栅极16的侧壁接触的预设范围，即图形化掩膜层141被配置为在栅极16的侧壁接触的预设范围内镂空。
S312：在图形化掩膜层以及第二半导体层上生长应力补偿层。
具体地，在图形化掩膜层141远离衬底10的一侧采用MBE法生长应力补偿层15以及在开口结构142处生长应力补偿层15，应力补偿层15覆盖图形化掩膜层141和部分第二半导体层14。应力补偿层15各处的厚度一样。
在一些实施例中，所述步骤S312，即在图形化掩膜层141以及第二半导体层14上生长应力补偿层15，包括：在图形化掩膜层141以及第二半导体层14上生长一层氮面氮化物层，以形成应力补偿层15。
在一些实施例中，氮面氮化物层可以由氮面氮化镓组成。
在另一些实施例中，所述步骤S312，即在图形化掩膜层141以及第二半导体层14上生长应力补偿层15，包括：在图形化掩膜层141以及第二半导体层14上生长一层氧面氧化锌，以形成应力补偿层15。
S313：去除图形化掩膜层以及图形化掩膜层上的应力补偿层。
具体地，采用化学腐蚀的方法去除图形化掩膜层141以及图形化掩膜层141远离衬底10一侧表面的应力补偿层15，保留开口结构142内的应力补偿层15。
在另一实施方式中，对在外延层20上形成应力补偿层15具体包括如下步骤：
请参阅图8和图9，图8是图4中步骤S3另一实施例的流程示意图，图9是图8中步骤S321至S322对应的结构示意图。
S321：在第二半导体层远离衬底的一侧制备第一应力补偿层。
具体地，在第二半导体层14远离衬底10的一侧采用MBE法制备第一应力补偿层152，第一应力补偿层152完全覆盖第二半导体层14。第一应力补偿层152各处的厚度一样。
在一些实施例中，所述S321，即在第二半导体层14远离衬底10的一侧制备第一应力补偿层152，包括：在第二半导体层14远离衬底10的一侧生长一层氮面氮化物结构，以制备第一应力补偿层152。
在一些实施例中，氮面氧化物结构可以由氮面氮化镓组成。
在另一些实施例中，所述步骤321，即在第二半导体层14远离衬底10的一侧制备第一应力补偿层152，包括：在第二半导体层14远离衬底10的一侧生长一层氧面氧化锌结构，以制备第一应力补偿层152。
S322：刻蚀第一应力补偿层，保留与栅极的侧壁接触的预设范围内的第二应力补偿层，得到应力补偿层。
具体地，蚀刻第一应力补偿层152，保留栅极16的侧壁的接触范围内的第二应力补偿层153，得到图形化后的应力补偿层15。即，第二应力补偿层153为图形化后的应力补偿层15。
S4：在应力补偿层和第二半导体层远离所述衬底的一侧制备钝化层。
具体地，在第二半导体层14远离衬底10的一侧制备钝化层19，钝化层19覆盖第二半导体层14以及应力补偿层15。钝化层19的厚度大于或等于应力补偿层15的厚度。钝化层19可以为二氧化硅、氮化硅或氮化铝等介电材料。
S5：在外延层上设置源极、漏极和栅极，源极、漏极和栅极彼此之间间隔设置；栅极具有面向漏极的侧壁，应力补偿层与侧壁接触。
具体地，刻蚀钝化层19形成开孔以裸露部分第二半导体层14，且在开孔处制备源极17、漏极18、栅极16，也就是说，源极17、漏极18、栅极16设置于第二半导体层14远离衬底10的表面。栅极16位于源极17和应力补偿层15之间，分别与漏极18和源极17间隔设置。应力补偿层15与栅极16面向漏极18的侧壁接触。
在一具体实施例中，首先，去除部分钝化层19使第二半导体层14部分暴露形成第一暴露部191，第一暴露部191为多个，多个第一暴露部191间隔设置。一个第一暴露部191上仅制备一个源极17，一个第一暴露部191上仅制备一个漏极18，源极17和漏极18间隔设置。源极17和漏极18分别可以为Ti、Al、Ni和Au中的至少一种，源极17和漏极18还可以为其他材料，此处不作限制，根据实际需求进行选择。在制备源极17和漏极18时，可以先蒸镀金属材料，剥离后在退火炉中进 行回火，让源极17和漏极18分别在第一暴露部191处与第二半导体层14形成欧姆接触。源极17和漏极18的回火温度为500℃～800℃。在本实施方式中，采用蒸镀的方式制备源极17和漏极18，在其他可选实施方式中，可以采用溅射等其他方式制备源极17和漏极18，此处不作限制。
然后，去除部分钝化层19使第二半导体层14部分暴露形成第二暴露部192，在第二暴露部192上制备栅极16，栅极16位于应力补偿层15和源极17之间，且与应力补偿层15靠近源极17的侧面接触。栅极16也位于源极17和漏极18之间。栅极16可以为镍、镍锰合金、镍铬合金以及镍钼铁合金等金属材料，栅极16的材料，此处不作限制，根据实际需求进行选择。在制备栅极16时，可以先蒸镀金属材料，剥离后在退火炉中进行回火，让栅极16在第二暴露部192处与第二半导体层14形成肖特基接触。栅极16的回火温度为300℃～600℃。在本实施方式中，采用蒸镀的方式制备栅极16，在其他可选实施方式中，可以采用溅射等其他方式制备栅极16，此处不作限制。
下面主要对高电子迁移率晶体管进行制备，包括如下实施方式。
第一实施方式：
(1)采用MOCVD设备在6寸硅衬底上生长AlN成核层。首先在1060℃高温氢气环境下对硅衬底表面进行热处理，以去除硅衬底表面的氧化物；预通三甲基铝(Trimethyl Aluminum，TMAl)流量为50sccm，时间为1min；继续在1080℃条件下通入氨气流量为5000sccm和TMAl流量为400sccm，时间为50min，得到厚度为200nm的AlN成核层。
(2)采用MOCVD设备继续在步骤(1)的AlN成核层上继续生长高阻缓冲层，高阻缓冲层包括三层AlGaN结构，每层AlGaN结构的Al组分不同；三层AlGaN结构的Al组分分别为75％、50％和25％。其中，①生长Al组分为75％的AlGaN结构的生长条件为：MO(高纯金属有机化合物)流量，其中，三甲基镓(TriMethyl Gallium，TMGa)流量为30sccm，TMAl流量为500sccm，同时氨气流量为1500sccm；表面温度为1050℃，生长时间为15min，Al组分为75％的AlGaN结构的厚度为400nm；②生长Al组分为50％的AlGaN结构的生长条件为：MO流量，其中，TMGa流量为58sccm，TMAl流量为450sccm，同时氨气流量为2000sccm；表面温度为1050℃，生长时间为50min，Al组分为50％的AlGaN结构的厚度为900nm；③生长Al组分为25％的AlGaN结构的生长条件为：MO流量，其中，TMGa流量为180sccm，TMAl流量为450sccm，同时氨气流量为2000sccm；表面温度为1050℃，生长时间为45min，Al组分为25％的AlGaN结构的厚度为1500nm。
(3)采用MOCVD设备继续在步骤(2)的高阻缓冲层上生长高阻GaN层，高阻GaN层也为缓冲层。高阻GaN层为低温低压条件下生长的GaN层，TMGa流量 为200sccm，同时氨气流量为12000sccm，表面温度为980℃，生长速率为2.5um/h，生长时间为50min，高阻GaN层的厚度为3000nm。
(4)采用MOCVD设备继续在步骤(3)的高阻GaN层上生长高温GaN第一半导体层；高温GaN第一半导体层的生长条件为：TMGa流量为200sccm，同时氨气流量为30000sccm，表面温度为1080℃，生长速率为2μm/h，生长时间为6min，高温GaN第一半导体层的厚度为200nm。
(5)采用MOCVD设备继续在步骤(4)的高温GaN第一半导体层上继续生长第二半导体层。第二半导体层的生长条件为：表面温度为1080℃，氨气流量为8000sccm；AlN插层的生长条件为：通入TMAl的流量为400sccm，生长时间为16s，AlN插层的厚度为1nm；AlGaN第二半导体层的生长条件为：TMAl流量为400sccm，TMGa流量为180sccm。对应的Al组分为25％的AlGaN第二半导体层的生长时间为80s，AlGaN第二半导体层的厚度为20nm；GaN帽层的生长条件：通入TMGa的流量为150sccm，生长时间为15s，GaN帽层的厚度为2nm。
(6)在步骤(5)的第二半导体层表面生长一层300nm的二氧化硅层图形化掩膜层，利用光刻和刻蚀的方法在二氧化硅层图形化掩膜层上开孔露出需要生长应力补偿层的缺口结构。
(7)利用MBE在步骤(6)的缺口结构处生长200nm的氧面氧化锌应力补偿层，用化学腐蚀方法去除二氧化硅层图形化掩膜层和二氧化硅层图形化掩膜层远离硅衬底一侧表面的氧面氧化锌。
(8)在氧面氧化锌应力补偿层上生长二氧化硅钝化层，二氧化硅钝化层覆盖第二半导体层和氧面氧化锌应力补偿层。二氧化硅钝化层的厚度为1000nm。
(9)刻蚀部分二氧化硅钝化层，开孔源极区域和漏极区域，使部分第二半导体层暴露，形成第一暴露部。蒸镀Ti/Al/Ni/Au复合金属层，剥离后放入快速退火炉中，在650℃条件下回火后让源极和漏极分别在第一暴露部与第二半导体层形成欧姆接触。
(10)刻蚀部分二氧化硅钝化层，开孔栅极区域，使部分第二半导体层暴露，形成第二暴露部，在第二暴露部光刻栅极然后蒸镀Ni/Au金属层，剥离后放入快速退火炉中，在400℃条件下回火与第二半导体层形成肖特基接触。
第二实施方式：
(1)采用MOCVD设备在6寸硅衬底上生长AlN成核层。首先在1060℃高温氢气环境下对硅衬底表面进行热处理，以去除硅衬底表面的氧化物；预通TMAl流量为50sccm，时间为1min；继续在1080℃条件下通入氨气流量为5000sccm和TMAl流量为400sccm，生长时间为50min，得到厚度为200nm的AlN成核层。
(2)采用MOCVD设备继续在步骤(1)的AlN成核层上生长高阻GaN层， 高阻GaN层为缓冲层。高阻GaN层为低温低压条件下生长的GaN层，TMGa流量为200sccm，同时氨气流量为12000sccm，表面温度为980℃，生长速率为2.5μm/h，生长时间为50min，高阻GaN层的厚度为3000nm。
(3)采用MOCVD设备继续在步骤(2)的高阻GaN层上生长高温GaN第一半导体层；高温GaN第一半导体层的生长条件为：TMGa流量为200sccm，同时氨气流量为30000sccm，表面温度为1080℃，生长速率为2um/h，生长时间为6min，高温GaN第一半导体层的厚度为200nm。
(4)采用MOCVD设备继续在步骤(3)的GaN第一半导体层上继续生长第二半导体层。第二半导体层的生长条件为：表面温度为1080℃，氨气流量为8000sccm；AlN插层的生长条件：通入TMAl的流量为400sccm，生长时间为16s，AlN插层的厚度为1nm；AlGaN第二半导体层的生长条件为：TMAl流量为400sccm，TMGa流量为180sccm，对应的Al组分为25％的AlGaN第二半导体层的生长时间为80s，AlGaN第二半导体层的厚度为20nm；GaN帽层的生长条件：通入TMGa的流量为150sccm，生长时间为15s，GaN帽层的厚度为2nm。
(5)在步骤(4)的第二半导体层表面生长应力补偿层，利用MBE生长一层厚度为100nm的氮面GaN层，采用光刻和刻蚀的方法去掉除栅极附近外其他区域的应力补偿层，得到图形化氮面GaN层应力补偿层。
(6)在步骤(5)的应力补偿层上生长二氧化硅钝化层，二氧化硅钝化层覆盖第二半导体层和氮面GaN层应力补偿层，钝化层的厚度为1000nm。
(7)刻蚀部分二氧化硅钝化层，开孔源极区域和漏极区域，使部分第二半导体层暴露，形成第一暴露部。蒸镀Ti/Al/Ni/Au复合金属层，剥离后放入快速退火炉中，在650℃条件下回火后让源极和漏极分别在第一暴露部与第二半导体层形成欧姆接触。
(8)刻蚀部分二氧化硅钝化层，开孔栅极区域，使部分第二半导体层暴露，形成第二暴露部，在第二暴露部光刻栅极然后蒸镀Ni/Au金属层，剥离后放入快速退火炉中，在400℃条件下回火与第二半导体层形成肖特基接触。
本公开实施例提供一种高电子迁移率晶体管的制备方法，制备方法包括：提供一衬底；在衬底的表面形成外延层，外延层至少包括：第一半导体层和设置在第一半导体层上的第二半导体层，第一半导体层和第二半导体层为异质结构；在外延层上形成应力补偿层，且应力补偿层的压电系数与第二半导体层的压电系数相反；在外延层上设置源极、漏极和栅极，源极、漏极和栅极彼此之间间隔设置；栅极具有面向漏极的侧壁，应力补偿层与侧壁接触。通过在栅极面向漏极的侧壁设置与第二半导体层的压电系数相反的应力补偿层，可以在高压下产生与第二半导体层相反的逆压电应力，减小第二半导体层在高压下的应力形变从而提高第二半导体层的击穿 电场强度，还可以降低栅极边缘的二维电子气浓度调节栅极边缘电场强度，从而减小对多级场板的需求，进而简化器件的制备工艺。
以上所述仅为本公开实施例的实施方式，并非因此限制本公开实施例的专利范围，凡是利用本公开实施例说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本公开实施例的专利保护范围内。

Claims (20)

  1. 一种高电子迁移率晶体管，其中，包括：
    衬底；
    外延层，设置在所述衬底的表面，所述外延层至少包括：第一半导体层和设置在所述第一半导体层上的第二半导体层，所述第一半导体层和所述第二半导体层为异质结构；
    源极、漏极和栅极，彼此间隔地设置于所述外延层上且所述栅极设置于所述源极与所述漏极之间；其中，所述栅极具有面向所述漏极的侧壁；
    应力补偿层，设置于所述第二半导体层上，且与所述栅极的侧壁接触；所述应力补偿层的压电系数与所述第二半导体层的压电系数相反。
  2. 根据权利要求1所述的高电子迁移率晶体管，其中，所述应力补偿层与所述漏极间隔设置。
  3. 根据权利要求2所述的高电子迁移率晶体管，其中，沿所述栅极至所述漏极的排布方向，所述应力补偿层的宽度与所述栅极和所述漏极之间区域的宽度的比值为2％～20％。
  4. 根据权利要求1所述的高电子迁移率晶体管，其中，所述应力补偿层的材料为氮面氮化物。
  5. 根据权利要求4所述的高电子迁移率晶体管，其中，所述氮面氮化物为氮面氮化镓。
  6. 根据权利要求1所述的高电子迁移率晶体管，其中，所述应力补偿层的材料为氧面氧化锌。
  7. 根据权利要求1所述的高电子迁移率晶体管，其中，所述应力补偿层的厚度小于所述栅极的厚度，其中，厚度方向为所述衬底到所述外延层的方向。
  8. 根据权利要求1所述的高电子迁移率晶体管，其中，所述应力补偿层包括多个子应力补偿层，多个所述子应力补偿层在所述栅极的长度方向上间隔地设置于所述栅极的所述侧壁，其中，所述长度方向为平行于所述衬底的表面且垂直于所述栅极到所述漏极的方向。
  9. 根据权利要求8所述的高电子迁移率晶体管，其中，任意相邻的两个所述子应力补偿层之间的间隔相等。
  10. 根据权利要求1所述的高电子迁移率晶体管，其中，所述高电子迁移率晶体管还包括：
    设置在所述第二半导体层上的钝化层，所述钝化层位于所述源极与栅极之间以及所述栅极与所述漏极之间，且所述钝化层覆盖所述应力补偿层。
  11. 根据权利要求10所述的高电子迁移率晶体管，其中，所述钝化层的厚度大于所述应力补偿层的厚度，其中，厚度方向为所述衬底到所述外延层的方向。
  12. 根据权利要求10所述的高电子迁移率晶体管，其中，所述钝化层的厚度等于所述应力补偿层的厚度，其中，厚度方向为所述衬底到所述外延层的方向。
  13. 根据权利要求1所述的高电子迁移晶体管，其中，所述第二半导体层为镓面AlGaN 层。
  14. 根据权利要求1所述的高电子迁移率晶体管，其中，所述第二半导体层为沿所述衬底到所述外延层方向上叠置AlN插层、镓面AlGaN层和GaN帽层。
  15. 一种高电子迁移晶体管的制备方法，其中，包括：
    提供一衬底；
    在所述衬底的表面形成外延层，所述外延层至少包括：第一半导体层和设置在所述第一半导体层上的第二半导体层，所述第一半导体层和所述第二半导体层为异质结构；
    在所述外延层上形成应力补偿层，且所述应力补偿层的压电系数与所述第二半导体层的压电系数相反；
    在所述外延层上设置源极、漏极和栅极，所述源极、所述漏极和所述栅极彼此之间间隔设置；所述栅极具有面向所述漏极的侧壁，所述应力补偿层与所述侧壁接触。
  16. 根据权利要求15所述的制备方法，其中，所述在所述外延层上形成应力补偿层，包括：
    在所述第二半导体层远离所述衬底的一侧制备图形化掩膜层，其中，所述图形化掩膜层被配置为在所述栅极的侧壁接触的预设范围内镂空；
    在所述图形化掩膜层以及所述第二半导体层上生长所述应力补偿层；
    去除所述图形化掩膜层以及所述图形化掩膜层上的应力补偿层。
  17. 根据权利要求16所述的制备方法，其中，所述在所述图形化掩膜层以及所述第二半导体层上生长所述应力补偿层，包括：
    在所述图形化掩膜层以及所述第二半导体层上生长一层氮面氮化物层，以形成所述应力补偿层。
  18. 根据权利要求16所述的制备方法，其中，所述在所述图形化掩膜层以及所述第二半导体层上生长所述应力补偿层，包括：
    在所述图形化掩膜层以及所述第二半导体层上生长一层氧面氧化锌，以形成所述应力补偿层。
  19. 根据权利要求15所述的制备方法，其中，所述在所述外延层上形成应力补偿层，包括：
    在所述第二半导体层远离所述衬底的一侧制备第一应力补偿层；
    刻蚀第一应力补偿层，保留与所述栅极的侧壁接触的预设范围内的第二应力补偿层，得到所述应力补偿层。
  20. 根据权利要求15所述的制备方法，其中，所述在所述外延层上形成应力补偿层之后，且在所述外延层上设置源极、漏极和栅极之前，还包括：
    在所述应力补偿层和所述第二半导体层远离所述衬底的一侧制备钝化层；
    所述在外延层上设置源极、漏极和栅极，包括：
    刻蚀所述钝化层开孔并在所述开孔处制备所述源极、所述漏极以及所述栅极。
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