WO2024040614A1 - 基板、背光模组及显示装置 - Google Patents

基板、背光模组及显示装置 Download PDF

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Publication number
WO2024040614A1
WO2024040614A1 PCT/CN2022/115302 CN2022115302W WO2024040614A1 WO 2024040614 A1 WO2024040614 A1 WO 2024040614A1 CN 2022115302 W CN2022115302 W CN 2022115302W WO 2024040614 A1 WO2024040614 A1 WO 2024040614A1
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WO
WIPO (PCT)
Prior art keywords
buffer structure
reflective layer
circuit board
slit
closed
Prior art date
Application number
PCT/CN2022/115302
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English (en)
French (fr)
Inventor
王晨阳
王康丽
张冰
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/115302 priority Critical patent/WO2024040614A1/zh
Priority to CN202280002873.9A priority patent/CN117941086A/zh
Publication of WO2024040614A1 publication Critical patent/WO2024040614A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a substrate, a backlight module and a display device.
  • a substrate in one aspect, includes a circuit board and a first reflective layer.
  • the first reflective layer is disposed on the circuit board.
  • the first reflective layer includes a central area and an edge area surrounding the central area.
  • the first reflective layer includes at least one first buffer structure group, and the orthographic projection of the first buffer structure group on the circuit board falls into the edge area.
  • Each first buffer structure group includes a plurality of first slits spaced apart from each other, and the plurality of first slits in any first buffer structure group are arranged around the central area.
  • the first reflective layer includes a plurality of first buffer structure groups, there is a gap between any two adjacent first buffer structure groups, and the centers of the plurality of first buffer structure groups are The geometric centers of the central areas coincide.
  • the two adjacent first buffer structures Staggered set of first slits in the group.
  • each first slit in the first buffer structure group is connected end to end in a clockwise or counterclockwise direction to form a first closed pattern.
  • the first closed figure has a first perimeter, a first length accounting for at least 1/4 of the first perimeter, and the first length is a length of a plurality of first slits in the first buffer structure group. The sum of the lengths.
  • the edge area of the first reflective layer further includes at least one second buffer structure group, and the orthographic projection of the second buffer structure group on the circuit board falls into the edge area.
  • Each second buffer structure group includes at least one second slit extending in a direction perpendicular to the boundary of the central region.
  • the second buffer structure group includes a plurality of second slits, the plurality of second slits are The second slits extend in the same direction and are spaced apart.
  • the first reflective layer includes a plurality of second buffer structure groups.
  • the plurality of second buffer structure groups are spaced apart along the circumferential side of the central area of the first reflective layer, and two adjacent ones The second slits in the second buffer structure group are staggered.
  • any of the second buffer structure groups intersects with at least one of the first buffer structure groups.
  • each functional area is provided with multiple electronic components connected in series and/or in parallel.
  • the first slit is located between two adjacent functional areas.
  • the second slit is located between two adjacent functional areas.
  • the area of the edge region accounts for 15% to 25% of the area of the first reflective layer parallel to the surface of the circuit board.
  • the substrate further includes a plurality of electronic components and a plurality of packaging portions.
  • the plurality of electronic components are arranged on the circuit board.
  • One packaging part encloses at least one electronic component.
  • the first reflective layer also includes a plurality of hollow areas and at least one third buffer structure group.
  • An electronic component is located in a hollow area, and a packaging part covers at least one hollow area.
  • Each of the third buffer structure groups includes a plurality of third slits spaced apart from each other, and the plurality of third slits in one third buffer structure group are arranged around one of the packaging parts.
  • the first reflective layer is provided with a plurality of third buffer hole groups, at least two third buffer structure groups are arranged around the same packaging part, and among the at least two third buffer structure groups, There is a gap between any two adjacent third buffer structure groups.
  • the centers of at least two third buffer structure groups arranged around the same packaging part coincide with the geometric center of the packaging part.
  • the two adjacent third buffer structures in two adjacent third buffer structure groups, in a direction perpendicular to the boundary of the hollow area and parallel to the plane where the circuit board is located, the two adjacent third buffer structures A staggered set of third slits in the set.
  • each third slit in the third buffer structure group is connected end to end in a clockwise or counterclockwise direction to form a second closed pattern.
  • the outer boundary of the orthographic projection of the packaging part on the circuit board forms a third closed pattern.
  • the outer boundary of the orthographic projection of the hollow area on the circuit board forms a fourth closed pattern. At least two of the second closed figure, the third closed figure and the fourth closed figure are similar figures to each other.
  • both the second closed figure and the third closed figure are circles.
  • the ratio of the diameter of the second closed pattern corresponding to the third buffer structure group closest to the packaging part to the diameter of the packaging part is greater than 1 and less than or equal to 1.2; and/or, at least two third buffer structures Groups are arranged around the same package.
  • the ratio of the diameter difference between the two second closed figures corresponding to any two adjacent third buffer structure groups to the diameter of the packaging part is greater than 0 and less than or equal to 0.2.
  • the second closed figure is a polygon
  • the third closed figure is a circle.
  • the ratio of the diagonal of the second closed figure corresponding to the third buffer structure group closest to the packaging part to the diameter of the packaging part is greater than 1 and less than or equal to 1.2; and/or, at least two third The buffer structure group is arranged around the same packaging part.
  • the difference between the diagonals of the two second closed figures corresponding to any two adjacent third buffer structure groups and the diameter ratio of the packaging part is greater than 0 and Less than or equal to 0.2.
  • each third slit in the third buffer structure group is connected end to end in a clockwise or counterclockwise direction to form a second closed pattern.
  • the second closed figure has a second perimeter, the second length accounts for at least 1/4 of the second perimeter, and the second length is a length of a plurality of third slits in the third buffer structure group. The sum of the lengths.
  • the length of the first slit is approximately 1.9 mm to 2.1 mm, and the width of the first slit is approximately 0.02 mm to 0.08 mm.
  • the first reflective layer is provided with a second slit
  • the length of the second slit is approximately 1.9 mm to 2.1 mm
  • the width of the second slit is approximately 0.02 mm to 0.08 mm.
  • the first reflective layer is provided with a third slit
  • the length of the third slit is approximately 1.9 mm to 2.1 mm, and the width of the third slit is approximately 0.02 mm to 0.08 mm.
  • the first reflective layer further includes a plurality of hollow areas.
  • the substrate also includes a plurality of electronic components and a second reflective layer.
  • the plurality of electronic components are arranged on the circuit board, and one electronic component is located in a hollow area.
  • the second reflective layer is disposed between the first reflective layer and the circuit board; the reflective layer is provided with a plurality of openings, an electronic component is located in one opening, and one opening is located in a hollow area.
  • the ratio of the length of the electronic component to the length of the opening ranges from 0.50 ⁇ 0.70; and/or, in a direction perpendicular to the boundary of the opening and parallel to the plane where the circuit board is located, the ratio of the length of the opening to the length of the hollow area ranges from 0.15 ⁇ 0.3.
  • the backlight module includes the substrate described in any of the above embodiments and a plurality of optical films.
  • the substrate has opposite light-emitting sides and a non-light-emitting side, and the plurality of optical films are arranged on the light-emitting side of the substrate.
  • a display device in another aspect, includes the backlight module and a display panel described in the above embodiments.
  • the display panel is disposed on a side of the plurality of optical films in the backlight module away from the substrate.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is a cross-sectional view of a display device according to some embodiments.
  • Figure 3 is an equivalent circuit diagram of a substrate according to some embodiments.
  • Figure 4 is a top view of a first reflective layer according to some embodiments.
  • Figure 5 is a top view of another first reflective layer according to some embodiments.
  • Figure 6 is a top view of yet another first reflective layer according to some embodiments.
  • Figure 7 is a top view of a substrate according to some embodiments.
  • Figure 8 is a cross-sectional view at A-A' in Figure 7;
  • Figure 9A is a partial enlarged view of position A in Figure 8.
  • Figure 9B is a partial enlarged view of B in Figure 8.
  • Figure 10A is a partial enlarged view of a packaging portion of a substrate according to some embodiments.
  • Figure 10B is a partial enlarged view of a packaging portion of another substrate according to some embodiments.
  • Figure 11 is a partial enlarged view of the first reflective layer according to some embodiments.
  • Figure 12 is a top view of yet another first reflective layer according to some embodiments.
  • Figure 13 is a schematic diagram of the location of each test point.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and the areas of regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • a display device 1000 which may be any device that displays images, whether moving (eg, video) or stationary (eg, still images), and whether text or text.
  • the display device 1000 can be a television, a laptop, a tablet, a mobile phone, a personal digital assistant (English: Personal Digital Assistant; PDA for short), a navigator, a wearable device, an augmented reality (English: Augmented Reality) ; Abbreviation: AR) equipment, virtual reality (English: Virtual Reality; abbreviation: VR) equipment and any other products or components with display functions.
  • a personal digital assistant English: Personal Digital Assistant; PDA for short
  • PDA Personal Digital Assistant
  • AR Augmented Reality
  • VR Virtual Reality
  • the above-mentioned display device 1000 may be a liquid crystal display device.
  • the display device 1000 may include a display panel 100 , a backlight module 200 and a glass cover 300 .
  • the display panel 100 includes a light emitting side and a non-light emitting side arranged oppositely.
  • the light emitting side refers to the side of the display panel 100 used to display images (the upper side of the display panel 100 in FIG. 2 ), and the non-light emitting side refers to the other side opposite to the light emitting side (the lower side of the display panel 100 in FIG. 2 ). .
  • the backlight module 200 is disposed on the non-light emitting side of the display panel 100 , and is used to provide a light source for the display panel 100 .
  • the glass cover 300 is disposed on the light emitting side of the display panel 100 , and is used to protect the display panel 100 .
  • the material used for the glass cover 300 can be rigid materials such as glass, quartz, and plastic, or flexible materials such as polymer resin.
  • the backlight module 200 may include a substrate 210 and a plurality of optical films 220 .
  • the substrate 210 has an opposite light-emitting side and a non-light-emitting side.
  • the light-emitting side refers to the side of the substrate 210 that provides a light source (the upper side of the substrate 210 in FIG. 2 ), and the non-light-emitting side refers to the other side opposite to the light-emitting side (FIG. 2 the lower side of the middle substrate 210).
  • a plurality of optical films 220 are disposed on the light-emitting side of the substrate 210 .
  • the substrate 210 can directly emit white light, and the white light is uniformly processed by a plurality of optical films 220 and then emitted to the display panel 100 .
  • the substrate 210 may also emit light of other colors (for example, blue light), and then undergo color conversion and light uniformity processing through a plurality of optical films 220 before being emitted to the display panel 100 .
  • the plurality of optical films 220 include a diffusion plate 221 , a quantum dot film 222 , a diffusion sheet 223 and a composite film 224 arranged in sequence.
  • the diffusion plate 221 can blur the light emitted by the substrate 210 and provide support for the quantum dot film 222, the diffusion sheet 223 and the composite film 224.
  • the quantum dot film 222 can convert the light of a certain color emitted by the substrate 210 into white light under excitation, so as to improve the utilization rate of the light energy of the substrate 210 .
  • the diffusion sheet 223 can homogenize the light passing through the diffusion sheet 223 .
  • the composite film 224 can improve the light extraction efficiency of the backlight module 200 and improve the display brightness of the display device 1000 .
  • the composite film 224 may include a brightness enhancement film (English: Brightness Enhancement Film; abbreviation: BEF) and a reflective polarized brightness enhancement film (English: Dual Brightness Enhancement Film; abbreviation: DBEF), which utilizes total reflection, refraction and The principle of polarization increases the light flux within a certain angle range to increase the brightness of the display device 1000 .
  • BEF Brightness Enhancement Film
  • DBEF Dual Brightness Enhancement Film
  • the substrate 210 emits blue light in a direction away from the substrate 210 .
  • the quantum dot film 222 may include red quantum dot material, green quantum dot material, and transparent material.
  • red quantum dot material When the blue light emitted by the substrate 210 passes through the red quantum dot material, it is converted into red light; when the blue light passes through the green quantum dot material, it is converted into green light; the blue light can directly pass through the transparent material; then, Blue light, red light and green light are mixed and superimposed in a certain proportion to appear as white light.
  • the diffusion plate 221 and the diffusion sheet 223 can mix the white light evenly to improve the light shadow generated by the substrate 210 and improve the display quality of the display device 1000.
  • the first reflective layer 30 may also be provided with a plurality of through holes (not shown in the figure), and the through holes are used to correspond to areas where a support structure is provided on the substrate 210, where the support structure is used to provide a backlight module.
  • the required optical distance (OD) of the group is that one end of the support structure is in contact with the substrate 210 and the other end is in contact with the surface of the film closest to the substrate 210 among the plurality of optical films 220.
  • the size of the through holes is consistent with the size of the surface where the support structure contacts the substrate 210; the arrangement of the through holes is at least the same as the arrangement of the support structure on the substrate 210.
  • the through hole does not interfere with any one of the first buffer structure group 31, the second buffer structure group 32, the third buffer structure group 33, and the hollow area 301.
  • the substrate 210 includes a circuit board 10 , a plurality of electronic components 20 , a first reflective layer 30 and a packaging part 40 .
  • the circuit board 10 may be an FR4 type printed circuit board (English: Printed Circuit Board, PCB for short), or may be an easily deformable flexible PCB.
  • the material used in the circuit board 10 may include one or more ceramic materials such as silicon nitride, AlN and Al2O3, and may also include metal or metal compounds, such as a metal core printed circuit board (English: Metal Core PCB) or Metal copper clad laminate (English: Metal Copper Clade Laminate, abbreviation: MCCL).
  • the circuit board 10 includes a substrate 101 and at least one conductive layer 102 disposed on the substrate 101 .
  • the substrate 101 may be any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, etc.; or a semiconductor substrate such as a single crystal semiconductor substrate made of silicon or silicon carbide; or Any of polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, silicon on insulator (English: Silicon On Insulator, SOI), etc.; the substrate 101 can also be made of materials such as epoxy resin, A film layer made of one or more organic resin materials including triazine, silicone resin and polyimide.
  • the conductive layer 102 is made of one or more materials selected from the group consisting of copper, molybdenum-niobium alloy (MoNb), nickel, and indium tin oxide.
  • the circuit board 10 may include bonding pads 13 and circuit traces 14 , the bonding pads 13 are configured to connect electronic components 20 , and the circuit traces 14 are configured to connect different pads 13 or transmit signals.
  • bonding pad 13 and the circuit trace 14 may be located on the above-mentioned conductive layer 102, for example.
  • a plurality of electronic components 20 are provided on the circuit board 10 , and the electronic components 20 may include light-emitting devices 21 and microchips 22 .
  • the light-emitting device 21 may include one of a micro light-emitting diode (English: Micro Light Emitting Diode, abbreviation: Micro LED) and a sub-millimeter light-emitting diode (English: Mini Light Emitting Diode, abbreviation: Mini LED) or Various.
  • a micro light-emitting diode English: Micro Light Emitting Diode, abbreviation: Micro LED
  • a sub-millimeter light-emitting diode English: Mini Light Emitting Diode, abbreviation: Mini LED
  • the size (such as length) of Micro LED is less than 50 microns, for example, 10 microns to 50 microns.
  • the size (such as length) of Mini LED is 50 microns to 150 microns, such as 80 microns to 120 microns.
  • different light-emitting devices 21 can be selected and arranged according to actual needs.
  • the microchip 22 may include a sensing chip and a driving chip.
  • the sensing chip may be, for example, a light-sensitive sensor chip or a thermal sensor chip.
  • the driving chip is used to provide driving signals to the light emitting device 21 .
  • the microchip 22 includes a driver chip as an example.
  • the bonding pad 13 includes a first bonding pad 131 and a second bonding pad 132.
  • a light emitting device 21 is electrically connected to the circuit board 10 through the two first bonding pads 131, and a microchip 22 is electrically connected to the circuit board 10 through four second pads 132 .
  • the first reflective layer 30 is disposed on the circuit board 10 , and the first reflective layer 30 is configured to reflect the light emitted by the light-emitting device 21 towards the circuit board 10 , so that more light emitted by the light-emitting device 21 is emitted. to the display panel 100 (see FIG. 2 ), thereby improving the light extraction efficiency of the substrate 210 and improving the display effect.
  • the material of the first reflective layer 30 includes polyester material, which has higher reflectivity, better picture effect, and lower power consumption.
  • the material of the first reflective layer 30 includes a polymer obtained by condensation of polyol and polybasic acid; for example, the material of the first reflective layer 30 includes polyethylene terephthalate, polybutylene terephthalate. and at least one of linear thermoplastic resins such as polyarylate.
  • An adhesive layer is provided on the surface of the first reflective layer facing the circuit board, and the first reflective layer is attached and fixed to the circuit board by adhesive.
  • the first reflective layer 30 is provided with a plurality of hollow areas 301, a plurality of pads 13 are provided in one hollow area 301, and an electronic component 20 is located in a hollow area 301, that is, an electronic component 20 passes through the hollow area 301 and is electrically connected to the pad 13 on the circuit board 10 .
  • the shape of the outline of the orthographic projection of the hollow area 301 on the circuit board 10 may be circular, polygonal, etc., which is not specifically limited in the embodiment of the present disclosure.
  • the outline of the orthographic projection of the hollow area 301 on the circuit board 10 is a circle as an example for illustration.
  • the maximum size of the hollow area 301 is less than or equal to 2.5 mm.
  • the outline of the orthographic projection of the hollow area 301 on the circuit board 10 is circular, and the aperture of the hollow area 301 is 1.4 mm to 1.6 mm.
  • the aperture of the hollow area 301 is smaller, which allows more light emitted by the light-emitting device 21 to be directed to the display panel 100, thereby improving the light extraction efficiency of the substrate 210 and improving the display effect.
  • the first reflective layer 30 can be compatible with a display device in which the distance between the electronic components 20 (such as the light-emitting devices 21) is smaller, that is, it is compatible with a display device 1000 with a higher pixel density.
  • the electronic component 20 includes a light-emitting device 21
  • the hollow area 301 includes a first hollow area 3011
  • two first pads 131 are provided in the first hollow area 3011
  • one light-emitting device 21 corresponds to a first hollow area 3011
  • the two pins of the light-emitting device 21 are electrically connected to the two first pads 131 respectively.
  • the electronic component 20 includes a microchip 22
  • the hollow area 301 includes a second hollow area 3012
  • four second pads 132 are also provided in the second hollow area 3012 .
  • the chip 22 corresponds to a second hollow area 3012, and the four pins of the microchip 22 are electrically connected to the four second pads 132 respectively.
  • first hollow area 3011 and the second hollow area 3012 may be the same or different.
  • the hollow area 301 is positively related to the size of the corresponding electronic component 20 , and the shape of the hollow area 301 is similar to the outline of the orthographic projection of the corresponding electronic component 20 on the circuit board 10 .
  • the shape of the first hollow area 3011 is similar to the outline of the orthographic projection of the light-emitting device 21 on the circuit board 10; the shape of the second hollow area 3012 is similar to the outline of the orthographic projection of the microchip 22 on the circuit board 10. graphics.
  • one packaging part 40 wraps at least one electronic component 20 .
  • the shape of the packaging part 40 may be a hemispherical shape, a semi-ellipsoidal shape, etc., which are not specifically limited in the embodiment of the present disclosure.
  • high thixotropic glue can be sprayed onto the hemispherical packaging part 40 formed on the electronic component 20 through a glue dispenser.
  • the materials of the packaging portion 40 may be the same or different.
  • the electronic component 20 is an optical component
  • the packaging part 40 is made of a transparent material
  • the electronic component 20 is a non-optical component
  • the material of the packaging part 40 does not require light transmission, and can be made of transparent materials, reflective materials, or light-absorbing materials.
  • the electronic component 20 includes a light-emitting device 21
  • the above-mentioned packaging part 40 includes a first packaging part 41 that wraps the light-emitting device 21 .
  • the material of the first packaging part 41 is a transparent material, and the transparent material may include Transparent silicone.
  • the electronic component 20 includes a microchip 22
  • the above-mentioned packaging part 40 includes a second packaging part 42 that wraps the microchip 22
  • the second packaging part 42 may be made of transparent material to save processes;
  • the second encapsulation part 42 may also be made of reflective material, and the reflective material may include at least one of white ink, white resin, and silicone white glue;
  • the second encapsulating part 42 may also be made of light-absorbing material, and the light-absorbing material may include black ink, black resin. and at least one of silicone-based vinyl.
  • one encapsulation part 40 covers at least one hollow area 301.
  • the encapsulation part 40 covers the hollow area 301 of the first reflective layer 30, which can protect the electronic components 20 in the hollow area 301, which is beneficial to improving the waterproofness and corrosion resistance of the substrate 210, and improving the light extraction efficiency of the substrate 210.
  • the substrate was stored for 1000H at a temperature of 85°C and a humidity of 85%. Since the thermal expansion coefficient of the first reflective layer is different from that of the circuit board, the first reflective layer and The expansion and contraction of the circuit board are different, causing the first reflective layer to shrink from the periphery to the center relative to the circuit board. The packaging part is pulled by the first reflective layer, and the edge displacement of the circuit board accumulates, causing the circuit board to warp.
  • the packaging part when the tensile force on the packaging part reaches the sum of the friction between the packaging part and the circuit board and the resistance between the packaging part and the electronic component, the packaging part will crack and peel off from the substrate. At the same time, the packaging part will generate a thrust force on the electronic component it wraps. When the thrust force is greater than or equal to the resistance of the electronic component, the electronic component will fall off from the pad, thereby causing the adverse risk of the light-emitting device not lighting up.
  • the first reflective layer 30 includes a central area M1 and an edge area M2 surrounding the central area M1.
  • the area of the edge region M2 accounts for 15% to 25% of the area of the first reflective layer parallel to the surface of the circuit board. Specifically, in the direction parallel to the plane where the circuit board 10 is located, The size of the edge region M2 in a direction parallel to a certain boundary of the first reflective layer 30 accounts for 5% to 15% of the size of the boundary.
  • the edge area M2 of the first reflective layer 30 also includes at least one first buffer structure group 31 , and the orthographic projection of the first buffer structure group 31 on the circuit board 10 falls into the edge area M2 .
  • each first buffer structure group 31 includes a plurality of first slits 310 , and the plurality of first slits in each first buffer structure group 31 are spaced apart from each other. 310, and a plurality of first slits 310 in any first buffer structure group 31 are arranged around the central area M1.
  • both the central area M1 and the edge area M2 of the first reflective layer 30 can shrink and deform at the plurality of first slits 310 in the first buffer structure group 31 , so that the stress of the first reflective layer 30 is dispersed. , reducing the displacement accumulation of the edge area M2 of the first reflective layer 30, so that the tendency of relative movement between the edge area M2 of the first reflective layer 30 and the circuit board 10 is weakened, thereby reducing the impact of the edge area M2 of the first reflective layer 30 on the circuit board.
  • the stretching of 10 reduces the warpage of the circuit board 10 (substrate 210).
  • the relative movement tendency between the edge area M2 of the first reflective layer 30 and the circuit board 10 is weakened, which can further reduce the risk of cracking of the packaging part 40 located in the edge area M2 and further reduce the risk of cracking between the packaging part 40 located in the edge area M2 and the circuit board 10 .
  • the shape of the first slit 310 may be a regular shape such as a circle, a fan ring, a rectangle, etc., or may be an irregular shape.
  • the shape of the first slit 310 is generally a rectangle or a sector ring.
  • the long sides of the rectangle extend in the circumferential direction of the central region M1 .
  • the arc edge of the fan ring extends along the circumferential direction of the central area M1.
  • the length L1 of the first slit 310 is approximately 1.9 mm to 2.1 mm, and the width W1 of the first slit 310 is approximately 0.02 mm to 0.08 mm.
  • the length L1 of the first slit 310 is approximately any one of 1.9mm, 2.0mm, or 2.1mm, and the width W1 of the first slit 310 is approximately 0.02mm, 0.03mm, 0.04mm, 0.05mm, or 0.06mm. , 0.07mm or 0.08mm any one.
  • the length of the first slit 310 refers to the length of the arc edge of the fan ring.
  • the ratio between the extension length of each first slit 310 and the distance between two adjacent first slits 310 is not unique.
  • each first slit 310 in the above-mentioned first buffer structure group 31 is connected end to end in a clockwise or counterclockwise direction to form a first closed pattern S1.
  • the first closed figure S1 has a first circumference, the first length accounts for at least 1/4 of the first circumference, and the first length is the sum of the lengths of the plurality of first slits 310 in the first buffer structure group 31 .
  • the buffer zone formed by the plurality of first slits 310 in the first buffer structure group 31 has a more obvious buffering effect, and the structural strength between the plurality of first slits 310 is greater and the risk of breakage is smaller.
  • the first reflective layer 30 includes a plurality of first buffer structure groups 31 , and there is a gap between any two adjacent first buffer structure groups 31 .
  • a plurality of buffer zones can be formed on the peripheral side of the central area M1.
  • the distance between two adjacent first buffer structure groups 31 may be a positive integer multiple of the size of a functional area, for example, the distance between two adjacent first buffer structure groups 31 may be a positive integer multiple of the size of a functional area.
  • the interval between them is set by the width of a functional area; in some embodiments, the interval between two adjacent first buffer structure groups 31 (such as 31-1 and 31-2 in Figure 4) can also have a value range.
  • the value is between 0.5mm and 2.5mm, such as 0.8mm or 1mm; in some embodiments, two adjacent second buffer structure groups 32 can be arranged at other regular intervals.
  • the stress distribution in the edge area M2 of the first reflective layer 30 is more uniform, which can further reduce the accumulation of displacement in the edge area M2 of the first reflective layer 30 , so that the edge area M2 of the first reflective layer 30 is in contact with the circuit board 10
  • the tendency of relative movement is weakened, thereby reducing the stretching of the circuit board 10 by the edge area M2 of the first reflective layer 30 and reducing the warpage of the circuit board 10 (substrate 210).
  • the risk of cracking of the packaging part 40 located in the edge area M2 can be further reduced, and the luminescence of the substrate 210 located in the edge area M2 can be further reduced. There is a risk that the device 21 may fail to light up.
  • the centers of the plurality of first buffer structure groups 31 coincide with the geometric center of the central area M1, so that the spacing between the plurality of buffer zones formed by the plurality of first buffer structure groups 31 is approximately equal, so that the first reflective layer In the edge area M2 of the first reflective layer 30 , the tensile force exerted on the portion located between the buffer zones is evenly distributed, thereby avoiding the risk of cracking caused by excessive tensile force in the edge area M2 of the first reflective layer 30 located between the buffer zones.
  • the buffer areas of the multiple buffer zones formed by the first buffer structure group 31 in the edge area M2 can form a complete closed pattern, so that the edge area M2 of the first reflective layer 30 is located where the circuit board 10 is located.
  • the buffer zone can be buffered to prevent the local area of the edge area M2 of the first reflective layer 30 from not having the buffering effect of the buffer zone, resulting in a local area of the edge area M2 of the first reflective layer 30
  • the risk of cracking of the packaging part 40 due to excessive pulling force is beneficial to improving the waterproofness and corrosion resistance of the substrate 210 .
  • the edge area M2 of the first reflective layer 30 also includes at least one second buffer structure group 32 , and the second buffer structure group 32 is located directly on the circuit board 10 (see FIG. 8 ). The projection falls into the edge region M2.
  • each second buffer structure group 32 includes a plurality of second slits 320 spaced apart from each other.
  • the plurality of second slits 320 in any second buffer structure group 32
  • the slits 320 are spaced apart in a direction perpendicular to the boundary of the central region M1.
  • Each second buffer structure group 32 includes at least one second slit 320 extending in a direction perpendicular to the boundary of the central region M1. That is, referring to FIG. 12 , the extending direction of the second slit 320 is substantially perpendicular to the side of the first buffer structure group 31 forming the first closed pattern S1 .
  • the second buffer structure group 32 includes a plurality of second slits 320
  • the plurality of second slits 320 extend in the same direction and are arranged at intervals.
  • the second buffer structure group 32 at the corner position of the first reflective layer 30 may only include one second slit 320
  • the second buffer structure group 32 at non-corner positions The group 32 may include a plurality of second slits 320 extending in the same direction and spaced apart along the direction.
  • the edge region M2 of the first reflective layer 30 can shrink and deform at the plurality of second slits 320 in the second buffer structure group 32, so that the stress of the first reflective layer 30 is more dispersed and further reduced.
  • the edge area M2 of the first reflective layer 30 stretches the circuit board 10, reducing the warpage of the circuit board 10 (substrate 210), and further reducing the risk of cracking of the packaging portion 40 located in the edge area M2, and further reducing
  • the light-emitting device 21 located in the edge region M2 of the substrate 210 may have a defective risk of not lighting up.
  • the shape of the second slit 320 may be a regular shape such as a circle or a rectangle, or may be an irregular shape.
  • the second slit 320 is substantially rectangular in shape, and the long side of the rectangle extends in a direction perpendicular to the boundary of the central area M1 .
  • the length L2 of the second slit 320 is approximately 1.9 mm to 2.1 mm, and the width W2 of the second slit 320 is approximately 0.02 mm to 0.08 mm.
  • the length L2 of the second slit 320 is approximately any one of 1.9mm, 2.0mm, or 2.1mm, and the width W2 of the second slit 320 is approximately 0.02mm, 0.03mm, 0.04mm, 0.05mm, or 0.06mm. , 0.07mm or 0.08mm any one.
  • the ratio between the extension length of each second slit 320 and the distance between two adjacent second slits 320 is not unique.
  • the length of the second slit 320 and the length between the two adjacent second slits 320 range from 1 to 3.
  • the buffer zone formed by the plurality of second slits 320 in the second buffer structure group 32 has a more obvious buffering effect, and the structural strength between the plurality of second slits 320 is greater and the risk of breakage is smaller.
  • the first reflective layer 30 includes a plurality of second buffer structure groups 32 along the perimeter of the central region M1 of the first reflective layer 30 .
  • the sides are spaced apart, and the second slits 320 in two adjacent second buffer structure groups 32 are staggered.
  • the first reflective layer 30 includes a plurality of second buffer structure groups 32 , and there is a gap between any two adjacent first buffer structure groups 31 .
  • the distance between two adjacent second buffer structure groups 32 may be a positive integer multiple of the size of a functional area, for example, the distance between two adjacent second buffer structure groups 32 may be a positive integer multiple of the size of a functional area.
  • the interval between them is set by the width of a functional area; in some embodiments, the interval between two adjacent second buffer structure groups 32 can also range from 0.8mm to 2.5mm, for example, 1mm. ; In some embodiments, two adjacent second buffer structure groups 32 may be arranged at other regular intervals. It can be understood that two adjacent second buffer structure groups 32 refer to that the second slits 320 in the two second buffer structure groups 32 are spaced apart along the same direction (for example, the first direction). , and the two second buffer structure groups 32 are adjacently arranged along a non-first direction (for example, a second direction perpendicular to the first direction).
  • any second buffer structure group 32 intersects with at least one first buffer structure group 31 .
  • the plurality of second slits 320 of the second buffer structure group 32 and the plurality of first slits 310 of the first buffer structure group 31 form a grid structure, so that the edge region M2 of the first reflective layer 30 is subjected to The tensile force is distributed more evenly.
  • the substrate 210 includes a plurality of functional areas 50 , and each functional area 50 includes a plurality of electronic components 20 connected in series and/or in parallel.
  • each functional area 50 includes a plurality of light-emitting devices 21 and at least one microchip 22 connected in series and/or in parallel.
  • each functional area 50 includes four light-emitting devices 21 and one microchip 22 connected in series.
  • each functional area 50 can also include 5, 6, 7 or 8 light-emitting devices 21, and the connection method of the multiple light-emitting devices 21 in the functional area 50 is not limited to series connection, but can also be connected in parallel. This disclosure The embodiment is not limited thereto.
  • the first slit 310 and/or the second slit 320 may be located between two adjacent functional areas 50 . Arranged in this manner, the deformation and shrinkage of the first reflective layer 30 in each functional area 50 is approximately the same, so that the distribution of luminous centers in each functional area 50 is approximately the same, improving the uniformity of the brightness distribution of the display device 1000 (see FIG. 1 ). Improve display effect. It can be understood that part of the first slits 310 and/or the second slits 320 may also be located in a region where a certain functional area 50 is located.
  • the grid structure when the second buffer structure group 32 intersects with at least one first buffer structure group 31 to form a grid structure, at least part of the grid structure may correspond to one functional area 50, that is, the grid structure is arranged adjacent to between the functional areas 50; in some embodiments, the grid structure does not correspond to the functional area 50, that is, the grid structure can pass through the area where the functional area 50 is located. It can be understood that the grid structure is not configured in the functional area 50. The electronic components 20 do not interfere with each other.
  • At least one third buffer structure group 33 is also provided on the first reflective layer 30 .
  • Each third buffer structure group 33 includes a plurality of third slits 330 spaced apart from each other, and the plurality of third slits 330 in a third buffer structure group 33 are arranged around a packaging part 40 .
  • the first reflective layer 30 may shrink and deform at the plurality of third slits 330 in the third buffer structure group 33 , that is, the portion where the first reflective layer 30 contacts the encapsulation part 40 , in the third buffer structure group 33 .
  • the portion of the first reflective layer 30 that is in contact with the encapsulation part 40 has a weakened tendency to move relative to the circuit board 10 .
  • the pulling force of the first reflective layer 30 on the packaging part 40 is reduced, which can reduce the risk of cracking of the packaging part 40 and thereby reduce the risk of peeling of the packaging part 40 and the circuit board 10; at the same time, the first reflective layer 30 exerts less force on the packaging part 40.
  • the reduction of the pulling force of the packaging part 40 can also reduce the pushing force produced by the packaging part 40 on the electronic component 20 that it wraps, thereby reducing the risk of the substrate 210 causing defects such that the light-emitting device 21 does not light up.
  • the relative movement tendency of the first reflective layer 30 and the circuit board 10 is weakened, and the first reflective layer 30 can be reduced.
  • the stretching of the circuit board 10 reduces the warpage of the circuit board 10 (substrate 210).
  • the shape of the third slit 330 may be a regular shape such as a circle, a fan ring, a rectangle, etc., or may be an irregular shape.
  • the shape of the third slit 330 is generally a rectangle or a sector ring.
  • narrowly rectangular or fan-ring means that the shape is generally rectangular or fan-ring, but is not limited to a standard rectangle or fan-ring. That is, the "rectangle or sector ring” here includes not only a shape that is basically a rectangle or a sector ring, but also a shape similar to a rectangle or a sector ring in consideration of process conditions. For example, the corners or short sides of a rectangle are curved; for example, the corners or short sides of a fan ring are curved.
  • the shape of the third slit 330 is substantially rectangular, and the long side of the rectangle extends along the circumferential direction of the packaging part 40 .
  • the third slit 330 is generally in the shape of a fan ring, and the arc edge of the fan ring extends along the circumferential direction of the packaging part 40 .
  • the length L3 of the third slit 330 is approximately 1.9 mm to 2.1 mm, and the width W3 of the third slit 330 is approximately 0.02 mm to 0.08 mm.
  • the length L3 of the third slit 330 is approximately any one of 1.9mm, 2.0mm, or 2.1mm, and the width W3 of the third slit 330 is approximately 0.02mm, 0.03mm, 0.04mm, 0.05mm, or 0.06mm. , 0.07mm or 0.08mm any one.
  • the length of the third slit 330 refers to the length of the arc edge of the fan ring.
  • the ratio between the extension length of each third slit 330 and the distance between two adjacent third slits 330 is not unique.
  • each third slit 330 in the third buffer structure group 33 is connected end to end in a clockwise or counterclockwise direction to form a second closed pattern S2.
  • the second closed figure S2 has a second perimeter, and the second length accounts for at least 1/4 of the second perimeter.
  • the second length is the sum of the lengths of the plurality of third slits 330 in the third buffer structure group 33 .
  • the buffer zone formed by the plurality of third slits 330 in the third buffer structure group 33 has a more obvious buffering effect, and the structural strength between the plurality of third slits 330 is greater and the risk of breakage is smaller.
  • the first reflective layer 30 is provided with multiple third buffer structure groups 33 , and at least two third buffer structure groups 33 surround the same packaging part 40 is provided, and among at least two third buffer structure groups 33, there is a gap between any two adjacent third buffer structure groups 33.
  • a plurality of buffer zones are formed on the peripheral side of each packaging portion 40 . It can be understood that the interval between two adjacent third buffer structure groups 33 surrounding the same packaging part 40 ranges from 0.5 mm to 1.5 mm, for example, 1 mm.
  • the portion of the first reflective layer 30 that is in contact with the encapsulation portion 40 can further weaken its tendency to move relative to the circuit board 10 under the buffering action of multiple buffer strips, thereby reducing the impact of the first reflective layer 30 on the circuit board 10 .
  • the tensile force of the encapsulation part 40 further reduces the risk of the encapsulation part 40 cracking and peeling off from the circuit board 10 , and further reduces the risk of the substrate 210 having a defect such that the light-emitting device 21 does not light up.
  • the centers of at least two third buffer structure groups 33 arranged around the same packaging part 40 coincide with the geometric center of the packaging part 40 , so that the spacing between the multiple buffer strips is approximately equal, so that the first reflective layer 30
  • the tensile force received by the portion located between the buffer strips is evenly distributed, thereby avoiding the risk of cracking caused by excessive tensile force on the portion of the first reflective layer 30 located between the buffer strips.
  • two adjacent third buffer structure groups 33 are adjacent in a direction perpendicular to the boundary of the hollow area 301 and parallel to the plane where the circuit board 10 is located.
  • the third slits 330 in the two third buffer structure groups 33 are staggered.
  • the “plane on which the circuit board 10 is located” refers to the surface of the circuit board 10 with the largest plane area.
  • each packaging part 40 multiple buffer zones are formed on the peripheral side of each packaging part 40, and the buffer areas can form a complete closed pattern, so that the part where the first reflective layer 30 contacts the packaging part 40 is located where the circuit board 10 is located. Any direction parallel to the plane can be buffered by the buffering effect of the buffer tape to prevent the local area of the contact between the first reflective layer 30 and the packaging part 40 from not having the buffering effect of the buffering tape, resulting in excessive local pulling force on the packaging part 40 The risk of cracking is beneficial to improving the waterproofness and corrosion resistance of the substrate 210 .
  • each third slit 330 in the third buffer structure group 33 is connected end to end in a clockwise or counterclockwise direction to form a second closed pattern S2.
  • the outer boundary of the orthographic projection of the packaging part 40 on the circuit board 10 forms a third closed pattern S3.
  • the outer boundary of the orthographic projection of the hollow area 301 on the circuit board 10 forms a fourth closed pattern S4.
  • At least two of the second closed figure S2, the third closed figure S3 and the fourth closed figure S4 are similar figures to each other.
  • the second closed figure S2 , the third closed figure S3 and the fourth closed figure S4 are mutually similar figures.
  • the second closed figure S2, the third closed figure S3 and the fourth closed figure S4 are all circular.
  • the second closed pattern S2 and the third closed pattern S3 are similar patterns to each other, and the part where the first reflective layer 30 contacts the encapsulation part 40 is subject to any force in any direction parallel to the plane where the circuit board 10 is located.
  • the buffering effect of the buffer tape is roughly the same, and the tensile force received by the packaging part 40 is evenly distributed, thereby avoiding the risk of cracking due to excessive local pulling force on the packaging part 40 .
  • the third closed pattern S3 and the fourth closed pattern S4 are similar patterns to each other, and the sealing performance and reliability of the encapsulation part 40 covering the hollow area 301 are higher, which can improve the waterproofness and corrosion resistance of the substrate 210 .
  • both the second closed figure S2 and the third closed figure S3 are circular.
  • the ratio of the diameter of the second closed pattern S2 corresponding to the third buffer structure group 33 closest to the packaging part 40 to the diameter of the packaging part 40 is greater than 1 and less than or equal to 1.2.
  • the area of the part of the first reflective layer 30 located within the innermost buffer zone will not be too large, and the amount of expansion and contraction is small.
  • the accumulated displacement of the part where the first reflective layer 30 contacts the packaging part 40 is reduced, and the reduction Risk of cracking of encapsulation 40 .
  • the second closed figure S2 is a polygon (for example, a rectangle), and the third closed figure S3 is a circle.
  • the ratio of the diagonal line of the second closed figure S2 corresponding to the third buffer structure group 33 closest to the packaging part 40 to the diameter of the packaging part 40 is greater than 1 and less than or equal to 1.2.
  • the area of the part of the first reflective layer 30 located within the innermost buffer zone will not be too large, and the amount of expansion and contraction is small.
  • the accumulated displacement of the part where the first reflective layer 30 contacts the packaging part 40 is reduced, and the reduction Risk of cracking of encapsulation 40 .
  • the distances between the plurality of second closed figures S2 formed by the plurality of third buffer structure groups 33 are not unique.
  • both the second closed figure S2 and the third closed figure S3 are circular.
  • At least two third buffer structure groups 33 are arranged around the same packaging part 40 .
  • any two adjacent third slit 330 groups correspond to the two second closed patterns S2
  • the diameter difference which is the ratio to the diameter of the packaging part 40 , is greater than 0 and less than or equal to 0.2.
  • the distance between any two adjacent third slits 330 is relatively close, and the buffering effect is better.
  • the second closed figure S2 is a polygon (for example, a rectangle), and the third closed figure S3 is a circle.
  • At least two third buffer structure groups 33 are arranged around the same packaging part 40 .
  • any two adjacent third buffer structure groups 33 correspond to the two second closed graphics S2
  • the difference between the diagonals, and the ratio of the diameter of the packaging part 40 is greater than 0 and less than or equal to 0.2.
  • the distance between any two adjacent third slits 330 is relatively close, and the buffering effect is better.
  • the above-mentioned substrate 210 further includes a second reflective layer 60 , and the second reflective layer 60 is disposed between the first reflective layer 30 and the circuit board 10 .
  • the material of the second reflective layer 60 may include white ink and/or silicone white glue.
  • the material of the second reflective layer 60 may include resin (eg, epoxy resin, polytetrafluoroethylene resin), titanium dioxide (chemical formula TiO2), and organic solvent (eg, dipropylene glycol methyl ether).
  • the second reflective layer 60 can be directly disposed on the circuit board using a coating process, and the first reflective layer can be adhered to the surface of the second reflective layer away from the circuit board.
  • the second reflective layer 60 is provided with a plurality of openings 601 .
  • the length of the electronic component 20 The ratio to the length of the opening 601 ranges from 0.5 to 0.7.
  • an electronic component 20 is located in an opening 601, and an opening 601 is located in a hollow area 301.
  • the ratio of the length of the opening 601 to the length of the hollow area 301 ranges from 0.15 to 0.30.
  • the light emitted by the light-emitting device 21 between the hollow area 301 and the opening 601 can be reflected by the second reflective layer 60 to the display panel 100, thereby further improving the light extraction efficiency of the substrate 210 and improving the display effect.
  • Figure 13 is a schematic diagram of the location of each test point. The test results are shown in Table 1.
  • Related Art 1 and Related Art 2 both represent embodiments in which the first reflective layer is a continuous entire layer, and Embodiment 1 represents an embodiment in which the first reflective layer includes a first buffer structure group in an embodiment of the present disclosure.
  • Example 2 represents an embodiment in which the first reflective layer includes a first buffer structure group, a second buffer structure group, and a third buffer structure group in an embodiment of the present disclosure.
  • MAX represents the maximum value of warpage among the 8 test points.

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Abstract

一种基板，包括线路板和第一反射层。第一反射层设置于线路板上。第一反射层包括中心区和环绕中心区的边缘区，第一反射层包括至少一个第一缓冲结构组，第一缓冲结构组在线路板上的正投影落入边缘区。每个第一缓冲结构组包括多个相互间隔设置的第一狭缝，且任一第一缓冲结构组中的多个第一狭缝围绕中心区设置。

Description

基板、背光模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种基板、背光模组及显示装置。
背景技术
随着发光二极管技术的发展，采用亚毫米量级甚至微米量级的发光二极管(英文：Light-Emitting Diode，简称：LED)作为背光源的技术得到了广泛的应用。由此，不仅可以使应用该背光源的例如液晶显示器(英文：Liquid Crystal Display，简称：LCD)等产品的画面对比度达到有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示产品的水平，还可以使产品保留液晶显示的技术优势，进而提升画面的显示效果，为用户提供更优质的视觉体验。
公开内容
一方面，提供一种基板。所述基板包括线路板和第一反射层。所述第一反射层设置于所述线路板上。所述第一反射层包括中心区和环绕所述中心区的边缘区。所述第一反射层包括至少一个第一缓冲结构组，所述第一缓冲结构组在所述线路板上的正投影落入所述边缘区。每个第一缓冲结构组包括多个相互间隔设置的第一狭缝，且任一所述第一缓冲结构组中的多个第一狭缝围绕所述中心区设置。
在一些实施例中，所述第一反射层包括多个第一缓冲结构组，任意相邻的两个第一缓冲结构组之间具有间隔，且多个第一缓冲结构组的中心，与所述中心区的几何中心重合。
在一些实施例中，相邻的两个第一缓冲结构组中，沿垂直于所述中心区的边界，且与所述线路板所在的平面平行的方向，相邻的两个第一缓冲结构组中的第一狭缝的交错设置。
在一些实施例中，所述第一缓冲结构组中的各个第一狭缝沿顺时针或逆时针方向顺次首尾相连，形成第一封闭图形。所述第一封闭图形具有第一周长，第一长度至少占所述第一周长的1/4，所述第一长度为所述第一缓冲结构组中的多个第一狭缝的长度总和。
在一些实施例中，所述第一反射层的边缘区还包括至少一个第二缓冲结构组，所述第二缓冲结构组在所述线路板上的正投影落入所述边缘区。每个第二缓冲结构组包括至少一个沿垂直于所述中心区的边界的方向延伸的第二狭缝，在所述第二缓冲结构组中包括多个第二狭缝时，所述多个第二狭缝沿 同一方向延伸且间隔设置。
在一些实施例中，所述第一反射层包括多个第二缓冲结构组，多个第二缓冲结构组沿所述第一反射层的中心区的周侧间隔设置，且相邻的两个第二缓冲结构组中的第二狭缝交错设置。
在一些实施例中，任一所述第二缓冲结构组与至少一个所述第一缓冲结构组相交。
在一些实施例中，包括多个功能区，每个功能区设有串联和/或并联的多个电子元件。所述第一狭缝位于相邻的两个功能区之间。在所述第一反射层设有第二狭缝的情况下，所述第二狭缝位于相邻的两个功能区之间。
在一些实施例中，所述边缘区的面积占所述第一反射层的平行于所述线路板的表面的面积的15％～25％。
在一些实施例中，所述基板还包括多个电子元件和多个封装部。所述多个电子元件设置于所述线路板上。一个封装部至少包裹一个电子元件。所述第一反射层还包括多个镂空区和至少一个第三缓冲结构组。一个电子元件位于一个镂空区内，且一个封装部至少覆盖一个镂空区。每个所述第三缓冲结构组包括多个相互间隔设置的第三狭缝，且一个所述第三缓冲结构组中的多个第三狭缝围绕一个所述封装部设置。
在一些实施例中，所述第一反射层设有多个第三缓冲孔组，至少两个第三缓冲结构组围绕同一个封装部设置，且所述至少两个第三缓冲结构组中，任意相邻的两个第三缓冲结构组之间具有间隔。
在一些实施例中，围绕同一个封装部设置的至少两个第三缓冲结构组的中心，与所述封装部的几何中心重合。
在一些实施例中，相邻的两个第三缓冲结构组中，沿垂直于所述镂空区的边界，且与所述线路板所在的平面平行的方向，相邻的两个第三缓冲结构组中的第三狭缝的交错设置。
在一些实施例中，所述第三缓冲结构组中的各个第三狭缝沿顺时针或逆时针方向顺次首尾相连，形成第二封闭图形。所述封装部在所述线路板上的正投影的外边界形成第三封闭图形。所述镂空区在所述线路板上的正投影的外边界形成第四封闭图形。所述第二封闭图形、所述第三封闭图形和所述第四封闭图形中的至少两者互为相似图形。
在一些实施例中，所述第二封闭图形和所述第三封闭图形均为圆形。最靠近所述封装部的第三缓冲结构组对应的第二封闭图形的直径，与所述封装部的直径的比值，大于1且小于或等于1.2；和/或，至少两个第三缓冲结构组 环绕同一个封装部设置。所述至少两个第三缓冲结构组中，任意相邻的两个第三缓冲结构组对应的两个第二封闭图形的直径差，与所述封装部的直径比值，大于0且小于或等于0.2。
在一些实施例中，所述第二封闭图形为多边形，所述第三封闭图形为圆形。最靠近所述封装部的第三缓冲结构组对应的第二封闭图形的对角线，与所述封装部的直径的比值，大于1且小于或等于1.2；和/或，至少两个第三缓冲结构组环绕同一个封装部设置。所述至少两个第三缓冲结构组中，任意相邻的两个第三缓冲结构组对应的两个第二封闭图形的对角线的差，与所述封装部的直径比值，大于0且小于或等于0.2。
在一些实施例中，所述第三缓冲结构组中的各个第三狭缝沿顺时针或逆时针方向顺次首尾相连，形成第二封闭图形。所述第二封闭图形具有第二周长，第二长度至少占所述第二周长的1/4，所述第二长度为所述第三缓冲结构组中的多个第三狭缝的长度总和。
在一些实施例中，所述第一狭缝的长度大致为1.9mm～2.1mm，所述第一狭缝的宽度大致为0.02mm～0.08mm。在所述第一反射层设有第二狭缝的情况下，所述第二狭缝的长度大致为1.9mm～2.1mm，所述第二狭缝的宽度大致为0.02mm～0.08mm。在所述第一反射层设有第三狭缝的情况下，所述第三狭缝的长度大致为1.9mm～2.1mm，所述第三狭缝的宽度大致为0.02mm～0.08mm。
在一些实施例中，所述第一反射层还包括多个镂空区。所述基板还包括多个电子元件和第二反射层。所述多个电子元件设置于所述线路板上，且一个电子元件位于一个镂空区内。所述第二反射层设置于所述第一反射层和所述线路板之间；所述反射层上设有多个开口，一个电子元件位于一个开口内，且一个开口位于一个镂空区内。
在一些实施例中，在垂直于所述电子元件的边界，且与所述线路板所在的平面平行的方向上，所述电子元件的长度与所述开口的长度的比值的取值范围在0.50～0.70；和/或，在垂直于所述开口的边界，且与所述线路板所在的平面平行的方向上，所述开口的长度与所述镂空区的长度的比值的取值范围在0.15～0.3。
另一方面，提供一种背光模组。所述背光模组包括上述任一实施例中所述的基板和多个光学膜片。所述基板具有相对的出光侧和非出光侧，所述多个光学膜片设置于所述基板的出光侧。
又一方面，提供一种显示装置。所述显示装置包括上述实施例所述的背光模组和显示面板，所述显示面板设置于所述背光模组中的多个光学膜片远 离基板的一侧。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示装置的剖视图；
图3为根据一些实施例的基板的等效电路图；
图4为根据一些实施例的一种第一反射层的俯视图；
图5为根据一些实施例的另一种第一反射层的俯视图；
图6为根据一些实施例的又一种第一反射层的俯视图；
图7为根据一些实施例的基板的俯视图；
图8为图7中的A-A＇处的剖视图；
图9A为图8中的A处的局部放大图；
图9B为图8中的B处的局部放大图；
图10A为根据一些实施例的一种基板的封装部处的局部放大图；
图10B为根据一些实施例的另一种基板的封装部处的局部放大图；
图11为根据一些实施例的第一反射层的局部放大图；
图12为根据一些实施例的再一种第一反射层的俯视图；
图13为各个测试点位的位置的示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary  embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差 (即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
参阅图1，本公开的一些实施例提供了一种显示装置1000，显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。
示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(英文：Personal Digital Assistant；简称：PDA)、导航仪、可穿戴设备、增强现实(英文：Augmented Reality；简称：AR)设备、虚拟现实(英文：Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，上述显示装置1000可以为液晶显示装置。
如图2所示，显示装置1000可以包括显示面板100、背光模组200和玻璃盖板300。
显示面板100包括相对设置的出光侧和非出光侧。出光侧是指显示面板100用于显示画面的一侧(图2中显示面板100的上侧)，非出光侧是指与出 光侧相对的另一侧(图2中显示面板100的下侧)。
背光模组200设置于显示面板100的非出光侧，背光模组200用于为显示面板100提供光源。
玻璃盖板300设置于显示面板100的出光侧，玻璃盖板300用于保护显示面板100。示例性地，玻璃盖板300采用的材料可以选择玻璃、石英、塑料等刚性材料，或者，可以选择聚合物树脂等柔性材料。
在一些示例中，请继续参阅图2，背光模组200可以包括基板210和多个光学膜片220。
基板210具有相对的发光侧和非发光侧，发光侧是指基板210提供光源的一侧(图2中基板210的上侧)，非发光侧是指与发光侧相对的另一侧(图2中基板210的下侧)。
多个光学膜片220设置于基板210的发光侧。
其中，基板210可以直接发射白色光线，白色光线经多个光学膜片220进行匀光处理后射向显示面板100。或者，基板210也可以发射其他颜色的光(例如蓝色的光)，然后经多个光学膜片220进行色转换和匀光处理后射向显示面板100。
示例性地，参阅图2，沿远离基板210的方向，多个光学膜片220包括依次设置的扩散板221、量子点膜222、扩散片223和复合膜224。
其中，扩散板221能够对基板210发出的光线进行模糊化处理，并对量子点膜222、扩散片223和复合膜224提供支撑作用。量子点膜222可在基板210所发出的某种颜色的光线的激发下，将该光线转化为白色光线，以提高对基板210的光能的利用率。扩散片223能够对经过扩散片223的光线进行均匀化处理。复合膜224能够提升背光模组200的出光效率，提高显示装置1000的显示亮度。
需要说明的是，复合膜224可以包括增亮膜(英文：Brightness Enhancement Film；简称：BEF)和反射式偏光增亮膜(英文：Dual Brightness Enhancement Film；简称：DBEF)，利用全反射、折射和偏振原理提高某个角度范围内的光线通量，以提高显示装置1000的亮度。
例如，基板210发射蓝色光线，且沿远离基板210的方向。量子点膜222可以包括红色量子点材料、绿色量子点材料和透明材料。基板210发射的蓝色光线穿过红色量子点材料时，被转换为红色光线；蓝色光线穿过绿色量子点材料时，被转换为绿色光线；蓝色光线可以直接穿过透明材料；然后，蓝色光线、红色光线和绿色光线以一定比例混合叠加后呈现为白光。最终，扩 散板221和扩散片223能够将白色光混匀，以改善基板210所产生的灯影，提高显示装置1000的显示画质。
可以理解的是，第一反射层30还可以设置有多个通孔(图中未示出)，通孔用于对应在基板210上设置支撑结构的区域，其中，支撑结构用于提供背光模组所需要的光学距离(Optical Distance，OD)，即支撑结构的一端与基板210抵接，另一端与多个光学膜片220中最靠近基板210的膜片的表面抵接。通孔的尺寸，与支撑结构与基板210抵接的表面的尺寸一致；通孔的排布规律，至少与支撑结构在基板210上的设置规律相同。通孔与第一缓冲结构组31、第二缓冲结构组32、第三缓冲结构组33、镂空区301中的任一者互不干涉。
在一些实施例中，参阅图3、图7和图8，该基板210包括线路板10、多个电子元件20、第一反射层30和封装部40。
在一些示例中，线路板10可以是FR4类型印刷电路板(英文：Printed Circuit Board，简称：PCB)，或者可以是易于变形的柔性PCB。例如，线路板10采用的材料可以包括诸如氮化硅、AlN和Al2O3中的一种或多种陶瓷材料，也可以包括金属或金属化合物，例如金属芯印刷电路板(英文：Metal Core PCB)或金属覆铜层压板(英文：Metal Copper Clade Laminate，简称：MCCL)。
在另一些示例中，如图7和图8所示，线路板10包括衬底101和设置于衬底101上的至少一个导电层102。
上述衬底101可以采用包括诸如玻璃衬底、石英衬底、蓝宝石衬底、陶瓷衬底等中的任一种；或者半导体衬底诸如以硅或碳化硅等为材料的单晶半导体衬底或多晶半导体衬底、硅锗等的化合物半导体衬底、绝缘体上硅衬底(英文：Silicon On Insulator，简称：SOI)等中的任一种；衬底101还可以采用包括诸如环氧树脂、三嗪、硅树脂和聚酰亚胺中的一种或多种有机树脂材料制作的膜层。
上述导电层102采用的材料包括铜、钼铌合金(MoNb)、镍、氧化铟锡中的一种或多种。
其中，参阅图3和图8，线路板10可以包括焊盘13和电路走线14，焊盘13被配置为连接电子元件20，电路走线14被配为连接不同焊盘13或传输信号。
需要说明的是，焊盘13和电路走线14例如可以位于上述导电层102。
如图3和图8所示，多个电子元件20设置于线路板10上，电子元件20可以包括发光器件21和微型芯片22。
如图3所示，发光器件21可以包括微型发光二极管(英文：Micro Light Emitting Diode，简称：Micro LED)和次毫米发光二极管(英文：Mini Light Emitting Diode，简称：Mini LED)中的一种或多种。
需要说明的是，Micro LED的尺寸(例如长度)小于50微米，例如，10微米～50微米。Mini LED的尺寸(例如长度)为50微米～150微米，例如80微米～120微米。本公开实施例可以根据实际需求选择设置不同的发光器件21。
如图3所示，微型芯片22可以包括传感芯片和驱动芯片，传感芯片例如可以是光敏传感器芯片或热敏传感器芯片等。驱动芯片用于向发光器件21提供驱动信号。例如，图3中均以微型芯片22包括驱动芯片为例进行示意。
在此基础上，参阅图3和图8，焊盘13包括第一焊盘131和第二焊盘132，一个发光器件21通过两个第一焊盘131与线路板10电连接，一个微型芯片22通过四个第二焊盘132与线路板10电连接。
如图8所示，第一反射层30设置于线路板10上，第一反射层30被配置为反射发光器件21射向线路板10的光，使得发光器件21所发射的光线更多的射向显示面板100(参见图2)，从而提高基板210的出光效率，提高显示效果。
需要说明的是，第一反射层30的材料包括聚酯材料，其反射率较高，画面效果更佳，且功耗较低。示例性地，第一反射层30的材料包括多元醇和多元酸缩聚而得的聚合物；例如，第一反射层30的材料包括聚对苯二甲酸乙二酯、聚对苯二甲酸丁二酯和聚芳酯等线型热塑性树脂中的至少一种。第一反射层朝向线路板的表面设置有黏胶层，第一反射层通过黏贴的方式贴附固定在线路板上。其中，参阅图4和图8，第一反射层30设有多个镂空区301，一个镂空区301内设置有多个焊盘13，一个电子元件20位于一个镂空区301内，即一个电子元件20穿过镂空区301与线路板10上的焊盘13电连接。
需要说明的是，镂空区301在线路板10上的正投影的轮廓的形状可以是圆形、多边形等，本公开实施例在此不做具体限定。图4中以镂空区301在线路板10上的正投影的轮廓的形状为圆形为例进行示意。
其中，镂空区301的最大尺寸小于或等于2.5mm。例如，镂空区301在线路板10上的正投影的轮廓的形状为圆形，镂空区301的孔径为1.4mm～1.6mm。
在这种情况下，镂空区301的孔径较小，可以使得发光器件21所发射的光线更多的射向显示面板100，从而提高基板210的出光效率，提高显示效果。同时，第一反射层30可以兼容电子元件20(例如发光器件21)间距较小的 显示装置，即兼容像素密度较高的显示装置1000。
在一些实施例中，参阅图4和图9A，电子元件20包括发光器件21，镂空区301包括第一镂空区3011，第一镂空区3011内设置有两个第一焊盘131，一个发光器件21与一个第一镂空区3011对应，且该发光器件21的两个引脚分别与这两个第一焊盘131电连接。
在一些实施例中，参阅图4和图9B，电子元件20包括微型芯片22，镂空区301包括第二镂空区3012，第二镂空区3012内还设置有四个第二焊盘132，一个微型芯片22与一个第二镂空区3012对应，且该微型芯片22的四个引脚分别与这四个第二焊盘132电连接。
需要说明的是，第一镂空区3011和第二镂空区3012的尺寸可以相同，也可以不同。
示例性地，镂空区301与其对应的电子元件20的尺寸正相关，且镂空区301的形状与其对应的电子元件20在线路板10上的正投影的轮廓为相似图形。
例如，第一镂空区3011的形状与发光器件21在线路板10上的正投影的轮廓为相似图形；第二镂空区3012的形状与微型芯片22在线路板10上的正投影的轮廓为相似图形。
以下以第一镂空区3011和第二镂空区3012的尺寸相同为例，对本公开的一些实施例进行示例性说明。
如图8所示，一个封装部40至少包裹一个电子元件20。
需要说明的是，封装部40的形状可以是半球形或半椭圆球形等，本公开实施例在此不做具体限定。例如，可以通过点胶机喷涂高触变胶水至电子元件20上形成的半球形的封装部40。
根据不同的电子元件20，上述封装部40的材料可以相同，也可以不同。例如，电子元件20为光学元件，封装部40选用透明材料；电子元件20为非光学元件，封装部40的材料对透光没有要求，可以选用透明材料、反光材料或吸光材料。
在一些示例中，如图9A所示，电子元件20包括发光器件21，上述封装部40包括包裹发光器件21的第一封装部41，第一封装部41的材料采用透明材料，透明材料可以包括透明硅胶。
在一些示例中，如图9B所示，电子元件20包括微型芯片22，上述封装部40包括包裹微型芯片22的第二封装部42，第二封装部42可以采用透明材料，以节省工艺；第二封装部42也可以采用反光材料，反光材料可以包括白色油墨、白色树脂和硅系白胶中的至少一者；第二封装部42还可以采用吸光 材料，吸光材料可以包括黑色油墨、黑色树脂和硅系黑胶中的至少一者。
在一些实施例中，一个封装部40至少覆盖一个镂空区301。这样的话，封装部40覆盖第一反射层30的镂空区301，可以保护镂空区301内的电子元件20，有利于提高基板210的防水性以及抗腐蚀性，并且提升基板210的出光效率。
然而，在相关技术中，在产品信赖性评价测试中，基板在85℃温度，85％湿度下存储1000H，由于第一反射层的热膨胀系数与线路板的热膨胀系数不同，导致第一反射层和线路板的膨胀收缩不同，使得第一反射层相对线路板由四周向中心收缩，封装部受到第一反射层的拉力，且线路板的边缘位移累积，导致线路板产生翘曲。
此外，当封装部所受拉力达到封装部与线路板的摩擦力、以及封装部与电子元件的阻力之和时，封装部开裂，并与基板剥离。同时，封装部又会对其包裹的电子元件产生推力，当推力大于或等于电子元件的阻力时，导致电子元件从焊盘脱落，进而产生发光器件不亮的不良风险。
为了改善上述技术问题，如图4所示，第一反射层30包括中心区M1和环绕中心区M1的边缘区M2。
需要说明的是，边缘区M2的面积占所述第一反射层的平行于所述线路板的表面的面积的15％～25％，具体地，与线路板10所在的平面平行的方向上，边缘区M2在平行于第一反射层30某个边界的方向上的尺寸占该边界的尺寸的5％～15％。
其中，第一反射层30的边缘区M2还包括至少一个第一缓冲结构组31，第一缓冲结构组31在线路板10上的正投影落入边缘区M2。
此处，如图4和图11所示，每个第一缓冲结构组31包括多个第一狭缝310，且每个第一缓冲结构组31中的多个相互间隔设置的第一狭缝310，且任一第一缓冲结构组31中的多个第一狭缝310围绕中心区M1设置。
在这种情况下，第一反射层30的中心区M1和边缘区M2均可以在第一缓冲结构组31中的多个第一狭缝310处收缩变形，使得第一反射层30的应力分散，减少第一反射层30的边缘区M2的位移累积，使得第一反射层30的边缘区M2与线路板10的相对运动的趋势减弱，从而降低第一反射层30的边缘区M2对线路板10的拉伸，降低线路板10(基板210)的翘曲度。
此外，第一反射层30的边缘区M2与线路板10的相对运动的趋势减弱，可以进一步地降低位于边缘区M2的封装部40开裂的风险，进一步地降低位于边缘区M2的封装部40与线路板10剥离的风险；同时，还可以进一步地降 低位于边缘区M2的封装部40对其包裹的电子元件20产生的推力，进而降低基板210产生发光器件21不亮的不良的风险。
上述第一狭缝310的形状可以为圆形、扇环和长方形等规则图形，也可以为不规则图形。
示例性地，第一狭缝310的形状大致为长方形或扇环。
例如，如图11所示，第一狭缝310的形状大致为长方形的情况下，长方形的长边沿中心区M1的周向延伸。
又例如，如图12所示，在第一狭缝310的形状大致为扇环的情况下，扇环的弧边沿中心区M1的周向延伸。
其中，参见图11，第一狭缝310的长度L1大致为1.9mm～2.1mm，第一狭缝310的宽度W1大致为0.02mm～0.08mm。例如，第一狭缝310的长度L1大致为1.9mm、2.0mm或2.1mm中的任一者，第一狭缝310的宽度W1大致为0.02mm、0.03mm、0.04mm、0.05mm、0.06mm、0.07mm或0.08mm中的任一者。
需要说明的是，在本文中，在第一狭缝310的形状大致为扇环的情况下，第一狭缝310的长度指的是扇环的弧边的长度。
其中，上述第一缓冲结构组31中，每个第一狭缝310的延伸长度与相邻的两个第一狭缝310之间的距离的比值并不唯一。
示例性地，参阅图12，上述第一缓冲结构组31中的各个第一狭缝310沿顺时针或逆时针方向顺次首尾相连，形成第一封闭图形S1。第一封闭图形S1具有第一周长，第一长度至少占第一周长的1/4，第一长度为第一缓冲结构组31中的多个第一狭缝310的长度总和。
这样的话，第一缓冲结构组31中的多个第一狭缝310形成的缓冲带的缓冲效果较为明显，且多个第一狭缝310之间的结构强度较大，断裂的风险较小。
在一些实施例中，如图4、图11和图12所示，第一反射层30包括多个第一缓冲结构组31，任意相邻的两个第一缓冲结构组31之间具有间隔。以这种方式设置，中心区M1的周侧可以形成多个缓冲带。可以理解的是，在一些实施例中，相邻的两个第一缓冲结构组31之间的间隔可以为一个功能区尺寸的正整数倍，例如相邻的两个第一缓冲结构组31之间间隔一个功能区的宽度设置；在一些实施例中，相邻的两个第一缓冲结构组31(例如图4中的31-1和31-2)之间的间隔的取值范围也可以在0.5mm-2.5mm之间取值，例如为0.8mm或1mm；在一些实施例中，相邻的两个第二缓冲结构组32可以以其他 规则间隔设置。
也就是说，第一反射层30的边缘区M2的应力分散更加均匀，可以进一步地减少第一反射层30的边缘区M2的位移累积，使得第一反射层30的边缘区M2与线路板10的相对运动的趋势减弱，从而降低第一反射层30的边缘区M2对线路板10的拉伸，降低线路板10(基板210)的翘曲度。
同时，在多个第一缓冲结构组31形成的多个缓冲带的缓冲作用下，可以进一步地位于边缘区M2的封装部40开裂的风险，以及，进一步地降低基板210位于边缘区M2的发光器件21产生不亮的不良的风险。
此外，多个第一缓冲结构组31的中心，与中心区M1的几何中心重合，使得多个第一缓冲结构组31形成的多个缓冲带之间的间距大致相等，从而使得第一反射层30的边缘区M2，位于该缓冲带之间的部分受到的拉力分散均匀，避免第一反射层30的边缘区M2，位于缓冲带之间的部分的局部受到的拉力过大产生开裂的风险。
在此基础上，如图11和图12所示，相邻的两个第一缓冲结构组31中，沿垂直于中心区M1的边界，且与线路板10(参见图8)所在的平面平行的方向，相邻的两个第一缓冲结构组31中的第一狭缝310的交错设置。
这样的话，第一缓冲结构组31在边缘区M2形成的多个缓冲带，其缓冲区域可以围成一个完整的封闭图形，从而使得第一反射层30的边缘区M2，在线路板10所在的平面平行的任一方向上，均可以受到缓冲带的缓冲作用，避免第一反射层30的边缘区M2的局部区域无缓冲带的缓冲作用，而导致第一反射层30的边缘区M2的局部区域受到的拉力过大，而导致封装部40开裂的风险，有利于提高基板210的防水性以及抗腐蚀性。
在一些实施例中，如图5所示，第一反射层30的边缘区M2还包括至少一个第二缓冲结构组32，第二缓冲结构组32在线路板10(参见图8)上的正投影落入边缘区M2。
此处，如图5、图11和图12所示，每个第二缓冲结构组32包括多个相互间隔设置的第二狭缝320，任一第二缓冲结构组32中的多个第二狭缝320沿垂直于中心区M1的边界的方向间隔设置。每个第二缓冲结构组32包括至少一个沿垂直于中心区M1的边界的方向延伸的第二狭缝320。也即，参见图12，第二狭缝320的延伸方向与第一缓冲结构组31的形成第一封闭图形S1的边大致垂直。
在第二缓冲结构组32中包括多个第二狭缝320时，多个第二狭缝320沿同一方向延伸且间隔设置。如图5所示，例如在第一反射层30的边角位置处 的第二缓冲结构组32，其可以仅包括一个第二狭缝320，而在非边角处位置处的第二缓冲结构组32，可以包括多个沿同一方向延伸且沿该方向间隔设置的第二狭缝320。
在这种情况下，第一反射层30的边缘区M2可以在第二缓冲结构组32中的多个第二狭缝320处收缩变形，使得第一反射层30的应力更加分散，进一步地降低第一反射层30的边缘区M2对线路板10的拉伸，降低线路板10(基板210)的翘曲度，以及进一步地位于边缘区M2的封装部40开裂的风险，以及，进一步地降低基板210位于边缘区M2的发光器件21产生不亮的不良的风险。
上述第二狭缝320的形状可以为圆形和长方形等规则图形，也可以为不规则图形。
示例性地，如图11和图12所示，第二狭缝320的形状大致为长方形，长方形的长边沿垂直于中心区M1的边界的方向延伸。
其中，参见图11，第二狭缝320的长度L2大致为1.9mm～2.1mm，第二狭缝320的宽度W2大致为0.02mm～0.08mm。例如，第二狭缝320的长度L2大致为1.9mm、2.0mm或2.1mm中的任一者，第二狭缝320的宽度W2大致为0.02mm、0.03mm、0.04mm、0.05mm、0.06mm、0.07mm或0.08mm中的任一者。
其中，上述第二缓冲结构组32中，每个第二狭缝320的延伸长度与相邻的两个第二狭缝320之间的距离的比值并不唯一。
示例性地，参阅图11和图12，第二缓冲结构组32中，第二狭缝320长度与相邻的两个第二狭缝320之间的长度的取值范围为1～3。
这样的话，第二缓冲结构组32中的多个第二狭缝320形成的缓冲带的缓冲效果较为明显，且多个第二狭缝320之间的结构强度较大，断裂的风险较小。
在一些实施例中，如图5和图11所示，第一反射层30包括多个第二缓冲结构组32，多个第二缓冲结构组32沿第一反射层30的中心区M1的周侧间隔设置，且相邻的两个第二缓冲结构组32中的第二狭缝320交错设置。如图6所示，第一反射层30包括多个第二缓冲结构组32，任意相邻的两个第一缓冲结构组31之间具有间隔。可以理解的是，在一些实施例中，相邻的两个第二缓冲结构组32之间的间隔可以为一个功能区尺寸的正整数倍，例如相邻的两个第二缓冲结构组32之间间隔一个功能区的宽度设置；在一些实施例中，相邻的两个第二缓冲结构组32之间的间隔的取值范围也可以在0.8mm-2.5mm 之间取值，例如为1mm；在一些实施例中，相邻的两个第二缓冲结构组32可以以其他规则间隔设置。可以理解的是，相邻的两个第二缓冲结构组32，指的是，这两个第二缓冲结构组32中的第二狭缝320均沿同一方向(例如第一方向)间隔排布，且该两个第二缓冲结构组32沿非第一方向(例如与第一方向垂直的第二方向)相邻设置。
这样的话，多个第二缓冲结构组32形成的缓冲区域相互交错，缓冲效果较好。在一些实施例中，如图6和图11所示，任一第二缓冲结构组32与至少一个第一缓冲结构组31相交。这样的话，第二缓冲结构组32的多个第二狭缝320与第一缓冲结构组31的多个第一狭缝310形成网格结构，从而使得第一反射层30的边缘区M2受到的拉力分散更加均匀。
在一些实施例中，如图3和图8所示，基板210包括多个功能区50，每个功能区50包括串联和/或并联的多个电子元件20。
示例性地，每个功能区50包括串联和/或并联的多个发光器件21和至少一个微型芯片22。
例如，如图3、图7和图8所示，每个功能区50包括4个依次串联的发光器件21和一个微型芯片22。当然，每个功能区50还可以包括5个、6个、7个或8个发光器件21，并且功能区50中多个发光器件21的连接方式并不仅限于串联，还可以是并联，本公开实施例不限于此。
在此基础上，如图3、图7和图8所示，上述第一狭缝310和/或第二狭缝320，可以位于相邻的两个功能区50之间。以这种方式设置，第一反射层30在各个功能区50的变形收缩大致相同，使得各个功能区50的发光中心分布大致相同，提高显示装置1000(参见图1)的亮度分布的均匀性，提高显示效果。可以理解的是，部分第一狭缝310和/或第二狭缝320，也可以位于某个功能区50所在区域。
其中，在第二缓冲结构组32与至少一个第一缓冲结构组31相交，形成网格结构的情况下，至少部分网格结构可以与一个功能区50相对应，即网格结构设置在相邻的功能区50之间；在一些实施例中，网格结构与功能区50不对应，即网格结构可以穿过功能区50所在区域，可以理解的是，网格结构与设置在功能区50中的电子元件20互不干涉。
在一些实施例中，参阅图7、图8和图10A，第一反射层30上还设有至少一个第三缓冲结构组33。
其中，每个第三缓冲结构组33包括多个相互间隔设置的第三狭缝330，且一个第三缓冲结构组33中的多个第三狭缝330围绕一个封装部40设置。
在这种情况下，第一反射层30可以在第三缓冲结构组33中的多个第三狭缝330处收缩变形，即第一反射层30与封装部40接触的部分，在第三缓冲结构组33中的多个第三狭缝330形成的缓冲带的缓冲作用下，第一反射层30与封装部40接触的部分，与线路板10的相对运动的趋势减弱。也就是说，第一反射层30对封装部40的拉力减小，可以降低封装部40开裂的风险，进而降低封装部40与线路板10剥离的风险；同时，第一反射层30对封装部40的拉力减小，还可以降低封装部40对其包裹的电子元件20产生的推力，进而降低基板210产生发光器件21不亮的不良的风险。
此外，在第三缓冲结构组33中的多个第三狭缝330形成的缓冲带的缓冲作用下，第一反射层30与线路板10的相对运动的趋势减弱，可以降低第一反射层30对线路板10的拉伸，降低线路板10(基板210)的翘曲度。
上述第三狭缝330的形状可以为圆形、扇环和长方形等规则图形，也可以为不规则图形。
示例性地，第三狭缝330的形状大致为长方形或扇环。
需要说明的是，在本文中，“大致为长方形或扇环”是指，形状整体上呈长方形或扇环，但是并不局限为标准的长方形或扇环。即，这里的“长方形或扇环”不但包括基本长方形或扇环的形状，而且考虑到工艺条件，还包括类似于长方形或扇环的形状。例如，长方形的拐角处或短边为弯曲状；又例如，扇环的拐角处或短边为弯曲状。
例如，如图10B所示，第三狭缝330的形状大致为长方形，长方形的长边沿封装部40的周向延伸。
又例如，如图10A所示，第三狭缝330的形状大致为扇环，扇环的弧边沿封装部40的周向延伸。
其中，参见图10B，第三狭缝330的长度L3大致为1.9mm～2.1mm，第三狭缝330的宽度W3大致为0.02mm～0.08mm。例如，第三狭缝330的长度L3大致为1.9mm、2.0mm或2.1mm中的任一者，第三狭缝330的宽度W3大致为0.02mm、0.03mm、0.04mm、0.05mm、0.06mm、0.07mm或0.08mm中的任一者。
需要说明的是，在本文中，在第三狭缝330的形状大致为扇环的情况下，第三狭缝330的长度指的是扇环的弧边的长度。
其中，上述第三缓冲结构组33中，每个第三狭缝330的延伸长度与相邻的两个第三狭缝330之间的距离的比值并不唯一。
示例性地，参阅图10A和图10B，上述第三缓冲结构组33中的各个第三 狭缝330沿顺时针或逆时针方向顺次首尾相连，形成第二封闭图形S2。第二封闭图形S2具有第二周长，第二长度至少占第二周长的1/4。其中，第二长度为第三缓冲结构组33中的多个第三狭缝330的长度总和。
这样的话，第三缓冲结构组33中的多个第三狭缝330形成的缓冲带的缓冲效果较为明显，且多个第三狭缝330之间的结构强度较大，断裂的风险较小。
在一些实施例中，如图7、图10A和图10B所示，第一反射层30设有多个第三缓冲结构组33，且至少两个第三缓冲结构组33围绕同一个封装部40设置，且至少两个第三缓冲结构组33中，任意相邻的两个第三缓冲结构组33之间具有间隔。以这种方式设置，每个封装部40的周侧形成多个缓冲带。可以理解的是，围绕同一个封装部40的相邻的两个第三缓冲结构组33之间的间隔的取值范围在0.5mm～1.5mm，例如为1mm。
也就是说，第一反射层30与封装部40接触的部分，可以在多个缓冲带的缓冲作用下，进一步地减弱其与线路板10的相对运动的趋势，减小第一反射层30对封装部40的拉力，从而进一步地降低封装部40开裂并与线路板10剥离的风险，以及，进一步地降低基板210产生发光器件21不亮的不良的风险。
此外，围绕同一个封装部40设置的至少两个第三缓冲结构组33的中心，与封装部40的几何中心重合，使得多个缓冲带之间的间距大致相等，从而使得第一反射层30位于缓冲带之间的部分，受到的拉力分散均匀，避免第一反射层30位于缓冲带之间的部分的局部受到的拉力过大产生开裂的风险。
在此基础上，如图10A和图10B所示，相邻的两个第三缓冲结构组33中，沿垂直于镂空区301的边界，且与线路板10所在的平面平行的方向，相邻的两个第三缓冲结构组33中的第三狭缝330的交错设置。
需要说明的是，“线路板10所在的平面”是指线路板10具有最大平面面积的表面。
这样的话，每个封装部40的周侧形成多个缓冲带，其缓冲区域可以围成一个完整的封闭图形，从而使得第一反射层30与封装部40接触的部分，在线路板10所在的平面平行的任一方向上，均可以受到缓冲带的缓冲作用，避免第一反射层30与封装部40接触的部分的局部区域无缓冲带的缓冲作用，而导致封装部40局部受到的拉力过大产生开裂的风险，有利于提高基板210的防水性以及抗腐蚀性。
在一些实施例中，参阅图10A和图10B，第三缓冲结构组33中的各个第 三狭缝330沿顺时针或逆时针方向顺次首尾相连，形成第二封闭图形S2。封装部40在线路板10上的正投影的外边界形成第三封闭图形S3。镂空区301在线路板10上的正投影的外边界形成第四封闭图形S4。
其中，第二封闭图形S2、第三封闭图形S3和第四封闭图形S4中的至少两者互为相似图形。
示例性地，如图10A所示，第二封闭图形S2、第三封闭图形S3和第四封闭图形S4两两互为相似图形。例如，第二封闭图形S2、第三封闭图形S3和第四封闭图形S4均为圆形。
在这种情况下，第二封闭图形S2和第三封闭图形S3互为相似图形，第一反射层30与封装部40接触的部分，在线路板10所在的平面平行的任一方向上，受到的缓冲带的缓冲效果大致相同，封装部40受到的拉力分散均匀，避免封装部40局部受到的拉力过大产生开好吧裂的风险。此外，第三封闭图形S3和第四封闭图形S4互为相似图形，封装部40覆盖镂空区301的密封性和可靠性更高，可以提高基板210的防水性以及抗腐蚀性。
应理解，第二封闭图形S2的尺寸与第三封闭图形S3的尺寸的比值并不唯一。
在一些示例中，如图10A所示，第二封闭图形S2和第三封闭图形S3均为圆形。最靠近封装部40的第三缓冲结构组33对应的第二封闭图形S2的直径，与封装部40的直径的比值，大于1且小于或等于1.2。
这样的话，第一反射层30位于最内侧的缓冲带以内的部分的面积不会过大，膨胀收缩量较小，第一反射层30与封装部40接触的部分的位移累积量减小，降低封装部40开裂的风险。
在另一些示例中，如图10B所示，第二封闭图形S2为多边形(例如矩形)，第三封闭图形S3为圆形。最靠近封装部40的第三缓冲结构组33对应的第二封闭图形S2的对角线，与封装部40的直径的比值，大于1且小于或等于1.2。
这样的话，第一反射层30位于最内侧的缓冲带以内的部分的面积不会过大，膨胀收缩量较小，第一反射层30与封装部40接触的部分的位移累积量减小，降低封装部40开裂的风险。
此外，多个第三缓冲结构组33形成的多个第二封闭图形S2之间的距离也并不唯一。
在一些示例中，如图10A所示，第二封闭图形S2和第三封闭图形S3均为圆形。至少两个第三缓冲结构组33环绕同一个封装部40设置，至少两个第三缓冲结构组33中，任意相邻的两个第三狭缝330组对应的两个第二封闭 图形S2的直径差，与封装部40的直径比值，大于0且小于或等于0.2。
这样的话，任意相邻的两个第三狭缝330的距离较近，缓冲效果较好。
在另一些示例中，如图10B所示，第二封闭图形S2为多边形(例如矩形)，第三封闭图形S3为圆形。至少两个第三缓冲结构组33环绕同一个封装部40设置，至少两个第三缓冲结构组33中，任意相邻的两个第三缓冲结构组33对应的两个第二封闭图形S2的对角线的差，与封装部40的直径比值，大于0且小于或等于0.2。
这样的话，任意相邻的两个第三狭缝330的距离较近，缓冲效果较好。
在一些实施例中，参阅图7和图8，上述基板210还包括第二反射层60，第二反射层60设置于第一反射层30和线路板10之间。
需要说明的是，第二反射层60的材料可以包括白色油墨和/或硅系白胶。例如，第二反射层60的材料可以包括树脂(例如，环氧树脂、聚四氟乙烯树脂)、二氧化钛(化学式TiO2)以及有机溶剂(例如，二丙二醇甲醚)等。
应理解，第二反射层60采用涂覆工艺可以直接设置在线路板上，第一反射层可以黏附在第二反射层远离线路板的表面。
基于此，参阅图9A和图9B，第二反射层60上设有多个开口601，在垂直于电子元件20的边界，且与线路板10所在的平面平行的方向上，电子元件20的长度与开口601的长度的比值的取值范围在0.5～0.7。
其中，一个电子元件20位于一个开口601内，且一个开口601位于一个镂空区301内。示例性地，在垂直于开口601的边界，且与线路板10所在的平面平行的方向上，开口601的长度与镂空区301的长度的比值的取值范围在0.15～0.30。
在这种情况下，发光器件21射向镂空区301与开口601之间的光线，可以由第二反射层60反射至显示面板100，从而进一步地提高基板210的出光效率，提高显示效果。
为了对本公开的实施例的技术效果进行客观评价，以下，将上述实施例提供的基板进行翘曲度测试，图13为各个测试点位的位置的示意图，测试结果见表1。
表1基板的翘曲度测试表
Figure PCTCN2022115302-appb-000001
Figure PCTCN2022115302-appb-000002
其中，相关技术1和相关技术2均代表第一反射层为连续的整层的实施例，实施例1代表本公开的实施例中的第一反射层包括第一缓冲结构组的实施例，实施例2代表本公开的实施例中的第一反射层包括第一缓冲结构组、第二缓冲结构组和第三缓冲结构组的实施例。MAX代表的是8个测试点位中的翘曲度的最大值。
由表1可知，本公开的实施例的基板的翘曲度的最大值，远小于相关技术中的基板的翘曲度的最大值，基板的翘曲度降低。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种基板，包括：
    线路板；
    第一反射层，设置于所述线路板上；所述第一反射层包括中心区和环绕所述中心区的边缘区，所述第一反射层包括至少一个第一缓冲结构组，所述第一缓冲结构组在所述线路板上的正投影落入所述边缘区；
    每个第一缓冲结构组包括多个相互间隔设置的第一狭缝，且任一所述第一缓冲结构组中的多个第一狭缝围绕所述中心区设置。
  2. 根据权利要求1所述的基板，其中，所述第一反射层包括多个第一缓冲结构组，任意相邻的两个第一缓冲结构组之间具有间隔，且多个第一缓冲结构组的中心，与所述中心区的几何中心重合。
  3. 根据权利要求2所述的基板，其中，相邻的两个第一缓冲结构组中，沿垂直于所述中心区的边界，且与所述线路板所在的平面平行的方向，相邻的两个第一缓冲结构组中的第一狭缝的交错设置。
  4. 根据权利要求1～3中任一项所述的基板，其中，所述第一缓冲结构组中的各个第一狭缝沿顺时针或逆时针方向顺次首尾相连，形成第一封闭图形；
    所述第一封闭图形具有第一周长，第一长度至少占所述第一周长的1/4，所述第一长度为所述第一缓冲结构组中的多个第一狭缝的长度总和。
  5. 根据权利要求1～4中任一项所述的基板，其中，所述第一反射层的边缘区还包括至少一个第二缓冲结构组，所述第二缓冲结构组在所述线路板上的正投影落入所述边缘区；
    每个第二缓冲结构组包括至少一个沿垂直于所述中心区的边界的方向延伸的第二狭缝，在所述第二缓冲结构组中包括多个第二狭缝时，所述多个第二狭缝沿同一方向延伸且间隔设置。
  6. 根据权利要求5所述的基板，其中，所述第一反射层包括多个第二缓冲结构组，多个第二缓冲结构组沿所述第一反射层的中心区的周侧间隔设置，且相邻的两个第二缓冲结构组中的第二狭缝交错设置。
  7. 根据权利要求5或6所述的基板，其中，任一所述第二缓冲结构组与至少一个所述第一缓冲结构组相交。
  8. 根据权利要求1～7中任一项所述的基板，包括多个功能区，每个功能区设有串联和/或并联的多个电子元件；
    所述第一狭缝位于相邻的两个功能区之间；
    在所述第一反射层设有第二狭缝的情况下，所述第二狭缝位于相邻的两个功能区之间。
  9. 根据权利要求1～8中任一项所述的基板，其中，所述边缘区的面积占所述第一反射层的平行于所述线路板的表面面积的15％～25％。
  10. 根据权利要求1～9中任一项所述的基板，还包括：
    多个电子元件，设置于所述线路板上；
    多个封装部，一个封装部至少包裹一个电子元件；
    所述第一反射层还包括多个镂空区和至少一个第三缓冲结构组；一个电子元件位于一个镂空区内，且一个封装部至少覆盖一个镂空区；每个所述第三缓冲结构组包括多个相互间隔设置的第三狭缝，且一个所述第三缓冲结构组中的多个第三狭缝围绕一个所述封装部设置。
  11. 根据权利要求10所述的基板，其中，所述第一反射层设有多个第三缓冲孔组，至少两个第三缓冲结构组围绕同一个封装部设置，且所述至少两个第三缓冲结构组中，任意相邻的两个第三缓冲结构组之间具有间隔。
  12. 根据权利要求11所述的基板，其中，围绕同一个封装部设置的至少两个第三缓冲结构组的中心，与所述封装部的几何中心重合。
  13. 根据权利要求11或12所述的基板，其中，相邻的两个第三缓冲结构组中，沿垂直于所述镂空区的边界，且与所述线路板所在的平面平行的方向，相邻的两个第三缓冲结构组中的第三狭缝的交错设置。
  14. 根据权利要求10～13中任一项所述的基板，其中，所述第三缓冲结构组中的各个第三狭缝沿顺时针或逆时针方向顺次首尾相连，形成第二封闭图形；所述封装部在所述线路板上的正投影的外边界形成第三封闭图形；所述镂空区在所述线路板上的正投影的外边界形成第四封闭图形；
    所述第二封闭图形、所述第三封闭图形和所述第四封闭图形中的至少两者互为相似图形。
  15. 根据权利要求14所述的基板，其中，所述第二封闭图形和所述第三封闭图形均为圆形；
    最靠近所述封装部的第三缓冲结构组对应的第二封闭图形的直径，与所述封装部的直径的比值，大于1且小于或等于1.2；
    和/或，至少两个第三缓冲结构组环绕同一个封装部设置，所述至少两个第三缓冲结构组中，任意相邻的两个第三缓冲结构组对应的两个第二封闭图形的直径差，与所述封装部的直径比值，大于0且小于或等于0.2。
  16. 根据权利要求15所述的基板，其中，所述第二封闭图形为多边形，所述第三封闭图形为圆形；
    最靠近所述封装部的第三缓冲结构组对应的第二封闭图形的对角线，与 所述封装部的直径的比值，大于1且小于或等于1.2；
    和/或，至少两个第三缓冲结构组环绕同一个封装部设置，所述至少两个第三缓冲结构组中，任意相邻的两个第三缓冲结构组对应的两个第二封闭图形的对角线的差，与所述封装部的直径比值，大于0且小于或等于0.2。
  17. 根据权利要求10～16中任一项所述的基板，其中，所述第三缓冲结构组中的各个第三狭缝沿顺时针或逆时针方向顺次首尾相连，形成第二封闭图形；
    所述第二封闭图形具有第二周长，第二长度至少占所述第二周长的1/4，所述第二长度为所述第三缓冲结构组中的多个第三狭缝的长度总和。
  18. 根据权利要求1～17中任一项所述的基板，其中，所述第一狭缝的长度大致为1.9mm～2.1mm，所述第一狭缝的宽度大致为0.02mm～0.08mm；
    在所述第一反射层设有第二狭缝的情况下，所述第二狭缝的长度大致为1.9mm～2.1mm，所述第二狭缝的宽度大致为0.02mm～0.08mm；
    在所述第一反射层设有第三狭缝的情况下，所述第三狭缝的长度大致为1.9mm～2.1mm，所述第三狭缝的宽度大致为0.02mm～0.08mm。
  19. 根据权利要求1～18中任一项所述的基板，其中，所述第一反射层还包括多个镂空区，所述基板还包括：
    多个电子元件，设置于所述线路板上，且一个电子元件位于一个镂空区内；
    第二反射层，设置于所述第一反射层和所述线路板之间；所述第二反射层上设有多个开口，一个电子元件位于一个开口内，且一个开口位于一个镂空区内。
  20. 根据权利要求19所述的基板，其中，在垂直于所述电子元件的边界，且与所述线路板所在的平面平行的方向上，所述电子元件的长度与所述开口的长度的比值的取值范围在0.5～0.7；
    和/或，在垂直于所述开口的边界，且与所述线路板所在的平面平行的方向上，所述开口的长度与所述镂空区的长度的比值的取值范围在0.15～0.3。
  21. 一种背光模组，包括：
    如权利要求1～20中任一项所述的基板，所述基板具有相对的出光侧和非出光侧；
    多个光学膜片，设置于所述基板的出光侧。
  22. 一种显示装置，包括：
    如权利要求21所述的背光模组；
    显示面板，设置于所述背光模组中的多个光学膜片远离基板的一侧。
PCT/CN2022/115302 2022-08-26 2022-08-26 基板、背光模组及显示装置 WO2024040614A1 (zh)

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CN102667315A (zh) * 2009-12-28 2012-09-12 夏普株式会社 照明装置、显示装置以及电视接收装置
JP2013118117A (ja) * 2011-12-05 2013-06-13 Sharp Corp 照明装置、表示装置、及びテレビ受信装置
CN209373304U (zh) * 2019-02-28 2019-09-10 青岛海信电器股份有限公司 一种直下式曲面背光模组及曲面液晶显示设备
CN110908178A (zh) * 2018-09-17 2020-03-24 夏普株式会社 照明装置以及显示装置
CN211123565U (zh) * 2019-08-26 2020-07-28 京东方科技集团股份有限公司 背光模组及显示装置
CN113270437A (zh) * 2020-02-17 2021-08-17 京东方科技集团股份有限公司 背板及其制备方法、显示装置
CN216817700U (zh) * 2021-12-31 2022-06-24 佛山市国星光电股份有限公司 灯板、背光模组及背光装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102667315A (zh) * 2009-12-28 2012-09-12 夏普株式会社 照明装置、显示装置以及电视接收装置
JP2013118117A (ja) * 2011-12-05 2013-06-13 Sharp Corp 照明装置、表示装置、及びテレビ受信装置
CN110908178A (zh) * 2018-09-17 2020-03-24 夏普株式会社 照明装置以及显示装置
CN209373304U (zh) * 2019-02-28 2019-09-10 青岛海信电器股份有限公司 一种直下式曲面背光模组及曲面液晶显示设备
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CN113270437A (zh) * 2020-02-17 2021-08-17 京东方科技集团股份有限公司 背板及其制备方法、显示装置
CN216817700U (zh) * 2021-12-31 2022-06-24 佛山市国星光电股份有限公司 灯板、背光模组及背光装置

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