WO2024036765A1 - 半导体结构和半导体结构的制造方法 - Google Patents

半导体结构和半导体结构的制造方法 Download PDF

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Publication number
WO2024036765A1
WO2024036765A1 PCT/CN2022/130069 CN2022130069W WO2024036765A1 WO 2024036765 A1 WO2024036765 A1 WO 2024036765A1 CN 2022130069 W CN2022130069 W CN 2022130069W WO 2024036765 A1 WO2024036765 A1 WO 2024036765A1
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Prior art keywords
heat dissipation
chip module
chip
dissipation plate
semiconductor structure
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PCT/CN2022/130069
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English (en)
French (fr)
Inventor
吕开敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/451,095 priority Critical patent/US20240063187A1/en
Publication of WO2024036765A1 publication Critical patent/WO2024036765A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass

Definitions

  • Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • HBM High Bandwidth Memory
  • Chip stacking technology represented by HBM extends the original one-dimensional memory layout to three dimensions, that is, stacking many chips together and packaging them, thus greatly increasing the density of the chip and achieving large capacity and high bandwidth.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least conducive to improving the degree of heat dissipation of the chip, thereby improving the performance of the semiconductor structure.
  • the embodiments of the present disclosure provide a semiconductor structure, wherein the semiconductor structure includes: a load-bearing structure; a stack structure located on the load-bearing structure; the stack structure includes a stacked heat dissipation plate and a chip Module, the chip module includes at least one chip; the orthographic projection area of the heat dissipation plate on the bearing structure is greater than the orthographic projection area of the chip module on the bearing structure.
  • the embodiments of the present disclosure also provide a manufacturing method of a semiconductor structure.
  • the manufacturing method includes: providing a carrier structure and a stacked structure; disposing the stacked structure on the carrier structure;
  • the stacked structure includes a stacked heat dissipation plate and a chip module.
  • the chip module includes at least one chip; the area of the orthographic projection of the heat dissipation plate on the bearing structure is larger than the orthographic projection of the chip module on the bearing structure. area.
  • the area of the orthographic projection of the heat sink plate on the bearing structure is larger than the area of the orthographic projection of the chip module on the bearing structure. That is, the heat dissipation plate extends outward relative to the chip module, so that the heat dissipation plate can guide the heat generated by the chip module, and the heat is transferred to the periphery of the packaging structure along the heat dissipation plate, thereby improving the heat dissipation effect.
  • Figure 1 shows a schematic diagram of a semiconductor structure
  • Figure 2 shows a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 shows a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 shows a schematic diagram of yet another semiconductor structure provided by an embodiment of the present disclosure
  • FIGS 5-7 and 9-11 respectively show different top views of the heat sink and chip module provided by an embodiment of the present disclosure
  • Figure 8 shows a schematic diagram of yet another semiconductor structure provided by an embodiment of the present disclosure.
  • FIGS 12-14 respectively show schematic diagrams of different chip modules provided by another embodiment of the present disclosure.
  • FIG. 15 shows a schematic diagram of a heat dissipation plate provided by another embodiment of the present disclosure.
  • the chips 200 are bonded to each other through die attach film (DAF) or mold underfill (Mold underfill).
  • DAF die attach film
  • Mold underfill Mold underfill
  • Embodiments of the present disclosure provide a semiconductor structure, wherein the stacked structure includes a heat dissipation plate and a chip module, and the area of the orthographic projection of the heat dissipation plate on the bearing structure is greater than the area of the orthographic projection of the chip module on the bearing structure. That is, the heat dissipation plate extends outward relative to the chip module, and the heat generated by the chip module can be dissipated to the periphery of the packaging structure through the heat dissipation plate.
  • the heat sink can guide the direction of heat dissipation, thereby speeding up the heat dissipation of the chip.
  • an embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes: a carrying structure 1; a stacking structure 4 located on the carrying structure 1; the stacking structure 4 includes a stacked heat dissipation plate 3 and a chip Module 2, the chip module 2 includes at least one chip 21; the area of the orthographic projection of the heat sink 3 on the bearing structure 1 is greater than the area of the orthographic projection of the chip module 2 on the bearing structure 1.
  • the heat dissipation plate 3 extends outward relative to the chip module 2 in a direction parallel to the upper surface of the carrying structure 1 . Since heat spontaneously transfers from a high temperature place to a low temperature place, and the temperature of the chip module 2 is greater than the temperature of the periphery of the chip module 2, the heat sink 3 can quickly transfer the heat generated by the chip module 2 outward, thereby improving the heat dissipation of the chip module 2. degree, thereby avoiding the impact of high heat on the performance of the semiconductor structure.
  • the load-bearing structure 1 may be a substrate.
  • the substrate mainly plays the role of protecting the chip 21 and electrically connecting the chip 21 with the peripheral circuit board.
  • the substrate should be made of materials with good heat dissipation properties, such as organic substrates or ceramic substrates.
  • the chip 21 can be a memory chip, such as a dynamic random access memory (DRAM, Dynamic Random Access Memory).
  • DRAM Dynamic Random Access Memory
  • the chip 21 can also be a logic chip, and the memory chip communicates with the logic chip.
  • the chip 21 close to the carrying structure 1 may be a logic chip, and the chip 21 far away from the carrying structure 1 may be a memory chip.
  • the carrier structure 1 may be a logic chip.
  • the heat dissipation plate 3 may be a heat dissipation chip, such as a microfluidic heat dissipation chip.
  • a microfluidic heat dissipation chip There are microfluidic channels in the microfluidic heat dissipation chip.
  • the cooling liquid can enter the microfluidic channel to absorb heat, and then be discharged from the microfluidic channel to take away the heat.
  • the heat dissipation rate is controlled by controlling the flow speed of the cooling liquid in the microfluidic holes.
  • a two-phase cooling liquid can be selected, that is, the cooling liquid can undergo a phase change due to temperature changes, thereby taking away more heat.
  • the heat dissipation plate 3 can also be made of other highly thermally conductive materials, such as copper, graphene, aluminum nitride and other materials.
  • the heat dissipation plate 3 can also have a rough surface to increase the heat dissipation area, thereby improving the heat dissipation effect.
  • the surface of the heat dissipation plate 3 may include a nano-rough structure or a micro-rough structure.
  • the flatness of the surface of the heat dissipation plate 3 may be different; for example, the flatness of the surface of the heat dissipation plate 3 opposite to the chip module 2 may be greater than the flatness of the outwardly extending surface of the heat dissipation plate 3; for example, That is, the outwardly extending portion of the heat dissipation plate 3 may be provided with protrusions or depressions. In this way, the heat dissipation area can be increased around the periphery of the chip module 2, and the heat dissipation plate 3 and the chip module 2 can be easily welded, thereby improving the firmness of the welding.
  • each chip module 2 is disposed adjacent to at least one heat dissipation plate 3 , and some chip modules 2 can also be disposed adjacent to two heat dissipation plates 3 .
  • the alternating arrangement is also conducive to increasing the distance between adjacent chip modules 2, thereby providing more sufficient heat dissipation space for adjacent chip modules 2 to avoid heat accumulation.
  • At least one of the plurality of chip modules 2 includes a plurality of stacked chips 21 .
  • the thickness of the chip 21 is small, and multiple chips 21 can be stacked in a hybrid bonding manner. That is, the surface of the chip 21 has a bonding portion 23 and a dielectric layer (not shown in the figure).
  • the upper surface of the bonding portion 23 can be flush with the upper surface of the dielectric layer, or the upper surface of the bonding portion 23 can be relative to the dielectric layer.
  • the upper surface has a slight depression. Under heating conditions, the bonding portions 23 of two adjacent chips 21 will expand slightly and bond together to form an electrical connection; the dielectric layers of two adjacent chips 21 can be connected together through intermolecular forces.
  • bump welding technology may also be used to connect multiple chips 21 together. That is, the bumps allow the surfaces of adjacent chips 21 to be spaced apart, thereby providing more heat dissipation space for the adjacent chips 21 .
  • the thickness of one chip 21 is small, but the total thickness after stacking multiple chips 21 increases, which makes it easier to weld the heat sink 3 and the chip module 2 together.
  • the chip module 2 formed by stacking multiple chips 21 is alternately arranged with a heat sink 3 , which is beneficial to improving the utilization rate of the heat sink 3 and reducing the number of heat sinks 3 , which is beneficial to reducing the volume of the semiconductor structure.
  • the number of chips 21 within the chip module 2 is less than four. It should be noted that if there are too many chips 21 in the chip module 2, the chip 21 located in the middle of the chip module 2 will be far away from the heat sink 3, and the heat of the chip 21 may not be dissipated in time. Therefore, controlling the number of chips 21 of the chip module 2 to four or less is beneficial to improving the overall heat dissipation effect of the chip module 2 .
  • the chip 21 has a penetrating first through hole 61 , that is, the first through hole 61 extends in a direction perpendicular to the upper surface of the carrying structure 1 .
  • the first through hole 61 It can be through-silicon vias (TSV).
  • the surface of each chip 21 may also have a pad 22, and the pad 22 is electrically connected to the circuit in the chip 21, that is, the pad 22 serves as the lead-out interface of the circuit.
  • the first through hole 61 is connected to the pad 22 so that the first through hole 61 is electrically connected to the circuit in the chip 21 .
  • the first through holes 61 of the multiple chips 21 are facing each other and connected, so that the circuits in the entire chip module 2 are electrically connected together.
  • the chip 21 located on the topmost layer of the stacked structure 4 may not be provided with the first through hole 61 .
  • the topmost chip 21 has a surface with a pad 22 facing the subtop chip 21 and is electrically connected to the subtop chip 21 . In this way, it is helpful to omit the manufacturing step of the first through hole 61 and save production costs.
  • the chip 21 includes a front A and a back B arranged oppositely. It is worth noting that during the manufacturing process of the chip 21, a substrate is first provided, and then multi-layer devices, circuits and other structures are formed on the substrate.
  • the backside B of the chip 21 is the side where the substrate is located, and the frontside A of the chip 21 is the side where devices, circuits and other structures are located.
  • pads 22 may be formed on the front side A of chip 21 to simplify the production process.
  • the front side A of the chip 21 When the chip 21 is working, its front side A generates more heat. That is, the front side A of the chip 21 can be understood as the heating surface. In some embodiments, the front side A of the chip 21 disposed adjacent to the heat dissipation plate 3 faces the heat dissipation plate 3 . In this way, the distance between the heating surface and the heat dissipation plate 3 can be reduced, that is, the heat transfer path can be shortened, thereby increasing the heat dissipation speed. This is illustrated below with examples.
  • the front surfaces A of the top and bottom chips 21 in the chip module 2 face the heat sink 3 . That is, the heating surfaces of the outermost two chips 21 in the chip module 2 both face the heat dissipation plate 3, which is beneficial to improving the heat dissipation effect.
  • the chip module 2 includes two chips 21 , and the front surfaces A of the two chips 21 face the heat sink 3 . That is, the heating surfaces of all chips 21 in the chip module 2 can face the heat sink 3, thereby ensuring that the heat of each chip 21 in the chip module 2 can be dissipated in time.
  • the chip module 2 includes four chips 21 , wherein the front surfaces A of the two chips 21 located above face the heat dissipation plate 3 above the chip module 2 ; the front surfaces A of the two chips 21 located below face the chip. Heat sink 3 under module 2. That is, the distribution uniformity of each heating surface in the chip module 2 is improved, and the heating surfaces of two adjacent chips 21 are prevented from being arranged opposite each other to avoid heat accumulation.
  • the welding part 5 can not only improve the connection strength between the chip module 2 and the heat dissipation plate 3 , but also has excellent thermal conductivity and can transfer the heat generated by the chip module 2 to the heat dissipation plate 3 .
  • the heat dissipation plate 3 has a second through hole 62 penetrating therein; the welding portion 5 is electrically connected to the first through hole 61 and the second through hole 62 . That is, the welding part 5 can also function as an electrical connection.
  • the bottom of the stacked structure 4 may also be provided with a welding portion 5 to achieve electrical connection between the stacked structure 4 and the load-bearing structure 1 . That is to say, in the direction perpendicular to the upper surface of the load-bearing structure 1, the electrically connected soldering portion 5, the first through hole 61 and the second through hole 62 constitute a signal transmission path.
  • At least part of the soldering portion 5 is located at the edge of the chip module 2 . Since the orthographic projection area of the heat dissipation plate 3 on the load-bearing structure 1 is larger than the orthographic projection area of the chip module 2 on the load-bearing structure 1 , in order to increase the support force for the heat dissipation plate 3 , part of the welding portion 5 can be provided on the chip module 2 edge, that is, to increase the structural strength and prevent the heat sink 3 from tipping or collapsing.
  • the welding portions 5 are symmetrically distributed relative to the center of the chip module 2 . That is, the uniformity of the distribution of the welding portions 5 is improved, thereby balancing the connection force between the chip module 2 and the heat dissipation plate 3, and thereby improving the firmness of the stacked structure 4.
  • the semiconductor structure may further include: a packaging structure 7, which covers part of the surface of the heat sink 3 and exposes at least the outer peripheral surface of the heat sink 3; the packaging structure 7 also covers the chip module 2.
  • the outer peripheral surface of the heat sink 3 is flush with the outer peripheral surface of the packaging structure 7. In this way, the shape of the semiconductor structure is more regular.
  • the packaging structure 7 can also expose part of the upper surface and part of the lower surface of the heat dissipation plate 3 . In this way, the exposed area of the heat dissipation plate 3 is larger and can be directed outside the packaging structure 7 A heat dissipation path is formed on the top, which is beneficial to improving the heat dissipation effect.
  • the material of the packaging structure 7 may be epoxy resin material, that is, EMC (Epoxy molding compound).
  • EMC epoxy molding compound
  • the process of forming the packaging structure 7 may be a molding process.
  • the orthographic projection of the chip module 2 on the carrying structure 1 is located within the orthographic projection of the heat sink 3 on the carrying structure 1 . That is, the facing area of the chip module 2 and the heat sink 3 is the orthogonal projection area of the chip module 2 on the carrying structure 1. At this time, the facing area of the two is the largest, and the heat sink 3 can fully receive the heat transferred by the chip module 2. , thereby improving the heat dissipation effect.
  • the orthographic projection of the chip module 2 on the carrying structure 1 is located at the center of the orthographic projection of the heat dissipation plate 3 on the carrying structure 1 . That is, the center of the orthographic projection of the chip module 2 coincides with the center of the orthographic projection of the heat sink 3 . This is beneficial to improving the stability of the stacked structure 4 and improving the uniformity of heat dissipation of the chip module 2 .
  • all peripheral surfaces of the heat dissipation plate 3 are convexly disposed relative to all peripheral surfaces of the chip module 2 . That is, the front projection edge of the chip module 2 is spaced from the front projection edge of the heat sink 3.
  • the front projection of the chip module 2 on the load-bearing structure 1 and the front projection of the heat sink 3 on the load-bearing structure 1 can form a ring-shaped structure. . That is to say, the heat dissipation plate 3 can guide heat to be transferred along all peripheral directions of the chip module 2, which is beneficial to improving the degree of heat dissipation.
  • the orthographic projection of the heat sink 3 on the upper surface of the load-bearing structure 1 may be a rectangle
  • the orthographic projection of the chip module 2 on the upper surface of the load-bearing structure 1 may be a rectangle
  • the orthographic projection of the chip module 2 on the upper surface of the load-bearing structure 1 may be a rectangle
  • the width is greater than the width of the chip module 2 in the second direction Y, where the first direction X and the second direction Y are perpendicular, and both are parallel to the upper surface of the carrying structure 1 .
  • the projected edge has a second distance L2.
  • the orthographic projection of the heat sink 3 and the chip module 2 on the upper surface of the carrying structure 1 may also be circular.
  • the first distance L1 is greater than the second distance L2; thus, it is beneficial to balance the degree of heat dissipation everywhere in the chip module 2 and thereby improve the performance of the semiconductor structure.
  • the first distance L1 may also be equal to the second distance L2, that is, the annular structure formed by the orthographic projection of the heat sink 3 and the orthographic projection of the chip module 2 has a uniform annular width, so , which is conducive to increasing and reducing the size of the heat dissipation plate 3, thereby reducing the volume of the semiconductor structure.
  • part of the outer peripheral surface of the heat dissipation plate 3 is protruding relative to part of the outer peripheral surface of the chip module 2 . That is, part of the outer peripheral surface of the heat dissipation plate 3 may also be aligned with part of the outer peripheral surface of the chip module 2 .
  • the outer peripheral surfaces on opposite sides of the heat dissipation plate 3 are protrudingly disposed relative to the outer peripheral surfaces on opposite sides of the chip module 2 . In this way, it is beneficial to reduce the size of the heat dissipation plate 3, thereby reducing the volume of the semiconductor structure.
  • the orthographic projections of the heat dissipation plate 3 and the chip module 2 on the upper surface of the carrying structure 1 may both be rectangular, that is, the outer peripheral surfaces of the heat dissipation plate 3 and the chip module 2 may each include four sides.
  • the two opposite sides of the heat sink 3 are aligned with the two opposite sides of the chip module 2 , and the two opposite sides of the heat sink 3 are protruding relative to the two opposite sides of the chip module 2 .
  • the orthogonal projection areas of the multiple heat dissipation plates 3 on the load-bearing structure 1 are the same. In this way, the uniformity of the semiconductor structure is better and the manufacturing process is simpler.
  • the orthogonal projection areas of the plurality of heat dissipation plates 3 on the load-bearing structure 1 may also be different.
  • the front projection area of the bottom heat sink 3 is larger, and the front projection area of the top heat sink 3 is smaller. Therefore, the center of gravity of the stack structure 4 can be lowered to improve the stability of the stack structure 4 .
  • the ratio of the area of the orthographic projection of the heat sink 3 on the carrying structure 1 to the area of the orthogonal projection of the chip module 2 on the carrying structure 1 is 1.5:1 to 3:1.
  • the ratio of the orthographic projection areas of the two is maintained within the above range, the guiding role of the heat sink 3 in heat transfer can be improved, and the space area occupied by the stacked structure 4 on the load-bearing structure 1 can also be saved.
  • the orthogonal projected area of the heat sink 3 may also be proportional to the number of chips 21 in the chip module 2 closest to it.
  • one heat sink 3 has chip modules 2 on both upper and lower sides, and the total number of chips 21 of the two chip modules 2 is 3; another heat sink 3 has chip modules 2 on both upper and lower sides, and the two chip modules 2
  • the total number of chips 21 is 4, then the front projection area of the latter can be larger than the front projection area of the former.
  • the heat dissipation degree of each chip module 2 can be balanced, and space utilization can be improved to avoid wasting space.
  • the orthographic projections of the plurality of heat dissipation plates 3 on the load-bearing structure 1 coincide. That is, the orthogonal projected areas of the plurality of heat dissipation plates 3 are the same, and the plurality of heat dissipation plates 3 are arranged facing each other in a direction perpendicular to the upper surface of the load-bearing structure 1 .
  • the shape of the stacked structure 4 is relatively regular, which facilitates the formation of the packaging structure 7; it also helps to improve the stability of the stacked structure 4 and avoid the problem of tipping or collapse due to uneven stress on each layer of the heat dissipation plate 3.
  • the orthographic projections of the plurality of heat dissipation plates 3 on the load-bearing structure 1 have partial overlap. That is, multiple heat dissipation plates 3 can be arranged staggered to facilitate filling of packaging materials to reduce gaps generated when forming the packaging structure 7 , thereby improving the protection effect of the packaging structure 7 on the stacked structure 4 .
  • the orthographic projections of the odd-numbered layers of the heat dissipation plates 3 on the load-bearing structure 1 overlap, and the orthographic projections of the even-numbered layers of the heat dissipation plates 3 on the load-bearing structure 1 overlap.
  • the center of gravity of the stacked structure 4 can be moved closer to the central position, thereby improving the stability of the stacked structure 4 .
  • the two heat dissipation plates 3 are aligned in the second direction Y, that is, they have no offset in the second direction Y; the two heat dissipation plates 3 have an offset in the first direction X.
  • Such a staggered method is relatively simple and is conducive to ensuring the stability of the stacked structure 4 .
  • the two heat dissipation plates 3 have offsets in both the first direction X and the second direction Y. In this way, the filling space of the encapsulating material is larger, and therefore, large particles of encapsulating material can be used.
  • the centers of the two heat dissipation plates 3 are facing each other, and the length direction of one heat dissipation plate 3 is perpendicular to the length direction of the other heat dissipation plate 3 .
  • the center of the heat sink 3 can also be directly opposite to the center of the chip module 2 .
  • the thickness of the heat sink 3 will be described in detail below.
  • the thickness of multiple heat dissipation plates 3 can be the same, thereby improving the uniformity of the stacked structure 4 and making the production process simpler.
  • the thickness of the heat sink 3 is proportional to the number of chips 21 in the chip module 2 closest to it. Specifically, the chip modules 2 on the upper and lower sides of the bottom heat sink 3 have three chips 21 in total, and the chip modules 2 on the upper and lower sides of the top heat sink 3 have four chips 21 in total.
  • the thickness h2 of the bottom heat sink 3 is smaller than the top heat sink 3. 3 thickness h1. In this way, it is beneficial to improve the heat dissipation effect of the stacked structure 4 and reduce the thickness of the stacked structure 4 in the direction perpendicular to the upper surface of the load-bearing structure 1 .
  • the thickness of the heat dissipation plate 3 may be smaller than the thickness of the chip 21 . Since the front projection area of the heat sink 3 is larger than the front projection area of the chip 21 , the heat dissipation performance of the heat sink 3 is better. Correspondingly, the thickness of the heat dissipation plate 3 can be reduced to reduce the overall thickness of the stacked structure 4 .
  • the thickness of the chip 21 may be 30 ⁇ m to 80 ⁇ m, such as 40 ⁇ m, 50 ⁇ m, or 60 ⁇ m.
  • the thickness of the heat sink 3 can be 10 ⁇ m to 40 ⁇ m, such as 20 ⁇ m, 20 ⁇ m, or 30 ⁇ m, which can help ensure the heat dissipation effect of the heat sink 3 and avoid wasting space.
  • the bottommost chip module 2 in the stacked structure 4 is welded to the carrier structure 1, and the topmost chip module 2 in the stacked structure 4 is located on the topmost heat sink. 3 on. That is, no heat dissipation plate 3 is provided between the bottommost chip module 2 in the stacked structure 4 and the carrying structure 1 , and no heat dissipation plate 3 is provided above the topmost chip module 2 in the stacked structure 4 .
  • the heat generated by the chip module 2 at the outermost side of the stacked structure 4 is easier to dissipate, that is, the topmost and bottom chip modules 2 in the stacked structure 4
  • the heat generated is not easy to accumulate. Therefore, there is no need to provide the heat dissipation plate 3 on the outermost side of the stack structure 4 , thereby reducing the number of heat dissipation plates 3 and reducing the volume of the stack structure 4 .
  • the bottommost chip module 2 includes one chip 21
  • the topmost chip module 2 includes one chip 21 . Since the heat dissipation plate 3 is not provided on the outermost side of the stacked structure 4 , the number of chips 21 in the outermost chip module 2 can be reduced accordingly to balance the heat dissipation degree of each chip 21 .
  • the thickness of the topmost chip 21 is usually larger, so there is no need to be pre-bonded with other chips 21 to increase the total thickness of the chip module 2 .
  • the reason why the topmost chip 21 is thicker is that during the integration of subsequent products, other chips 21 such as processors will be provided next to the stacked structure 4 .
  • JEDEC Joint Electronic Equipment Engineering Council
  • the topmost chip 21 in the stacked structure 4 is generally thicker, and such a setting is used to match the height of other chips 21. height to meet JEDEC regulations.
  • the heat dissipation plate 3 is added to the stacked structure 4.
  • the heat dissipation plate 3 has excellent heat dissipation effect and can avoid heat accumulation in the chip 21.
  • the front projected area of the heat dissipation plate 3 is larger than the front projected area of the chip module 2, so that a heat dissipation path can be formed in the outer direction to improve the degree of heat dissipation.
  • both the material and the extension direction of the heat sink 3 are conducive to increasing the heat dissipation speed.
  • the heat dissipation plate 3 can function as a spacer between the chip modules 2 to increase the distance between adjacent chip modules 2 and provide more space for heat dissipation.
  • FIG. 12-15 and 2 another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure provided by an embodiment of the present application will be described in detail below with reference to the accompanying drawings.
  • the stacked structure 4 includes a stacked heat sink 3 and a chip module 2; the area of the orthographic projection of the heat sink 3 on the load-bearing structure 1 is larger than that of the chip module 2 on the load-bearing structure. The area of the orthographic projection on 1.
  • multiple chip modules 2 are provided, and the chip modules 2 include at least one chip 21 .
  • the partial chip module 2 may include two chips 21 , and the partial chip module 2 may include one chip 21 .
  • a first through hole 61 and a pad 22 are manufactured, wherein the pad 22 can lead the circuit in the chip 21 to the surface of the chip 21 , and the first through hole 61 is electrically connected to the pad 22 .
  • the two thin chips 21 are hybrid-bonded in the manner of backside B to backside B, so that the frontside A of the two chips 21 faces outward, and the first through holes 61 of the two chips 21 are electrically connected through the bonding portion 23 connect.
  • the pad 22 is located on the front side A of the chip 21 . Therefore, the pads 22 of the two chips 21 are arranged facing away.
  • a thicker chip 21 is provided as the top chip module 2.
  • a pad 22 is formed on the bottom of the chip 21 , and a soldering pad 51 and a soldering bump 52 connected to the pad 22 are formed. There is no need to form a penetrating first through hole 61 in the chip 21 to simplify the production process.
  • a chip 21 is provided as the underlying chip module 2 .
  • a first through hole 61 electrically connected to the pad 22 is formed in the chip 21 , and a soldering pad 51 and a soldering bump 52 connected to the first through hole 61 are formed at the bottom of the chip 21 .
  • a heat sink 3 is provided, a second through hole 62 is formed through the heat sink 3 , a soldering pad 51 is formed on the upper surface of the heat sink 3 , and a soldering pad 51 and a soldering bump 52 are formed on the lower surface of the heat sink 3 .
  • a load-bearing structure 1 is provided, on which a stack structure 4 is disposed.
  • a signal connection is formed between each chip 21 and the carrying structure 1 .
  • the heat-generating surface of the chip 21 needs to face the heat sink 3 .
  • the stacked structure 4 After the stacked structure 4 is arranged on the load-bearing structure 1 , it also includes: using a molding process to form the packaging structure 7 ; the packaging structure 7 covers part of the surface of the heat dissipation plate 3 and exposes at least the outer peripheral surface of the heat dissipation plate 3 ; the packaging structure 7 also covers Chip module 2. Since the outer peripheral surface of the heat dissipation plate 3 is exposed, heat can be transferred from the outer peripheral surface of the heat dissipation plate 3 to the outside of the packaging structure 7 , thereby improving the heat dissipation effect.
  • the molding process may be compression molding, in which the EMC is placed into a mold and then melted. Compression molding reduces defects such as voids.
  • the heating surface of the chip 21 is welded to the heat sink 3, and the heat generated by the chip 21 can be dissipated to the outside of the packaging structure 7 through the heat sink 3.
  • multiple chips 21 can be pre-bonded using hybrid bonding or bump welding technology.
  • the circuits of multiple chips 21 are connected together through conductive structures such as TSVs, bonding pads 51, and soldering bumps 52, and are electrically connected to the load-bearing structure 1 through the bonding pads 51 and soldering bumps 52 on the lower surface of the underlying chip module 2, thereby The signal interconnection between the chip module 2 and the carrying structure 1 is realized.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本公开实施例涉及半导体领域，提供一种半导体结构和半导体结构的制造方法，半导体结构包括：承载结构；位于所述承载结构上的堆叠结构；所述堆叠结构包括堆叠设置的散热板和芯片模块，所述芯片模块至少包括一个芯片；所述散热板在所述承载结构上的正投影的面积大于所述芯片模块在所述承载结构上的正投影的面积。本公开实施例至少可以提高半导体结构的散热程度。

Description

半导体结构和半导体结构的制造方法
交叉引用
本申请引用于2022年8月19日递交的名称为“半导体结构和半导体结构的制造方法”的第202211000015.9号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开实施例属于半导体领域，具体涉及一种半导体结构和半导体结构的制造方法。
背景技术
HBM(High Bandwidth Memory，高带宽内存)是一款新型的内存。以HBM为代表的芯片堆叠技术，将原本一维的存储器布局扩展到三维，即将很多个芯片堆叠在一起并进行封装，从而大幅度提高了芯片的密度，并实现了大容量和高带宽。
然而，随着堆叠层数的增加，芯片在工作时产生的热量会堆积，从而对产品性能造成不良影响。比如，温度升高会影响半导体结构的体积，进而导致材料产生机械裂纹；温度升高还会影响芯片的电气性能，从而难以达到预期功能。
发明内容
本公开实施例提供一种半导体结构和半导体结构的制造方法，至少有利于提高芯片的散热程度，从而提高半导体结构的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，其中，半导体结构包括：承载结构；位于所述承载结构上的堆叠结构；所述堆叠结构包括堆叠设置的散热板和芯片模块，所述芯片模块至少包括一个芯片；所述散热板在所述承载结构上的正投影的面积大于所述芯片模块在所述承载结构上的正投影的面积。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，制造方法包括：提供承载结构和堆叠结构；将所述堆叠结构设置在所述承载结构上；所述堆叠结构包括堆叠设置的散热板和芯片模块， 所述芯片模块至少包括一个芯片；所述散热板在所述承载结构上的正投影的面积大于所述芯片模块在所述承载结构上的正投影的面积。
本公开实施例提供的技术方案至少具有以下优点：散热板在承载结构上的正投影的面积大于芯片模块在承载结构上的正投影的面积。即，散热板相对于芯片模块向外延伸，使得散热板可以对芯片模块产生的热量起到引导作用，热量沿着散热板传递到封装结构外围，从而提高散热效果。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了一种半导体结构的示意图；
图2示出了本公开一实施例提供的一种半导体结构的示意图；
图3示出了本公开一实施例提供的另一种半导体结构的示意图；
图4示出了本公开一实施例提供的又一种半导体结构的示意图；
图5-图7、图9-图11分别示出了本公开一实施例提供的散热板和芯片模块的不同俯视图；
图8示出了本公开一实施例提供的再一种半导体结构的示意图；
图12-图14分别示出了本公开另一实施例提供的不同芯片模块的示意图；
图15示出了本公开另一实施例提供的散热板的示意图。
具体实施方式
参考图1，经分析发现，随着堆叠层数越来越多，芯片200与芯片200之间通过固晶用胶膜(die attach film，DAF)或者模塑底部填充胶(Mold underfill)等粘结层进行填充粘结。随着芯片200越来越薄，芯片200与芯片200之间的空间越来越小，因此，散热空间缩小，芯片200产生的热量堆积，从而会对半导体结构的性能产生影响。
本公开实施例提供一种半导体结构，其中，堆叠结构包括散热板和芯片模块，散热板在承载结构上的正投影的面积大于芯片模块在承载结构上的正投影的面积。即，散热板相对于芯片模块向外延伸，芯片模块产生的热量可以通过散热板散到封装结构外围。散热板能够对散热方向起到引导作用， 从而加快芯片的散热速度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图2-图11所示，本公开一实施例提供一种半导体结构，半导体结构包括：承载结构1；位于承载结构1上的堆叠结构4；堆叠结构4包括堆叠设置的散热板3和芯片模块2，芯片模块2至少包括一个芯片21；散热板3在承载结构1上的正投影的面积大于芯片模块2在承载结构1上的正投影的面积。
即，在平行于承载结构1上表面的方向上，散热板3相对于芯片模块2向外延伸。由于热量自发地由高温处向低温处传递，而芯片模块2温度大于芯片模块2外围的温度，因此，散热板3可以将芯片模块2产生的热量迅速向外传递，从而提高芯片模块2的散热程度，进而避免高热量对半导体结构的性能产生影响。
以下将结合附图对半导体结构进行详细说明。
参考图2-图4、图8，在一些实施例中，承载结构1可以为基板。基板主要起保护芯片21，以及电连接芯片21与外围电路板的作用。基板选用具有良好散热性能的材料，比如有机基板或陶瓷基板等。在另一些实施例中，芯片21可以为存储芯片，比如动态随机存取存储器(DRAM，Dynamic Random Access Memory)，芯片21也可以为逻辑芯片，存储芯片与逻辑芯片进行通信。
在一些实施例中，靠近承载结构1的芯片21可以为逻辑芯片，远离承载结构1的芯片21可以为存储芯片。
在一些实施例中，承载结构1可以是逻辑芯片。
在一些实施例中，散热板3可以为散热芯片，比如微流道散热芯片。微流道散热芯片中设有微流通道，冷却液体可以进入微流通道吸收热量，此后从微流通道排成以带走热量，通过控制冷却液体在微流通孔中的流动速度以控制散热速率，另外可以选用两相冷却液体，即冷却液体可以因温度变化而产生相变，从而带走更多热量。在另一些实施例中，散热板3还可以其它高导热材料，比如铜、石墨烯、氮化铝等材料。
此外，散热板3还可以具有粗糙的表面，以增加散热面积，从而提高散热效果。比如，散热板3的表面可以包括纳米粗糙结构或微米粗糙结构。在一些实施例中，散热板3表面各处的平整程度可以不同；比如，散热板3 与芯片模块2相对的表面的平整度，可以大于散热板3向外延伸的表面的平整度；举例而言，散热板3向外延伸的部分可以设有凸起或凹陷。如此，可以在芯片模块2的外围增大散热面积，且能够便于将散热板3与芯片模块2进行焊接，从而提高焊接的牢固性。
继续参考图2-图4、图8，在一些实施例中，芯片模块2为多个；在垂直于堆叠结构4的上表面的方向上，芯片模块2与散热板3交替排列。即每个芯片模块2至少与一个散热板3相邻设置，且部分芯片模块2还可以与两个散热板3相邻设置。如此，有利于提高芯片模块2与散热板3分布的均一性，从而加快热量传递过程。另外，交替排列的方式还有利于增加相邻芯片模块2之间的距离，从而为相邻芯片模块2提供更充足的散热空间，以避免热量堆积。
在一些实施例中，多个芯片模块2中的至少一者包括多个层叠设置的芯片21。示例地，芯片21的厚度较小，多个芯片21可以采用混合键合的方式进行堆叠。即芯片21的表面具有键合部23和介质层(图中未示出)，键合部23的上表面可以与介质层的上表面齐平，或者键合部23的上表面相对于介质层的上表面具有轻微的凹陷。在升温条件下，相邻两个芯片21的键合部23会轻微膨胀并键合在一起，从而形成电气连接；相邻两个芯片21的介质层可以通过分子间作用力连接在一起。
在另一些实施例中，也可以采用凸点焊接技术将多个芯片21连接在一起。即凸点使得相邻芯片21的表面间隔设置，从而可以为相邻芯片21提供较多的散热空间。
值得说明的是，一个芯片21的厚度较小，而多个芯片21层叠后的总厚度增加，从而能够便于将散热板3与芯片模块2焊接在一起。此外，相比于单个芯片21与散热板3交替设置，多个芯片21堆叠形成的芯片模块2与散热板3交替设置，有利于提高散热板3的利用率，并能够减少散热板3的数量，从而有利于减小半导体结构的体积。
在一些实施例中，芯片模块2内的芯片21数量少于四个。需要注意的是，若芯片模块2的芯片21数量过多，则位于芯片模块2中间位置的芯片21与散热板3的距离较远，此芯片21的热量可能无法及时散出。因此，将芯片模块2的芯片21数量控制在四个及四个以内，有利于提高芯片模块2整体的散热效果。
继续参考图2-图4、图8，芯片21内具有贯穿的第一通孔61，即第一通孔61在垂直于承载结构1上表面的方向上延伸，示例地，第一通孔61可以为硅穿孔(Through-Silicon Vias,TSV)。此外，每个芯片21的表面还可以具有衬垫22，衬垫22与芯片21内的电路电连接，即衬垫22作为电路的 引出接口。另外，第一通孔61与衬垫22相连，使得第一通孔61与芯片21内的电路电连接。在一个芯片模块2具有多个芯片21时，多个芯片21的第一通孔61正对且相连，从而使得整个芯片模块2内的电路电连接在一起。
在一些实施例中，位于堆叠结构4最顶层的芯片21可以不设置第一通孔61。最顶层的芯片21具有衬垫22的表面朝向次顶层的芯片21，并与次顶层的芯片21电连接。如此，有利于省去第一通孔61的制造步骤，节约生产成本。
继续参考图2-图4、图8，芯片21包括相对设置的正面A和背面B。值得注意的是，在芯片21的制造过程中，首先会提供一个衬底，此后在衬底上形成多层器件、电路等结构。芯片21的背面B即衬底所在的一侧，芯片21的正面A即器件、电路等结构所在的一侧。在一些实施例中，衬垫22可以形成在芯片21的正面A，以简化生产工艺。
芯片21在工作时，其正面A所产生的热量更多。即芯片21的正面A可以理解为发热面。在一些实施例中，与散热板3相邻设置的芯片21的正面A朝向该散热板3。如此，可以减小发热面与散热板3的距离，即缩短热量传递路径，进而提高散热速度。以下将对此进行举例说明。
在芯片模块2包括多个层叠设置的芯片21时，芯片模块2中顶层和底层的芯片21的正面A朝向散热板3。即芯片模块2中最外两侧的芯片21的发热面均朝向散热板3，从而有利于提高散热效果。
在一些实施例中，参考图2-图4、图8，芯片模块2包括两个芯片21，且两个芯片21的正面A均朝向散热板3。即芯片模块2内所有芯片21的发热面均可以朝向散热板3，从而保证芯片模块2内各芯片21的热量都能够及时散出。
在另一些实施例中，芯片模块2包括四个芯片21，其中，位于上方的两个芯片21的正面A朝向芯片模块2上方的散热板3；位于下方的两个芯片21的正面A朝向芯片模块2下方的散热板3。即，提高芯片模块2内各发热面的分布的均匀性，避免两个相邻芯片21的发热面相对设置，以避免热量堆积。
参考图2-图4、图8，芯片模块2与散热板3之间具有多个焊接部5。即，焊接部5不仅能够提高芯片模块2与散热板3的连接强度，且焊接部5优良的导热性较能够将芯片模块2产生的热量传递至散热板3。
此外，散热板3内具有贯穿的第二通孔62；焊接部5与第一通孔61和第二通孔62电连接。即，焊接部5还能够起到电气连接的作用。此外，堆叠结构4的底部还可以设有焊接部5，从而实现堆叠结构4与承载结构1的电连接。也就是说，在垂直于承载结构1上表面的方向上，电连接的焊接 部5、第一通孔61和第二通孔62构成信号传输路径。由此，无需通过引线或引线框架等导电结构将各芯片模块2与承载结构1进行电连接，从而有利于缩小半导体结构的体积，提高半导体结构的集成度。
在一些实施例中，至少部分焊接部5位于芯片模块2的边缘。由于散热板3在承载结构1上的正投影面积大于芯片模块2在承载结构1上的正投影面积，因此，为了增加对散热板3的支撑力，可以将部分焊接部5设置在芯片模块2的边缘，即提高结构强度，避免散热板3的发生倾倒或坍塌。
焊接部5相对于芯片模块2的中心呈对称分布。即，提高焊接部5分布的均一性，从而平衡芯片模块2与散热板3之间的连接力，进而提高堆叠结构4的牢固性。
参考图2-图4、图8，半导体结构还可以包括：封装结构7，封装结构7覆盖散热板3的部分表面，并至少露出散热板3的外周面；封装结构7还覆盖芯片模块2。在一些实施例中，参考图2、图3、图8，散热板3的外周面与封装结构7的外周面齐平，如此，半导体结构的形状更为规整。在另一些实施例中，参考图4，封装结构7还可以露出散热板3的部分上表面和部分下表面，如此，散热板3被暴露的面积更大，并能够在封装结构7的外侧方向上形成散热路径，从而有利于提高散热效果。
示例地，封装结构7的材料可以为环氧树脂材料，即EMC(Epoxy molding compound)。形成封装结构7的工艺可以为模塑工艺。
以下将对芯片模块2的正投影与承载结构1的正投影的位置关系和尺寸关系进行详细说明。
具体地，如图2-图11所示，芯片模块2在承载结构1上的正投影位于散热板3在承载结构1上的正投影内。即，芯片模块2与散热板3的正对面积为芯片模块2在承载结构1上的正投影面积，此时，二者的正对面积最大，散热板3能够充分接收芯片模块2传递的热量，从而提高散热效果。
在一些实施例中，参考图5-图7，芯片模块2在承载结构1上的正投影位于散热板3在承载结构1上的正投影的中心位置。即芯片模块2的正投影的中心与散热板3的正投影的中心相重合。由此，有利于提高堆叠结构4的稳定性，且提高芯片模块2散热的均匀性。
在一些实施例中，参考图5和图6，散热板3的所有外周面相对于芯片模块2的所有外周面呈凸出设置。即，芯片模块2的正投影边缘与散热板3的正投影边缘相间隔，芯片模块2在所述承载结构1上的正投影与散热板3在承载结构1上的正投影可以构成环状结构。也就是说，散热板3能够引导热量沿着芯片模块2的所有外周方向进行传递，如此，有利于提高散热程度。
继续参考图5和图6，散热板3在承载结构1上表面的正投影可以为矩形，芯片模块2在承载结构1上表面的正投影可以为矩形，芯片模块2在第一方向X上的宽度大于芯片模块2在第二方向Y上的宽度，其中第一方向X与第二方向Y垂直，且二者均平行于承载结构1的上表面。在第一方向X上，散热板3的正投影边缘与芯片模块2的正投影边缘之间具有第一距离L1；在第二方向Y上，散热板3的正投影边缘与芯片模块2的正投影边缘具有第二距离L2。此外，散热板3和芯片模块2在承载结构1上表面的正投影还可以为圆形。
参考图5，在一些实施例中，第一距离L1大于第二距离L2；从而有利于均衡芯片模块2各处的散热程度，进而提高半导体结构的性能。参考图6，在另一些实施例中，第一距离L1也可以等于第二距离L2，即，散热板3的正投影与芯片模块2的正投影构成的环状结构具有均一的环宽，如此，有利于提高减小散热板3的尺寸，从而缩小半导体结构的体积。
在一些实施例中，参考图7，散热板3的部分外周面相对于芯片模块2的部分外周面呈凸出设置。即，散热板3的部分外周面还可以与芯片模块2的部分外周面对齐。示例地，散热板3相对两侧的外周面相对于芯片模块2相对两侧的外周面呈凸出设置。如此，有利于减小散热板3的尺寸，从而缩小半导体结构的体积。
举例而言，继续参考图7，散热板3和芯片模块2在承载结构1上表面的正投影可以均为矩形，即，散热板3和芯片模块2的外周面可以均包括四个侧面。其中，散热板3的两个相对侧面与芯片模块2的两个相对侧面对齐，且散热板3的两个相对侧面相对于芯片模块2的两个相对侧面呈凸出设置。
以下将对多个散热板3之间的位置关系和正投影的面积关系进行详细说明。
在一些实施例中，散热板3为多个，且多个散热板3在承载结构1上的正投影的面积相同。如此，半导体结构的均一性更好，且制造工艺更简单。
在另一些实施例中，多个散热板3在承载结构1上的正投影的面积也可以不同。例如，越底层的散热板3的正投影面积更大，越顶层的散热板3的正投影的面积更小，由此，可以降低堆叠结构4的重心，以提高堆叠结构4的稳定性。
散热板3在承载结构1上的正投影的面积与芯片模块2在承载结构1上的正投影的面积的比例为1.5:1～3:1。当二者的正投影面积的比例保持在上述范围时，既能够提高散热板3的热量传递的引导作用，还能够节约堆叠结构4在承载结构1上所占据的空间面积。
此外，散热板3的正投影面积也可以与其距离最近的芯片模块2中的芯片21的数量成正比。举例而言，一个散热板3上下两侧均具有芯片模块2，两个芯片模块2的芯片21总数为3个；另一个散热板3上下两侧均具有芯片模块2，且两个芯片模块2的芯片21总数为4个，则后者的正投影面积可以大于前者的正投影面积。由此，可以均衡各芯片模块2的散热程度，且提高空间的利用率，避免造成空间浪费。
在一些实施例中，参考图2-图7，多个散热板3在承载结构1上的正投影相重合。即，多个散热板3的正投影面积相同，且多个散热板3在垂直于承载结构1上表面的方向上正对设置。由此，堆叠结构4的形状较为规整，能够便于形成封装结构7；且有利于提高堆叠结构4的稳定性，避免因各层散热板3受力不均而发生倾倒或坍塌的问题。
在另一些实施例中，参考图8-图11，多个散热板3在承载结构1上的正投影具有部分重合。即，多个散热板3可以交错设置，从而便于填充封装材料，以减少在形成封装结构7时所产生空隙，进而提高封装结构7对堆叠结构4的保护效果。
此外，在散热板3的数量大于四个时，奇数层的散热板3在承载结构1上的正投影相重合，偶数层的散热板3在承载结构1上的正投影相重合。由此，堆叠结构4的重心可以向中心位置靠近，从而提高堆叠结构4的稳定性。
参考图9，两个散热板3在第二方向Y上对齐，即二者在第二方向Y上不具有偏移；两个散热板3在第一方向X上散热板3具有偏移。这样的交错方式较为简单，且有利于保证堆叠结构4的稳定性。
参考图10，两个散热板3在第一方向X和第二方向Y上均具有偏移。如此，封装材料的填充空间更大，因而，可以使用大颗粒的封装材料。
参考图11，两个散热板3的中心正对，一散热板3的长度方向与另一散热板3的长度方向相垂直。此外，散热板3的中心还可以与芯片模块2的中心正对。由此，可以提高堆叠结构4的稳定性，避免发生坍塌或倾斜的问题。
以下将对散热板3的厚度进行详细说明。
参考图2，多个散热板3的厚度可以相同，从而提高堆叠结构4的均一性，且生产工艺更简单。
参考图3，在散热板3的厚度与其距离最近的芯片模块2中的芯片21的数量成正比。具体地，底层散热板3的上下两侧的芯片模块2共有三个芯片21，顶层散热板3的上下两侧的芯片模块2共有四个芯片21，底层散热板3的厚度h2小于顶层散热板3的厚度h1。如此，有利于提高堆叠结构4 的散热效果，并且降低堆叠结构4在垂直于承载结构1上表面的方向上的厚度。
在垂直于承载结构1上表面的方向上，散热板3的厚度可以小于芯片21的厚度。由于散热板3的正投影面积大于芯片21的正投影面积，因此，散热板3的散热性能较好。相应地，可以缩小散热板3的厚度，以缩小堆叠结构4的整体厚度。
举例而言，芯片21的厚度可以为30μm～80μm，比如40μm、50μm、60μm。散热板3的厚度可以为10μm～40μm，比如20μm、20μm、30μm，从而有利于保证散热板3的散热效果，且避免空间浪费。
在一些实施例中，参考图2-图4、图8，堆叠结构4中的最底层的芯片模块2焊接在承载结构1上，堆叠结构4中最顶层的芯片模块2位于最顶层的散热板3上。即，堆叠结构4中最底层的芯片模块2与承载结构1之间不设置散热板3，堆叠结构4中最顶层的芯片模块2之上不设置散热板3。
需要说明的是，相比于处于堆叠结构4中间位置的芯片模块2，堆叠结构4最外侧的芯片模块2产生的热量更容易散出，即堆叠结构4中最顶层和最底层的芯片模块2产生的热量不易堆积。因此，堆叠结构4的最外侧可以无需设置散热板3，从而减少散热板3的数量，以减小堆叠结构4的体积。
在一些实施例中，最底层的芯片模块2包括一个芯片21，最顶层的芯片模块2包括一个芯片21。由于堆叠结构4的最外侧未设置散热板3，因此，可以相应减少最外侧的芯片模块2的芯片21数量，以平衡各芯片21的散热程度。
此外，最顶层的芯片21的厚度通常更大，因此，无需和其他的芯片21进行预先键合以增加芯片模块2的总厚度。最顶层的芯片21的厚度更大的原因在于：在后续产品的集成中，堆叠结构4的旁边还设有其他芯片21，比如处理器等。目前JEDEC(联合电子设备工程委员会)规定这些芯片21的顶面高度要遵循相应的高度标准，因此堆叠结构4中最顶层的芯片21一般要厚一些，通过这样的设定去匹配其他芯片21的高度，以满足JEDEC的规定。
综上所述，本公开实施例中，在堆叠结构4中增加散热板3，散热板3具有优良的散热效果，能够避免芯片21的热量堆积。此外，散热板3的正投影面积比芯片模块2的正投影面积更大，从而能够在外侧方向上形成散热路径，以提高散热程度。也就是说，散热板3的材质和延伸方向均有利于提高散热速度。此外，散热板3可以起到间隔芯片模块2的作用，以增大相邻芯片模块2之间的距离，提供更多的散热空间。
如图12-图15、图2所示，本公开另一实施例提供一种半导体结构的 制造方法，以下将结合附图对本申请一实施例提供的半导体结构的制造方法进行详细说明。
参考图12-图15、图2，提供堆叠结构4，堆叠结构4包括堆叠设置的散热板3和芯片模块2；散热板3在承载结构1上的正投影的面积大于芯片模块2在承载结构1上的正投影的面积。
具体地，参考图12-图15，提供多个芯片模块2，芯片模块2至少包括一个芯片21。在一些实施例中，部分芯片模块2可以包括两个芯片21，部分芯片模块2可以包括一个芯片21。
参考图12，制造第一通孔61和衬垫22，其中衬垫22可以将芯片21内的电路引出至芯片21的表面，第一通孔61与衬垫22电连接。将两个薄的芯片21以背面B对背面B的方式进行混合键合，从而使得两个芯片21的正面A朝外设置，且两个芯片21的第一通孔61通过键合部23电连接。在一些实施例中，衬垫22位于芯片21的正面A，因此，两个芯片21的衬垫22背向设置。
参考图13，提供一个较厚的芯片21作为顶层的芯片模块2。在芯片21的底部形成衬垫22，并形成与衬垫22相连的焊垫51和焊接凸块52。此芯片21内无需形成贯穿的第一通孔61，以简化生产工艺。
参考图14，提供一个芯片21作为底层的芯片模块2。在芯片21内形成与衬垫22电连接的第一通孔61，在芯片21的底部形成与第一通孔61相连的焊垫51和焊接凸块52。
参考图15，提供散热板3，形成贯穿散热板3的第二通孔62，并在散热板3的上表面形成焊垫51，在散热板3的下表面形成焊垫51和焊接凸块52。
参考图2，提供承载结构1，将堆叠结构4设置在承载结构1上。从而使得各芯片21与承载结构1之间形成信号连接。在堆叠过程中，需要将芯片21的发热面朝向散热板3。
将堆叠结构4设置在承载结构1上后，还包括：采用模塑工艺形成封装结构7；封装结构7覆盖散热板3的部分表面，并至少露出散热板3的外周面；封装结构7还覆盖芯片模块2。由于散热板3的外周面被露出，因而热量可以从散热板3的外周面传递至封装结构7的外部，从而提高散热效果。
示例地，模塑工艺可为压缩模塑法，即EMC被放入模具中，然后再进行熔化。压缩模塑法可以减少空隙等缺陷。
综上所述，多层堆叠的芯片模块2中，将芯片21的发热面焊接在散热板3上，芯片21产生的热量可以通过散热板3散到封装结构7外部。此 外，由于芯片21比较薄，因此可以使用混合键合或凸点焊接技术的方式将多个芯片21预先键合。多个芯片21的电路通过TSV、焊垫51、焊接凸块52等导电结构连接在一起，并通过底层芯片模块2下表面的焊垫51和焊接凸块52与承载结构1进行电连接，从而实现了芯片模块2与承载结构1的信号互连。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (16)

  1. 一种半导体结构，包括：
    承载结构；
    位于所述承载结构上的堆叠结构；
    所述堆叠结构包括堆叠设置的散热板和芯片模块，所述芯片模块至少包括一个芯片；
    所述散热板在所述承载结构上的正投影的面积大于所述芯片模块在所述承载结构上的正投影的面积。
  2. 根据权利要求1所述的半导体结构，其中，
    所述芯片模块为多个；
    在垂直于所述堆叠结构的上表面的方向上，所述芯片模块与所述散热板交替排列。
  3. 根据权利要求1所述的半导体结构，其中，
    所述芯片包括相对设置的正面和背面；
    所述芯片模块包括多个层叠设置的所述芯片，且所述芯片模块中顶层和底层的所述芯片的正面朝向所述散热板。
  4. 根据权利要求3所述的半导体结构，其中，
    所述芯片模块包括两个所述芯片，且两个所述芯片的正面均朝向所述散热板。
  5. 根据权利要求1所述的半导体结构，其中，还包括：
    封装结构，覆盖所述散热板的部分表面，并至少露出所述散热板的外周面；所述封装结构还覆盖所述芯片模块。
  6. 根据权利要求1所述的半导体结构，其中，
    所述芯片模块与所述散热板之间具有多个焊接部。
  7. 根据权利要求6所述的半导体结构，其中，
    所述芯片模块内具有贯穿的第一通孔；
    所述散热板内具有贯穿的第二通孔；
    所述焊接部与所述第一通孔和所述第二通孔电连接。
  8. 根据权利要求6所述的半导体结构，其中，
    至少部分所述焊接部位于所述芯片模块的边缘。
  9. 根据权利要求6所述的半导体结构，其中，
    所述焊接部相对于所述芯片模块的中心呈对称分布。
  10. 根据权利要求1所述的半导体结构，其中，所述芯片模块在所述承载结构上的正投影位于所述散热板在所述承载结构上的正投影的中心位置。
  11. 根据权利要求1所述的半导体结构，其中，
    在垂直于承载结构上表面的方向上，所述散热板的厚度小于所述芯片的厚度。
  12. 根据权利要求1所述的半导体结构，其中，
    所述散热板为多个，且多个所述散热板在所述承载结构上的正投影的面积相同。
  13. 根据权利要求1所述的半导体结构，其中，所述散热板的厚度与其距离最近的所述芯片模块中的所述芯片的数量成正比。
  14. 根据权利要求1所述的半导体结构，其中，所述堆叠结构中的最底层的所述芯片模块焊接在所述承载结构上，且最底层的所述芯片模块包括一个所述芯片；
    所述堆叠结构中最顶层的所述芯片模块位于最顶层的所述散热板上，且最顶层的所述芯片模块包括一个所述芯片。
  15. 一种半导体结构的制造方法，包括：
    提供承载结构和堆叠结构；
    将所述堆叠结构设置在所述承载结构上；所述堆叠结构包括堆叠设置的散热板和芯片模块，所述芯片模块至少包括一个芯片；所述散热板在所述承载结构上的正投影的面积大于所述芯片模块在所述承载结构上的正投影的面积。
  16. 根据权利要求15所述的半导体结构的制造方法，其中，将所述堆叠结构设置在所述承载结构上后，还包括：
    采用模塑工艺形成封装结构；所述封装结构覆盖所述散热板的部分表面，并至少露出所述散热板的外周面；所述封装结构还覆盖所述芯片模块。
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CN102522380A (zh) * 2011-12-21 2012-06-27 华为技术有限公司 一种PoP封装结构
CN103430301A (zh) * 2011-05-26 2013-12-04 华为技术有限公司 热增强堆叠式封装和方法
CN103839903A (zh) * 2014-03-10 2014-06-04 中国科学院微电子研究所 带散热功能的三维堆叠芯片及其制造方法
CN112420640A (zh) * 2020-11-26 2021-02-26 苏州矽锡谷半导体科技有限公司 一种堆叠封装结构及其制备方法

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CN103430301A (zh) * 2011-05-26 2013-12-04 华为技术有限公司 热增强堆叠式封装和方法
CN102522380A (zh) * 2011-12-21 2012-06-27 华为技术有限公司 一种PoP封装结构
CN103839903A (zh) * 2014-03-10 2014-06-04 中国科学院微电子研究所 带散热功能的三维堆叠芯片及其制造方法
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