WO2024027737A1 - Quartz resonator having sandwich structure formed by double base plates and piezoelectric layer, and electronic device - Google Patents

Quartz resonator having sandwich structure formed by double base plates and piezoelectric layer, and electronic device Download PDF

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Publication number
WO2024027737A1
WO2024027737A1 PCT/CN2023/110651 CN2023110651W WO2024027737A1 WO 2024027737 A1 WO2024027737 A1 WO 2024027737A1 CN 2023110651 W CN2023110651 W CN 2023110651W WO 2024027737 A1 WO2024027737 A1 WO 2024027737A1
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Prior art keywords
packaging substrate
electrode
quartz
piezoelectric layer
resonator
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PCT/CN2023/110651
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French (fr)
Chinese (zh)
Inventor
庞慰
张孟伦
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天津大学
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Publication of WO2024027737A1 publication Critical patent/WO2024027737A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/0538Constructional combinations of supports or holders with electromechanical or other electronic elements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/125Driving means, e.g. electrodes, coils
    • H03H9/13Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/19Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator consisting of quartz

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular to a quartz resonator in which a double substrate and a piezoelectric layer form a sandwich structure, and an electronic device.
  • the fundamental frequency of the chip is mainly determined by the thickness of the resonance area of the chip.
  • Wafer-level manufacturing can significantly reduce the manufacturing cost of a single resonator and achieve consistent quality control between resonators; generally speaking, the larger the wafer size, the lower the manufacturing cost of a single resonator.
  • the boundary conditions of the resonator can be optimized and the lateral leakage of acoustic waves can be reduced, thereby further improving the performance of the resonator.
  • the resonator adopts a cantilever beam structure, which reduces the mechanical stability of the resonator.
  • mechanical grinding is used to create the resonance area in the existing technology, which limits the scale of wafer-level manufacturing (it is difficult to achieve more than two inches). wafer manufacturing).
  • a quartz resonator including:
  • a bottom electrode, a top electrode and a quartz piezoelectric layer is an inverted platform structure including a boss;
  • a packaging structure including a first packaging substrate, a second packaging substrate and a bonding sealing layer,
  • the joint sealing layer includes a piezoelectric layer encapsulation part, the piezoelectric layer encapsulation part is a part of the quartz piezoelectric layer, and the piezoelectric layer encapsulation part includes the boss;
  • the first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a sandwich structure including the first packaging substrate, the quartz piezoelectric layer, and the second packaging substrate. .
  • Embodiments of the present invention also relate to a method for manufacturing a quartz resonator, including the steps:
  • Forming a quartz piezoelectric layer on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, and the quartz piezoelectric layer includes:
  • the anti-high platform structure of the boss is suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
  • a first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the boss on both sides of the quartz piezoelectric layer to form a package including the first packaging substrate, quartz A sandwich structure of the piezoelectric layer and the second packaging substrate, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
  • Embodiments of the present invention also relate to an electronic device, including the above-mentioned quartz resonator.
  • FIG. 1-14 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention.
  • Figure 15 is a schematic cross-sectional view of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • 16-35 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to yet another exemplary embodiment of the present invention.
  • 36-38 are schematic cross-sectional views of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • 39-49 are schematic cross-sectional views of the manufacturing process of a quartz resonator structure according to an exemplary embodiment of the present invention.
  • Figure 50 is a schematic flow chart of fundamental frequency adjustment in the resonance area of a quartz wafer
  • Figure 51 is a schematic flowchart of resonant frequency adjustment of a quartz resonator.
  • the present invention proposes a quartz wafer manufacturing process based on micro/nano electromechanical systems (M/NEMS) photolithography technology, which can be used to produce small-sized, frequency-accurate quartz resonators.
  • M/NEMS micro/nano electromechanical systems
  • a wafer-level frequency/thickness monitoring and control method is adopted, which reduces the requirements for the uniformity of quartz wafer thickness processing and reduces the processing difficulty.
  • This program is suitable for the production of quartz wafers in different frequency bands. It is universally applicable and is not limited by the quartz wafer area, which has obvious advantages.
  • a sandwich structure is adopted, which is beneficial to miniaturization and flattening of the resonator.
  • a quartz piezoelectric layer with an anti-platform structure is manufactured on a quartz wafer based on micro/nano electromechanical systems (M/NEMS) photolithography technology, which is beneficial to optimizing the boundary conditions of the quartz resonator and reducing lateral leakage of sound waves. , which is conducive to improving the performance of quartz resonators.
  • M/NEMS micro/nano electromechanical systems
  • the present invention's wafer manufacturing solution based on micro-nano electromechanical systems makes full use of the advantages of MEMS photolithography technology and wafer-level process manufacturing methods, and uses the method of wet etching wafer contours to get rid of the impact of cutting technology on wafer size. Limitation, can realize the processing of smaller size wafers of 1210, 1008 and below.
  • wafer processing solutions for wafer manufacturing can improve dimensional processing accuracy and improve wafer processing efficiency.
  • the present invention proposes a wafer-level wafer manufacturing and frequency control process, which eliminates the need for ultra-high-precision grinding technology for quartz wafers, and at the same time greatly reduces the difficulty of frequency modulation, making frequency modulation completely unconstrained by wafer area expansion.
  • this solution meets the requirements for miniaturized manufacturing of wafers from low frequency to high frequency (30-300MHz) and ultra-high frequency (300MHz-3GHz), and is of great significance to promoting the development of the quartz wafer field.
  • Top electrode the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • the electrical connection part of the top electrode The material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys.
  • the top electrode and its electrical connections, the bottom electrode and its electrical connections may be the same metal material.
  • the material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or Compounds of the above metals or their alloys, etc.
  • Second conductive via hole or second package substrate conductive via hole Second conductive via hole or second package substrate conductive via hole.
  • 72A, 72B Metal bonding layer, which can be gold-gold, gold-tin, copper-tin bonding, etc.
  • 74A, 74B Filling metal layer.
  • the filling metal layer, the external connection part, the top electrode and its electrical connection part, the bottom electrode and its electrical connection part may be the same metal material.
  • each part is described using a feasible material as an example, but is not limited thereto.
  • FIGS. 1-14 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention.
  • the resonant structure of the quartz resonator adopts a single-sided reverse platform structure. Compared with the flat structure of the piezoelectric layer, this structure has better structural stability, improves the impact resistance of the chip, and is also conducive to improving the resonator. boundary conditions to improve the performance of the resonator.
  • Step 1 Make mask 20A.
  • a mask 20 is made on one side (for example, the front side) of a quartz wafer (for example, with a diameter of 1-8 inches and a thickness of 100 ⁇ m to 1 mm) using micro/nano electromechanical system photolithography.
  • the mask 20A is patterned to form mask openings 22. Specifically, the through-hole etching region 14 and the resonant region 12 for preparation are exposed.
  • a mask 20A is also provided on the other side of the quartz wafer 10 (for example, the secondary surface), covering the entire other side.
  • the mask may be a metal mask, such as chromium gold (a layer of gold on the top and a layer of chromium on the bottom), or other Inert metal;
  • the mask can be SU-8 glue, or other photoresists suitable for dry etching.
  • the material of the mask 20A can also be applied to other embodiments, which will not be described again below.
  • FIGS. 1 to 14 only the area corresponding to a single quartz resonator on the wafer is shown. As can be understood, there are multiple quartz resonators on the quartz wafer 10 as shown in FIGS. 1 to 14 Area. In other embodiments, similar understanding should be made, which will not be described again.
  • Step 2 Wet etching.
  • the mask 20A is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
  • a part of the resonance area of the quartz wafer is etched to form an anti-mountain 18 on the periphery of the resonance area to form an anti-mountain structure.
  • Figure 2 shows a single-sided reverse elevated platform structure.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Remove mask 20A. As shown in FIG. 3 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
  • Step 4 Make the top electrode.
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Top electrode 30 covers via etched area 14 .
  • Step 5 Join the first package substrate.
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the first packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the junction between the first packaging substrate 50 and the quartz wafer 10 72A.
  • Step 6 Quartz wafer thinning. As shown in FIG. 6 , the quartz wafer 10 is thinned by grinding and polishing processes until the remaining thickness of the resonance region is within, for example, 1 ⁇ m compared with the design value (ie, the film thickness d 0 mentioned above).
  • Step 7 Wafer-level film thickness measurement.
  • the thickness of the polished quartz wafer in the resonant region was measured using optical methods. The measurement point must be selected in the area with the top electrode on the other side of the quartz film.
  • the optical measurement method of transparent film thickness is used to measure the quartz film thickness in the resonance area of each wafer, and the difference between it and the design value d0 is obtained, which provides a basis for the next step of adjusting the film thickness of each wafer. according to.
  • Step 8 Adjust quartz film thickness. As shown in Figure 8, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 7 and Figure 8 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 50.
  • Step 9 Set a through-hole perforation mask 20B on the upper surface of the structure shown in Figure 8. As shown in Figure 9, the mask 20B is provided with mask openings at positions corresponding to the through-hole etching areas 14.
  • Step 10 For example, dry etching is used to etch the portion of the quartz wafer 10 located at the through-hole etching area 14 to form the through-hole 14 through the through-hole etching area 14, as shown in FIG. 10 .
  • Step 11 Remove mask 20B. After step 10, the mask 20B can be removed by wet etching to obtain the structure as shown in FIG. 11.
  • Step 12 Make the bottom electrode and electrical connections.
  • the resonator bottom electrode 40 and the electrical connection portion 32 are fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • the electrical connection portion 32 is electrically connected to the metal in the via etching area 14, and is disposed on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other.
  • Step 13 Frequency measurement and frequency modulation.
  • the measured resonant frequency f of the quartz resonator is smaller than the predetermined resonant frequency f 0 .
  • the quality of the top electrode 30 can be changed by using a particle beam to improve the quartz resonator.
  • the resonant frequency of the resonator when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 41.
  • Step 14 Bond the second package substrate.
  • the second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the second package substrate 60 is provided with a second conductive via 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • FIG. 15 is a schematic cross-sectional view of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • the structure shown in FIG. 15 differs from the structure shown in FIG. 14 only in the position of the second conductive via hole 64, and other structures will not be described again.
  • the second conductive via 64 is aligned with the via etching area 14
  • the second conductive via 64 is offset from the via etching area 14 .
  • Such misaligned packaging helps to improve the stability of the structure and reduce air-tightness damage caused by through-hole damage caused by stress, mechanical deformation and other issues.
  • through-hole dislocation can shield to a certain extent the noise caused by interference such as stress, heat, and electromagnetic signals transmitted through the through-holes.
  • a segmentation operation can be performed to form the final packaged quartz resonator into individual devices.
  • the size of the finally formed quartz piezoelectric layer is less than 1 mm ⁇ 1 mm, and/or the thickness of the resonance region of the quartz piezoelectric layer is less than 40 ⁇ m or the fundamental frequency of the quartz resonator is above 40 MHz. This also applies to other embodiments of the invention.
  • the packaging substrate may be a quartz substrate or a substrate made of other materials, such as silicon, glass, sapphire, etc. No further details will be given in the following embodiments.
  • the packaging substrate when it is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • the package cover is made of transparent material. Therefore, frequency modulation can also occur after the packaging is completed, using laser to directly adjust the frequency through the transparent quartz packaging cover to adjust the frequency changes caused by packaging stress. No further details will be given in the following embodiments.
  • FIGS. 16 to 35 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to yet another exemplary embodiment of the present invention.
  • the resonant structure of the quartz resonator adopts a double-sided reverse platform structure.
  • this structure has better structural stability, improves the impact resistance of the chip, and can further Improve the boundary conditions of the resonance area of the chip and reduce the lateral leakage of sound waves, thereby improving the performance of the resonator;
  • the double-sided anti-elevation structure provides space for the vibration area, which can avoid digging grooves in the package cover and contribute to the thinness of the chip. change.
  • Step 1 Make mask 20A.
  • a mask 20A is made on one side (eg, the front) of a quartz wafer (eg, 1-8 inches in diameter, 100 ⁇ m to 1 mm in thickness) using micro/nano electromechanical system photolithography.
  • Mask 20A is patterned to form mask openings 22 and the area of resonant region 12 is covered.
  • a mask 20A is also provided on the other side (for example, the secondary surface) of the quartz wafer 10, covering the entire the other side.
  • Step 2 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Further pattern the mask 20A to expose the resonant region, as shown in Figure 18.
  • Step 4 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching In Figure 19, a part of the resonance area of the quartz wafer is etched, and at the same time, the through hole etching area 14 is further etched. In this way, in Figure 19, the depth of the through hole etching area 14 is greater than the etching depth of the resonance area. .
  • step 4 may also be replaced by dry etching, or wet etching may be combined with dry etching.
  • Step 5 Remove mask 20A. As shown in FIG. 20 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
  • Step 6 Make the top electrode.
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Top electrode 30 covers via etched area 14 .
  • Step 7 Join the first package substrate.
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
  • Step 8 Quartz wafer thinning. As shown in FIG. 23 , the quartz wafer 10 is thinned by grinding and polishing processes.
  • Step 9 Make mask 20B.
  • a mask 20B is fabricated using micro/nano electromechanical system photolithography on the structure shown in FIG. 23 , and is patterned to form mask openings 22 and expose the resonant region.
  • the material of mask 20B may be consistent with that of mask 20A.
  • Step 10 Wet etching.
  • the mask 20B in Figure 24 is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to The quartz wafer 10 described above is etched.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • a double-sided reverse mesa structure is formed, and a through-hole etching area 14' opposite to the through-hole etching area 14 on one side is also formed on the other side of the quartz wafer 10, as shown in Figure 25.
  • the etching depth of the via etching region 14 ′ is consistent with the etching depth of the resonance region on the other side of the quartz wafer 10 .
  • the etching depth between the via etching region 14 ′ and the via Part of the quartz piezoelectric layer remains between the hole etching areas 14 .
  • step 10 may also be replaced by dry etching, or wet etching may be combined with dry etching.
  • Step 11 Remove mask 20B. As shown in FIG. 26 , the structure shown in FIG. 25 can be cleaned, dried, and then the mask 20B is removed by wet etching.
  • Step 12 Wafer-level film thickness measurement.
  • the optical method was used to measure the thickness of quartz in the resonance area after grinding. The measurement point must be selected in the area with the top electrode on the other side of the quartz film. As shown in Figure 27, the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 13 Adjust quartz film thickness. As shown in Figure 28, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 27 and Figure 28 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 50.
  • Step 14 Make the bottom electrode.
  • the resonator bottom electrode 40 is formed on the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 15 Make mask 20C.
  • a mask 20C is fabricated using micro/nano electromechanical system photolithography on the structure shown in FIG. 29 , and is patterned to form mask openings 22 , which are exposed. Excluding the via etching area 14' etched in step 10, the mask 20C covers the bottom electrode 40.
  • the material of mask 20E may be consistent with that of mask 20 .
  • Step 16 For example, dry etching is used to etch the portion of the quartz wafer 10 located at the through-hole etching area 14' to penetrate the through-hole etching area 14', as shown in Figure 31.
  • Step 17 Remove mask 20C. As shown in FIG. 32 , the structure shown in FIG. 31 can be cleaned, dried, and then the mask 20C is removed by wet etching.
  • Step 18 Make the electrical connection part 32.
  • the electrical connection portion 32 is formed on the quartz wafer 10 by metal sputtering or evaporation.
  • the electrical connection portion 32 is electrically connected to the metal in the via etching area 14, and is disposed on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other.
  • Step 19 Frequency measurement and frequency modulation.
  • the measured resonant frequency f of the quartz resonator is smaller than the predetermined resonant frequency f 0 .
  • the quality of the top electrode 30 can be changed by using a particle beam to improve the quartz resonator.
  • the resonant frequency of the resonator when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 51.
  • Step 20 Bond the second package substrate.
  • the second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the second packaging substrate 60 is provided with a second conductive via 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • a segmentation operation may be performed to form the final packaged quartz resonator into individual devices.
  • FIGS. 36-38 are schematic cross-sectional views of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • the structure shown in Figures 36-38 is different from the structure shown in Figure 35 only in the position or structure of the second conductive via hole 64, and other structures will not be described again.
  • the second conductive via 64 is offset from the via 14 .
  • This misaligned packaging helps Improve the stability of the structure and reduce air tightness damage caused by through-hole damage caused by stress, mechanical deformation and other issues.
  • through-hole dislocation can shield to a certain extent the noise caused by interference such as stress, heat, and electromagnetic signals transmitted through the through-holes.
  • the structure shown in Figure 37 improves the through hole manufacturing process and changes the cross-sectional shape of the through hole to a vertical type, thereby improving the air tightness of the through hole.
  • changing the package bottom plate to a flat plate helps reduce the total thickness of the chip and improves the mechanical stability of the resonance area.
  • 39-49 are schematic cross-sectional views of a manufacturing process of a quartz resonator structure according to yet another exemplary embodiment of the present invention.
  • Step 1 Make mask 20.
  • a mask 20 is made on one side (for example, the front) of a quartz wafer (for example, 1-8 inches in diameter and 100 ⁇ m to 1 mm in thickness) using micro/nano electromechanical system photolithography.
  • Mask 20 is patterned to form a frame mask, and areas of resonant region 12 are exposed.
  • a mask 20 is also provided on the other side of the quartz wafer 10 (for example, the secondary surface).
  • the mask 20 is patterned to form a frame mask, and the resonant region 12 is exposed.
  • Step 2 Wet etching.
  • the mask 20 is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching for example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • the portions corresponding to the resonance region on both sides of the quartz wafer 10 are etched.
  • Step 3 Remove mask 20. As shown in FIG. 41 , after the quartz wafer 10 is etched, the mask 20 can be removed by cleaning, drying, and then wet etching.
  • Step 4 Make the top electrode.
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 5 Wafer-level film thickness measurement.
  • the quartz thickness in the resonance area is measured using optical methods. The measurement point must be selected in the area with the top electrode on the other side of the quartz film.
  • the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 6 Adjust quartz film thickness. As shown in Figure 44, using ion beam etching or wet etching The quartz plate in the resonance area of the wafer is etched twice. Repeat the operations in Figure 43 and Figure 44 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 50.
  • Step 7 Make the bottom electrode.
  • the resonator bottom electrode 40 is fabricated on the quartz wafer 10 shown in step 6 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 8 Join the first package substrate.
  • the quartz wafer 10 in step 7 and the quartz wafer or the first packaging substrate 50 are bonded together using metal diffusion bonding, which can be gold-gold, gold-tin, copper-tin bonding, etc. .
  • the quartz wafer 10 and the quartz wafer or the first packaging substrate 50 can also be joined together in other ways, which are not limited here.
  • the packaging substrate 50 may also use other packaging materials.
  • the first package substrate 50 is provided with a first conductive via hole 54 in advance, and the first conductive via hole is electrically connected to the corresponding electrode lead-out part.
  • the first packaging substrate 50 may be a quartz substrate, and its thickness may be 20-200 ⁇ m, and may be prepared from a quartz wafer that is exactly the same size and specification as the resonator wafer.
  • a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
  • a filling metal layer 74A is provided between the first packaging substrate 50 and the quartz wafer 10 and spaced apart from the outer side of the metal bonding layer 72A.
  • the filling metal layer 74A only needs to be provided on the side where the external connection is provided in the subsequent step 11.
  • metal bonding layer 72A is spaced apart from fill metal layer 74A by a distance in the range of 2-200 microns.
  • Step 9 Frequency measurement and frequency modulation.
  • the quality of the top electrode 30 can be changed using, for example, a particle beam to improve the corresponding quartz resonator. the resonant frequency.
  • the frequency modulation step does not need to be performed. This process can be seen in Figure 51.
  • Step 10 Bond the second package substrate.
  • the structure in step 9 and the second packaging substrate or packaging quartz wafer 60 are bonded together using metal diffusion bonding, which can be gold-gold, gold-tin, copper-tin bonding, etc.
  • metal diffusion bonding can be gold-gold, gold-tin, copper-tin bonding, etc.
  • the quartz wafer 10 and the second packaging substrate or the packaging quartz wafer 60 can also be joined together in other ways, which are not limited here.
  • the second packaging substrate or packaging quartz crystal Circle 60 can also use other packaging materials.
  • the second package substrate 60 is provided with a second conductive via hole 64 in advance, and the second conductive via hole is electrically connected to the corresponding electrode lead-out part.
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • a filling metal layer 74B is provided between the second packaging substrate 60 and the quartz wafer 10 and spaced apart from the outer side of the metal bonding layer 72B.
  • the filling metal layer 74B only needs to be provided on the side where the external connection is provided in the subsequent step 11.
  • metal bonding layer 72B is spaced apart from fill metal layer 74B by a distance in the range of 2-200 microns.
  • a splitting operation may be performed to form a plurality of packaging particles, that is, at least the quartz wafer is cut or split to form a plurality of mechanically separated independent sandwich resonant structures.
  • the sandwich structure includes the first packaging substrate 50, the quartz crystal. Circle 10 or quartz piezoelectric layer and second packaging substrate 60 .
  • Step 11 Shot electroplating to form the external connection portion 70: As shown in Figure 49, the external connection portion 70 is electrically connected to the second conductive via 64 on the side of the first package substrate 50 away from the top electrode and extends through the sandwich structure. The end surface extends to the side of the second package substrate 60 away from the bottom electrode.
  • the packaging substrate may also be pre-set with a cavity, so that when the packaging substrate faces the corresponding electrode and is bonded to the quartz wafer, the electrode is connected to the quartz wafer.
  • the cavities are opposite.
  • the present invention also proposes a method for manufacturing a quartz resonator, including the steps:
  • Forming a quartz piezoelectric layer on a quartz wafer 10 includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, where the quartz piezoelectric layer is An inverse platform structure including a boss, suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
  • a first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a structure including the first packaging substrate, the quartz piezoelectric layer, and the quartz piezoelectric layer.
  • Dividing After forming the sandwich structure, at least the sandwich structure is cut or split to form a plurality of mechanically separated sandwich structure particles.
  • micro/nano electromechanical systems (M/NEMS) photolithography technology is used in combination with wet etching/dry etching to: make the size of the particles less than 1 mm ⁇ 1 mm; and/or The thickness of the resonant region of the shot particles is less than 40 ⁇ m or the fundamental frequency of the resonator formed based on the shot particles is above 40 MHz.
  • M/NEMS micro/nano electromechanical systems
  • micro/nano electromechanical system photolithography technology it is possible to obtain fine patterns for subsequent etching that facilitate the formation of particle sizes less than 1 mm ⁇ 1 mm, while based on wet etching/dry etching, it is possible to Obtain particles with a size less than 1mm ⁇ 1mm; based on wet etching/dry etching, it can replace the mechanical mask to obtain a quartz piezoelectric layer thickness less than 40 ⁇ m.
  • At least part of the electrical connection through hole or through hole 14 is a tapered hole, or more specifically, the cross section of the electrical connection through hole is a shape that shrinks from the upper and lower sides of the boss to the middle, which is beneficial to forming An electrical connection with good conductivity and stable resistance.
  • the resonant region refers to the overlapping region of the top electrode, bottom electrode, piezoelectric layer, and cavity or gap in the thickness direction of the piezoelectric layer in the formed quartz resonator.
  • the resonance area of the wafer corresponds to the area in the wafer that needs to be formed as a resonance area of the resonator;
  • the resonance area of the piezoelectric layer corresponds to the area in the piezoelectric layer that needs to be formed as the resonance area of the resonator.
  • the non-resonant region is a portion outside the resonant region.
  • the non-resonant region of the piezoelectric layer refers to the region outside the resonant region of the piezoelectric layer in the horizontal or lateral direction.
  • each numerical range except that it is clearly stated that it does not include the endpoint value, can be the endpoint value or the median value of each numerical range, which are all within the protection scope of the present invention. .
  • the quartz resonator according to the present invention can be used to form a quartz crystal oscillator chip or an electronic device including a quartz resonator.
  • the electronic device here may be an electronic component such as an oscillator, a communication device such as a walkie-talkie or a mobile phone, or a large-scale product using a quartz resonator such as an automobile.
  • a quartz resonator including:
  • a bottom electrode, a top electrode and a quartz piezoelectric layer is an inverted platform structure including a boss;
  • a packaging structure including a first packaging substrate, a second packaging substrate and a bonding sealing layer,
  • the joint sealing layer includes a piezoelectric layer encapsulation part, the piezoelectric layer encapsulation part is a part of the quartz piezoelectric layer, and the piezoelectric layer encapsulation part includes the boss;
  • the first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a sandwich structure including the first packaging substrate, the quartz piezoelectric layer, and the second packaging substrate. .
  • the quartz piezoelectric layer has a single-sided reverse platform structure.
  • the quartz piezoelectric layer has a double-sided reverse platform structure.
  • Both the first packaging substrate and the second packaging substrate are quartz substrates.
  • the size of the quartz piezoelectric layer is less than 1mm ⁇ 1mm; and/or
  • the thickness of the resonant region of the quartz piezoelectric layer is less than 40 ⁇ m or the fundamental frequency of the resonator is above 40 MHz.
  • the side of the first packaging substrate and the second packaging substrate facing the boss is a flat surface.
  • a cavity is provided on a side of the first packaging substrate and/or the second packaging substrate facing the quartz piezoelectric layer, and the projection of the resonance area of the quartz resonator in the thickness direction falls into the cavity.
  • One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
  • the quartz piezoelectric layer is provided with an electrical connection through hole in the non-resonant region, and the electrode lead-out portion of the first electrode extends to the other side of the quartz piezoelectric layer through the electrical connection through hole to connect with the third electrode.
  • the two electrodes are located on the same side of the quartz piezoelectric layer.
  • the substrate in the first packaging substrate and the second packaging substrate on the other side of the quartz piezoelectric layer is provided with Substrate conductive vias;
  • the substrate conductive via hole is electrically connected to a portion of the electrode lead-out portion of the first electrode extending to the other side of the quartz piezoelectric layer via the electrical connection via hole.
  • the substrate conductive through holes and the electrical connection through holes are staggered in the horizontal direction; or
  • the substrate conductive via hole and the electrical connection via hole are aligned in the thickness direction.
  • the substrate conductive through holes are straight holes, tapered holes, or holes with upper and lower sides narrowing toward the middle.
  • One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
  • the first packaging substrate is opposite to the first electrode, and the second packaging substrate is opposite to the second electrode;
  • the first packaging substrate is provided with a first packaging substrate conductive through hole, and the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode;
  • the second packaging substrate is provided with a second packaging substrate conductive through hole, and the second packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the second electrode;
  • the resonator further includes an external connection portion, which is electrically connected to the conductive via hole of the first packaging substrate on a side of the first packaging substrate away from the first electrode and extends through the end surface of the sandwich structure of the resonator. and extends to the side of the second packaging substrate away from the second electrode, or the external connection portion is electrically connected to the second packaging substrate conductive via hole on the side of the second packaging substrate away from the second electrode and extends through the The end surface of the sandwich structure of the resonator extends to a side of the first packaging substrate away from the first electrode.
  • the first packaging substrate and the second packaging substrate are respectively bonded to the piezoelectric layer packaging part on both sides of the quartz piezoelectric layer based on a metal bonding layer;
  • the resonator further includes a filling metal layer outside the metal bonding layer and separated from the metal bonding layer.
  • the filling metal layer is connected to the external connection part.
  • the metal bonding layer The layer is spaced apart from the fill metal layer by a distance in the range of 2-200 microns.
  • An electronic device including the quartz resonator according to any one of 1-13.
  • a method of manufacturing a quartz resonator including the steps:
  • Forming a quartz piezoelectric layer on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, and the quartz piezoelectric layer includes:
  • the anti-high platform structure of the boss is suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
  • a first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the boss on both sides of the quartz piezoelectric layer to form a package including the first packaging substrate, quartz A sandwich structure of the piezoelectric layer and the second packaging substrate, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
  • Dividing After forming the sandwich structure, at least the sandwich structure is cut or split to form a plurality of mechanically separated sandwich structure particles.
  • One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
  • the step of forming a quartz piezoelectric layer using a quartz wafer further includes: providing an electrical connection via hole in a non-resonant region of the quartz piezoelectric layer, and the electrode lead-out portion of the first electrode is adapted to extend through the electrical connection via hole. to the other side of the quartz piezoelectric layer so as to be on the same side of the quartz piezoelectric layer as the second electrode;
  • the method further includes the step of: arranging a substrate conductive via hole in the second packaging substrate, and the substrate conductive via hole and the electrode lead-out portion of the first electrode extend to the quartz piezoelectric layer through the electrical connection via hole.
  • the other side is partially electrically connected.
  • the first packaging substrate is provided with a first packaging substrate conductive through hole, the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode, and the The two packaging substrates are provided with a second packaging substrate conductive through hole, and the second packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the second electrode;
  • the method further includes the step of: providing an external connection part to the sandwich structure shot to form an independent quartz resonator, wherein: the external connection part is electrically conductive with the first packaging substrate on a side of the first packaging substrate away from the first electrode.
  • the through hole is electrically connected and extends through the end surface of the sandwich structure of the resonator to a side of the second packaging substrate away from the second electrode, or the external connection portion is on a side of the second packaging substrate away from the second electrode.
  • the side is electrically connected to the conductive via hole of the second packaging substrate and extends through the end surface of the sandwich structure of the resonator to a side of the first packaging substrate away from the first electrode.
  • the step of providing the external connection part includes: forming the external connection part by metal sputtering or evaporation.
  • the first packaging substrate and the second packaging substrate are respectively joined to the boss in a metal bonding manner on both sides of the quartz piezoelectric layer to form a package including a first packaging substrate, a quartz piezoelectric layer, a third Sandwich structure of two packaging substrates;
  • the method further includes the steps of: arranging a filling metal layer spaced apart from the bonding layer outside the bonding layer formed by metal bonding; and
  • the external connection portion is in contact with the filling metal layer to facilitate planarization of the external connection portion at the end face of the sandwich structure.

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Abstract

The present invention relates to a quartz resonator, comprising a bottom electrode, a top electrode and a quartz piezoelectric layer, the quartz piezoelectric layer having an inverted highly-protruded structure comprising bosses; a packaging structure, comprising a first packaging substrate, a second packaging substrate and a bonding sealing layer, the bonding sealing layer comprising a piezoelectric layer packaging portion, the piezoelectric layer packaging portion being a part of the quartz piezoelectric layer, and the piezoelectric layer packaging portion comprising the bosses. The first packaging substrate and the second packaging substrate are respectively bonded to the bosses on the two sides of the quartz piezoelectric layer so as to form a sandwich structure comprising the first packaging substrate, the quartz piezoelectric layer and the second packaging substrate. The present invention also relates to an electronic device.

Description

双基板和压电层形成三明治结构的石英谐振器及电子器件Quartz resonators and electronic devices with a sandwich structure formed by double substrates and piezoelectric layers 技术领域Technical field
本发明的实施例涉及半导体领域,尤其涉及一种双基板和压电层形成三明治结构的石英谐振器,以及一种电子器件。Embodiments of the present invention relate to the field of semiconductors, and in particular to a quartz resonator in which a double substrate and a piezoelectric layer form a sandwich structure, and an electronic device.
背景技术Background technique
高基频、小型化和低矮化是石英晶振片(下文中简称为晶片)发展的趋势。传统晶片制造方案多采用研磨切片的方式获得一定频率的散粒薄片,然后进行后续的镀电极与调频。然而,切片所采用的线切割技术对1mm×1mm及以下尺寸难以实现,基本无法覆盖1.2mm×1.0mm及以下尺寸的晶片制造,更无法满足1.0mm×0.8mm及以下尺寸规格晶片制造。晶片的基频主要受晶片谐振区域的厚度决定,晶片的基频由以下公式支配:
f0(MHz)=1670(MHz·μm)/d(μm)      (1)
High fundamental frequency, miniaturization and low profile are the development trends of quartz crystal oscillators (hereinafter referred to as wafers). Traditional wafer manufacturing solutions mostly use grinding and slicing to obtain granular flakes of a certain frequency, and then perform subsequent electrode plating and frequency modulation. However, the wire cutting technology used in slicing is difficult to achieve for sizes of 1mm×1mm and below. It is basically unable to cover the manufacturing of wafers with sizes of 1.2mm×1.0mm and below, and it cannot meet the manufacturing requirements for wafers with sizes of 1.0mm×0.8mm and below. The fundamental frequency of the chip is mainly determined by the thickness of the resonance area of the chip. The fundamental frequency of the chip is governed by the following formula:
f 0 (MHz)=1670(MHz·μm)/d(μm) (1)
晶圆级制造可以实现单颗谐振器制造成本的大幅降低,以及谐振器之间的品控一致性;通常来说,晶圆尺寸越大,单颗谐振器的制造成本越低。Wafer-level manufacturing can significantly reduce the manufacturing cost of a single resonator and achieve consistent quality control between resonators; generally speaking, the larger the wafer size, the lower the manufacturing cost of a single resonator.
然而,对于晶圆级制造方案,几百至数千颗晶片排列在单片晶圆上,对各个位置点石英厚度的精确控制挑战巨大,这也就直接导致了整片晶圆上晶片频率的准确性与一致性难以得到保证。因此,晶圆级晶片调频存在极大的挑战。目前已有技术采取的办法主要集中在采用具有超高精度膜厚监控系统的研磨技术,制备厚度均一度在几纳米之内的石英薄膜。这种频率控制与调节技术对材料和制造工艺提出了极高的要求,而且晶圆面积越大,制造难度越高,阻碍了 低成本、高效率的制造方案的产生。However, for wafer-level manufacturing solutions, where hundreds to thousands of wafers are arranged on a single wafer, precise control of the quartz thickness at each location is a huge challenge, which directly leads to changes in the frequency of the wafers on the entire wafer. Accuracy and consistency cannot be guaranteed. Therefore, there are great challenges in wafer-level chip frequency modulation. The current methods adopted by existing technologies mainly focus on using grinding technology with ultra-high-precision film thickness monitoring systems to prepare quartz films with a thickness uniformity within a few nanometers. This frequency control and adjustment technology places extremely high requirements on materials and manufacturing processes. The larger the wafer area, the higher the manufacturing difficulty, which hinders The generation of low-cost, high-efficiency manufacturing solutions.
此外,还希望在晶圆级制造单颗谐振器的基础上,优化谐振器的边界条件、减少声波横向泄漏,从而进一步提高谐振器的性能。但是,通过现有的机械研磨减薄方式难以优化谐振器的边界条件。In addition, it is also hoped that on the basis of manufacturing a single resonator at the wafer level, the boundary conditions of the resonator can be optimized and the lateral leakage of acoustic waves can be reduced, thereby further improving the performance of the resonator. However, it is difficult to optimize the boundary conditions of the resonator through the existing mechanical grinding thinning method.
现有三明治结构中,谐振器采用悬臂梁式结构,谐振器的机械稳定性降低,且现有技术中采用机械研磨方式制造谐振区域,限制了晶圆级制造的规模(难以实现两英寸以上的晶圆制造)。In the existing sandwich structure, the resonator adopts a cantilever beam structure, which reduces the mechanical stability of the resonator. In addition, mechanical grinding is used to create the resonance area in the existing technology, which limits the scale of wafer-level manufacturing (it is difficult to achieve more than two inches). wafer manufacturing).
发明内容Contents of the invention
为缓解或解决现有技术中的上述问题的至少一个方面,提出本发明。In order to alleviate or solve at least one aspect of the above-mentioned problems in the prior art, the present invention is proposed.
根据本发明的实施例的一个方面,提出了一种石英谐振器,包括:According to an aspect of an embodiment of the present invention, a quartz resonator is proposed, including:
底电极,顶电极和石英压电层,所述石英压电层为包括凸台的反高台结构;A bottom electrode, a top electrode and a quartz piezoelectric layer. The quartz piezoelectric layer is an inverted platform structure including a boss;
封装结构,包括第一封装基板、第二封装基板和接合密封层,a packaging structure, including a first packaging substrate, a second packaging substrate and a bonding sealing layer,
其中:in:
所述接合密封层包括压电层封装部,所述压电层封装部为石英压电层的一部分,所述压电层封装部包括所述凸台;The joint sealing layer includes a piezoelectric layer encapsulation part, the piezoelectric layer encapsulation part is a part of the quartz piezoelectric layer, and the piezoelectric layer encapsulation part includes the boss;
所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构。The first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a sandwich structure including the first packaging substrate, the quartz piezoelectric layer, and the second packaging substrate. .
本发明的实施例还涉及一种石英谐振器的制造方法,包括步骤:Embodiments of the present invention also relate to a method for manufacturing a quartz resonator, including the steps:
提供石英晶圆;Provide quartz wafers;
以石英晶圆形成石英压电层,包括步骤:至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层,所述石英压电层为包括凸台的反高台结构,在石英压电层的两侧适于设置包括第一电极的第一电极层和包括第二电极的第二电极层;Forming a quartz piezoelectric layer on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, and the quartz piezoelectric layer includes: The anti-high platform structure of the boss is suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
提供第一封装基板和第二封装基板,所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构,第一封装基板与第一电极层相对,第二封装基板与第二电极层相对;和A first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the boss on both sides of the quartz piezoelectric layer to form a package including the first packaging substrate, quartz A sandwich structure of the piezoelectric layer and the second packaging substrate, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
分割:形成所述三明治结构之后,至少将所述三明治结构切割或者裂片, 以形成机械分离的多个三明治结构散粒。Divide: after forming the sandwich structure, at least cut or split the sandwich structure, To form multiple mechanically separated sandwich structure particles.
本发明的实施例还涉及一种电子器件,包括上述的石英谐振器。Embodiments of the present invention also relate to an electronic device, including the above-mentioned quartz resonator.
附图说明Description of the drawings
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点,图中相同的附图标记始终表示相同的部件,其中:These and other features and advantages of various disclosed embodiments of the present invention may be better aided in understanding by the following description and accompanying drawings, in which like reference numerals refer to like parts throughout, wherein:
图1-14为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图;1-14 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention;
图15为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图;Figure 15 is a schematic cross-sectional view of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention;
图16-35为根据本发明的又一个示例性实施例的石英谐振器的制作过程的截面示意图;16-35 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to yet another exemplary embodiment of the present invention;
图36-38为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图;36-38 are schematic cross-sectional views of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention;
图39-图49为根据本发明的一个示例性实施例的石英谐振器结构的制作过程的截面示意图;39-49 are schematic cross-sectional views of the manufacturing process of a quartz resonator structure according to an exemplary embodiment of the present invention;
图50为石英晶圆的谐振区域的基频调节的流程示意图;Figure 50 is a schematic flow chart of fundamental frequency adjustment in the resonance area of a quartz wafer;
图51为石英谐振器的谐振频率调节的流程示意图。Figure 51 is a schematic flowchart of resonant frequency adjustment of a quartz resonator.
具体实施方式Detailed ways
下面通过实施例,并结合附图,对本发明的技术方案作进一步具体的说明。在说明书中,相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释,而不应当理解为对本发明的一种限制。发明的一部分实施例,而并不是全部的实施例。基于本发明中的实施例,本领域普通技术人员所获得的所有其他实施例,都属于本发明保护的范围。The technical solution of the present invention will be further described in detail below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numbers indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the general inventive concept of the present invention and should not be understood as a limitation of the present invention. Some, but not all, embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art fall within the scope of protection of the present invention.
本发明提出一种基于微/纳机电系统(M/NEMS)光刻技术的石英晶片制造工艺,可以用于制作小尺寸、频率精准的石英谐振器。The present invention proposes a quartz wafer manufacturing process based on micro/nano electromechanical systems (M/NEMS) photolithography technology, which can be used to produce small-sized, frequency-accurate quartz resonators.
本发明中,采用了晶圆级频率/厚度监测与调控方法,降低了对石英晶圆片厚度加工均一度的要求,降低了加工难度。本方案对不同频段的石英晶片的制 造普遍适用,并且不受石英晶圆面积的限制,具有明显的优势。In the present invention, a wafer-level frequency/thickness monitoring and control method is adopted, which reduces the requirements for the uniformity of quartz wafer thickness processing and reduces the processing difficulty. This program is suitable for the production of quartz wafers in different frequency bands. It is universally applicable and is not limited by the quartz wafer area, which has obvious advantages.
在本发明中,采用了三明治结构,这有利于实现谐振器的小型化和扁平化。In the present invention, a sandwich structure is adopted, which is beneficial to miniaturization and flattening of the resonator.
在本发明中,在石英晶圆上基于微/纳机电系统(M/NEMS)光刻技术制造具有反高台结构的石英压电层,从而有利于优化石英谐振器的边界条件、减少声波横向泄漏,有利于提升石英谐振器的性能。In the present invention, a quartz piezoelectric layer with an anti-platform structure is manufactured on a quartz wafer based on micro/nano electromechanical systems (M/NEMS) photolithography technology, which is beneficial to optimizing the boundary conditions of the quartz resonator and reducing lateral leakage of sound waves. , which is conducive to improving the performance of quartz resonators.
本发明基于微纳机电系统(M/NEMS)的晶片制造方案充分利用了MEMS光刻技术和晶圆级工艺制造方式的优势,利用湿法刻蚀晶片轮廓的方法,摆脱了切割技术对晶片尺寸的限制,可以实现1210、1008及以下更小尺寸晶片的加工。此外,晶圆制造的晶片加工方案能够提高尺寸加工精度,提高晶片加工效率。The present invention's wafer manufacturing solution based on micro-nano electromechanical systems (M/NEMS) makes full use of the advantages of MEMS photolithography technology and wafer-level process manufacturing methods, and uses the method of wet etching wafer contours to get rid of the impact of cutting technology on wafer size. Limitation, can realize the processing of smaller size wafers of 1210, 1008 and below. In addition, wafer processing solutions for wafer manufacturing can improve dimensional processing accuracy and improve wafer processing efficiency.
本发明提出了一种晶圆级晶片制造与频率控制制程,摆脱了石英晶片对超高精度研磨技术的需求,同时大大降低了调频的难度,使得调频完全不受晶圆面积扩大的制约。同时,该方案满足了从低频到高频(30-300MHz)、超高频率(300MHz-3GHz)晶片的小型化制造,对推动石英晶片领域的发展具有重要意义。The present invention proposes a wafer-level wafer manufacturing and frequency control process, which eliminates the need for ultra-high-precision grinding technology for quartz wafers, and at the same time greatly reduces the difficulty of frequency modulation, making frequency modulation completely unconstrained by wafer area expansion. At the same time, this solution meets the requirements for miniaturized manufacturing of wafers from low frequency to high frequency (30-300MHz) and ultra-high frequency (300MHz-3GHz), and is of great significance to promoting the development of the quartz wafer field.
下面参照图1-51示例性说明根据本发明的石英谐振器的制作过程。本发明中,附图标记示意性说明如下:The manufacturing process of the quartz resonator according to the present invention is illustrated below with reference to FIGS. 1-51. In the present invention, the reference signs are schematically explained as follows:
10:石英晶圆或晶圆。10: Quartz wafer or wafer.
12:谐振区域。12: Resonance area.
14:通孔刻蚀区或通孔。14: Through hole etching area or through hole.
14’:通孔刻蚀区。14’: Through hole etching area.
16:压电层封装部。16: Piezoelectric layer encapsulation department.
18:反高台。18: Anti-high platform.
20、20A、20B、20C:掩膜层或掩膜。20, 20A, 20B, 20C: mask layer or mask.
22:掩膜槽或掩膜开孔。22: Mask slot or mask opening.
30:顶电极,材料可选钼、钌、金、铝、镁、钨、铜,钛、铱、锇、铬或以上金属的复合或其合金等。30: Top electrode, the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
32:顶电极的电连接部,材料可选钼、钌、金、铝、镁、钨、铜,钛、铱、锇、铬或以上金属的复合或其合金等。在可选的实施例中,顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。32: The electrical connection part of the top electrode. The material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys. In alternative embodiments, the top electrode and its electrical connections, the bottom electrode and its electrical connections may be the same metal material.
40:底电极,材料可选钼、钌、金、铝、镁、钨、铜,钛、铱、锇、铬或 以上金属的复合或其合金等。40: Bottom electrode, the material can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or Compounds of the above metals or their alloys, etc.
50:第一封装基板或第一封装石英晶圆。50: First packaging substrate or first packaging quartz wafer.
52:第一空腔。52: First cavity.
54:第一导电通孔或第一封装基板导电通孔。54: First conductive via hole or first package substrate conductive via hole.
60:第二封装基板或第二封装石英晶圆。60: Second packaging substrate or second packaging quartz wafer.
62:第二空腔。62: Second cavity.
64:第二导电通孔或第二封装基板导电通孔。64: Second conductive via hole or second package substrate conductive via hole.
72A、72B:金属键合层,可以是金金、金锡、铜锡键合等方式。72A, 72B: Metal bonding layer, which can be gold-gold, gold-tin, copper-tin bonding, etc.
74A、74B:填充金属层,在可选的实施例中,填充金属层、外连接部、顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。74A, 74B: Filling metal layer. In an optional embodiment, the filling metal layer, the external connection part, the top electrode and its electrical connection part, the bottom electrode and its electrical connection part may be the same metal material.
在本发明的具体实施例中,各部分以其中可行的一种材料为例进行说明,但不限于此。In the specific embodiments of the present invention, each part is described using a feasible material as an example, but is not limited thereto.
图1-图14为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图。本实施例中石英谐振器的谐振结构利用采用单面反高台的结构,该结构相比于压电层为平坦结构具有更好结构稳定性,提高了晶片抗冲击能力,也有利于提高谐振器的边界条件从而提升谐振器的性能。1-14 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention. In this embodiment, the resonant structure of the quartz resonator adopts a single-sided reverse platform structure. Compared with the flat structure of the piezoelectric layer, this structure has better structural stability, improves the impact resistance of the chip, and is also conducive to improving the resonator. boundary conditions to improve the performance of the resonator.
下面参照图1-图14示例性说明石英谐振器的制作过程,其包括步骤如下:The following is an example of the manufacturing process of a quartz resonator with reference to Figures 1-14, which includes the following steps:
步骤1:制作掩膜20A。如图1所示,在石英晶圆(例如直径为1-8英寸,厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20,处于正面的掩膜20A被图案化,以形成掩膜开孔22,具体的,用于制备的通孔刻蚀区14以及谐振区域12的区域被露出。在石英晶圆10的另一侧(例如次面)也设置掩膜20A,其覆盖整个另一侧。Step 1: Make mask 20A. As shown in FIG. 1 , a mask 20 is made on one side (for example, the front side) of a quartz wafer (for example, with a diameter of 1-8 inches and a thickness of 100 μm to 1 mm) using micro/nano electromechanical system photolithography. The mask 20A is patterned to form mask openings 22. Specifically, the through-hole etching region 14 and the resonant region 12 for preparation are exposed. A mask 20A is also provided on the other side of the quartz wafer 10 (for example, the secondary surface), covering the entire other side.
这里,对于后续使用湿法刻蚀(例如图1-图14所示实施例的步骤2),掩膜可以是金属掩膜,例如铬金(上面一层金、下面一层铬),或者其他惰性金属;对于后续使用干法刻蚀(例如图1-图14所示实施例的步骤2),掩膜可以是SU-8胶,或者其他适合干法刻蚀的光刻胶。掩膜20A的材料也可以适用于其他实施例,后面不再赘述。Here, for the subsequent use of wet etching (for example, step 2 of the embodiment shown in FIGS. 1 to 14 ), the mask may be a metal mask, such as chromium gold (a layer of gold on the top and a layer of chromium on the bottom), or other Inert metal; for subsequent use of dry etching (for example, step 2 of the embodiment shown in Figures 1 to 14), the mask can be SU-8 glue, or other photoresists suitable for dry etching. The material of the mask 20A can also be applied to other embodiments, which will not be described again below.
需要指出的是,在图1-图14中,仅仅示出了晶圆上的单个石英谐振器对应的区域,如能够理解的,在石英晶圆10上存在多个图1-图14所示的区域。在其他的实施例中,也应做相似的理解,后面不再赘述。 It should be noted that in FIGS. 1 to 14 , only the area corresponding to a single quartz resonator on the wafer is shown. As can be understood, there are multiple quartz resonators on the quartz wafer 10 as shown in FIGS. 1 to 14 Area. In other embodiments, similar understanding should be made, which will not be described again.
步骤2:湿法刻蚀。如图2所示,以掩膜20A作为阻挡层,利用刻蚀液(例如温度高于20℃、浓度高于5%的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如,在高温高浓度刻蚀液作用下,可以获得较高的刻蚀速率和较为陡峭的晶面坡度。在图2中,石英晶圆的谐振区域被刻蚀了一部分而在谐振区域的外围形成反高台18,以形成反高台结构。图2中为单面反高台结构。Step 2: Wet etching. As shown in Figure 2, the mask 20A is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer. 10 Carry out etching. For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained. In FIG. 2 , a part of the resonance area of the quartz wafer is etched to form an anti-mountain 18 on the periphery of the resonance area to form an anti-mountain structure. Figure 2 shows a single-sided reverse elevated platform structure.
虽然没有示出,步骤2也可以用干法刻蚀代替,或者将湿法刻蚀与干法刻蚀结合。Although not shown, step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
步骤3:去除掩膜20A。如图3所示,上述石英晶圆10刻蚀之后,可以进行清洗、烘干,然后湿法刻蚀的方式去除掩膜20A。Step 3: Remove mask 20A. As shown in FIG. 3 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
步骤4:制作顶电极。如图4所示,利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成,其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了通孔刻蚀区14。Step 4: Make the top electrode. As shown in FIG. 4 , the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation. The top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc. Top electrode 30 covers via etched area 14 .
步骤5:接合第一封装基板。如图5所示,将上述石英晶圆10与预先刻蚀了第一空腔52的石英晶圆或第一封装基板50对准,使得顶电极30恰好位于第一空腔52之内。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起,可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起,这里不做限定。第一封装基板50也可以采用其他的封装材料。Step 5: Join the first package substrate. As shown in FIG. 5 , align the quartz wafer 10 with the quartz wafer or the first packaging substrate 50 with the first cavity 52 etched in advance, so that the top electrode 30 is exactly located within the first cavity 52 . The first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here. The first packaging substrate 50 may also use other packaging materials.
在本发明的实施例中,第一封装基板50是石英基板的情况下,其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。In the embodiment of the present invention, when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 μm and completely consistent with the wafer size specifications of the quartz wafer 10 .
如图5所示的实施例中,在第一封装基板50与石英晶圆10之间以金属键合的情况下,第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。In the embodiment shown in FIG. 5 , when the first packaging substrate 50 and the quartz wafer 10 are bonded with metal, a metal bonding layer is also provided at the junction between the first packaging substrate 50 and the quartz wafer 10 72A.
步骤6:石英晶圆减薄。如图6所示,利用研磨与抛光工艺对石英晶圆10进行减薄,减薄至谐振区域的剩余厚度比设计值(即上述膜厚d0)富余值在例如1μm之内。Step 6: Quartz wafer thinning. As shown in FIG. 6 , the quartz wafer 10 is thinned by grinding and polishing processes until the remaining thickness of the resonance region is within, for example, 1 μm compared with the design value (ie, the film thickness d 0 mentioned above).
步骤7:晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英晶圆厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图7所示,利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量,并得到与设计值d0之间的差值,以为下一步逐个晶片进行膜厚调节提供依 据。Step 7: Wafer-level film thickness measurement. The thickness of the polished quartz wafer in the resonant region was measured using optical methods. The measurement point must be selected in the area with the top electrode on the other side of the quartz film. As shown in Figure 7, the optical measurement method of transparent film thickness is used to measure the quartz film thickness in the resonance area of each wafer, and the difference between it and the design value d0 is obtained, which provides a basis for the next step of adjusting the film thickness of each wafer. according to.
步骤8:调节石英薄膜厚度。如图8所示,利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图7和图8操作,对晶片进行多次厚度调节,最终获得精准的厚度。该流程可以参见图50。Step 8: Adjust quartz film thickness. As shown in Figure 8, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 7 and Figure 8 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 50.
步骤9:在图8所示结构的上表面设置通孔穿孔掩膜20B,如图9所示,掩膜20B在对应于通孔刻蚀区14的位置设置有掩膜开孔。Step 9: Set a through-hole perforation mask 20B on the upper surface of the structure shown in Figure 8. As shown in Figure 9, the mask 20B is provided with mask openings at positions corresponding to the through-hole etching areas 14.
步骤10:例如,利用干法刻蚀的方式刻蚀石英晶圆10的处于通孔刻蚀区14处的部分,以贯穿通孔刻蚀区14而形成通孔14,如图10所示。Step 10: For example, dry etching is used to etch the portion of the quartz wafer 10 located at the through-hole etching area 14 to form the through-hole 14 through the through-hole etching area 14, as shown in FIG. 10 .
步骤11:去除掩膜20B。步骤10之后,可以利用湿法刻蚀的方式去除掩膜20B,以得到如图11所示的结构。Step 11: Remove mask 20B. After step 10, the mask 20B can be removed by wet etching to obtain the structure as shown in FIG. 11.
步骤12:制作底电极和电连接部。如图12所示,利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器底电极40和电连接部32。底电极40至少由一层金属构成,其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。电连接部32与通孔刻蚀区14内的金属电连接,其与底电极40设置在石英晶圆10的同一侧且彼此间隔开。Step 12: Make the bottom electrode and electrical connections. As shown in FIG. 12 , the resonator bottom electrode 40 and the electrical connection portion 32 are fabricated on the quartz wafer 10 by metal sputtering or evaporation. The bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc. The electrical connection portion 32 is electrically connected to the metal in the via etching area 14, and is disposed on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other.
步骤13:测频与调频。如图13所示,测量所得的石英谐振器的谐振频率f,在测得的谐振频率小于预定谐振频率f0的情况下,可以利用例如粒子束的方式改变顶电极30的质量,以提升石英谐振器的谐振频率。如能够理解的,在测得的谐振频率符合设定频率的情况下,可以不用执行调频步骤。该流程可以参见图41。Step 13: Frequency measurement and frequency modulation. As shown in FIG. 13 , the measured resonant frequency f of the quartz resonator is smaller than the predetermined resonant frequency f 0 . For example, the quality of the top electrode 30 can be changed by using a particle beam to improve the quartz resonator. The resonant frequency of the resonator. As can be understood, when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 41.
步骤14:接合第二封装基板。如图14所示,将步骤13中的石英晶圆10与预先刻蚀了第二空腔62的石英晶圆或第二封装基板60对准,使得底电极40恰好位于第二空腔62之内。第二封装基板60与石英晶圆10可以利用金属扩散键合方式键合在一起,可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起,这里不做限定。如图14所示,第二封装基板60设置有第二导电通孔64,其与顶电极30的电连接部32电连接。Step 14: Bond the second package substrate. As shown in FIG. 14 , align the quartz wafer 10 in step 13 with the quartz wafer or the second packaging substrate 60 with the second cavity 62 pre-etched, so that the bottom electrode 40 is exactly located between the second cavity 62 Inside. The second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here. As shown in FIG. 14 , the second package substrate 60 is provided with a second conductive via 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
在本发明的实施例中,第二封装基板60是石英基板的情况下,其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。In the embodiment of the present invention, when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 μm and completely consistent with the wafer size specifications of the quartz wafer 10 .
如图14所示的实施例中,在第二封装基板60与石英晶圆10之间以金属键合的情况下,第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。 In the embodiment shown in FIG. 14 , when the second packaging substrate 60 and the quartz wafer 10 are bonded with metal, a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
图15为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图。图15所示结构与图14所示结构的不同仅仅在于第二导电通孔64的位置的不同,其他结构不再赘述。在图14中,第二导电通孔64与通孔刻蚀区14对齐,而在图15中,第二导电通孔64与通孔刻蚀区14错开。这样错位封装有助于提高结构的稳定性,减少因应力、机械变形等问题带来的通孔损伤导致的气密性破坏。与此同时,通孔错位可以一定程度上屏蔽通过通孔传递应力、热量以及电磁信号等干扰带来的噪声。15 is a schematic cross-sectional view of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention. The structure shown in FIG. 15 differs from the structure shown in FIG. 14 only in the position of the second conductive via hole 64, and other structures will not be described again. In FIG. 14 , the second conductive via 64 is aligned with the via etching area 14 , while in FIG. 15 , the second conductive via 64 is offset from the via etching area 14 . Such misaligned packaging helps to improve the stability of the structure and reduce air-tightness damage caused by through-hole damage caused by stress, mechanical deformation and other issues. At the same time, through-hole dislocation can shield to a certain extent the noise caused by interference such as stress, heat, and electromagnetic signals transmitted through the through-holes.
步骤14之后,可以执行分割操作,以将最终封装形成的石英谐振器形成为单独的器件。After step 14, a segmentation operation can be performed to form the final packaged quartz resonator into individual devices.
在本发明的一个实施例中,最终形成的石英压电层的尺寸小于1mm×1mm,和/或石英压电层的谐振区域的厚度小于40μm或者石英谐振器的基频在40MHz以上。这也适用于本发明的其他实施例。In one embodiment of the present invention, the size of the finally formed quartz piezoelectric layer is less than 1 mm × 1 mm, and/or the thickness of the resonance region of the quartz piezoelectric layer is less than 40 μm or the fundamental frequency of the quartz resonator is above 40 MHz. This also applies to other embodiments of the invention.
在本发明中,封装基板可以是石英基板,也可以其他材料的基板,如硅、玻璃、蓝宝石等。在后面的实施例中不再赘述。在本发明中,封装基板是石英基板的情况下,其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。In the present invention, the packaging substrate may be a quartz substrate or a substrate made of other materials, such as silicon, glass, sapphire, etc. No further details will be given in the following embodiments. In the present invention, when the packaging substrate is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 μm and completely consistent with the wafer size specifications of the quartz wafer 10 .
在本发明中,在为全石英封装的情况下,封装盖为透明材料。因此,调频也可以发生在封装完成之后,利用激光透过透明的石英封装盖直接调节频率,用来调整因为封装应力带来的频率变动。在后面的实施例中不再赘述。In the present invention, in the case of an all-quartz package, the package cover is made of transparent material. Therefore, frequency modulation can also occur after the packaging is completed, using laser to directly adjust the frequency through the transparent quartz packaging cover to adjust the frequency changes caused by packaging stress. No further details will be given in the following embodiments.
图16-图35为根据本发明的再一个示例性实施例的石英谐振器的制作过程的截面示意图。本实施例中石英谐振器的谐振结构利用采用双面反高台的结构,该结构相比于图1-图14所示的实施例具有更好结构稳定性,提高了晶片抗冲击能力,可以进一步改善晶片谐振区域的边界条件,减少声波横向泄露,从而提高谐振器的性能;并且,双面的反高台结构为振动区域提供了空间,可以避免在封装盖上挖槽,有助于晶片的薄型化。16 to 35 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to yet another exemplary embodiment of the present invention. In this embodiment, the resonant structure of the quartz resonator adopts a double-sided reverse platform structure. Compared with the embodiments shown in Figures 1 to 14, this structure has better structural stability, improves the impact resistance of the chip, and can further Improve the boundary conditions of the resonance area of the chip and reduce the lateral leakage of sound waves, thereby improving the performance of the resonator; in addition, the double-sided anti-elevation structure provides space for the vibration area, which can avoid digging grooves in the package cover and contribute to the thinness of the chip. change.
下面参照图16-图35示例性说明石英谐振器的制作过程,其包括步骤如下:The following is an example of the manufacturing process of a quartz resonator with reference to Figures 16-35, which includes the following steps:
步骤1:制作掩膜20A。如图16所示,在石英晶圆(例如直径为1-8英寸,厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20A,处于正面的掩膜20A被图案化,以形成掩膜开孔22,谐振区域12的区域被覆盖。在石英晶圆10的另一侧(例如次面)也设置掩膜20A,其覆盖整 个另一侧。Step 1: Make mask 20A. As shown in FIG. 16 , a mask 20A is made on one side (eg, the front) of a quartz wafer (eg, 1-8 inches in diameter, 100 μm to 1 mm in thickness) using micro/nano electromechanical system photolithography. Mask 20A is patterned to form mask openings 22 and the area of resonant region 12 is covered. A mask 20A is also provided on the other side (for example, the secondary surface) of the quartz wafer 10, covering the entire the other side.
步骤2:湿法刻蚀。如图17所示,以掩膜20A作为阻挡层,利用刻蚀液(例如温度高于20℃、浓度高于5%的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如,在高温高浓度刻蚀液作用下,可以获得较高的刻蚀速率和较为陡峭的晶面坡度。Step 2: Wet etching. As shown in Figure 17, using the mask 20A as a barrier layer, use an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) to etch the quartz wafer. 10 Carry out etching. For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
虽然没有示出,步骤2也可以用干法刻蚀代替,或者将湿法刻蚀与干法刻蚀结合。Although not shown, step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
步骤3:对掩膜20A进一步图案化,以露出谐振区域,如图18所示。Step 3: Further pattern the mask 20A to expose the resonant region, as shown in Figure 18.
步骤4:湿法刻蚀。如图19所示,以掩膜20A作为阻挡层,利用刻蚀液(例如温度高于20℃、浓度高于5%的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。在图19中,石英晶圆的谐振区域被刻蚀了一部分,同时通孔刻蚀区14被进一步刻蚀,如此,图19中,通孔刻蚀区14的深度大于谐振区域的刻蚀深度。Step 4: Wet etching. As shown in Figure 19, using the mask 20A as a barrier layer, use an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) to etch the quartz wafer. 10 Carry out etching. In Figure 19, a part of the resonance area of the quartz wafer is etched, and at the same time, the through hole etching area 14 is further etched. In this way, in Figure 19, the depth of the through hole etching area 14 is greater than the etching depth of the resonance area. .
虽然没有示出,步骤4也可以用干法刻蚀代替,或者将湿法刻蚀与干法刻蚀结合。Although not shown, step 4 may also be replaced by dry etching, or wet etching may be combined with dry etching.
步骤5:去除掩膜20A。如图20所示,上述石英晶圆10刻蚀之后,可以进行清洗、烘干,然后湿法刻蚀的方式去除掩膜20A。Step 5: Remove mask 20A. As shown in FIG. 20 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
步骤6:制作顶电极。如图21所示,利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成,其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了通孔刻蚀区14。Step 6: Make the top electrode. As shown in FIG. 21 , the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation. The top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc. Top electrode 30 covers via etched area 14 .
步骤7:接合第一封装基板。如图22所示,将上述石英晶圆10与预先刻蚀了第一空腔52的石英晶圆或第一封装基板50对准,使得顶电极30恰好位于第一空腔52之内。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起,可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起,这里不做限定。封装基板50也可以采用其他的封装材料。Step 7: Join the first package substrate. As shown in FIG. 22 , align the quartz wafer 10 with the quartz wafer or the first packaging substrate 50 with the first cavity 52 etched in advance, so that the top electrode 30 is exactly located within the first cavity 52 . The first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here. The packaging substrate 50 may also use other packaging materials.
在本发明的实施例中,第一封装基板50是石英基板的情况下,其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。In the embodiment of the present invention, when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 μm and completely consistent with the wafer size specifications of the quartz wafer 10 .
如图22所示的实施例中,在第一封装基板50与石英晶圆10之间以金属键合的情况下,第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。 In the embodiment shown in FIG. 22 , when the first packaging substrate 50 and the quartz wafer 10 are bonded with metal, a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
步骤8:石英晶圆减薄。如图23所示,利用研磨与抛光工艺对石英晶圆10进行减薄。Step 8: Quartz wafer thinning. As shown in FIG. 23 , the quartz wafer 10 is thinned by grinding and polishing processes.
步骤9:制作掩膜20B。如图24所示,图23所示结构上利用微/纳机电系统光刻的方式制作掩膜20B,其被图案化以形成掩膜开孔22和露出谐振区域。掩膜20B的材料可以与掩膜20A的一致。Step 9: Make mask 20B. As shown in FIG. 24 , a mask 20B is fabricated using micro/nano electromechanical system photolithography on the structure shown in FIG. 23 , and is patterned to form mask openings 22 and expose the resonant region. The material of mask 20B may be consistent with that of mask 20A.
步骤10:湿法刻蚀。如图25所示,以图24中的掩膜20B作为阻挡层,利用刻蚀液(例如温度高于20℃、浓度高于5%的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如,在高温高浓度刻蚀液作用下,可以获得较高的刻蚀速率和较为陡峭的晶面坡度。最终形成双面反高台结构,也在石英晶圆10的另一侧形成了与在一侧的通孔刻蚀区14相对的通孔刻蚀区14’,如图25所示。在图25所示的结构中,通孔刻蚀区14’的刻蚀深度与石英晶圆10的另一侧的谐振区域的刻蚀深度一致,但是,在通孔刻蚀区14’与通孔刻蚀区14之间还留有部分石英压电层。Step 10: Wet etching. As shown in Figure 25, the mask 20B in Figure 24 is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to The quartz wafer 10 described above is etched. For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained. Finally, a double-sided reverse mesa structure is formed, and a through-hole etching area 14' opposite to the through-hole etching area 14 on one side is also formed on the other side of the quartz wafer 10, as shown in Figure 25. In the structure shown in FIG. 25 , the etching depth of the via etching region 14 ′ is consistent with the etching depth of the resonance region on the other side of the quartz wafer 10 . However, the etching depth between the via etching region 14 ′ and the via Part of the quartz piezoelectric layer remains between the hole etching areas 14 .
虽然没有示出,步骤10也可以用干法刻蚀代替,或者将湿法刻蚀与干法刻蚀结合。Although not shown, step 10 may also be replaced by dry etching, or wet etching may be combined with dry etching.
步骤11:去除掩膜20B。如图26所示,图25所示结构可以进行清洗、烘干,然后湿法刻蚀的方式去除掩膜20B。Step 11: Remove mask 20B. As shown in FIG. 26 , the structure shown in FIG. 25 can be cleaned, dried, and then the mask 20B is removed by wet etching.
步骤12:晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图27所示,利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量,并得到与设计值d0之间的差值,以为下一步逐个晶片进行膜厚调节提供依据。Step 12: Wafer-level film thickness measurement. The optical method was used to measure the thickness of quartz in the resonance area after grinding. The measurement point must be selected in the area with the top electrode on the other side of the quartz film. As shown in Figure 27, the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
步骤13:调节石英薄膜厚度。如图28所示,利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图27和图28操作,对晶片进行多次厚度调节,最终获得精准的厚度。该流程可以参见图50。Step 13: Adjust quartz film thickness. As shown in Figure 28, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 27 and Figure 28 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 50.
步骤14:制作底电极。如图29所示,利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器底电极40。底电极40至少由一层金属构成,其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。Step 14: Make the bottom electrode. As shown in FIG. 29 , the resonator bottom electrode 40 is formed on the quartz wafer 10 by metal sputtering or evaporation. The bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
步骤15:制作掩膜20C。如图30所示,在图29所示结构上利用微/纳机电系统光刻的方式制作掩膜20C,其被图案化以形成掩膜开孔22,该掩膜开孔露 出在步骤10中刻蚀出的通孔刻蚀区14’,掩膜20C覆盖了底电极40。掩膜20E的材料可以与掩膜20的一致。Step 15: Make mask 20C. As shown in FIG. 30 , a mask 20C is fabricated using micro/nano electromechanical system photolithography on the structure shown in FIG. 29 , and is patterned to form mask openings 22 , which are exposed. Excluding the via etching area 14' etched in step 10, the mask 20C covers the bottom electrode 40. The material of mask 20E may be consistent with that of mask 20 .
步骤16:例如,利用干法刻蚀的方式刻蚀石英晶圆10的处于通孔刻蚀区14’处的部分,以贯穿通孔刻蚀区14’,如图31所示。Step 16: For example, dry etching is used to etch the portion of the quartz wafer 10 located at the through-hole etching area 14' to penetrate the through-hole etching area 14', as shown in Figure 31.
步骤17:去除掩膜20C。如图32所示,图31所示结构可以进行清洗、烘干,然后湿法刻蚀的方式去除掩膜20C。Step 17: Remove mask 20C. As shown in FIG. 32 , the structure shown in FIG. 31 can be cleaned, dried, and then the mask 20C is removed by wet etching.
步骤18:制作电连接部32。如图33所示,利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作电连接部32。电连接部32与通孔刻蚀区14内的金属电连接,其与底电极40设置在石英晶圆10的同一侧且彼此间隔开。Step 18: Make the electrical connection part 32. As shown in FIG. 33 , the electrical connection portion 32 is formed on the quartz wafer 10 by metal sputtering or evaporation. The electrical connection portion 32 is electrically connected to the metal in the via etching area 14, and is disposed on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other.
步骤19:测频与调频。如图34所示,测量所得的石英谐振器的谐振频率f,在测得的谐振频率小于预定谐振频率f0的情况下,可以利用例如粒子束的方式改变顶电极30的质量,以提升石英谐振器的谐振频率。如能够理解的,在测得的谐振频率符合设定频率的情况下,可以不用执行调频步骤。该流程可以参见图51。Step 19: Frequency measurement and frequency modulation. As shown in FIG. 34 , the measured resonant frequency f of the quartz resonator is smaller than the predetermined resonant frequency f 0 . For example, the quality of the top electrode 30 can be changed by using a particle beam to improve the quartz resonator. The resonant frequency of the resonator. As can be understood, when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 51.
步骤20:接合第二封装基板。如图35所示,将步骤19中的石英晶圆10与预先刻蚀了第二空腔62的石英晶圆或第二封装基板60对准,使得底电极40恰好位于第二空腔62之内。第二封装基板60与石英晶圆10可以利用金属扩散键合方式键合在一起,可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起,这里不做限定。如图35所示,第二封装基板60设置有第二导电通孔64,其与顶电极30的电连接部32电连接。Step 20: Bond the second package substrate. As shown in FIG. 35 , align the quartz wafer 10 in step 19 with the quartz wafer or the second packaging substrate 60 with the second cavity 62 pre-etched, so that the bottom electrode 40 is exactly located between the second cavity 62 Inside. The second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here. As shown in FIG. 35 , the second packaging substrate 60 is provided with a second conductive via 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
在本发明的实施例中,第二封装基板60是石英基板的情况下,其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。In the embodiment of the present invention, when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 μm and completely consistent with the wafer size specifications of the quartz wafer 10 .
如图35所示的实施例中,在第二封装基板60与石英晶圆10之间以金属键合的情况下,第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。In the embodiment shown in FIG. 35 , when the second packaging substrate 60 and the quartz wafer 10 are bonded with metal, a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
步骤20之后,可以执行分割操作,以将最终封装形成的石英谐振器形成为单独的器件。After step 20, a segmentation operation may be performed to form the final packaged quartz resonator into individual devices.
图36-38为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图。图36-38所示结构与图35所示结构的不同仅仅在于第二导电通孔64的位置或结构的不同,其他结构不再赘述。36-38 are schematic cross-sectional views of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention. The structure shown in Figures 36-38 is different from the structure shown in Figure 35 only in the position or structure of the second conductive via hole 64, and other structures will not be described again.
在图36-图38中,第二导电通孔64与通孔14错开。这样错位封装有助于 提高结构的稳定性,减少因应力、机械变形等问题带来的通孔损伤导致的气密性破坏。与此同时,通孔错位可以一定程度上屏蔽通过通孔传递应力、热量以及电磁信号等干扰带来的噪声。图37所示结构与图36所示结构相比,通过改善通孔制作工艺,将通孔的截面形状改为垂直型,提高了通孔的气密性。图38所示结构中,改封装底板为平板,有助于减少了晶片总厚度,并提高谐振区域的机械稳定性。In FIGS. 36-38 , the second conductive via 64 is offset from the via 14 . This misaligned packaging helps Improve the stability of the structure and reduce air tightness damage caused by through-hole damage caused by stress, mechanical deformation and other issues. At the same time, through-hole dislocation can shield to a certain extent the noise caused by interference such as stress, heat, and electromagnetic signals transmitted through the through-holes. Compared with the structure shown in Figure 36, the structure shown in Figure 37 improves the through hole manufacturing process and changes the cross-sectional shape of the through hole to a vertical type, thereby improving the air tightness of the through hole. In the structure shown in Figure 38, changing the package bottom plate to a flat plate helps reduce the total thickness of the chip and improves the mechanical stability of the resonance area.
图39-图49为根据本发明的还一个示例性实施例的石英谐振器结构的制作过程的截面示意图。39-49 are schematic cross-sectional views of a manufacturing process of a quartz resonator structure according to yet another exemplary embodiment of the present invention.
步骤1:制作掩膜20。如图39所示,在石英晶圆(例如直径为1-8英寸,厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20,处于正面的掩膜20被图案化,以形成边框掩膜,谐振区域12的区域被露出。在石英晶圆10的另一侧(例如次面)也设置掩膜20,其掩膜20被图案化,以形成边框掩膜,谐振区域12的区域被露出。Step 1: Make mask 20. As shown in FIG. 39 , a mask 20 is made on one side (for example, the front) of a quartz wafer (for example, 1-8 inches in diameter and 100 μm to 1 mm in thickness) using micro/nano electromechanical system photolithography. Mask 20 is patterned to form a frame mask, and areas of resonant region 12 are exposed. A mask 20 is also provided on the other side of the quartz wafer 10 (for example, the secondary surface). The mask 20 is patterned to form a frame mask, and the resonant region 12 is exposed.
步骤2:湿法刻蚀。如图40所示,以掩膜20作为阻挡层,利用刻蚀液(例如温度高于20℃、浓度高于5%的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如,在高温高浓度刻蚀液作用下,可以获得较高的刻蚀速率和较为陡峭的晶面坡度。Step 2: Wet etching. As shown in Figure 40, the mask 20 is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer. 10 Carry out etching. For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
虽然没有示出,步骤2也可以用干法刻蚀代替,或者将湿法刻蚀与干法刻蚀结合。Although not shown, step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
如图40所示,石英晶圆10的两侧与谐振区域对应的部分均被刻蚀。As shown in FIG. 40 , the portions corresponding to the resonance region on both sides of the quartz wafer 10 are etched.
步骤3:去除掩膜20。如图41所示,上述石英晶圆10刻蚀之后,可以进行清洗、烘干,然后湿法刻蚀的方式去除掩膜20。Step 3: Remove mask 20. As shown in FIG. 41 , after the quartz wafer 10 is etched, the mask 20 can be removed by cleaning, drying, and then wet etching.
步骤4:制作顶电极。如图42所示,利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成,其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。Step 4: Make the top electrode. As shown in FIG. 42 , the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation. The top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
步骤5:晶圆级膜厚测量。利用光学方法对谐振区域石英厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图43所示,利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量,并得到与设计值d0之间的差值,以为下一步逐个晶片进行膜厚调节提供依据。Step 5: Wafer-level film thickness measurement. The quartz thickness in the resonance area is measured using optical methods. The measurement point must be selected in the area with the top electrode on the other side of the quartz film. As shown in Figure 43, the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
步骤6:调节石英薄膜厚度。如图44所示,利用离子束刻蚀或者湿法刻蚀 的方式对晶片谐振区域石英片进行二次刻蚀。重复图43和图44操作,对晶片进行多次厚度调节,最终获得精准的厚度。该流程可以参见图50。Step 6: Adjust quartz film thickness. As shown in Figure 44, using ion beam etching or wet etching The quartz plate in the resonance area of the wafer is etched twice. Repeat the operations in Figure 43 and Figure 44 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 50.
步骤7:制作底电极。如图45所示,利用金属溅射或者蒸镀的方式在步骤6所示的石英晶圆10上制作谐振器底电极40。底电极40至少由一层金属构成,其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。Step 7: Make the bottom electrode. As shown in FIG. 45 , the resonator bottom electrode 40 is fabricated on the quartz wafer 10 shown in step 6 by metal sputtering or evaporation. The bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
步骤8:接合第一封装基板。如图46所示,将步骤7中的石英晶圆10与石英晶圆或第一封装基板50利用金属扩散键合方式键合在一起,可以是金金、金锡、铜锡键合等方式。可选的,石英晶圆10与石英晶圆或第一封装基板50也可以采用其他的方式接合在一起,这里不做限定。封装基板50也可以采用其他的封装材料。Step 8: Join the first package substrate. As shown in Figure 46, the quartz wafer 10 in step 7 and the quartz wafer or the first packaging substrate 50 are bonded together using metal diffusion bonding, which can be gold-gold, gold-tin, copper-tin bonding, etc. . Optionally, the quartz wafer 10 and the quartz wafer or the first packaging substrate 50 can also be joined together in other ways, which are not limited here. The packaging substrate 50 may also use other packaging materials.
如图46所示,第一封装基板50预先设置有第一导电通孔54,该第一导电通孔与对应的电极引出部电连接。As shown in FIG. 46 , the first package substrate 50 is provided with a first conductive via hole 54 in advance, and the first conductive via hole is electrically connected to the corresponding electrode lead-out part.
在本发明的实施例中,第一封装基板50可以是石英基板,其厚度可以是20-200μm、与谐振器晶圆尺寸和规格完全一致的石英晶圆制备而成。In an embodiment of the present invention, the first packaging substrate 50 may be a quartz substrate, and its thickness may be 20-200 μm, and may be prepared from a quartz wafer that is exactly the same size and specification as the resonator wafer.
如图46所示的实施例中,在第一封装基板50与石英晶圆10之间以金属键合的情况下,第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。In the embodiment shown in FIG. 46 , when the first packaging substrate 50 and the quartz wafer 10 are bonded with metal, a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
进一步的实施例中,如图46所示,在第一封装基板50与石英晶圆10之间,在金属键合层72A的外侧与之间隔开的设置有填充金属层74A。如能够理解的,在后续的步骤11中设置外连接部的一侧才需要设置填充金属层74A。In a further embodiment, as shown in FIG. 46 , a filling metal layer 74A is provided between the first packaging substrate 50 and the quartz wafer 10 and spaced apart from the outer side of the metal bonding layer 72A. As can be understood, the filling metal layer 74A only needs to be provided on the side where the external connection is provided in the subsequent step 11.
在本发明的一个实施例中,金属键合层72A与填充金属层74A间隔开的距离在2-200微米的范围内。In one embodiment of the present invention, metal bonding layer 72A is spaced apart from fill metal layer 74A by a distance in the range of 2-200 microns.
步骤9:测频与调频。如图47所示,测量所得的石英谐振器的谐振频率,在测得的谐振频率小于预定谐振频率的情况下,可以利用例如粒子束的方式改变顶电极30的质量,以提升对应石英谐振器的谐振频率。如能够理解的,在测得的谐振频率符合设定频率的情况下,可以不用执行调频步骤。该流程可以参见图51。Step 9: Frequency measurement and frequency modulation. As shown in FIG. 47 , when the measured resonant frequency of the quartz resonator is less than the predetermined resonant frequency, the quality of the top electrode 30 can be changed using, for example, a particle beam to improve the corresponding quartz resonator. the resonant frequency. As can be understood, when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 51.
步骤10:接合第二封装基板。如图48所示,将步骤9中的结构与第二封装基板或封装石英晶圆60利用金属扩散键合方式键合在一起,可以是金金、金锡、铜锡键合等方式。可选的,石英晶圆10与第二封装基板或封装石英晶圆60也可以采用其他的方式接合在一起,这里不做限定。第二封装基板或封装石英晶 圆60也可以采用其他的封装材料。Step 10: Bond the second package substrate. As shown in FIG. 48 , the structure in step 9 and the second packaging substrate or packaging quartz wafer 60 are bonded together using metal diffusion bonding, which can be gold-gold, gold-tin, copper-tin bonding, etc. Optionally, the quartz wafer 10 and the second packaging substrate or the packaging quartz wafer 60 can also be joined together in other ways, which are not limited here. The second packaging substrate or packaging quartz crystal Circle 60 can also use other packaging materials.
如图48所示,第二封装基板60预先设置有第二导电通孔64,该第二导电通孔与对应的电极引出部电连接。As shown in FIG. 48 , the second package substrate 60 is provided with a second conductive via hole 64 in advance, and the second conductive via hole is electrically connected to the corresponding electrode lead-out part.
在本发明的实施例中,第二封装基板60是石英基板的情况下,其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。In the embodiment of the present invention, when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 μm and completely consistent with the wafer size specifications of the quartz wafer 10 .
如图48所示的实施例中,在第二封装基板60与石英晶圆10之间以金属键合的情况下,第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。In the embodiment shown in FIG. 48 , when the second packaging substrate 60 and the quartz wafer 10 are bonded with metal, a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
进一步的实施例中,如图48所示,在第二封装基板60与石英晶圆10之间,在金属键合层72B的外侧与之间隔开的设置有填充金属层74B。如能够理解的,在后续的步骤11中设置外连接部的一侧才需要设置填充金属层74B。In a further embodiment, as shown in FIG. 48 , a filling metal layer 74B is provided between the second packaging substrate 60 and the quartz wafer 10 and spaced apart from the outer side of the metal bonding layer 72B. As can be understood, the filling metal layer 74B only needs to be provided on the side where the external connection is provided in the subsequent step 11.
在本发明的一个实施例中,金属键合层72B与填充金属层74B间隔开的距离在2-200微米的范围内。In one embodiment of the present invention, metal bonding layer 72B is spaced apart from fill metal layer 74B by a distance in the range of 2-200 microns.
步骤10之后,可以执行分割操作,以形成多个封装散粒,即至少将石英晶圆切割或者裂片,以形成机械分离的多个独立三明治谐振结构,三明治结构包括第一封装基板50、石英晶圆10或者石英压电层以及第二封装基板60。After step 10, a splitting operation may be performed to form a plurality of packaging particles, that is, at least the quartz wafer is cut or split to form a plurality of mechanically separated independent sandwich resonant structures. The sandwich structure includes the first packaging substrate 50, the quartz crystal. Circle 10 or quartz piezoelectric layer and second packaging substrate 60 .
步骤11:散粒电镀以形成外连接部70:如图49所示,外连接部70在第一封装基板50的远离顶电极的一侧与第二导电通孔64电连接且延伸过三明治结构的端面而延伸到第二封装基板60的远离底电极的一侧。Step 11: Shot electroplating to form the external connection portion 70: As shown in Figure 49, the external connection portion 70 is electrically connected to the second conductive via 64 on the side of the first package substrate 50 away from the top electrode and extends through the sandwich structure. The end surface extends to the side of the second package substrate 60 away from the bottom electrode.
虽然没有示出,在图39-图49所示的实施例中,封装基板也可以是预先设置有空腔,从而在封装基板与对应的电极相对而与石英晶圆键合连接时,电极与所述空腔相对。Although not shown, in the embodiments shown in FIGS. 39-49 , the packaging substrate may also be pre-set with a cavity, so that when the packaging substrate faces the corresponding electrode and is bonded to the quartz wafer, the electrode is connected to the quartz wafer. The cavities are opposite.
基于图1-图49所示的实施例,本发明也提出了一种石英谐振器的制造方法,包括步骤:Based on the embodiments shown in Figures 1 to 49, the present invention also proposes a method for manufacturing a quartz resonator, including the steps:
提供石英晶圆10;Provide quartz wafer 10;
以石英晶圆10形成石英压电层,包括步骤:至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层,所述石英压电层为包括凸台的反高台结构,在石英压电层的两侧适于设置包括第一电极的第一电极层和包括第二电极的第二电极层;Forming a quartz piezoelectric layer on a quartz wafer 10 includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, where the quartz piezoelectric layer is An inverse platform structure including a boss, suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
提供第一封装基板和第二封装基板,所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石 英压电层、第二封装基板的三明治结构,第一封装基板与第一电极层相对,第二封装基板与第二电极层相对;和A first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a structure including the first packaging substrate, the quartz piezoelectric layer, and the quartz piezoelectric layer. A sandwich structure of a piezoelectric layer and a second packaging substrate, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
分割:形成所述三明治结构之后,至少将所述三明治结构切割或者裂片,以形成机械分离的多个三明治结构散粒。Dividing: After forming the sandwich structure, at least the sandwich structure is cut or split to form a plurality of mechanically separated sandwich structure particles.
在本发明的实施例中,采用微/纳机电系统(M/NEMS)光刻技术与湿法刻蚀/干法刻蚀相结合,可以:使得散粒的尺寸小于1mm×1mm;和/或使得散粒的谐振区域的厚度小于40μm或者基于该散粒形成的谐振器的基频在40MHz以上。具体的,基于微/纳机电系统光刻技术,可以获得用于后续刻蚀的、便于形成小于1mm×1mm的散粒尺寸的精细图案,而基于湿法刻蚀/干法刻蚀,则可以获得小于1mm×1mm尺寸的散粒;基于湿法刻蚀/干法刻蚀,可以替代机械掩膜获得小于40μm的石英压电层厚度。In embodiments of the present invention, micro/nano electromechanical systems (M/NEMS) photolithography technology is used in combination with wet etching/dry etching to: make the size of the particles less than 1 mm × 1 mm; and/or The thickness of the resonant region of the shot particles is less than 40 μm or the fundamental frequency of the resonator formed based on the shot particles is above 40 MHz. Specifically, based on micro/nano electromechanical system photolithography technology, it is possible to obtain fine patterns for subsequent etching that facilitate the formation of particle sizes less than 1 mm × 1 mm, while based on wet etching/dry etching, it is possible to Obtain particles with a size less than 1mm×1mm; based on wet etching/dry etching, it can replace the mechanical mask to obtain a quartz piezoelectric layer thickness less than 40μm.
在本发明中,电连接通孔或者通孔14的至少一部分为锥形孔,或者更具体的,电连接通孔的截面为自凸台的上下两侧向中间缩小的形状,这有利于形成导电性良好、阻值稳定的电连接。In the present invention, at least part of the electrical connection through hole or through hole 14 is a tapered hole, or more specifically, the cross section of the electrical connection through hole is a shape that shrinks from the upper and lower sides of the boss to the middle, which is beneficial to forming An electrical connection with good conductivity and stable resistance.
在本发明中,谐振区域是指在形成的石英谐振器中,顶电极、底电极、压电层以及空腔或空隙在压电层的厚度方向上的重合区域。在本发明中,晶圆的谐振区域对应于在晶圆中需要形成为谐振器的谐振区域的区域;压电层的谐振区域对应于在压电层中需要形成为谐振器的谐振区域的区域。在本发明中,非谐振区域是谐振区域之外的部分,对于压电层的非谐振区域,指的是在压电层的谐振区域在水平方向或横向方向外侧的区域。In the present invention, the resonant region refers to the overlapping region of the top electrode, bottom electrode, piezoelectric layer, and cavity or gap in the thickness direction of the piezoelectric layer in the formed quartz resonator. In the present invention, the resonance area of the wafer corresponds to the area in the wafer that needs to be formed as a resonance area of the resonator; the resonance area of the piezoelectric layer corresponds to the area in the piezoelectric layer that needs to be formed as the resonance area of the resonator. . In the present invention, the non-resonant region is a portion outside the resonant region. The non-resonant region of the piezoelectric layer refers to the region outside the resonant region of the piezoelectric layer in the horizontal or lateral direction.
需要指出的是,在本发明中,各个数值范围,除了明确指出不包含端点值之外,除了可以为端点值,还可以为各个数值范围的中值,这些均在本发明的保护范围之内。It should be pointed out that in the present invention, each numerical range, except that it is clearly stated that it does not include the endpoint value, can be the endpoint value or the median value of each numerical range, which are all within the protection scope of the present invention. .
如本领域技术人员能够理解的,根据本发明的石英谐振器可以用于形成石英晶振芯片或包括石英谐振器的电子器件。这里的电子器件,可以是例如振荡器等电子元件,也可以例如对讲机、手机等的通信设备,还可以是汽车等应用了石英谐振器的大型产品。As those skilled in the art can understand, the quartz resonator according to the present invention can be used to form a quartz crystal oscillator chip or an electronic device including a quartz resonator. The electronic device here may be an electronic component such as an oscillator, a communication device such as a walkie-talkie or a mobile phone, or a large-scale product using a quartz resonator such as an automobile.
基于以上,本发明提出了如下技术方案:Based on the above, the present invention proposes the following technical solutions:
1、一种石英谐振器,包括:1. A quartz resonator, including:
底电极,顶电极和石英压电层,所述石英压电层为包括凸台的反高台结构; A bottom electrode, a top electrode and a quartz piezoelectric layer. The quartz piezoelectric layer is an inverted platform structure including a boss;
封装结构,包括第一封装基板、第二封装基板和接合密封层,a packaging structure, including a first packaging substrate, a second packaging substrate and a bonding sealing layer,
其中:in:
所述接合密封层包括压电层封装部,所述压电层封装部为石英压电层的一部分,所述压电层封装部包括所述凸台;The joint sealing layer includes a piezoelectric layer encapsulation part, the piezoelectric layer encapsulation part is a part of the quartz piezoelectric layer, and the piezoelectric layer encapsulation part includes the boss;
所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构。The first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a sandwich structure including the first packaging substrate, the quartz piezoelectric layer, and the second packaging substrate. .
2、根据1所述的谐振器,其中:2. The resonator according to 1, wherein:
所述石英压电层为单面反高台结构。The quartz piezoelectric layer has a single-sided reverse platform structure.
3、根据1所述的谐振器,其中:3. The resonator according to 1, wherein:
所述石英压电层为双面反高台结构。The quartz piezoelectric layer has a double-sided reverse platform structure.
4、根据1所述的谐振器,其中:4. The resonator according to 1, wherein:
第一封装基板和第二封装基板均为石英基板。Both the first packaging substrate and the second packaging substrate are quartz substrates.
5、根据1所述的谐振器,其中:5. The resonator according to 1, wherein:
所述石英压电层的尺寸小于1mm×1mm;和/或The size of the quartz piezoelectric layer is less than 1mm×1mm; and/or
所述石英压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。The thickness of the resonant region of the quartz piezoelectric layer is less than 40 μm or the fundamental frequency of the resonator is above 40 MHz.
6、根据1-5中任一项所述的谐振器,其中:6. The resonator according to any one of 1-5, wherein:
所述第一封装基板和第二封装基板中面对所述凸台的一侧为平坦面。The side of the first packaging substrate and the second packaging substrate facing the boss is a flat surface.
7、根据1-5中任一项所述的谐振器,其中:7. The resonator according to any one of 1-5, wherein:
第一封装基板和/或第二封装基板面对所述石英压电层的一侧设置有空腔,所述石英谐振器的谐振区域在厚度方向上的投影落入所述空腔内。A cavity is provided on a side of the first packaging substrate and/or the second packaging substrate facing the quartz piezoelectric layer, and the projection of the resonance area of the quartz resonator in the thickness direction falls into the cavity.
8、根据1-7中任一项所述的谐振器,其中:8. The resonator according to any one of 1-7, wherein:
顶电极和底电极中的一个电极为第一电极、另一个为第二电极,所述第一电极处于石英压电层的一侧,所述第二电极处于石英压电层的另一侧;One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
所述石英压电层在非谐振区域设置有电连接通孔,所述第一电极的电极引出部经由所述电连接通孔延伸到所述石英压电层的另一侧从而与所述第二电极处于所述石英压电层的同一侧。The quartz piezoelectric layer is provided with an electrical connection through hole in the non-resonant region, and the electrode lead-out portion of the first electrode extends to the other side of the quartz piezoelectric layer through the electrical connection through hole to connect with the third electrode. The two electrodes are located on the same side of the quartz piezoelectric layer.
9、根据8所述的谐振器,其中:9. The resonator according to 8, wherein:
处于石英压电层的另一侧的第一封装基板和第二封装基板中的基板设置有 基板导电通孔;The substrate in the first packaging substrate and the second packaging substrate on the other side of the quartz piezoelectric layer is provided with Substrate conductive vias;
所述基板导电通孔与所述第一电极的电极引出部经由所述电连接通孔延伸到所述石英压电层的另一侧的部分电连接。The substrate conductive via hole is electrically connected to a portion of the electrode lead-out portion of the first electrode extending to the other side of the quartz piezoelectric layer via the electrical connection via hole.
10、根据9所述的谐振器,其中:10. The resonator according to 9, wherein:
所述基板导电通孔与所述电连接通孔在水平方向上错开;或者The substrate conductive through holes and the electrical connection through holes are staggered in the horizontal direction; or
所述基板导电通孔与所述电连接通孔在厚度方向上对齐。The substrate conductive via hole and the electrical connection via hole are aligned in the thickness direction.
11、根据10所述的谐振器,其中:11. The resonator according to 10, wherein:
所述基板导电通孔为直孔、锥形孔或者上下两侧向中间缩小的孔。The substrate conductive through holes are straight holes, tapered holes, or holes with upper and lower sides narrowing toward the middle.
12、根据1-7中任一项所述的谐振器,其中:12. The resonator according to any one of 1-7, wherein:
顶电极和底电极中的一个电极为第一电极、另一个为第二电极,所述第一电极处于石英压电层的一侧,所述第二电极处于石英压电层的另一侧;One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
第一封装基板与第一电极相对,第二封装基板与第二电极相对;The first packaging substrate is opposite to the first electrode, and the second packaging substrate is opposite to the second electrode;
第一封装基板设置有第一封装基板导电通孔,所述第一封装基板导电通孔与第一电极的电极引出部电连接;The first packaging substrate is provided with a first packaging substrate conductive through hole, and the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode;
第二封装基板设置有第二封装基板导电通孔,所述第二封装基板导电通孔与第二电极的电极引出部电连接;The second packaging substrate is provided with a second packaging substrate conductive through hole, and the second packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the second electrode;
所述谐振器还包括外连接部,所述外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第二封装基板的远离第二电极的一侧,或者所述外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第一封装基板的远离第一电极的一侧。The resonator further includes an external connection portion, which is electrically connected to the conductive via hole of the first packaging substrate on a side of the first packaging substrate away from the first electrode and extends through the end surface of the sandwich structure of the resonator. and extends to the side of the second packaging substrate away from the second electrode, or the external connection portion is electrically connected to the second packaging substrate conductive via hole on the side of the second packaging substrate away from the second electrode and extends through the The end surface of the sandwich structure of the resonator extends to a side of the first packaging substrate away from the first electrode.
13、根据12所述的谐振器,其中:13. The resonator according to 12, wherein:
所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述压电层封装部基于金属键合层接合;The first packaging substrate and the second packaging substrate are respectively bonded to the piezoelectric layer packaging part on both sides of the quartz piezoelectric layer based on a metal bonding layer;
所述谐振器还包括在金属键合层的外侧而与金属键合层分隔开的填充金属层,所述填充金属层与所述外连接部相接,可选的,所述金属键合层与所述填充金属层间隔开的距离在2-200微米的范围内。The resonator further includes a filling metal layer outside the metal bonding layer and separated from the metal bonding layer. The filling metal layer is connected to the external connection part. Optionally, the metal bonding layer The layer is spaced apart from the fill metal layer by a distance in the range of 2-200 microns.
14、一种电子器件,包括根据1-13中任一项所述的石英谐振器。14. An electronic device, including the quartz resonator according to any one of 1-13.
15、一种石英谐振器的制造方法,包括步骤:15. A method of manufacturing a quartz resonator, including the steps:
提供石英晶圆; Provide quartz wafers;
以石英晶圆形成石英压电层,包括步骤:至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层,所述石英压电层为包括凸台的反高台结构,在石英压电层的两侧适于设置包括第一电极的第一电极层和包括第二电极的第二电极层;Forming a quartz piezoelectric layer on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, and the quartz piezoelectric layer includes: The anti-high platform structure of the boss is suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
提供第一封装基板和第二封装基板,所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构,第一封装基板与第一电极层相对,第二封装基板与第二电极层相对;和A first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the boss on both sides of the quartz piezoelectric layer to form a package including the first packaging substrate, quartz A sandwich structure of the piezoelectric layer and the second packaging substrate, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
分割:形成所述三明治结构之后,至少将所述三明治结构切割或者裂片,以形成机械分离的多个三明治结构散粒。Dividing: After forming the sandwich structure, at least the sandwich structure is cut or split to form a plurality of mechanically separated sandwich structure particles.
16、根据15所述的方法,其中:16. The method according to 15, wherein:
顶电极和底电极中的一个电极为第一电极、另一个为第二电极,所述第一电极处于石英压电层的一侧,所述第二电极处于石英压电层的另一侧;One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
以石英晶圆形成石英压电层的步骤还包括:在所述石英压电层的非谐振区域设置电连接通孔,所述第一电极的电极引出部适于经由所述电连接通孔延伸到所述石英压电层的另一侧从而与所述第二电极处于所述石英压电层的同一侧;The step of forming a quartz piezoelectric layer using a quartz wafer further includes: providing an electrical connection via hole in a non-resonant region of the quartz piezoelectric layer, and the electrode lead-out portion of the first electrode is adapted to extend through the electrical connection via hole. to the other side of the quartz piezoelectric layer so as to be on the same side of the quartz piezoelectric layer as the second electrode;
所述方法还包括步骤:在第二封装基板设置基板导电通孔,所述基板导电通孔与所述第一电极的电极引出部经由所述电连接通孔延伸到所述石英压电层的另一侧的部分电连接。The method further includes the step of: arranging a substrate conductive via hole in the second packaging substrate, and the substrate conductive via hole and the electrode lead-out portion of the first electrode extend to the quartz piezoelectric layer through the electrical connection via hole. The other side is partially electrically connected.
17、根据15所述的方法,其中:17. The method according to 15, wherein:
在提供第一封装基板和第二封装基板的步骤中,第一封装基板设置有第一封装基板导电通孔,所述第一封装基板导电通孔与第一电极的电极引出部电连接,第二封装基板设置有第二封装基板导电通孔,所述第二封装基板导电通孔与第二电极的电极引出部电连接;In the step of providing the first packaging substrate and the second packaging substrate, the first packaging substrate is provided with a first packaging substrate conductive through hole, the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode, and the The two packaging substrates are provided with a second packaging substrate conductive through hole, and the second packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the second electrode;
所述方法还包括步骤:为三明治结构散粒提供外连接部以形成独立的石英谐振器,其中:所述外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第二封装基板的远离第二电极的一侧,或者所述外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第一封装基板的远离第一电极的一侧。 The method further includes the step of: providing an external connection part to the sandwich structure shot to form an independent quartz resonator, wherein: the external connection part is electrically conductive with the first packaging substrate on a side of the first packaging substrate away from the first electrode. The through hole is electrically connected and extends through the end surface of the sandwich structure of the resonator to a side of the second packaging substrate away from the second electrode, or the external connection portion is on a side of the second packaging substrate away from the second electrode. The side is electrically connected to the conductive via hole of the second packaging substrate and extends through the end surface of the sandwich structure of the resonator to a side of the first packaging substrate away from the first electrode.
18、根据17所述的方法,其中:18. The method according to 17, wherein:
提供外连接部的步骤包括:以金属溅射或者蒸镀的方式形成外连接部。The step of providing the external connection part includes: forming the external connection part by metal sputtering or evaporation.
19、根据18所述的方法,其中:19. The method according to 18, wherein:
所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台以金属键合的方式接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构;The first packaging substrate and the second packaging substrate are respectively joined to the boss in a metal bonding manner on both sides of the quartz piezoelectric layer to form a package including a first packaging substrate, a quartz piezoelectric layer, a third Sandwich structure of two packaging substrates;
在提供外连接部之前,所述方法还包括步骤:在以金属键合形成的键合层的外侧设置与键合层间隔开的填充金属层;且Before providing the external connection, the method further includes the steps of: arranging a filling metal layer spaced apart from the bonding layer outside the bonding layer formed by metal bonding; and
在提供外连接部的步骤中,所述外连接部与所述填充金属层接触以便于在三明治结构的端面的外连接部平坦化。In the step of providing the external connection portion, the external connection portion is in contact with the filling metal layer to facilitate planarization of the external connection portion at the end face of the sandwich structure.
尽管已经示出和描述了本发明的实施例,对于本领域的普通技术人员而言,可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化,本发明的范围由所附权利要求及其等同物限定。 Although embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention. The scope of the invention is determined by The appended claims and their equivalents are defined.

Claims (19)

  1. 一种石英谐振器,包括:A quartz resonator including:
    底电极,顶电极和石英压电层,所述石英压电层为包括凸台的反高台结构;A bottom electrode, a top electrode and a quartz piezoelectric layer. The quartz piezoelectric layer is an inverted platform structure including a boss;
    封装结构,包括第一封装基板、第二封装基板和接合密封层,a packaging structure, including a first packaging substrate, a second packaging substrate and a bonding sealing layer,
    其中:in:
    所述接合密封层包括压电层封装部,所述压电层封装部为石英压电层的一部分,所述压电层封装部包括所述凸台;The joint sealing layer includes a piezoelectric layer encapsulation part, the piezoelectric layer encapsulation part is a part of the quartz piezoelectric layer, and the piezoelectric layer encapsulation part includes the boss;
    所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构。The first packaging substrate and the second packaging substrate are respectively joined to the bosses on both sides of the quartz piezoelectric layer to form a sandwich structure including the first packaging substrate, the quartz piezoelectric layer, and the second packaging substrate. .
  2. 根据权利要求1所述的谐振器,其中:The resonator of claim 1, wherein:
    所述石英压电层为单面反高台结构。The quartz piezoelectric layer has a single-sided reverse platform structure.
  3. 根据权利要求1所述的谐振器,其中:The resonator of claim 1, wherein:
    所述石英压电层为双面反高台结构。The quartz piezoelectric layer has a double-sided reverse platform structure.
  4. 根据权利要求1所述的谐振器,其中:The resonator of claim 1, wherein:
    第一封装基板和第二封装基板均为石英基板。Both the first packaging substrate and the second packaging substrate are quartz substrates.
  5. 根据权利要求1所述的谐振器,其中:The resonator of claim 1, wherein:
    所述石英压电层的尺寸小于1mm×1mm;和/或The size of the quartz piezoelectric layer is less than 1mm×1mm; and/or
    所述石英压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。The thickness of the resonant region of the quartz piezoelectric layer is less than 40 μm or the fundamental frequency of the resonator is above 40 MHz.
  6. 根据权利要求1-5中任一项所述的谐振器,其中:The resonator according to any one of claims 1-5, wherein:
    所述第一封装基板和第二封装基板中面对所述凸台的一侧为平坦面。The side of the first packaging substrate and the second packaging substrate facing the boss is a flat surface.
  7. 根据权利要求1-5中任一项所述的谐振器,其中:The resonator according to any one of claims 1-5, wherein:
    第一封装基板和/或第二封装基板面对所述石英压电层的一侧设置有空腔,所述石英谐振器的谐振区域在厚度方向上的投影落入所述空腔内。A cavity is provided on a side of the first packaging substrate and/or the second packaging substrate facing the quartz piezoelectric layer, and the projection of the resonance area of the quartz resonator in the thickness direction falls into the cavity.
  8. 根据权利要求1-7中任一项所述的谐振器,其中:The resonator according to any one of claims 1-7, wherein:
    顶电极和底电极中的一个电极为第一电极、另一个为第二电极,所述 第一电极处于石英压电层的一侧,所述第二电极处于石英压电层的另一侧;One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, and the The first electrode is located on one side of the quartz piezoelectric layer, and the second electrode is located on the other side of the quartz piezoelectric layer;
    所述石英压电层在非谐振区域设置有电连接通孔,所述第一电极的电极引出部经由所述电连接通孔延伸到所述石英压电层的另一侧从而与所述第二电极处于所述石英压电层的同一侧。The quartz piezoelectric layer is provided with an electrical connection through hole in the non-resonant region, and the electrode lead-out portion of the first electrode extends to the other side of the quartz piezoelectric layer through the electrical connection through hole to connect with the third electrode. The two electrodes are located on the same side of the quartz piezoelectric layer.
  9. 根据权利要求8所述的谐振器,其中:The resonator of claim 8, wherein:
    处于石英压电层的另一侧的第一封装基板和第二封装基板中的基板设置有基板导电通孔;The substrate in the first packaging substrate and the second packaging substrate on the other side of the quartz piezoelectric layer is provided with a substrate conductive via hole;
    所述基板导电通孔与所述第一电极的电极引出部经由所述电连接通孔延伸到所述石英压电层的另一侧的部分电连接。The substrate conductive via hole is electrically connected to a portion of the electrode lead-out portion of the first electrode extending to the other side of the quartz piezoelectric layer via the electrical connection via hole.
  10. 根据权利要求9所述的谐振器,其中:The resonator of claim 9, wherein:
    所述基板导电通孔与所述电连接通孔在水平方向上错开;或者The substrate conductive through holes and the electrical connection through holes are staggered in the horizontal direction; or
    所述基板导电通孔与所述电连接通孔在厚度方向上对齐。The substrate conductive via hole and the electrical connection via hole are aligned in the thickness direction.
  11. 根据权利要求10所述的谐振器,其中:The resonator of claim 10, wherein:
    所述基板导电通孔为直孔、锥形孔或者上下两侧向中间缩小的孔。The substrate conductive through holes are straight holes, tapered holes, or holes with upper and lower sides narrowing toward the middle.
  12. 根据权利要求1-7中任一项所述的谐振器,其中:The resonator according to any one of claims 1-7, wherein:
    顶电极和底电极中的一个电极为第一电极、另一个为第二电极,所述第一电极处于石英压电层的一侧,所述第二电极处于石英压电层的另一侧;One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
    第一封装基板与第一电极相对,第二封装基板与第二电极相对;The first packaging substrate is opposite to the first electrode, and the second packaging substrate is opposite to the second electrode;
    第一封装基板设置有第一封装基板导电通孔,所述第一封装基板导电通孔与第一电极的电极引出部电连接;The first packaging substrate is provided with a first packaging substrate conductive through hole, and the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode;
    第二封装基板设置有第二封装基板导电通孔,所述第二封装基板导电通孔与第二电极的电极引出部电连接;The second packaging substrate is provided with a second packaging substrate conductive through hole, and the second packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the second electrode;
    所述谐振器还包括外连接部,所述外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第二封装基板的远离第二电极的一侧,或者所述外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第一封装基板的远离第一电极的一侧。The resonator further includes an external connection portion, which is electrically connected to the conductive via hole of the first packaging substrate on a side of the first packaging substrate away from the first electrode and extends through the end surface of the sandwich structure of the resonator. and extends to the side of the second packaging substrate away from the second electrode, or the external connection portion is electrically connected to the second packaging substrate conductive via hole on the side of the second packaging substrate away from the second electrode and extends through the The end surface of the sandwich structure of the resonator extends to a side of the first packaging substrate away from the first electrode.
  13. 根据权利要求12所述的谐振器,其中:The resonator of claim 12, wherein:
    所述第一封装基板和所述第二封装基板分别在所述石英压电层的两 侧与所述压电层封装部基于金属键合层接合;The first packaging substrate and the second packaging substrate are respectively located on both sides of the quartz piezoelectric layer. The side is bonded to the piezoelectric layer encapsulation part based on a metal bonding layer;
    所述谐振器还包括在金属键合层的外侧而与金属键合层分隔开的填充金属层,所述填充金属层与所述外连接部相接,可选的,所述金属键合层与所述填充金属层间隔开的距离在2-200微米的范围内。The resonator further includes a filling metal layer outside the metal bonding layer and separated from the metal bonding layer. The filling metal layer is connected to the external connection part. Optionally, the metal bonding layer The layer is spaced apart from the fill metal layer by a distance in the range of 2-200 microns.
  14. 一种电子器件,包括根据权利要求1-13中任一项所述的石英谐振器。An electronic device including the quartz resonator according to any one of claims 1-13.
  15. 一种石英谐振器的制造方法,包括步骤:A method for manufacturing a quartz resonator, including the steps:
    提供石英晶圆;Provide quartz wafers;
    以石英晶圆形成石英压电层,包括步骤:至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层,所述石英压电层为包括凸台的反高台结构,在石英压电层的两侧适于设置包括第一电极的第一电极层和包括第二电极的第二电极层;Forming a quartz piezoelectric layer on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, and the quartz piezoelectric layer includes: The inverted platform structure of the boss is suitable for disposing a first electrode layer including a first electrode and a second electrode layer including a second electrode on both sides of the quartz piezoelectric layer;
    提供第一封装基板和第二封装基板,所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构,第一封装基板与第一电极层相对,第二封装基板与第二电极层相对;和A first packaging substrate and a second packaging substrate are provided, and the first packaging substrate and the second packaging substrate are respectively joined to the boss on both sides of the quartz piezoelectric layer to form a package including the first packaging substrate, quartz A sandwich structure of the piezoelectric layer and the second packaging substrate, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
    分割:形成所述三明治结构之后,至少将所述三明治结构切割或者裂片,以形成机械分离的多个三明治结构散粒。Dividing: After forming the sandwich structure, at least the sandwich structure is cut or split to form a plurality of mechanically separated sandwich structure particles.
  16. 根据权利要求15所述的方法,其中:The method of claim 15, wherein:
    顶电极和底电极中的一个电极为第一电极、另一个为第二电极,所述第一电极处于石英压电层的一侧,所述第二电极处于石英压电层的另一侧;One of the top electrode and the bottom electrode is a first electrode, and the other is a second electrode, the first electrode is on one side of the quartz piezoelectric layer, and the second electrode is on the other side of the quartz piezoelectric layer;
    以石英晶圆形成石英压电层的步骤还包括:在所述石英压电层的非谐振区域设置电连接通孔,所述第一电极的电极引出部适于经由所述电连接通孔延伸到所述石英压电层的另一侧从而与所述第二电极处于所述石英压电层的同一侧;The step of forming a quartz piezoelectric layer using a quartz wafer further includes: arranging an electrical connection via hole in a non-resonant region of the quartz piezoelectric layer, and the electrode lead-out portion of the first electrode is adapted to extend through the electrical connection via hole. to the other side of the quartz piezoelectric layer so as to be on the same side of the quartz piezoelectric layer as the second electrode;
    所述方法还包括步骤:在第二封装基板设置基板导电通孔,所述基板导电通孔与所述第一电极的电极引出部经由所述电连接通孔延伸到所述石英压电层的另一侧的部分电连接。The method further includes the step of: arranging a substrate conductive via hole in the second packaging substrate, and the substrate conductive via hole and the electrode lead-out portion of the first electrode extend to the quartz piezoelectric layer through the electrical connection via hole. The other side is partially electrically connected.
  17. 根据权利要求15所述的方法,其中:The method of claim 15, wherein:
    在提供第一封装基板和第二封装基板的步骤中,第一封装基板设置有 第一封装基板导电通孔,所述第一封装基板导电通孔与第一电极的电极引出部电连接,第二封装基板设置有第二封装基板导电通孔,所述第二封装基板导电通孔与第二电极的电极引出部电连接;In the step of providing the first packaging substrate and the second packaging substrate, the first packaging substrate is provided with The first packaging substrate conductive via hole is electrically connected to the electrode lead-out portion of the first electrode. The second packaging substrate is provided with a second packaging substrate conductive via hole. The second packaging substrate conductive via hole The hole is electrically connected to the electrode lead-out portion of the second electrode;
    所述方法还包括步骤:为三明治结构散粒提供外连接部以形成独立的石英谐振器,其中:所述外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第二封装基板的远离第二电极的一侧,或者所述外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过所述谐振器的三明治结构的端面而延伸到第一封装基板的远离第一电极的一侧。The method further includes the step of: providing an external connection part to the sandwich structure shot to form an independent quartz resonator, wherein: the external connection part is electrically conductive with the first packaging substrate on a side of the first packaging substrate away from the first electrode. The through hole is electrically connected and extends through the end surface of the sandwich structure of the resonator to a side of the second packaging substrate away from the second electrode, or the external connection portion is on a side of the second packaging substrate away from the second electrode. The side is electrically connected to the conductive via hole of the second packaging substrate and extends through the end surface of the sandwich structure of the resonator to a side of the first packaging substrate away from the first electrode.
  18. 根据权利要求17所述的方法,其中:The method of claim 17, wherein:
    提供外连接部的步骤包括:以金属溅射或者蒸镀的方式形成外连接部。The step of providing the external connection part includes: forming the external connection part by metal sputtering or evaporation.
  19. 根据权利要求18所述的方法,其中:The method of claim 18, wherein:
    所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台以金属键合的方式接合以形成包括第一封装基板、石英压电层、第二封装基板的三明治结构;The first packaging substrate and the second packaging substrate are respectively joined to the boss in a metal bonding manner on both sides of the quartz piezoelectric layer to form a package including a first packaging substrate, a quartz piezoelectric layer, a third Sandwich structure of two packaging substrates;
    在提供外连接部之前,所述方法还包括步骤:在以金属键合形成的键合层的外侧设置与键合层间隔开的填充金属层;且Before providing the external connection, the method further includes the steps of: arranging a filling metal layer spaced apart from the bonding layer outside the bonding layer formed by metal bonding; and
    在提供外连接部的步骤中,所述外连接部与所述填充金属层接触以便于在三明治结构的端面的外连接部平坦化。 In the step of providing the external connection portion, the external connection portion is in contact with the filling metal layer to facilitate planarization of the external connection portion at the end face of the sandwich structure.
PCT/CN2023/110651 2022-08-05 2023-08-02 Quartz resonator having sandwich structure formed by double base plates and piezoelectric layer, and electronic device WO2024027737A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260845A (en) * 2008-04-18 2009-11-05 Daishinku Corp Method of manufacturing piezoelectric vibration device, and piezoelectric vibration device
JP2010130400A (en) * 2008-11-28 2010-06-10 Daishinku Corp Piezoelectric vibration device
JP2010206322A (en) * 2009-02-27 2010-09-16 Daishinku Corp Package member, method of manufacturing the package member, and piezoelectric vibration device using the package member
CN114696773A (en) * 2020-12-31 2022-07-01 诺思(天津)微系统有限责任公司 Bulk acoustic wave resonator, method of manufacturing the same, filter, and electronic apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260845A (en) * 2008-04-18 2009-11-05 Daishinku Corp Method of manufacturing piezoelectric vibration device, and piezoelectric vibration device
JP2010130400A (en) * 2008-11-28 2010-06-10 Daishinku Corp Piezoelectric vibration device
JP2010206322A (en) * 2009-02-27 2010-09-16 Daishinku Corp Package member, method of manufacturing the package member, and piezoelectric vibration device using the package member
CN114696773A (en) * 2020-12-31 2022-07-01 诺思(天津)微系统有限责任公司 Bulk acoustic wave resonator, method of manufacturing the same, filter, and electronic apparatus

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