KR100636780B1 - Packaging wafer fabrication method using glass wafer, and, packaging wafer fabricated by the same - Google Patents

Abstract

Disclosed is a packaging substrate manufacturing method using a glass substrate. The manufacturing method comprises the steps of: (a) etching a predetermined area of the upper surface of the glass substrate to a predetermined thickness to produce a cavity, (b) laminating a seed layer on the lower surface of the glass substrate, (c) And further etching the glass substrate region in which the cavity is formed, to produce a via hole penetrating the upper and lower surfaces of the glass substrate, and (d) filling the via hole using a predetermined conductive material. In this case, in step (a), the glass substrate is etched using a sand blaster, so that the etching surface of the glass substrate has a predetermined angle of inclination. As a result, a packaging substrate having excellent RF characteristics can be manufactured at a low price.

Packaging Board, Glass Board, Via Hole, Tilt, Sand Blaster

Description

Packaging wafer fabrication method using glass wafer, and, packaging wafer fabricated by the same}

1 is a vertical cross-sectional view showing the structure of a conventional packaging silicon substrate,

2 is a vertical cross-sectional view showing the structure of a packaging substrate according to an embodiment of the present invention;

3 is a vertical cross-sectional view showing the structure of a packaging substrate according to another embodiment of the present invention;

4 (a) to 4 (h) is a vertical cross-sectional view for explaining a manufacturing method for manufacturing the packaging substrate of FIG.

4 (i) is a vertical cross sectional view showing a further process for manufacturing the packaging substrate of FIG. 3, and

5 is a vertical cross-sectional view showing the structure of a chip packaged using the packaging substrate according to the embodiment of FIG.

Explanation of symbols on the main parts of the drawing

110: glass substrate 120: polysilicon layer

130: shield 135: via hole

140: seed layer 150: conductive material layer

160 electrode

The present invention relates to a packaging substrate and a method for manufacturing the same, and more particularly, to a method for manufacturing a packaging substrate using a glass substrate on which electrical wiring is formed and a packaging substrate manufactured according to the method.

Recently, with the development of MEMS (Micro Electro Mechanical Systems) technology, small high-performance circuit devices have been developed. These circuit elements require packaging in order to be manufactured in one single chip. Packaging refers to the work that allows the circuit elements to have physical functions and formations to be mounted on electronic components. That is, in order to prevent foreign substances from entering or being damaged by an external impact, it means an operation of sealing and packaging the circuit elements. In this case, in order to seal and package the circuit element, the circuit element is covered using a packaging substrate. The packaging substrate is preferably provided with electrodes so that internal circuitry can be electrically connected to external circuitry.

1 is a vertical cross-sectional view showing the structure of a conventional packaging silicon substrate. Referring to FIG. 1, after the seed layer 10 is stacked below the substrate 11, the substrate 11 is vertically etched to expose the seed layer 10, and the metal layer is exposed using the exposed seed layer 10. By plating (12), electrical wiring is produced. In this case, as the substrate 11 is vertically etched, the surface of the substrate 11 to be plated of the metal layer 12 is also bent vertically. Therefore, the metal layer 12 may not be completely covered, or may require a subsequent process such as polishing after excessive plating. In addition, there is a problem that the electrode layer formation may be difficult because the predetermined region 13 of the substrate 11 is exposed. That is, there is a problem that the connection between the circuit element and the metal layer 12 below the packaging substrate may be broken. In addition, there was a problem that voids may be formed during the plating process.

In addition, when packaging a radio frequency (RF) device such as a thin film bulk acoustic resonator, there is a problem that the RF characteristics are degraded when a general silicon substrate is used as the packaging substrate. Accordingly, it is common to use an expensive high resistivity silicon wafer as a packaging substrate, which causes a problem of increasing chip prices.

In addition, since silicon and high-resistance silicon wafers have low light transmittance, there is a problem that they cannot be used when packaging requiring light transmission is required in the optical field.

On the other hand, glass wafers have a higher resistance than ordinary silicon substrates, are inexpensive, and have high light transmittance. However, there is a problem in that it is difficult to apply a semiconductor process applied to a silicon substrate due to the characteristics of the glass substrate. Therefore, there was a difficulty in producing electrical wiring and the like required for the packaging substrate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a packaging substrate manufactured using a glass substrate having low cost, good resistance characteristics, and high light transmittance, and a method of manufacturing the same. Is in.

Another object of the present invention is to provide a packaging substrate and a method of manufacturing the same, which facilitate the formation of electrodes by manufacturing the via hole penetrating the glass substrate to be inclined at a predetermined angle.

Packaging substrate according to an embodiment of the present invention for achieving the above object, the glass substrate, the seed layer laminated on the lower surface of the glass substrate, penetrates the upper surface and the lower surface of the glass substrate, the inner side And a via hole inclined at a predetermined angle, and a conductive material layer filling the via hole.

Preferably, the glass substrate may further include an electrode stacked on an upper surface of the glass substrate and electrically connected to the conductive material layer.

On the other hand, the manufacturing method of the packaging substrate according to an embodiment of the present invention, (a) etching a predetermined area of the upper surface of the glass substrate to a predetermined thickness to produce a cavity, (b) a seed on the lower surface of the glass substrate Laminating a seed layer, (c) further etching the glass substrate region in which the cavity is formed, to fabricate a via hole penetrating the upper and lower surfaces of the glass substrate, and (d) a predetermined conductive material Embedding the via hole using a.

In this case, in the step (a), by etching the glass substrate using a sand blaster, it is preferable that the etching surface of the glass substrate has a predetermined angle of inclination.

Also preferably, in the step (c), the glass substrate may be additionally etched using one of a wet etching method and a dry etching method to flatten the side surface of the cavity.

More preferably, the method for manufacturing a packaging substrate may further include stacking an electrode on an upper surface of the glass substrate and electrically connecting the conductive material.

On the other hand, the step (a), the step of laminating a polysilicon layer on the surface of the glass substrate, the step of laminating a protective film of a predetermined type on the surface of the polysilicon layer laminated on the upper surface of the glass substrate, sandblast (sand forming a cavity by etching the polysilicon layer and the glass substrate in the region where the protective film is not laminated using a blaster), and removing the polysilicon layer laminated on the lower surface of the glass substrate. Can be.

In this case, it is preferable to use a photosensitive film as the protective film.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

2 is a vertical cross-sectional view showing the structure of a packaging substrate according to an embodiment of the present invention. Referring to FIG. 2, the packaging substrate includes a glass substrate 110, a seed layer 140, a via hole 135, and a conductive material layer 150.

The via hole 135 penetrates the upper and lower surfaces of the glass substrate 110. At this time, the side surface of the via hole 135, that is, the etching surface of the glass substrate 110 has a predetermined angle of inclination. This is to prevent the electrode from being broken by exposing a portion located at the corner portion of the etching region when the electrode is formed.

A sand blasting process is used to manufacture the via holes 135. That is, the via hole 135 is manufactured by etching the glass substrate 110 using an abrasive such as sand, because it is difficult to use a semiconductor etching process due to the characteristics of the glass substrate 110. The manufacturing process of the via hole 135 will be described in more detail in the steps to be described later.

A conductive material is embedded in the via hole 135 to form the conductive material layer 150. Conductive materials include copper (Cu), aluminum (Al), tungsten (W), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), chromium (Cr), palladium (Pd) and molybdenum Ordinary metals such as (Mo) can be used.

On the other hand, the seed layer 140 is stacked on the lower surface of the silicon substrate 110, and serves as a seed so that the conductive material is plated in the via hole 135. The material of the seed layer 140 may be chromium (Cr), gold (Au), or the like.

Accordingly, the conductive material layer 150 plated by the seed layer 140 has a cone shape in which the area of the upper surface is relatively larger than the area of the lower surface. Therefore, the electrode can be easily formed on the conductive material layer 150, and the risk of forming a void in the form of being plated is reduced.

On the other hand, Figure 3 is a vertical cross-sectional view showing the configuration of a packaging substrate according to another embodiment of the present invention. Referring to FIG. 3, it can be seen that the electrode 160 is added to the upper surface of the packaging substrate of FIG. 2. As the inner side surface of the via hole 135 is made obliquely, the edge of the glass substrate 110 in the region where the via hole 135 is manufactured is not bent vertically, but rather is bent gently. Therefore, the glass substrate 110 of the corner portion is not exposed.

4 (a) to 4 (h) are vertical cross-sectional views for explaining a manufacturing method of manufacturing the packaging substrate of FIG. First, as shown in FIG. 4A, a polysilicon layer 120 is laminated on the surface of the glass substrate 110.

Next, as shown in FIG. 4B, the passivation layer 130 is patterned on the polysilicon layer 120 stacked on the upper surface of the glass substrate 110. In this case, a photosensitive film such as a dry film resistor (DFR) may be used as the protective film 130. In order to use a sand blaster, it is preferable to use a sand blaster-only film having a thickness of about 100 microns.

Next, as shown in FIG. 4C, the glass substrate 110 on which the protective film 130 is laminated is introduced into the sand blaster to thereby form a polysilicon layer in which the protective film 130 is not laminated using an abrasive such as sand. The 130 and the glass substrate 110 are etched to fabricate the cavity 135. In this case, the glass substrate 110 under the cavity 135 remains at a predetermined thickness without being completely etched, so that the seed layer 140 may be stacked in a later step. Meanwhile, in etching the glass substrate 110, the glass substrate 110 may be manufactured to have a predetermined angle of inclination without etching in the vertical direction.

Next, as shown in FIG. 4 (d), the protective film 130 is removed. At this time, the polysilicon layer 120 stacked on the lower surface of the glass substrate 110 is also removed. Removal of the polysilicon layer 120 is preferably dry etching using a fluoride such as xenon difluoride (XeF ₂ ).

Next, as shown in FIG. 4E, the seed layer 140 is stacked on the entire surface of the lower surface of the glass substrate 110.

Next, as shown in FIG. 4F, the glass substrate 110 under the cavity 135 is further etched to fabricate the via hole 135 penetrating the upper and lower surfaces of the glass substrate 110. Accordingly, the seed layer 140 stacked on the lower surface of the glass substrate 110 is exposed through the via hole 135. In this case, the etching method may use a wet etching method or a dry etching method. The wet etching method is a method of etching using a chemical solution such as acetic acid solution, hydrofluoric acid, aqueous solution of phosphoric acid, etc., and the dry etching method is a method of etching using gas, plasma, ion beam, etc. to be. At this time, it is preferable that the side surface inside the via hole 135 is also etched flat so that the conductive material can be plated well in the steps described below.

Next, as shown in FIG. 4G, the polysilicon layer 120 stacked on the surface of the glass substrate 110 is removed. This is to prevent the electrical signal transmitted through the conductive material layer 150 and the electrode 160 from leaking through the polysilicon layer 120 in the following steps.

Next, as shown in FIG. 4 (h), the via hole 135 is filled with a conductive material. In this case, the plating process by the seed layer 140 can be used. Meanwhile, in FIG. 4H, the seed layer 140 is entirely stacked on the bottom surface of the glass substrate 110, but the seed layer 140 may be etched in a predetermined pattern for connection with the circuit device. .

Meanwhile, in order to manufacture a packaging substrate as illustrated in FIG. 3, the process illustrated in FIG. 4 (i) is additionally performed. That is, the conductive material is stacked on the upper surface of the conductive material layer 150 and the glass substrate 110 to manufacture the electrode 160.

5 is a vertical cross-sectional view showing a configuration of a circuit device chip packaged using a packaging substrate manufactured according to an embodiment of the present invention. Referring to FIG. 5, the device chip includes a packaging substrate 200, a base substrate 300, a circuit device 310, bumps 320a and b, and a connection portion 330. The base substrate 300 may be a general silicon substrate. Accordingly, after the circuit device 310 is mounted on the silicon substrate, the circuit board 310 is packaged by coupling the packaging substrate 200 using the bumps 320a and b.

The packaging substrate 200 has a structure as shown in FIGS. 2 and 3. That is, the glass substrate 210, the conductive material layer 220, the seed layer 230, and the electrode 240 are included. Accordingly, the upper and lower portions of the packaging substrate 200 may be electrically connected. Since the description of the structure of the packaging substrate 200 has been described above, further description thereof will be omitted.

 The circuit device 310 is electrically connected to the seed layer 230 and the connection part 330 formed on the lower surface of the packaging substrate 200. The connection part 330 may be implemented with a wire or a conductive bump. In the case of the conductive bumps, protrusions having a size of several tens of micrometers to hundreds of micrometers of gold, solder, or other metals are formed on pads (not shown) formed on the surface of the circuit device 310. Conductive bumps can be produced and used. The circuit device 310 may be various RF devices such as an acoustic resonator, a filter, a duplexer, and the like.

As described above, according to the present invention, the packaging substrate can be manufactured using the glass substrate. In the case of a glass substrate, the RF loss is low and the price is inexpensive. Thus, the packaging of the RF device is prevented from deteriorating the RF characteristic, and at the same time, the chip manufacturing cost can be reduced. In addition, since the glass substrate has better light transmittance than silicon or a high resistance silicon wafer, it can be usefully used when packaging an optical element. In addition, according to the present invention, in manufacturing a via hole for electrically connecting the upper and lower packaging substrate, by manufacturing the side surface inside the via hole has a predetermined inclination, it is possible to more easily manufacture the electrode for connecting to the external terminal. Will be.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

Claims (8)

Glass substrates; A seed layer having a flat plate stacked on a lower surface of the glass substrate; A via hole penetrating an upper surface and a lower surface of the glass substrate and having an inner side surface inclined at a predetermined angle; And, And a conductive material layer filling the via hole. The method of claim 1, And an electrode stacked on an upper surface of the glass substrate and electrically connected to the conductive material layer. (a) forming a cavity by etching a predetermined region of the upper surface of the glass substrate to a predetermined thickness; (b) depositing a seed layer in the form of a plate on a lower surface of the glass substrate; (c) further etching the glass substrate region in which the cavity is formed to fabricate a via hole penetrating the upper and lower surfaces of the glass substrate; And, (d) filling the via hole using a predetermined conductive material. The method of claim 3, In step (a), And etching the glass substrate using a sand blaster, such that an etching surface of the glass substrate has an inclination of a predetermined angle. The method of claim 4, wherein Step (c) is, And further etching the glass substrate using one of a wet etching method and a dry etching method to flatten the side surface of the cavity. The method of claim 4, wherein Stacking an electrode on an upper surface of the glass substrate and electrically connecting the conductive material to the conductive material. The method of claim 3, In step (a), Stacking a polysilicon layer on a surface of the glass substrate; Stacking a protective film of a predetermined type on a surface of the polysilicon layer laminated on the upper surface of the glass substrate; Forming a cavity by etching a polysilicon layer and a glass substrate in a region where the protective layer is not laminated using a sand blaster; And, Removing the polysilicon layer laminated on the lower surface of the glass substrate. The method of claim 7, wherein The protective film is a manufacturing method of a packaging substrate, characterized in that using a dry film resist (Dry Film Resist).

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