CN211183922U

CN211183922U - Quartz piezoelectric chip and wafer for increasing energy locking benefit

Info

Publication number: CN211183922U
Application number: CN202020206680.3U
Authority: CN
Inventors: 李宗杰
Original assignee: GUANGDONG FAILONG CRYSTAL TECHNOLOGY CO LTD
Current assignee: GUANGDONG FAILONG CRYSTAL TECHNOLOGY CO LTD
Priority date: 2020-02-25
Filing date: 2020-02-25
Publication date: 2020-08-04
Anticipated expiration: 2030-02-25

Abstract

The utility model provides an increase quartzy piezoelectric chip and wafer of energy shutting benefit, this wafer include the quartzy piezoelectric chip that the array was arranged, quartzy piezoelectric chip has a basement, the upper surface and the lower surface symmetry of basement one end are provided with the recess, the recess middle part is provided with the boss, the degree of depth that highly is less than the recess of boss. The quartz piezoelectric wafer has a groove type double-lug boss crystal structure, and a groove area between a lug boss and the edge of a substrate forms a first energy trap area of the wafer; the boss is a main oscillation area of the wafer, and the height of the boss is smaller than the depth of the groove to form a second energy trap area of the wafer; therefore, the groove type double-boss structure of the quartz piezoelectric wafer forms a double energy trap effect on the wafer, and the energy locking benefit of the wafer is greatly increased, so that the impedance of the whole wafer is reduced, and finally the whole crystal oscillator has very good low-frequency physical characteristics.

Description

Quartz piezoelectric chip and wafer for increasing energy locking benefit

Technical Field

The utility model relates to a piezoelectric chip technical field especially relates to a quartz piezoelectric chip and wafer of increase energy shutting benefit.

Background

Quartz lithography crystals generally refer to wafers that are fabricated by photolithography techniques to form structures on the surface of a quartz wafer, including raised (Mesa) and recessed (Inverted Mesa) three-dimensional structures. In the conventional process, the mechanical polishing process is used to develop miniaturized quartz crystal, and besides the physical property of the quartz crystal has its size limit, the factors such as the increase of impedance and the reduction of yield rate caused by miniaturization will be the bottleneck. Technically, the low-frequency small quartz crystal also needs to be chamfered (below), that is, the edge of the quartz crystal is thinned, so as to achieve effective Energy Trapping (Energy Trapping) and increase the Energy blocking efficiency. Therefore, in the manufacture of ultra-small quartz crystal and low-frequency quartz crystal, it will be the most important technical gap for manufacturers who rely on the traditional grinding method to manufacture quartz crystal.

The design appearance of the chips seen in the market at present is that after the periphery of a single chip frame is etched and hollowed, electrodes on the upper surface and the lower surface are plated, and then the chips are taken down one by one in a way of pulling off the chips, the method is mainly a process developed under the development of miniaturization trend because the thickness of a quartz wafer is thinner, and has the advantages that the precision of the chip frame and the precision of the plated electrodes are the precision degree of the photoetching grade, so that the consistency of batch production can be ensured; the drawback is that the space for etching the hollow-out region and the chip supporting region must be reserved, which results in a significant reduction of about 30-50% in the number of chips that can be produced per quartz photolithographic wafer. Another method is similar to the semiconductor wafer cutting method: the etched quartz crystal is cut and taken down one by one, and because of no side electrode, the upper and lower electrodes of the chip can not be conducted, and further measurement can not be carried out, and the subsequent process is required. In the prior art, the specification entitled quartz photolithographized wafer and dicing technique (publication No. CN110027123A, published: 2019-07-19) discloses how to produce ultra-small quartz crystals by photolithography and laser dicing and greatly increase the chip number of the wafer; meanwhile, the prior art only aims at the high-frequency (>50MHz) small quartz wafer, but does not effectively improve the energy locking benefit of the low-frequency small quartz wafer, so that the improvement is particularly necessary.

SUMMERY OF THE UTILITY MODEL

The utility model provides an increase quartzy piezoelectric wafer of energy shutting benefit has solved small-size wafer and has been difficult to the technical problem who increases energy shutting benefit when resonant frequency is lower.

In order to solve the technical problem, the utility model discloses the technical scheme who takes is: the utility model provides an increase quartzy piezoelectric wafer of energy shutting benefit, quartzy piezoelectric wafer has a basement, the upper surface and the lower surface symmetry of basement one end are provided with the recess, the recess middle part is provided with the boss, the height of boss is less than the degree of depth of recess.

Further, the height of boss is h, the degree of depth of recess is d, and satisfies the following conditional expression:

h/d＝0.1～0.9。

preferably, h/d is 0.8.

Preferably, the depth of the groove is 1-30 microns.

Further, the battery further comprises a first electrode film and a second electrode film, wherein the first electrode film is arranged on the surface of the boss, the second electrode film is arranged at the other end far away from the groove and comprises a first pin and a second pin, the first pin and the second pin are separated and arranged in an insulating mode, and the first pin is electrically connected with the first electrode film through a conductive film.

Furthermore, a first notch and a second notch are respectively formed in the position, close to the first pin and the second pin, of the substrate, a third electrode film is arranged on the surface of the first notch, a fourth electrode film is arranged on the surface of the second notch, the third electrode film is electrically connected with the first pin, and the fourth electrode film is electrically connected with the second pin.

Preferably, the groove is a circular groove or a rectangular groove.

Preferably, the boss is a circular boss or a rectangular boss.

A wafer comprises a plurality of quartz piezoelectric chips, wherein the quartz piezoelectric chips are distributed in an array mode, and a first gap and a second gap between every two adjacent quartz piezoelectric chips form a hollow-out area of the quartz piezoelectric wafer. The hollow area provides convenience for leading out the pins without additionally welding leading-out points.

Drawings

FIG. 1 is a schematic diagram of a quartz piezoelectric wafer for increasing energy locking efficiency according to the present invention;

FIG. 2 is a side-by-side schematic view of the quartz piezoelectric wafers of FIG. 1;

fig. 3 is a schematic structural diagram of a wafer according to the present invention.

Detailed Description

The following embodiments of the present invention will be specifically explained with reference to the accompanying drawings, which are only used for reference and illustration, and do not limit the scope of the present invention.

As shown in fig. 1 to 3, a wafer 100 includes a plurality of quartz piezoelectric chips 10, where the quartz piezoelectric chips 10 are distributed in an array, and a first gap 6 and a second gap 7 between two adjacent quartz piezoelectric chips 10 form a hollow area of the quartz piezoelectric wafer 100. The wafer 100 is subjected to photolithography and laser cutting processes of the prior art to produce the quartz piezoelectric chip 10 of the present invention.

The quartz piezoelectric wafer 10 is provided with a substrate 1, grooves 2 are symmetrically formed in the upper surface and the lower surface of one end of the substrate 1, a boss 3 is arranged in the middle of each groove 2, and the height of each boss 3 is smaller than the depth of each groove 2. A first energy trap area of the wafer is formed in the groove 2 area between the lug boss and the edge of the substrate 1; the boss 3 is the main oscillation area of the wafer, and the height of the boss 3 is smaller than the depth of the groove 2, and the second energy trap area of the wafer is formed, so that the groove type double boss structure of the quartz piezoelectric wafer forms a double energy trap effect on the wafer, the energy locking benefit of the wafer is greatly increased, and the impedance of the whole wafer is reduced.

As a further improvement of this embodiment, the height of the boss 3 is h, the depth of the groove 2 is d, and the following conditional expression is satisfied: h/d is 0.1-0.9.

In this example, h/d is 0.8.

Preferably, the depth of the groove 2 is 1 to 30 micrometers. Specifically, the depth of the groove 2 is 15 μm.

As a further improvement of the present embodiment, the liquid crystal display device further includes a first electrode film 4 and a second electrode film 5, the first electrode film 4 is disposed on the surface of the boss 3, the second electrode film 5 is disposed at the other end away from the groove 2, the second electrode film 5 includes a first pin 51 and a second pin 52, the first pin 51 and the second pin 52 are separately and insulatively disposed, and the first pin 51 is electrically connected to the first electrode film 4 through a conductive thin film 45.

Preferably, the substrate 1 is provided with a first notch 6 and a second notch 7 respectively near the first pin 51 and the second pin 52, a third electrode film 8 is disposed on the surface of the first notch 6, a fourth electrode film 9 is disposed on the surface of the second notch 7, the third electrode film 8 is electrically connected to the first pin 51, and the fourth electrode film 9 is electrically connected to the second pin 52.

Preferably, the groove 2 is a circular groove or a rectangular groove.

Preferably, the boss 3 is a circular boss or a rectangular boss. The size and the shape of the groove and the concave platform are set according to actual needs.

The above disclosure is only for the preferred embodiments of the present invention, and the scope of the present invention should not be limited thereby, and the scope of the present invention is not intended to be limited thereby.

Claims

1. A quartz piezoelectric wafer for increasing energy locking efficiency is characterized in that: the quartz piezoelectric wafer is provided with a substrate, grooves are symmetrically formed in the upper surface and the lower surface of one end of the substrate, a boss is arranged in the middle of each groove, and the height of each boss is smaller than the depth of each groove.

2. The quartz piezoelectric wafer for increasing energy locking efficiency according to claim 1, wherein the height of the boss is h, the depth of the groove is d, and the following conditional expression is satisfied:

h/d＝0.1～0.9。

3. the quartz piezoelectric wafer for increasing energy locking efficiency according to claim 2, wherein: h/d is 0.8.

4. A quartz piezoelectric wafer for increasing energy locking efficiency as claimed in claim 3, wherein: the depth of the groove is 1-30 microns.

5. The quartz piezoelectric wafer for increasing energy locking efficiency according to claim 1, wherein: still include first electrode film and second electrode film, first electrode film sets up the surface of boss, the second electrode film sets up the other end of keeping away from the recess, and this second electrode film includes first pin and second pin, first pin and the separation of second pin and insulating setting, first pin with first electrode film passes through conducting film electric connection.

6. The quartz piezoelectric wafer for increasing energy locking efficiency according to claim 5, wherein: the base is provided with a first notch and a second notch respectively at positions close to the first pin and the second pin, a third electrode film is arranged on the surface of the first notch, a fourth electrode film is arranged on the surface of the second notch, the third electrode film is electrically connected with the first pin, and the fourth electrode film is electrically connected with the second pin.

7. The quartz piezoelectric wafer for increasing energy locking efficiency according to claim 1, wherein: the groove is a circular groove or a rectangular groove.

8. The quartz piezoelectric wafer for increasing energy locking efficiency according to claim 1, wherein: the boss is a circular boss or a rectangular boss.

9. A wafer, characterized by comprising a plurality of quartz piezoelectric chips according to any one of claims 1 to 8, wherein the quartz piezoelectric chips are distributed in an array, and the first gap and the second gap between two adjacent quartz piezoelectric chips form a hollow area of the quartz piezoelectric wafer.