WO2024027049A1 - 一种超导量子芯片及其参数确定方法 - Google Patents
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Definitions
- the invention relates to the field of quantum chips, and in particular to a superconducting quantum chip and a parameter determination method thereof.
- Quantum chips are the core components of quantum computers, mainly including superconducting system quantum chips, semiconductor quantum chips, quantum dot chips, ion traps and NV (diamond) color centers.
- quantum chips of superconducting systems usually use structures such as qubits, read cavities, resonators, Josephson junctions, microwave lines and ports formed on the substrate.
- the resonators in traditional superconducting quantum chips all use coplanar waveguides with uniform impedance, that is, the resonators are Coplanar Waveguide-Uniformity Impedance Resonator (CPW-UIR), and the resonator length is ⁇ . g /4, where ⁇ g is the waveguide wavelength corresponding to the resonant frequency.
- CPW-UIR Coplanar Waveguide-Uniformity Impedance Resonator
- the requirements for quantum chip integration are also getting higher and higher.
- the resonators are laid out in the form of meandering lines, but this layout still has a large of space occupied.
- the object of the present invention is to provide a superconducting quantum chip and a parameter determination method thereof, so as to reduce the size of the superconducting quantum chip.
- the specific plan is as follows:
- a superconducting quantum chip includes a chip substrate and a quantum module formed on the chip substrate.
- the quantum module includes a bit capacitor unit, a read line unit, and a Josephson junction unit.
- the quantum module also includes a common Surface waveguide-step impedance resonator unit.
- the coplanar waveguide-step impedance resonator unit is specifically a coplanar waveguide-2-step step impedance resonator unit.
- the coplanar waveguide-step impedance resonator unit is specifically a coplanar waveguide-3-step step impedance resonator unit.
- the bit capacitor unit is specifically a cross-structured bit capacitor unit.
- the reading line unit is specifically a transmission line with a coplanar waveguide structure.
- the coplanar waveguide-step impedance resonator unit is specifically a ⁇ g /4 type coplanar waveguide-step impedance resonator unit, where ⁇ g is the coplanar waveguide-step impedance resonator unit.
- the waveguide wavelength corresponding to the resonant frequency.
- this application also discloses a parameter determination method for a superconducting quantum chip, which is applied to any of the above superconducting quantum chips, including:
- the characteristic impedance of each order transmission line of the coplanar waveguide-step impedance resonator unit determine the characteristic impedance of each order transmission line of the coplanar waveguide-step impedance resonator unit and use it as the characteristic impedance parameter;
- the curvilinear relationship between the electrical length of the characteristic line and the total electrical length is determined; the total electrical length is specifically the sum of the electrical lengths of all the characteristic lines;
- the electrical length corresponding to the preset accuracy is determined respectively, so that the electrical length is used as the transmission line of each stage of the coplanar waveguide-step impedance resonator unit. electrical length parameter.
- the coplanar waveguide-step impedance resonator unit is a coplanar waveguide-2-step step impedance resonator unit;
- the characteristic impedance ratio of the characteristic impedance of the second-order characteristic line and the characteristic impedance of the first-order characteristic line is calculated.
- the process of determining the curve relationship between the electrical length of the characteristic line and the total electrical length under the characteristic impedance ratio includes:
- the process of determining the electrical length corresponding to the preset accuracy within the electrical length interval of the characteristic line at each stage includes:
- a second-level electrical length parameter of the second-level characteristic line is determined.
- This application discloses a superconducting quantum chip, which includes a chip substrate and a quantum module formed on the chip substrate.
- the quantum module includes a bit capacitor unit, a read line unit, and a Josephson junction unit.
- the quantum module also includes a coplanar waveguide-step impedance resonator unit.
- a coplanar waveguide-step impedance resonator unit is used to realize the function of the resonator.
- Figure 1 is a structural distribution diagram of a superconducting quantum chip in an embodiment of the present invention
- Figure 2 is a structural distribution diagram of a coplanar waveguide-uniform impedance resonator unit in an embodiment of the present invention
- Figure 3 is a step flow chart of a method for determining parameters of a superconducting quantum chip in an embodiment of the present invention
- Figure 4 is a structural distribution diagram of a coplanar waveguide-2-step step impedance resonator unit in an embodiment of the present invention
- Figure 5 is a graph showing the relationship between the electrical length ⁇ 1 and the normalized electrical length Ln in the embodiment of the present invention.
- Figures 6a and 6b are respectively structural distribution diagrams of the superconducting quantum chip and the traditional superconducting quantum chip in this embodiment
- Figures 7a and 7b are simulation results of the single-bit superconducting quantum chip in this embodiment.
- Figures 8a and 8b show the simulation results of a traditional single-bit superconducting quantum chip.
- the requirements for quantum chip integration are also getting higher and higher.
- the resonators are laid out in the form of meandering lines, but this layout still has a large of space occupied.
- a coplanar waveguide-step impedance resonator unit is used to realize the function of the resonator. Due to the physical characteristics of the coplanar waveguide-step impedance resonator unit, under the same parallel resonance conditions, compared with The electrical length of uniform impedance resonators and step impedance resonators is significantly smaller, thereby reducing the layout size of a single qubit, making the size of a quantum chip with a specific number of bits smaller, the quantum chip having a higher degree of freedom, and the quantum chip integration being improved. .
- FIG. 1 is a structural diagram of a superconducting quantum chip applied to a single-bit superconducting quantum chip.
- the superconducting quantum chip includes a chip substrate 10 and a
- the quantum module on the chip substrate 10 includes a bit capacitor unit 20, a read line unit 30, and a Josephson junction unit.
- the quantum module also includes a coplanar waveguide-step impedance resonator unit 40.
- the bit capacitor unit 20 formed on the chip substrate 10 is specifically a cross-structured bit capacitor unit; further, the read line unit 30 formed on the chip substrate 10 is specifically a coplanar waveguide. Structural CPW transmission lines.
- the coplanar waveguide-step impedance resonator unit 40 mainly includes a coplanar waveguide-step impedance resonator (CPW-SIR), which is composed of two or more with different characteristic impedances.
- CPW-SIR coplanar waveguide-step impedance resonator
- Coplanar Waveguide, coplanar waveguide The characteristic impedance of a transmission line.
- the physical size of the resonator can be adjusted within a certain range with changes in the electrical length relationship and characteristic impedance relationship of multiple CPW transmission lines, which serves as the basis for the miniaturization design of the superconducting quantum chip in this embodiment.
- the coplanar waveguide-step impedance resonator unit is specifically a ⁇ g /4 type coplanar waveguide-step impedance resonator unit, where ⁇ g is the coplanar waveguide-step impedance resonator unit.
- the resonant frequency corresponds to the waveguide wavelength.
- the coplanar waveguide-step impedance resonator unit can usually be selected, specifically the coplanar waveguide-2-step step impedance resonator unit, or Coplanar waveguide-3-step step impedance resonator unit.
- This application discloses a superconducting quantum chip, which includes a chip substrate and a quantum module formed on the chip substrate.
- the quantum module includes a bit capacitor unit, a read line unit, and a Josephson junction unit.
- the quantum module also includes a coplanar waveguide-step impedance resonator unit.
- a coplanar waveguide-step impedance resonator unit is used to realize the function of the resonator.
- embodiments of the present application also disclose a parameter determination method for a superconducting quantum chip, which can be applied to any of the above superconducting quantum chips, as shown in Figure 3, including:
- the preset accuracy is set based on actual processing capabilities or design requirements. It is known that the coplanar waveguide-step impedance resonator unit includes multi-stage transmission lines, and the characteristic impedance of each stage transmission line is determined respectively.
- S3 Determine the curve relationship between the electrical length of the characteristic line and the total electrical length under the characteristic impedance ratio; the total electrical length is specifically the sum of the electrical lengths of all characteristic lines;
- the coplanar waveguide-step impedance resonator unit 40 mainly includes a coplanar waveguide-step impedance resonator (CPW-SIR), which is composed of two or more with different characteristic impedances.
- CPW-SIR coplanar waveguide-step impedance resonator
- a transverse electromagnetic field or quasi-transverse electromagnetic field mode resonator composed of CPW transmission lines, where ⁇ 1, ⁇ 2... ⁇ n are the electrical lengths of different sections of CPW transmission lines, and Z1, Z2...Zn are respectively CPW (Coplanar Waveguide, coplanar) sections. waveguide) characteristic impedance of a transmission line.
- the physical size of the resonator can be adjusted within a certain range with changes in the electrical length relationship and characteristic impedance relationship of multiple CPW transmission lines, which serves as the basis for the miniaturization design of the superconducting quantum chip in this embodiment.
- the coplanar waveguide-step impedance resonator unit is a coplanar waveguide-2-step step impedance resonator unit; taking the coplanar waveguide-2-step step impedance resonator unit as an example, its structure
- the graph is shown in Figure 4. Ignoring the node step discontinuity and the edge capacitance of the open section, the input impedance Zin can be approximately expressed as:
- the resonance conditions of the coplanar waveguide-2-step step impedance resonator unit are not only related to the electrical length ⁇ 1 and ⁇ 2, but also related to the characteristic impedance ratio Rz.
- the structure only depends on the electrical length of the CPW transmission line.
- the coplanar waveguide-2-step step impedance resonator unit has an additional parameter, characteristic impedance ratio Rz, to adjust the total electrical length of the resonator unit.
- the total electrical length ⁇ total of the coplanar waveguide-2-step step impedance resonator unit is specifically:
- the corresponding electrical length of the CPW-UIR in the traditional superconducting quantum chip is ⁇ /2.
- the normalized electrical length Ln of the coplanar waveguide-2-order step impedance resonator unit can be obtained as :
- the relationship curve between the electrical length ⁇ 1 and the normalized electrical length Ln is shown in Figure 5. It can be seen that when Rz>1, the normalized electrical length Ln has a maximum value. value exists. At this time, the electrical length of CPW-UIR is less than the total electrical length ⁇ total of the coplanar waveguide-2-order step impedance resonator unit in this embodiment. On the contrary, when Rz ⁇ 1, the normalized electrical lengths all have polarity.
- the electrical length of CPW-UIR is greater than the total electrical length ⁇ total of the coplanar waveguide-2-order step impedance resonator unit in this embodiment, so the coplanar waveguide-2-order step impedance resonator unit with Rz ⁇ 1 is selected. , the total electrical length ⁇ total can be reduced.
- Other multi-order coplanar waveguide-step impedance resonator units also have such characteristics, and this theory can be applied to the miniaturization design of superconducting quantum chips.
- a coplanar waveguide-2-step step impedance resonator unit or a coplanar waveguide-3-step step impedance resonator unit is selected as the coplanar waveguide-step impedance resonator unit.
- step S2 is a process of calculating the characteristic impedance ratio between the characteristic impedances of all characteristic lines.
- step S3 is a process of determining the curve relationship between each characteristic line and the total electrical length of all characteristic lines under the characteristic impedance ratio, including:
- step S5 is a process of determining the electrical length corresponding to the preset accuracy within the electrical length interval of each stage characteristic line, including:
- the second-order electrical length parameter of the second-order characteristic line is determined.
- the planar waveguide-step impedance resonator unit is specifically a coplanar waveguide-2-step step impedance resonator unit.
- the process of calculating the coplanar waveguide-2-step step impedance resonator unit is as follows:
- the characteristic impedance parameters are determined including: the characteristic impedance Z1 of the first-order characteristic line is approximately 74 ⁇ , and the characteristic impedance ZW of the second-order characteristic line is approximately 38 ⁇ ;
- the minimum total electrical length interval can be selected as the first 1/n between the minimum value and the maximum value on the curve relationship Ln.
- an electrical length that meets the preset accuracy requirements is determined for easy design or processing as the first-order electrical length parameter of the first-order characteristic line.
- the second-order characteristics can be determined. The second-order electrical length parameter of the line.
- the total electrical length of all characteristic lines in the coplanar waveguide-step impedance resonator unit is approximately 3437.053um, and the layout area of the meandering line part is 914um ⁇ 123.7um; in the same Under parallel resonance conditions, the length of the resonator in a traditional single-bit superconducting quantum chip is about 4277.244um, and the layout area of the meandering line part is 1152um ⁇ 123.7um.
- the simulation results of the traditional single-bit superconducting quantum chip is 6.1978GHz.
- the size of the resonator based on the coplanar waveguide-2-order step impedance resonator unit is smaller than that of the traditional UIR. about 19.6%.
- step S3 determine the curvilinear relationship in which the electrical length of the characteristic line with the characteristic impedance as the denominator is the independent variable and the total electrical length of all characteristic lines is the dependent variable under the specific multiple characteristic impedance ratios of the group; subsequently, in this Under the curve relationship, determining the minimum total electrical length interval, the electrical length interval of the independent variable, and determining the specific electrical length parameters are all similar to the above, and will not be described again here.
- a coplanar waveguide-step impedance resonator unit is used to realize the function of the resonator. Due to the physical characteristics of the coplanar waveguide-step impedance resonator unit, under the same parallel resonance conditions, compared with The electrical length of uniform impedance resonators and step impedance resonators is significantly smaller, thereby reducing the layout size of a single qubit, making the size of a quantum chip with a specific number of bits smaller, the quantum chip having a higher degree of freedom, and the quantum chip integration being improved. .
Abstract
一种超导量子芯片及其参数确定方法，涉及量子芯片领域，该超导量子芯片包括芯片衬底和形成于所述芯片衬底上的量子模块，所述量子模块包括比特电容单元、读取线单元、约瑟夫森结单元，所述量子模块还包括共面波导-阶跃阻抗谐振器单元。本申请的超导量子芯片中以共面波导-阶跃阻抗谐振器单元来实现谐振器的功能，由于共面波导-阶跃阻抗谐振器单元的物理特性，在同一并联谐振条件下，相比均匀阻抗谐振器，阶跃阻抗谐振器的电长度明显更小，进而缩小了单个量子比特的布局尺寸，使得特定比特数的量子芯片尺寸更小、量子芯片自由度更高，量子芯片集成度提高。
Description
本申请要求于2022年08月03日提交中国专利局、申请号为202210928530.7、申请名称为“一种超导量子芯片及其参数确定方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本发明涉及量子芯片领域，特别涉及一种超导量子芯片及其参数确定方法。
量子芯片是量子计算机的核心部件，主要包括超导体系量子芯片、半导体量子芯片、量子点芯片、离子阱及NV(金刚石)色心等。目前，超导体系的量子芯片通常采用在衬底上形成量子比特、读取腔、谐振器、约瑟夫森结、微波线路及端口等结构。
传统的超导量子芯片中谐振器均采用均匀阻抗形式的共面波导，也即谐振器为共面波导-均匀阻抗谐振器(Coplanar Waveguide-Uniformity Impedance Resonator，CPW-UIR)，谐振器长度为λ
g/4，其中λ
g为谐振频率对应的波导波长。
随着对量子计算机计算能力需求的提升，对于量子芯片集成度的要求也越来越高，传统超导量子芯片为了缩小尺寸，谐振器以蜿蜒线形式布局，但是这种布局仍然具有较大的空间占用。
因此，如何提供一种解决上述技术问题的方案是目前本领域技术人员需要解决的问题。
发明内容
有鉴于此，本发明的目的在于提供一种超导量子芯片及其参数确定方法，以缩小超导量子芯片的尺寸。其具体方案如下：
一种超导量子芯片，包括芯片衬底和形成于所述芯片衬底上的量子模块，所述量子模块包括比特电容单元、读取线单元、约瑟夫森结单元，所 述量子模块还包括共面波导-阶跃阻抗谐振器单元。
优选的，所述共面波导-阶跃阻抗谐振器单元具体为共面波导-2阶阶跃阻抗谐振器单元。
优选的，所述共面波导-阶跃阻抗谐振器单元具体为共面波导-3阶阶跃阻抗谐振器单元。
优选的，所述比特电容单元具体为十字结构的比特电容单元。
优选的，所述读取线单元具体为共面波导结构的传输线。
优选的，所述共面波导-阶跃阻抗谐振器单元具体为λ
g/4型共面波导-阶跃阻抗谐振器单元，其中λ
g为所述共面波导-阶跃阻抗谐振器单元的谐振频率对应的波导波长。
相应的，本申请还公开了一种超导量子芯片的参数确定方法，应用于如上文任一项所述超导量子芯片，包括：
根据预设精度，确定共面波导-阶跃阻抗谐振器单元的每阶传输线的特征阻抗并作为特征阻抗参数；
计算所有所述特征线的所述特征阻抗之间的特征阻抗比；
确定所述特征阻抗比下，所述特征线的电长度与总电长度的曲线关系；所述总电长度具体为所有所述特征线的所述电长度的和；
根据所述曲线关系，确定所述总电长度的最小总电长度区间及其对应的所述特征线的电长度区间；
在每阶所述特征线的电长度区间内，分别确定对应所述预设精度的所述电长度，以将所述电长度作为所述共面波导-阶跃阻抗谐振器单元的每阶传输线的电长度参数。
优选的，所述共面波导-阶跃阻抗谐振器单元为共面波导-2阶阶跃阻抗谐振器单元；
所述计算所有所述特征线的所述特征阻抗之间的特征阻抗比的过程包括：
计算第2阶所述特征线的所述特征阻抗和第1阶所述特征线的所述特征阻抗的特征阻抗比。
优选的，所述确定所述特征阻抗比下，所述特征线的电长度与总电长 度的曲线关系的过程，包括：
确定所述特征阻抗比下，第1阶所述特征线与总电长度的曲线关系。
优选的，所述在每阶所述特征线的电长度区间内，分别确定对应所述预设精度的所述电长度的过程，包括：
在第1阶所述特征线的电长度区间内，确定对应所述预设精度的所述电长度作为第1阶所述特征线的第1阶电长度参数；
根据所述曲线关系，确定第1阶所述电长度参数对应的所述总电长度；
根据所述总电长度和第1阶所述电长度参数，确定第2阶所述特征线的第2阶电长度参数。
本申请公开了一种超导量子芯片，包括芯片衬底和形成于所述芯片衬底上的量子模块，所述量子模块包括比特电容单元、读取线单元、约瑟夫森结单元，所述量子模块还包括共面波导-阶跃阻抗谐振器单元。本申请的超导量子芯片中以共面波导-阶跃阻抗谐振器单元来实现谐振器的功能，由于共面波导-阶跃阻抗谐振器单元的物理特性，在同一并联谐振条件下，相比均匀阻抗谐振器，阶跃阻抗谐振器的电长度明显更小，进而缩小了单个量子比特的布局尺寸，使得特定比特数的量子芯片尺寸更小、量子芯片自由度更高，量子芯片集成度提高。
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例中一种超导量子芯片的结构分布图；
图2为本发明实施例中一种共面波导-均匀阻抗谐振器单元的结构分布图；
图3为本发明实施例中一种超导量子芯片的参数确定方法的步骤流程图；
图4为本发明实施例中一种共面波导-2阶阶跃阻抗谐振器单元的结构 分布图；
图5为本发明实施例中电长度θ1与归一化电长度Ln的关系曲线图；
图6a和图6b分别为本实施例中超导量子芯片和传统超导量子芯片的结构分布图；
图7a和图7b为本实施例中单比特超导量子芯片的仿真结果图；
图8a和图8b为传统单比特超导量子芯片的仿真结果图。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
随着对量子计算机计算能力需求的提升，对于量子芯片集成度的要求也越来越高，传统超导量子芯片为了缩小尺寸，谐振器以蜿蜒线形式布局，但是这种布局仍然具有较大的空间占用。
本申请的超导量子芯片中以共面波导-阶跃阻抗谐振器单元来实现谐振器的功能，由于共面波导-阶跃阻抗谐振器单元的物理特性，在同一并联谐振条件下，相比均匀阻抗谐振器，阶跃阻抗谐振器的电长度明显更小，进而缩小了单个量子比特的布局尺寸，使得特定比特数的量子芯片尺寸更小、量子芯片自由度更高，量子芯片集成度提高。
本发明实施例公开了一种超导量子芯片，参见图1所示，图1为该超导量子芯片应用于单比特超导量子芯片的结构图，超导量子芯片包括芯片衬底10和形成于芯片衬底10上的量子模块，量子模块包括比特电容单元20、读取线单元30、约瑟夫森结单元，量子模块还包括共面波导-阶跃阻抗谐振器单元40。
在一些具体的实施例中，形成于芯片衬底10上的比特电容单元20具体为十字结构的比特电容单元；进一步的，形成于芯片衬底10上的读取线单元30具体为共面波导结构CPW的传输线。
可以理解的是，共面波导-阶跃阻抗谐振器单元40主要包括共面波导-阶跃阻抗谐振器(Coplanar Waveguide-Step Impedance Resonator，CPW-SIR)，是由两个及以上具有不同特征阻抗的CPW传输线组合而成的横向电磁场或准横向电磁场模式的谐振器，参见图2所示，其中θ1、θ2…θn分别为不同段CPW传输线的电长度，Z1、Z2…Zn分别为各段CPW(Coplanar Waveguide，共面波导)传输线的特征阻抗。随着CPW传输线数量的增加，谐振器物理尺寸在一定范围内能够随多段CPW传输线的电长度关系、特征阻抗关系的变化进行调整，进而作为本实施例中超导量子芯片小型化设计的依据。
在一些具体的实施例中，共面波导-阶跃阻抗谐振器单元具体为λ
g/4型共面波导-阶跃阻抗谐振器单元，其中λ
g为共面波导-阶跃阻抗谐振器单元的谐振频率对应的波导波长。
进一步的，考虑到谐振腔单元的加工精度和小型化效果两方面的影响，通常可选择共面波导-阶跃阻抗谐振器单元具体为共面波导-2阶阶跃阻抗谐振器单元，或为共面波导-3阶阶跃阻抗谐振器单元。
根据本实施例中的描述，一个具体的超导量子芯片的参数可包括：芯片衬底10为Si硅片，其介电常数ε
r＝11.9，厚度为500um；读取线单元30线宽为10um，槽宽5um；共面波导-阶跃阻抗谐振器单元具体为共面波导-2阶阶跃阻抗谐振器单元，其中第1阶特征线，即Z1段CPW传输线特征阻抗约为74Ω，对应中心线线宽w＝2um，槽线宽s＝5um，第2阶特征线，即Z2段CPW传输线特征阻抗约为38Ω，对应中心线线宽w＝8um，槽线宽s＝2um。
本申请公开了一种超导量子芯片，包括芯片衬底和形成于所述芯片衬底上的量子模块，所述量子模块包括比特电容单元、读取线单元、约瑟夫森结单元，所述量子模块还包括共面波导-阶跃阻抗谐振器单元。本申请的超导量子芯片中以共面波导-阶跃阻抗谐振器单元来实现谐振器的功能，由于共面波导-阶跃阻抗谐振器单元的物理特性，在同一并联谐振条件下，相比均匀阻抗谐振器，阶跃阻抗谐振器的电长度明显更小，进而缩小了单个量子比特的布局尺寸，使得特定比特数的量子芯片尺寸更小、量子芯片自 由度更高，量子芯片集成度提高。
相应的，本申请实施例还公开了一种超导量子芯片的参数确定方法，应用于如上文任一项超导量子芯片，参见图3所示，包括：
S1：根据预设精度，确定共面波导-阶跃阻抗谐振器单元的每阶传输线的特征阻抗并作为特征阻抗参数；
其中，预设精度根据实际加工能力或设计需求进行设定。已知共面波导-阶跃阻抗谐振器单元包括多阶传输线，分别确定每阶传输线的特征阻抗。
S2：计算所有特征线的特征阻抗之间的特征阻抗比；
S3：确定特征阻抗比下，特征线的电长度与总电长度的曲线关系；总电长度具体为所有特征线的电长度的和；
S4：根据曲线关系，确定最小总电长度区间及其对应的各特征线的电长度区间；
S5：在每阶特征线的电长度区间内，分别确定对应预设精度的电长度，以将电长度作为共面波导-阶跃阻抗谐振器单元的每阶传输线的电长度参数。
可以理解的是，共面波导-阶跃阻抗谐振器单元40主要包括共面波导-阶跃阻抗谐振器(Coplanar Waveguide-Step Impedance Resonator，CPW-SIR)，是由两个及以上具有不同特征阻抗的CPW传输线组合而成的横向电磁场或准横向电磁场模式的谐振器，其中θ1、θ2…θn分别为不同段CPW传输线的电长度，Z1、Z2…Zn分别为各段CPW(Coplanar Waveguide，共面波导)传输线的特征阻抗。随着CPW传输线数量的增加，谐振器物理尺寸在一定范围内能够随多段CPW传输线的电长度关系、特征阻抗关系的变化进行调整，进而作为本实施例中超导量子芯片小型化设计的依据。
在一些具体的实施例中，共面波导-阶跃阻抗谐振器单元为共面波导-2阶阶跃阻抗谐振器单元；以共面波导-2阶阶跃阻抗谐振器单元为例，其结构图如图4所示，忽略节阶跃非连续性和开路段的边缘电容，由传输线理论可将输入阻抗Zin近似表示为：
其并联谐振条件为：
Z2-Z1×tanθ1×tanθ2＝0；
进而有：
可以看出共面波导-2阶阶跃阻抗谐振器单元的谐振条件不仅与电长度θ1和θ2有关，还与特征阻抗比Rz有关，相比于共面波导-均匀阻抗谐振器CPW-UIR的结构只取决于CPW传输线的电长度，共面波导-2阶阶跃阻抗谐振器单元多了一个参数特征阻抗比Rz来调整谐振器单元的总电长度。
进一步的，共面波导-2阶阶跃阻抗谐振器单元的总电长度θtotal具体为：
θtotal＝θ1+θ2＝θ1+arctan(Rz/tanθ1)；
此时，对应传统超导量子芯片中CPW-UIR的电长度为π/2，对θtotal归一化处理后可得到共面波导-2阶阶跃阻抗谐振器单元的归一化电长度Ln为：
进一步的，对于不同的特征阻抗比Rz，电长度θ1与归一化电长度Ln的关系曲线如图5所示，可以看到，当Rz＞1时，归一化电长度Ln均有极大值存在，此时CPW-UIR的电长度小于本实施例中共面波导-2阶阶跃阻抗谐振器单元的总电长度θtotal，相反的，当Rz＜1时，归一化电长度均有极小值存在，CPW-UIR的电长度大于本实施例中共面波导-2阶阶跃阻抗谐振器单元的总电长度θtotal，因此选择Rz＜1的共面波导-2阶阶跃阻抗谐振器单元，可缩小总电长度θtotal，其他多阶的共面波导-阶跃阻抗谐振器单元同样具有这样的特性，进而将该理论应用于超导量子芯片的小型化设计中。考虑产品精度和效益，一般选择共面波导-2阶阶跃阻抗谐振器单元或共面波导-3阶阶跃阻抗谐振器单元作为共面波导-阶跃阻抗谐振器单元。
在一些具体的实施例中，当共面波导-阶跃阻抗谐振器单元为共面波导-2阶阶跃阻抗谐振器单元，步骤S2计算所有特征线的特征阻抗之间的特征阻抗比的过程包括：
计算第2阶特征线的特征阻抗和第1阶特征线的特征阻抗的特征阻抗比。
进一步的，步骤S3确定特征阻抗比下，各特征线与所有特征线的总电长度的曲线关系的过程，包括：
确定特征阻抗比下，第1阶特征线与所有特征线的总电长度的曲线关系。
进一步的，步骤S5在每阶特征线的电长度区间内，分别确定对应预设精度的电长度的过程，包括：
在第1阶特征线的电长度区间内，确定对应预设精度的电长度作为第1阶特征线的第1阶电长度参数；
根据曲线关系，确定第1阶电长度参数对应的总电长度；
根据总电长度和第1阶电长度参数，确定第2阶特征线的第2阶电长度参数。
以一个具体的超导量子谐振器为例，其芯片衬底10为Si硅片，其介电常数ε
r＝11.9，厚度为500um；读取线单元30线宽为10um，槽宽5um；共面波导-阶跃阻抗谐振器单元具体为共面波导-2阶阶跃阻抗谐振器单元，计算共面波导-2阶阶跃阻抗谐振器单元的过程如下：
根据预设精度，确定特征阻抗参数包括：第1阶特征线的特征阻抗Z1约为74Ω，第2阶特征线的特征阻抗ZW约为38Ω；
计算所有特征线的特征阻抗之间的特征阻抗比为
确定该特征阻抗比下，第1阶特征线与所有特征线的总电长度的曲线关系，该曲线关系与图5中Rz＝0.5的曲线近似，可作为参考；
根据Rz＝0.514的曲线关系，确定最小总电长度区间及其对应的各特征线的电长度区间，其中最小总长度区间中元素包括曲线关系Ln的极小值，但考虑设计要求，并不一定要直接选择极小值，仅从接近最小值的结果中选择一个便于加工的数据即可，因此最小总电长度区间可选择为曲线关系 Ln上最小值到最大值之间的前1/n的区间，n可根据实际设计需求进行调整，例如n＝3时取曲线关系中Ln最小的前1/3的区间作为最小总电长度区间，进而再确定对应的第1阶特征线的电长度区间。
进一步的，第1阶特征线的电长度区间内确定便于设计或加工的满足预设精度要求的一个电长度作为第1阶特征线的第1阶电长度参数，例如可取第1阶电长度参数为θ1＝45°，根据曲线关系，可确定第1阶电长度参数θ1＝45°时对应的总电长度，然后再根据总电长度和第1阶电长度参数θ1，可确定第2阶特征线的第2阶电长度参数。
如图6a和图6b所示，此时共面波导-阶跃阻抗谐振器单元中所有特征线的总电长度约为3437.053um，蜿蜒线部分的布局面积为914um×123.7um；在相同的并联谐振条件下，传统的单比特超导量子芯片中谐振器长度约为4277.244um，蜿蜒线部分的布局面积为1152um×123.7um。
具体的，如图7a和图7b所示该条件下单比特超导量子芯片的仿真结果，谐振器工作频率为6.1956GHz；
具体的，如图8a和图8b所示传统单比特超导量子芯片的仿真结果，谐振器工作频率为6.1978GHz。
可以看出，本实施例中超导量子芯片和传统和超导量子芯片在相近工作频率时，基于共面波导-2阶阶跃阻抗谐振器单元的谐振器尺寸比传统UIR的谐振器尺寸缩小了约19.6％。
可以理解的是，以上对共面波导-2阶阶跃阻抗谐振器单元进行了具体的描述，有关共面波导-3阶阶跃阻抗谐振器单元的参数确定方法与之类似，只是随着传输线的增多，特征阻抗比不再是一个单一量，在步骤S2计算特征阻抗比时一般以某一个特征线的特征阻抗作为分母，其他特征线的特征阻抗作为分子，分别计算对应的多个特征阻抗比；在步骤S3中，确定该组特定的多个特征阻抗比下，特征阬作为分母的特征线的电长度为自变量、所有特征线的总电长度为因变量的曲线关系；后续在该曲线关系下，确定最小总电长度区间、自变量的电长度区间、具体的电长度参数确定均与上文类似，此处不再赘述。
本申请的超导量子芯片中以共面波导-阶跃阻抗谐振器单元来实现谐 振器的功能，由于共面波导-阶跃阻抗谐振器单元的物理特性，在同一并联谐振条件下，相比均匀阻抗谐振器，阶跃阻抗谐振器的电长度明显更小，进而缩小了单个量子比特的布局尺寸，使得特定比特数的量子芯片尺寸更小、量子芯片自由度更高，量子芯片集成度提高。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本发明所提供的一种超导量子芯片及其参数确定方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。
Claims (10)
- 一种超导量子芯片，其特征在于，包括芯片衬底和形成于所述芯片衬底上的量子模块，所述量子模块包括比特电容单元、读取线单元、约瑟夫森结单元，所述量子模块还包括共面波导-阶跃阻抗谐振器单元。
- 根据权利要求1所述超导量子芯片，其特征在于，所述共面波导-阶跃阻抗谐振器单元具体为共面波导-2阶阶跃阻抗谐振器单元。
- 根据权利要求1所述超导量子芯片，其特征在于，所述共面波导-阶跃阻抗谐振器单元具体为共面波导-3阶阶跃阻抗谐振器单元。
- 根据权利要求1至3任一项所述超导量子芯片，其特征在于，所述比特电容单元具体为十字结构的比特电容单元。
- 根据权利要求4所述超导量子芯片，其特征在于，所述读取线单元具体为共面波导结构的传输线。
- 根据权利要求5所述超导量子芯片，其特征在于，所述共面波导-阶跃阻抗谐振器单元具体为λ g/4型共面波导-阶跃阻抗谐振器单元，其中λ g为所述共面波导-阶跃阻抗谐振器单元的谐振频率对应的波导波长。
- 一种超导量子芯片的参数确定方法，其特征在于，应用于如权利要求1至6任一项所述超导量子芯片，包括：根据预设精度，确定共面波导-阶跃阻抗谐振器单元的每阶传输线的特征阻抗并作为特征阻抗参数；计算所有所述特征线的所述特征阻抗之间的特征阻抗比；确定所述特征阻抗比下，所述特征线的电长度与总电长度的曲线关系；所述总电长度具体为所有所述特征线的所述电长度的和；根据所述曲线关系，确定所述总电长度的最小总电长度区间及其对应的所述特征线的电长度区间；在每阶所述特征线的电长度区间内，分别确定对应所述预设精度的所述电长度，以将所述电长度作为所述共面波导-阶跃阻抗谐振器单元的每阶传输线的电长度参数。
- 根据权利要求7所述参数确定方法，其特征在于，所述共面波导-阶跃阻抗谐振器单元为共面波导-2阶阶跃阻抗谐振器单元；所述计算所有所述特征线的所述特征阻抗之间的特征阻抗比的过程包括：计算第2阶所述特征线的所述特征阻抗和第1阶所述特征线的所述特征阻抗的特征阻抗比。
- 根据权利要求8所述参数确定方法，其特征在于，所述确定所述特征阻抗比下，所述特征线的电长度与总电长度的曲线关系的过程，包括：确定所述特征阻抗比下，第1阶所述特征线与总电长度的曲线关系。
- 根据权利要求9所述参数确定方法，其特征在于，所述在每阶所述特征线的电长度区间内，分别确定对应所述预设精度的所述电长度的过程，包括：在第1阶所述特征线的电长度区间内，确定对应所述预设精度的所述电长度作为第1阶所述特征线的第1阶电长度参数；根据所述曲线关系，确定第1阶所述电长度参数对应的所述总电长度；根据所述总电长度和第1阶所述电长度参数，确定第2阶所述特征线的第2阶电长度参数。
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