WO2024066565A1 - 一种放大电路、芯片及量子比特读取系统 - Google Patents

一种放大电路、芯片及量子比特读取系统 Download PDF

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Publication number
WO2024066565A1
WO2024066565A1 PCT/CN2023/103490 CN2023103490W WO2024066565A1 WO 2024066565 A1 WO2024066565 A1 WO 2024066565A1 CN 2023103490 W CN2023103490 W CN 2023103490W WO 2024066565 A1 WO2024066565 A1 WO 2024066565A1
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Prior art keywords
lumped
inductor
capacitor
series
amplifier circuit
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PCT/CN2023/103490
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English (en)
French (fr)
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伍昀凡
龙俊伶
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华为技术有限公司
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Publication of WO2024066565A1 publication Critical patent/WO2024066565A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F19/00—Amplifiers using superconductivity effects

Definitions

  • the present application relates to the field of quantum computing technology, and in particular to an amplification circuit, a chip and a quantum bit reading system.
  • Quantum computing can solve problems such as large number factorization and quantum chemical simulation.
  • Quantum computing can provide exponential acceleration advantages for these problems.
  • the basic principle of quantum computing is to use quantum bits (such as ions) to encode information.
  • the state of a single quantum bit (or quantum state) not only has two classical states of 0 and 1, but also a superposition state of 0 and 1.
  • the quantum bit can be in the 0 state with half the probability and in the 1 state with half the probability.
  • n quantum bits can be in the superposition state of 2n quantum states at the same time, which can exponentially increase the speed of calculation.
  • Superconducting quantum computing Since superconducting quantum computing has high scalability (such as increasing the number of quantum bits), it is expected to realize universal quantum computing.
  • Superconducting quantum computing is based on superconducting circuits.
  • Superconducting circuits are microwave circuits that work in an ultra-low temperature environment provided by a dilution refrigerator. When performing quantum computing, superconducting circuits need to input microwave signals, and the input microwave signals interact with superconducting quantum bits to complete the computing process. The results of quantum bit calculations are also read using microwave signals. The power of the read microwave signal is 10-16 watts (W) or lower (the power of a few photons).
  • the microwave signal is read at room temperature, which causes the introduced thermal noise to be much higher than the microwave signal being read.
  • a high signal-to-noise ratio i.e., the ratio of signal strength to noise strength
  • reading a quantum bit requires a bandwidth of a certain center frequency, and when a large number of quantum bits are read simultaneously, the total bandwidth required is also large.
  • an impedance converter type parallel Josephson parametric amplifier is used to perform large-bandwidth quantum limit amplification of the signal to be read, please refer to Figure 1.
  • the impedance converter type parallel Josephson parametric amplifier includes an impedance converter and a nonlinear resonator.
  • the impedance converter can be composed of a coplanar waveguide with a cross-line capacitance bridge, and the nonlinear resonator is formed by parallel connection of a parallel plate capacitor and a nonlinear adjustable inductor.
  • the impedance transformer type parallel Josephson parametric amplifier Since the process of parallel plate capacitors requires the production of multilayer films, and the waveguide with cross-line capacitance bridge also requires multilayer processes, the impedance transformer type parallel Josephson parametric amplifier has high manufacturing complexity and long cycle. In addition, the impedance transformer will introduce additional electromagnetic wave modes in the parametric amplifier, resulting in uneven gain of the parametric amplifier, which in turn affects the working performance of the parametric amplifier.
  • the present application provides an amplifier circuit, a chip and a quantum bit reading system for simplifying the manufacturing process of the amplifier circuit.
  • the present application provides an amplifier circuit, which includes N lumped capacitor and inductor modules connected in series, where N is a positive integer, and the lumped capacitor and inductor modules include a lumped capacitor unit and a lumped inductor unit, and the lumped capacitor unit and the lumped inductor unit are connected in series; the lumped inductor unit of at least one lumped capacitor and inductor module among the N lumped capacitor and inductor modules includes at least one superconducting quantum interference device (SQUID), and the lumped capacitor and inductor module including the SQUID also includes a pump signal line, and the pump signal line is mutually coupled with the SQUID.
  • N is a positive integer
  • the lumped capacitor and inductor modules include a lumped capacitor unit and a lumped inductor unit, and the lumped capacitor unit and the lumped inductor unit are connected in series
  • N series-connected lumped capacitor and inductor modules can be equivalent to a circuit in which an equivalent lumped capacitor module is connected in series with an equivalent lumped inductor module.
  • the equivalent lumped capacitor module and the series-connected equivalent lumped inductor module form a nonlinear resonator, and the Q value of the coupling between the nonlinear resonator and the external environment is equal to the ratio of the impedance of the nonlinear resonator to the impedance of the external environment.
  • the Q value needs to be greater than 1/2. Therefore, the capacitance value in the nonlinear resonator can be designed to be smaller.
  • Capacitors with smaller capacitance values can be made by a planar capacitor process. Since the planar capacitor process can be completed by one-step photolithography, the process complexity of making the amplifier circuit can be reduced.
  • the lumped capacitor unit includes one or more first lumped capacitors, and the plurality of first lumped capacitors are connected in series and/or in parallel.
  • the first lumped capacitor is formed by a planar capacitor process.
  • the manufacturing process of the first lumped capacitor formed by the planar capacitor process is simple.
  • the first lumped capacitor comprises an interdigital capacitor.
  • the equivalent capacitance Cc of N series-connected lumped capacitor and inductor modules is equal to the equivalent capacitance Cc of N series-connected lumped capacitor and inductor modules.
  • the equivalent parasitic capacitance Cs of the inductor module to ground satisfies the relationship: Cc /( Cc + Cs )>0.3, wherein the equivalent parasitic capacitance to ground of the N series-connected lumped capacitor and inductor modules is connected in parallel with the equivalent lumped inductor module of the N series-connected lumped capacitor and inductor modules, and the equivalent lumped inductor module is grounded.
  • the bandwidth of the amplifier circuit depends on the coupling strength between the nonlinear resonator in the amplifier circuit and the external environment (characterized by the Q value), the smaller the Q value, the greater the coupling strength and the larger the bandwidth of the amplifier circuit. Since the equivalent capacitance Cc and the equivalent parasitic capacitance to ground Cs can affect the Q value, by setting Cc /( Cc + Cs )>0.3, the Q value is made less than 10, so that the amplifier circuit can have a larger bandwidth.
  • the amplifier circuit further includes a second lumped capacitor, which is connected in parallel to an equivalent lumped inductor module of the N series-connected lumped capacitor and inductor modules, and the equivalent lumped inductor module is grounded.
  • the bandwidth of the amplifier circuit can be changed from a narrowband to a wideband, which helps to increase the adjustable range of the bandwidth of the amplifier circuit.
  • the equivalent capacitance C c of the N series-connected lumped capacitor-inductor modules and the capacitance C c2 of the second lumped capacitor satisfy the relationship: C c /(C c +C c2 )>0.3.
  • the Q value is made smaller than 10, so that the amplifier circuit can have a larger bandwidth.
  • the lumped inductor unit may further include one or more Josephson junctions; the connection manner of the multiple Josephson junctions includes series connection and/or parallel connection.
  • the lumped inductor unit further includes one or more first lumped inductors, where the first lumped inductors are inductors other than Josephson junctions and SQUIDs; the connection modes of the multiple first lumped inductors include series connection and/or parallel connection.
  • the first lumped inductor includes a linear lumped inductor.
  • the lumped inductor unit includes one or more SQUIDs, one or more Josephson junctions, and one or more first lumped inductors
  • the one or more SQUIDs can be connected in series or in parallel
  • the one or more Josephson junctions can be connected in series or in parallel
  • the one or more first lumped inductors can be connected in series or in parallel
  • the SQUIDs, Josephson junctions and first lumped inductors can be connected in series or in parallel.
  • one end of the pump signal line is used to connect to a pump source, and the other end is used to be grounded; the radio frequency signal from the pump source transmitted by the pump signal line is used to provide energy for the signal to be amplified.
  • the signal to be amplified can be amplified by the radio frequency signal transmitted in the pump signal line.
  • the pump signal line includes a coplanar waveguide.
  • the coplanar waveguide as the pump signal line, it helps to further simplify the preparation process of the amplifier circuit. Moreover, if the coplanar waveguide and the SQUID are coplanar, the mutual inductance between the pump signal line and the SQUID can be enhanced.
  • the present application provides a chip, comprising a substrate and the above-mentioned first aspect or any one of the amplifier circuits in the first aspect, wherein the amplifier circuit is disposed on the substrate.
  • the lumped capacitor unit and the lumped inductor unit are located at different positions of the substrate; and a superconducting metal film is covered on the substrate between the lumped capacitor unit and the lumped inductor unit.
  • the present application provides a quantum bit reading system, which includes a circulator and the second aspect or any one of the chips in the second aspect; the circulator is used to input the signal to be amplified into the chip, and output the amplified signal after amplification by the chip.
  • the quantum bit reading system also includes a first isolator and/or a second isolator; the first isolator is used to prevent reverse transmission of the signal to be amplified and/or the amplified signal; the second isolator is used to prevent reverse transmission of the amplified signal.
  • the first isolator is used to prevent the reverse transmission of the signal to be amplified and/or the amplified signal, thereby preventing the influence of the signal to be amplified on the quantum bit and preventing the amplifier circuit from interfering with the reverse effect of the signal to be amplified.
  • the second isolator is used to prevent the reverse transmission of the amplified signal, thereby ensuring the stable operation of the amplifier circuit and preventing interference from circuits other than the circulator.
  • FIG1 is a schematic diagram of the structure of an impedance converter type parallel Josephson parametric amplifier in the prior art
  • FIG2 is a schematic diagram of the structure of an amplifier circuit provided by the present application.
  • FIG3 is a schematic diagram of an equivalent circuit of an amplifier circuit provided by the present application.
  • FIG4 is a schematic diagram of the structure of a SQUID provided by the present application.
  • FIG5 is a schematic diagram of the structure of a Josephson junction provided by the present application.
  • FIG6 is a schematic diagram of a possible structure of a lumped capacitor unit provided in the present application.
  • FIG7 is a schematic diagram of an equivalent circuit of another amplifier circuit provided by the present application.
  • FIG8 is a schematic diagram of a possible structure of a lumped inductor provided in the present application.
  • FIG9 is a schematic diagram of the structure of a coplanar waveguide provided by the present application.
  • FIG10a is a schematic diagram of the structure of another amplifier circuit provided by the present application.
  • FIG10b is a schematic structural diagram of another amplifier circuit provided by the present application.
  • FIG10c is a schematic diagram of the structure of another amplifier circuit provided by the present application.
  • FIG10d is a schematic structural diagram of another amplifier circuit provided by the present application.
  • FIG11 is a schematic diagram of the structure of another amplifier circuit provided by the present application.
  • FIG12 is a schematic diagram of the structure of another amplifier circuit provided by the present application.
  • FIG13 is a schematic diagram of the structure of another amplifier circuit provided by the present application.
  • FIG14 is a schematic diagram of the layout of an amplifier circuit on a chip provided by the present application.
  • FIG15 is a schematic diagram of the layout of an amplifier circuit on a chip provided by the present application.
  • FIG16 is a schematic diagram of the layout of an amplifier circuit on a chip provided by the present application.
  • FIG17 is a schematic diagram of the layout of an amplifier circuit on a chip provided by the present application.
  • FIG18 is a schematic diagram of the structure of a circulator provided by the present application.
  • FIG19 is a schematic diagram of the architecture of a quantum bit reading system provided in this application.
  • Magnetic flux is a scalar, symbol " ⁇ ", unit Weber (Wb).
  • Wb unit Weber
  • the bandwidth of an amplifier circuit refers to the frequency range in which the amplifier circuit can achieve sufficient amplification.
  • the human ear is equivalent to an amplifier circuit for vibration signals and can only respond to vibrations of 20-20 kilohertz (KHz), which is the bandwidth of the ear.
  • KHz kilohertz
  • the dynamic range of an amplifier circuit refers to the upper and lower limits of the signal energy that the amplifier circuit can reasonably amplify. Taking the human ear as an example, the ear cannot hear sounds below 0 decibels (dB) because the signal energy is equivalent to the self-noise and the ear cannot distinguish it. Sounds above 100dB will make the ear extremely uncomfortable or even cause physical damage, which is the upper limit that the ear can withstand. Therefore, the dynamic range of the ear is about 100dB.
  • the noise limit determined by quantum mechanics refers to the smallest quantum noise that can be obtained without using squeezed states of light.
  • Inductance is a property of a closed loop and a physical quantity. When current passes through a coil, a magnetic field is induced in the coil, and the induced magnetic field generates an induced current to resist the current passing through the coil. It is a circuit parameter that describes the induced electromotive force effect caused in the coil or in another coil due to the change of coil current. Inductance is a general term for self-inductance and mutual inductance. The device that provides inductance is called an inductor. An inductor has a certain inductance, which only hinders the change of current. If the inductor is in a state where no current passes through it, it will try to hinder the flow of current when the circuit is connected; if the inductor is in a state where current passes through it, it will try to maintain the current unchanged when the circuit is disconnected.
  • Mutual induction is a common electromagnetic induction phenomenon that occurs not only between two coils wound on the same core, but also between any two circuits close to each other. For example, mutual induction also occurs between a SQUID with adjustable inductance and a pump signal line.
  • impedance In a circuit with resistance, inductance and capacitance, the resistance to the current in the circuit is called impedance.
  • Lumped components refer to components whose size is much smaller than the wavelength corresponding to the circuit's operating frequency. For signals, the characteristics of lumped components always remain fixed and are independent of frequency. In other words, when a signal passes through a lumped component, the change of the signal at each point inside the lumped component is quite small and can be regarded as no change.
  • a circuit composed of lumped components can be called a lumped circuit.
  • a transverse electromagnetic wave is an electromagnetic wave whose electric field component and magnetic field component are perpendicular to each other and to the propagation direction.
  • the quality factor also known as the quality factor or Q value, is a basic parameter used to characterize the characteristics of a resonant circuit in a circuit. Specifically, it can be used to represent a quality indicator of the ratio of the energy stored in an energy storage device (such as an inductor, capacitor, etc.) and the resonant circuit to the energy lost per cycle.
  • an energy storage device such as an inductor, capacitor, etc.
  • a circuit composed of an inductor L and a capacitor C that can resonate at one or several frequencies is collectively called a resonant circuit.
  • a resonant circuit composed of an inductor L and a capacitor C in series is called a series resonant circuit.
  • the resonant frequency refers to the frequency at which the resonant circuit resonates (or is called resonance).
  • the inductive reactance and the capacitive reactance of the resonant circuit are equal, and the resonant circuit is purely resistive to the outside, which is resonance.
  • the resonant circuit amplifies the input signal by a certain multiple.
  • the essence of resonance is that the electric field energy in the capacitor and the magnetic field energy in the inductor are converted to each other, one increases and the other decreases, and they are completely compensated.
  • the sum of the electric field energy and the magnetic field energy remains unchanged, and the power supply does not have to convert energy back and forth with the capacitor or inductor, but only needs to supply the electric energy consumed by the resistor in the circuit.
  • Parasitic capacitance is an unavoidable capacitance that exists between various parts of electronic components or circuits. For example, when two electrical conductors with different voltages are close together, the electric field between them will cause charge to be stored on them. This effect is parasitic capacitance.
  • Parasitic capacitance to ground refers to the capacitance between each electronic component on the signal line and the ground due to parasitic effects.
  • the quantum bit read signal is extremely weak, taking the superconducting quantum bit system as an example, the quantum bit read signal is usually in the 4-8 GHz frequency band, and the power is 10-16 watts (W) or lower (the power of several photons). Such a weak read signal will also be lost in the subsequent transmission. Therefore, if the quantum bit read signal is directly transmitted, it will be submerged in noise (such as thermal noise, electrical noise). Based on this, it is necessary to amplify the quantum bit read signal.
  • the impedance transformer type parallel Josephson parametric amplifier is usually used to amplify the quantum bit read signal.
  • the impedance transformer type parallel Josephson parametric amplifier includes an impedance transformer and a nonlinear resonator, please refer to Figure 1 above. Since the parallel plate capacitor needs to make a multilayer film, and the waveguide with a cross-line capacitance bridge also requires a multilayer process, the impedance transformer type parallel Josephson parametric amplifier has a high manufacturing complexity and a long cycle. Moreover, the impedance transformer will introduce additional electromagnetic wave modes in the parametric amplifier, which will lead to uneven gain in the parametric amplifier and further affect the working performance of the parametric amplifier.
  • the present application proposes an amplifier circuit.
  • the amplifier circuit can be manufactured by a simple manufacturing process. It should be noted that the amplifier circuit provided by the present application can be applied to high-fidelity quantum state reading, preparation of entangled microwave photons, quantum weak measurement, quantum feedback and other scenarios.
  • the amplifier circuit includes N lumped capacitor and inductor modules, where N is a positive integer.
  • the lumped capacitor and inductor modules include a lumped capacitor unit and a lumped inductor unit, and the lumped capacitor unit is connected in series with the lumped inductor unit.
  • the lumped inductor unit included in at least one of the N lumped capacitor and inductor modules includes at least one SQUID.
  • the lumped capacitor and inductor module including the SQUID also includes a pump signal line, and the pump signal line is mutually inductively coupled with the SQUID.
  • the specific structure of the SQUID can be found in the introduction of Figure 4 below.
  • the inductance of the SQUID is adjustable, and the pump signal line is adjacent to the SQUID.
  • the mutual inductance of the pump signal transmitted in the adjacent pump signal line and the SQUID can change the magnetic flux in the SQUID loop, thereby adjusting the inductance of the SQUID.
  • the amplifier circuit of FIG2 can be equivalent to a circuit in which an equivalent lumped capacitor module is connected in series with an equivalent lumped inductor module, wherein the equivalent lumped inductor module includes at least one SQUID.
  • the equivalent lumped inductor module includes at least one SQUID.
  • one end of the equivalent lumped inductor module is connected to the equivalent lumped capacitor module, and the other end of the equivalent lumped inductor module is grounded, see FIG3. It can be understood that the equivalent amplifier circuit of FIG3 The circuit does not consider the influence of parasitic capacitance. Based on this, the equivalent lumped inductance module can also be ungrounded and the equivalent lumped capacitance module can be grounded.
  • the equivalent lumped capacitor module and the equivalent lumped inductor module are connected in series to form a nonlinear resonator (or nonlinear resonant cavity or nonlinear resonant circuit).
  • the Q value of the coupling between the nonlinear resonator and the external environment is equal to the ratio of the impedance of the nonlinear resonator to the impedance of the external environment.
  • the impedance of the nonlinear resonator without considering the parasitic capacitance to the ground is equal to C is the capacitance of the nonlinear resonator, that is, the capacitance of the equivalent lumped capacitance module, and L is the inductance of the nonlinear resonator, that is, the inductance of the equivalent lumped inductance module.
  • the external environment refers to the part other than the amplifying circuit connected to the amplifying circuit through the input and output lines, which is collectively referred to as the external environment of the amplifying circuit. For details, please refer to the relevant introduction in Figure 19 below, which will not be repeated here.
  • the Q value needs to be greater than 1/2. Therefore, it is necessary to design the impedance of the nonlinear resonator to be greater than the impedance of the external environment (such as the impedance of the external environment is about 50 ohms ( ⁇ )). In order to achieve this requirement, the value of the capacitor in the nonlinear resonator is lower than the value of the capacitor in the existing circuit in which the inductor and capacitor are connected in parallel.
  • the capacitance of the nonlinear resonator can be less than 2 picofarads (pF).
  • Capacitors with smaller capacitance values can be made by planar capacitor technology. Since the planar capacitor process can be completed by one-step photolithography, the process complexity of making the amplifier circuit can be reduced. It is understandable that the Q value of the nonlinear resonator in the circuit in which the inductor and the capacitor are connected in parallel in the prior art is equal to the ratio of the impedance of the external environment to the impedance of the nonlinear resonator. Moreover, based on the above-mentioned amplifier circuit, the introduction of additional electromagnetic wave modes into the circuit can be reduced, which is conducive to smoothing the gain region and preventing the occurrence of double peak gain.
  • SQUID is a loop device formed by two Josephson junctions in parallel, see Figure 4.
  • the SQUID formed by two Josephson junctions in parallel can also be called a direct current (DC) SQUID, which will produce a macroscopic superconducting quantum interference effect.
  • the Josephson junction is an S-I-S structure consisting of two layers of superconductors (such as superconducting metal layers) with a layer of insulator (or non-superconductor) sandwiched between them, see Figure 5.
  • the non-superconducting layer is a "potential barrier" for electrons. When the temperature is low enough, the superconductor quickly exchanges pairs of electrons through the potential barrier, producing a quantum tunneling effect.
  • both the Josephson junction and the SQUID are nonlinear inductors.
  • the inductance of the Josephson junction is fixed and cannot be adjusted.
  • the inductance of the Josephson junction is [0.1nH, 10nH].
  • a superconductor is a conductor with zero resistance at a certain temperature.
  • Superconductors not only have the characteristics of zero resistance, but also have the characteristics of complete anti-magnetism. Complete diamagnetism is also known as the Meissner effect.
  • “Diamagnetism” refers to the phenomenon that when the magnetic field strength is lower than the critical value, the magnetic lines of force cannot pass through the superconductor and the magnetic field inside the superconductor is zero.
  • the amplification circuit in the present application may include but is not limited to a quantum limit amplifier, and the quantum limit amplifier includes but is not limited to a Josephson Parametric Amplifier (JPA).
  • JPA Josephson Parametric Amplifier
  • the quantum limit amplifier refers to an amplifier that introduces noise that is quantum limit. Further, the quantum limit amplifier includes a broadband quantum limit amplifier.
  • the lumped capacitor unit includes a first lumped capacitor; or, the lumped capacitor unit includes a plurality of first lumped capacitors connected in series and/or in parallel.
  • the lumped capacitor unit can be composed of any plurality of first lumped capacitors connected in series and/or in parallel. It can also be understood that if the lumped capacitor unit includes a plurality of first lumped capacitors, the plurality of first lumped capacitors can be connected in series and/or in parallel.
  • FIG6 is a possible structural example of a lumped capacitor unit provided in the present application.
  • FIG6 (b) shows a schematic diagram of a lumped capacitor unit including two first lumped capacitors connected in series.
  • FIG6 (c) shows a schematic diagram of a lumped capacitor unit including two first lumped capacitors connected in parallel.
  • the lumped capacitor unit includes a first lumped capacitor C 1 and a first lumped capacitor C 2 connected in parallel, based on this, the total capacitance C of the lumped capacitor unit is equal to C 1 +C 2 .
  • the lumped capacitor unit includes a first lumped capacitor C1 and a first lumped capacitor C2 connected in parallel and then connected in series with a first lumped capacitor C3 . Based on this, the total capacitance C of the lumped capacitor unit is equal to 1/(1/( C1 + C2 )+1/ C3 ).
  • the lumped capacitor unit may include more first lumped capacitors than (d) in FIG6 above, and the plurality of first lumped capacitors may be connected in series, in parallel, or partially in series and partially in parallel, which is not limited in the present application.
  • the number of first lumped capacitors included in the lumped capacitor unit is related to the capacitor process, the size of the amplifier circuit, and the total capacitance of the lumped capacitor unit.
  • the first lumped capacitor can be made by a planar capacitor process. It can also be understood that each first lumped capacitor included in the lumped capacitor unit can be made by a planar capacitor process.
  • the planar capacitor process includes but is not limited to an etching process or a stripping process.
  • etching process it refers to first coating a layer of superconducting metal film on the substrate, then uniformly coating a layer of photoresist on the superconducting metal film, exposing and developing the area to be etched (the area where only the substrate is not covered by the metal film in the chip design), and then etching the developed superconducting metal by a wet method to form the desired structure.
  • the stripping process refers to uniformly coating a layer of photoresist on the substrate, exposing and developing the area where the superconducting metal film needs to be coated, and coating the superconducting metal film on the substrate after exposure and development, and then placing it in a solution to strip the photoresist to form the desired structure.
  • the first lumped capacitor can be, for example, a finger capacitor.
  • the bandwidth of the amplifier circuit depends on the coupling strength (characterized by the Q value) between the nonlinear resonator in the amplifier circuit and the external environment.
  • the Q value is related to the capacitance in the amplifier circuit.
  • the equivalent capacitance C c of the N series-connected lumped capacitor and inductor modules and the equivalent parasitic capacitance to ground C s of the N series-connected lumped capacitor and inductor modules satisfy the relationship 1: C c /(C c +C s )>0.3.
  • the equivalent capacitance C c of the N series-connected lumped capacitor and inductor modules is the capacitance of the equivalent lumped capacitor module in FIG3
  • the equivalent parasitic capacitance to ground C s of the N series-connected lumped capacitor and inductor modules is the parasitic capacitance to ground of the equivalent lumped capacitor module in FIG3
  • the equivalent parasitic capacitance to ground of the N series-connected lumped capacitor and inductor modules is connected in parallel with the equivalent lumped inductor module of the N series-connected lumped capacitor and inductor modules, and the equivalent lumped inductor module is grounded. It can be understood that the above relationship is obtained through circuit simulation.
  • the lumped capacitance unit includes a first lumped capacitor.
  • the equivalent capacitance Cc of the N series-connected lumped capacitor and inductor modules is equal to the capacitance Cc11 of the first lumped capacitor
  • the equivalent parasitic capacitance to ground Cs of the N series-connected lumped capacitor and inductor modules is equal to the capacitance Cs11 of the parasitic capacitance to ground of the lumped capacitor and inductor module. Therefore, the above relationship 1 can be expressed as: C c11 /(C c11 +C s11 )>0.3
  • the lumped capacitance unit includes a plurality of first lumped capacitors connected in series and/or in parallel.
  • the equivalent capacitance Cc of the N series-connected lumped capacitor and inductor modules is equal to the total capacitance Cc12 of the multiple first lumped capacitors.
  • the total capacitance of the multiple first lumped capacitors can be determined in combination with the introduction of the above formula 1 and/or formula 2, which will not be repeated here.
  • the equivalent parasitic capacitance to ground Cs of the N series-connected lumped capacitor and inductor modules is equal to the total capacitance Cs12 of the parasitic capacitance to ground of the lumped capacitor and inductor modules. Therefore, the above relationship 1 can be expressed as: C c12 /(C c12 +C s12 )>0.3
  • the capacitances of different first lumped capacitors may be the same or different, and this application does not limit this.
  • this situation 1.2 one possible situation is that the parasitic capacitance Cs12 to ground of each of the multiple first lumped capacitors is small. It can be understood that the more the number of first lumped capacitors included in the lumped capacitor unit, the smaller the value of the parasitic capacitance to ground of each first lumped capacitor will be.
  • the amplifier circuit further includes a second lumped capacitor, the second lumped capacitor is connected in parallel with the equivalent lumped inductor module of the lumped capacitor and inductor module, and the equivalent lumped inductor module is grounded.
  • the equivalent parasitic capacitance Cs of the lumped capacitor and inductor module to ground can be ignored compared to the total capacitance of the second lumped capacitor.
  • the equivalent capacitance Cc of the lumped capacitor and inductor module and the capacitance Cc2 of the second lumped capacitor satisfy the relationship 2: Cc /( Cc + Cc2 )>0.3.
  • Case 2 The amplifier circuit includes multiple series-connected lumped capacitor and inductor modules, N>1.
  • the equivalent capacitance C c of the N series-connected lumped capacitor and inductor modules is equal to the total capacitance C cc of each lumped capacitor and inductor module.
  • the total capacitance of each lumped capacitor and inductor module can be found in the introduction of the above situation 1.1 or situation 1.2, which will not be repeated here.
  • the amplifier circuit also includes a second lumped capacitor, the second lumped capacitor is connected in parallel with the equivalent lumped inductor module of the N series-connected lumped capacitor and inductor modules, and the equivalent lumped inductor module is grounded. Further, the equivalent parasitic capacitance Cs to ground of the N series-connected lumped capacitor and inductor modules can be ignored compared to the total capacitance of the second lumped capacitor. It can also be understood that the equivalent parasitic capacitance Cs to ground of the N series-connected lumped capacitor and inductor modules is smaller.
  • the equivalent capacitance Cc of the N series-connected lumped capacitor and inductor modules and the capacitance Cc2 of the second lumped capacitor satisfy the relationship 2: Cc /( Cc + Cc2 )>0.3.
  • various parameters of the amplifier circuit such as Q value, bandwidth, resonant frequency, etc.
  • the bandwidth of the amplifier circuit can be changed from narrow band to wide band, which is helpful to increase the adjustable range of parameters (such as bandwidth).
  • the amplifier circuit can be equivalent to the equivalent amplifier circuit shown in Figure 7.
  • the amplifier circuit can be equivalent to the equivalent amplifier circuit shown in Figure 3.
  • the lumped inductor unit included in at least one lumped capacitor and inductor module among the N lumped capacitor and inductor modules includes at least one SQUID, and the lumped capacitor and inductor module including the SQUID further includes a pump signal line.
  • lumped inductor unit including at least one SQUID. If the lumped inductor unit includes multiple SQUIDs, the multiple SQUIDs may be connected in series, or in parallel, or partially in series and partially in parallel. It is understood that in order to facilitate the manufacture of the amplifier circuit, the number of SQUIDs included is usually not more than 100.
  • the lumped inductor unit may further include at least one Josephson junction. It can also be understood that the lumped inductor unit includes at least one SQUID and at least one Josephson junction.
  • the lumped inductor unit may further include at least one lumped linear inductor. It can also be understood that the lumped inductor unit includes at least one SQUID and at least one lumped linear inductor. Generally, the inductance of the lumped linear inductor cannot be adjusted.
  • the lumped inductor unit may further include at least one Josephson junction and at least one lumped linear inductor. It can also be understood that the lumped inductor unit includes at least one SQUID, at least one Josephson junction and at least one lumped linear inductor.
  • the lumped inductor unit in the lumped capacitor and inductor module that does not include a SQUID in the N lumped capacitor and inductor modules includes at least one Josephson junction and/or at least one lumped linear inductor.
  • FIG8 is a possible structural example of the lumped inductor provided in the present application.
  • FIG8 (b) shows a schematic diagram of the structure of a lumped inductor unit including a lumped linear inductor and a SQUID connected in series.
  • the total inductance L of the lumped inductor unit is equal to the sum of the inductance of the lumped linear inductor and the inductance of the SQUID
  • the inductance of the SQUID is represented by L1
  • FIG8 (c) shows a schematic diagram of the series structure of a lumped inductor unit including a lumped linear inductor, a Josephson junction and a SQUID.
  • the total inductance L of the lumped inductor unit is equal to the sum of the inductance of the lumped linear inductor, the inductance of the Josephson junction and the inductance of the SQUID.
  • the inductance of the SQUID is represented by L1
  • the inductance of the lumped linear inductor is represented by L2
  • (d) in Figure 8 shows a schematic diagram of a lumped inductor unit including a Josephson junction and a lumped linear inductor connected in parallel, and then a lumped linear inductor and a SQUID are connected in series. Based on this, the total inductance L of the lumped inductor unit is equal to 1/(1/ L3 +1/ L2 )+ L2 + L1 .
  • the number and connection method of the SQUID, Josephson junction and lumped linear inductor included in the lumped inductor unit given in 8 above are only examples, and this application does not limit this.
  • the number of SQUID, Josephson junction and lumped linear inductor included in the lumped inductor unit is related to the total inductance of the lumped inductor unit, the manufacturing process, etc.
  • one end of the pump signal line is connected to the pump source, and the other end is grounded (e.g., the ground of the chip).
  • the pump signal line is used to transmit the pump signal.
  • the pump source includes a DC signal source and an RF signal source.
  • the pump signal includes a DC signal and an RF signal.
  • the RF signal is mainly used to amplify the quantum bit read signal, and the quantum bit read signal can be called the signal to be amplified.
  • the DC signal is used to adjust the operating frequency of the nonlinear resonator in the amplifier circuit.
  • the DC signal provided by the DC signal source is used to adjust the operating frequency of the nonlinear resonator in the amplifier circuit. Since the pump signal line is close to the SQUID, the DC signal transmitted in the pump signal line and the mutual inductance of the SQUID can change the magnetic flux of the SQUID, thereby changing the inductance of the SQUID, and then changing the operating frequency of the nonlinear resonator.
  • the RF signal provided by the RF signal source is used to amplify the signal to be amplified. In other words, the RF signal provided by the RF signal source powers the quantum bit reading signal (signal to be amplified). For example, the RF signal is at the same frequency as the signal to be amplified.
  • the pump signal uses the nonlinear characteristics of the nonlinear resonator to construct an equivalent parametric modulation dynamic equation, and powers the system in a parametric modulation manner, thereby achieving amplification of the signal to be amplified.
  • the frequency of the RF signal is twice the frequency of the signal to be amplified. Based on this, the pump signal can directly modulate the parameters in the dynamic equation of the nonlinear resonator to power the system, thereby achieving amplification of the signal to be amplified.
  • the amplification process of the RF signal with the same frequency as the signal to be amplified can also be understood as a four-wave mixing process, and the amplification process of the RF signal with a frequency twice that of the signal to be amplified can also be understood as a three-wave mixing process.
  • the pump signal line includes a coplanar waveguide (or coplanar microstrip transmission line), see FIG9 .
  • a coplanar waveguide is a coplanar dual conductor system.
  • a coplanar waveguide is three parallel conduction strip layers (such as metal films) made on the surface of a dielectric layer.
  • the conduction strip layer located in the center is called the central conduction strip layer, and the width of the central conduction strip layer is S, which is used to transmit microwave signals (i.e., pump signals).
  • the conduction strip layers on both sides are used for grounding.
  • the width between the central conduction strip layer and the conduction strip layers on both sides is w, and there is air between the central conductor and the planar conductors on both sides.
  • a coplanar waveguide is a distributed circuit element, and its capacitance, inductance, reactance, and impedance are evenly distributed along the coplanar waveguide signal propagation direction.
  • the coplanar waveguide propagates TEM waves (or quasi-TEM waves).
  • the impedance of the waveguide is equal everywhere, so there is no signal reflection, and the signal can pass almost losslessly.
  • the coplanar waveguide has no cutoff frequency.
  • microwave signals of most frequency bands can be transmitted unimpeded, so it is also called a transmission line, i.e. a coplanar waveguide transmission line.
  • the pump signal line can also be other possible transmission lines, and this application does not limit this.
  • the pump signal line is coplanar with the SQUID; or, the pump signal line can also be located above or below the plane where the SQUID is located.
  • the pump signal line is a coplanar waveguide and is coplanar with the SQUID, the preparation of the amplifier circuit can be simplified and the mutual inductance can be enhanced.
  • the amplifier circuit includes a lumped capacitor and inductor module, and the lumped capacitor and inductor module includes a lumped capacitor unit, a lumped inductor unit and a pump signal line, and the lumped inductor unit is grounded.
  • the lumped capacitor unit is taken as an example including a first lumped capacitor
  • the lumped inductor unit is taken as an example including multiple SQUIDs connected in series
  • the inductance of each Josephson junction constituting the SQUID is in the range of [0.1nH, 10nH].
  • the capacitance of the first lumped capacitor is less than 2pF, and the parasitic capacitance to the ground of the lumped capacitor and inductor module is less than 2pF.
  • the ratio of the capacitance of the first lumped capacitor to the parasitic capacitance to the ground of the lumped capacitor and inductor module is greater than 3:7.
  • the first lumped capacitor, the parasitic capacitance to the ground of the lumped capacitor and inductor module and the multiple SQUIDs connected in series constitute a nonlinear resonator of the amplifier circuit.
  • the resonant frequency of the nonlinear resonator is usually between 4 and 10GHz, and the Q value of the nonlinear resonator is less than 10. Based on this, the bandwidth of the amplifier circuit is relatively large.
  • FIG10b it is a schematic diagram of the structure of another amplifier circuit provided by the present application.
  • the amplifier circuit includes a lumped capacitor and inductor module, and the lumped capacitor and inductor module includes a lumped capacitor unit, a lumped inductor unit and a pump signal line, and the lumped inductor unit is grounded.
  • the lumped capacitor unit includes two first lumped capacitors as an example, and the rest can refer to the introduction of FIG10a above, which will not be repeated here.
  • the amplifier circuit includes two lumped capacitor and inductor modules, namely, lumped capacitor and inductor module A and lumped capacitor and inductor module B. Among them, at least one of the lumped capacitor and inductor module A and the lumped capacitor and inductor module B includes a pump signal line. In this example, the lumped capacitor and inductor module B includes a pump signal line. Example.
  • the lumped capacitor and inductor module A includes a lumped capacitor unit and a lumped inductor unit.
  • the lumped capacitor and inductor module B includes a lumped capacitor unit, a lumped inductor unit and a pump signal line, and the lumped inductor unit included in the lumped capacitor and inductor module B is grounded.
  • the lumped capacitor unit, the lumped inductor unit and the pump signal line included in the lumped capacitor and inductor module B can refer to the introduction of the above Figure 10a
  • the lumped capacitor unit and the lumped inductor unit included in the lumped capacitor and inductor module A can refer to the introduction of the above Figure 10a, which will not be repeated here.
  • the ratio of the total capacitance of the two first lumped capacitors to the parasitic capacitance to the ground of the two modules of the lumped capacitor and inductor module A and the lumped capacitor and inductor module B is greater than 3:7.
  • the total capacitance of the two first lumped capacitors/(the parasitic capacitance to the ground of the two modules of the lumped capacitor and inductor module A and the lumped capacitor and inductor module B) is greater than 3:7.
  • the amplifier circuit includes a lumped capacitor and inductor module and a second lumped capacitor, and the lumped capacitor and inductor module include a lumped capacitor unit, a lumped inductor unit and a pump signal line, and the lumped inductor unit is grounded.
  • the lumped capacitor unit is taken as an example including a first lumped capacitor
  • the lumped inductor unit is taken as an example including multiple SQUIDs connected in series
  • the inductance of each Josephson junction constituting the SQUID is in the range of [0.1nH, 10nH].
  • the capacitance of the first lumped capacitor is less than 2pF, and the capacitance of the second lumped capacitor is less than 2pF.
  • the parasitic capacitance of the lumped capacitor and inductor module to the ground is negligible compared to the capacitance of the second lumped capacitor.
  • the ratio of the capacitance of the first lumped capacitor to the capacitance of the second lumped capacitor is greater than 3:7.
  • the amplifier circuit includes a lumped capacitor and inductor module, and the lumped capacitor and inductor module includes a lumped capacitor unit, a lumped inductor unit and a pump signal line.
  • the lumped inductor unit is grounded as an example.
  • the lumped capacitor unit is taken as an example including a first lumped capacitor
  • the lumped inductor unit is taken as an example including multiple Josephson junctions connected in series and a SQUID, and the series-connected Josephson junctions are connected in series with the SQUID.
  • the inductance of each Josephson junction constituting the SQUID is in the range of [0.1nH, 10nH]
  • the inductance of the series-connected Josephson junctions is in the range of [0.1nH, 10nH].
  • the capacitance of the first lumped capacitor is less than 2pF
  • the capacitance of the parasitic capacitance of the lumped capacitor and inductor module to the ground is less than 2pF.
  • the ratio of the capacitance of the first lumped capacitor to the parasitic capacitance of the lumped capacitor and inductor module to the ground is greater than 3:7.
  • the first lumped capacitor, the parasitic capacitance to ground of the lumped capacitance and inductance module, the multiple Josephson junctions connected in series and the SQUID constitute a nonlinear resonator of the amplifier circuit.
  • the nonlinear resonator please refer to the above related introduction, which will not be repeated here.
  • the amplifier circuit includes a lumped capacitor and inductor module, and the lumped capacitor and inductor module includes a lumped capacitor unit, a lumped inductor unit and a pump signal line.
  • the lumped inductor unit is grounded as an example.
  • the lumped capacitor unit is taken as an example including a first lumped capacitor
  • the lumped inductor unit is taken as an example including a lumped linear inductor and a SQUID
  • the lumped linear inductor is connected in series with the SQUID.
  • the inductance of each Josephson junction constituting the SQUID is in the range of [0.1nH, 10nH], and the inductance of the lumped linear inductor is less than 1000nH.
  • the capacitance of the first lumped capacitor is less than 2pF, and the capacitance of the parasitic capacitance of the lumped capacitor and inductor module to the ground is less than 2pF.
  • the ratio of the capacitance of the first lumped capacitor to the parasitic capacitance of the lumped capacitor and inductor module to the ground is greater than 3:7.
  • the first lumped capacitor, the parasitic capacitance of the lumped capacitor and inductor module to the ground, the SQUID and the lumped linear inductor constitute a nonlinear resonator of the amplifier circuit.
  • nonlinear resonators please refer to the aforementioned related introduction, which will not be repeated here.
  • the quantum bit read signal when amplified, it can be a cascaded multi-stage amplifier circuit that amplifies in sequence. Since the first-stage amplifier circuit in the cascaded multi-stage amplifier circuit has a greater impact on the final signal-to-noise ratio of the signal, the amplifier circuit in the above example can be used as the first-stage amplifier circuit, and the noise introduced by the first-stage amplifier is the quantum limit.
  • the present application may also provide a chip.
  • the chip may include the amplifier circuit in any of the above embodiments. Further, optionally, the chip also includes a substrate, and the amplifier circuit is arranged on the substrate. As follows, an example is given in which the amplifier circuit includes a capacitor and inductor module.
  • FIG14 is a schematic diagram of the layout of an amplifier circuit on a chip provided by the present application.
  • the amplifier circuit is taken as an example of the amplifier circuit shown in FIG10a above.
  • the first lumped capacitor is connected to the SQUID via a superconducting metal film. It can also be understood that the superconducting metal film is covered on the substrate between the first lumped capacitor and the SQUID to achieve the connection between the lumped capacitor unit and the lumped inductor unit.
  • FIG15 is a schematic diagram of the layout of another amplifier circuit on a chip provided by the present application.
  • the amplifier circuit is taken as an example of the amplifier circuit shown in FIG11 above.
  • the first lumped capacitor is adjacent to the second lumped capacitor, and the substrate between the first lumped capacitor and the multiple SQUIDs connected in series is covered with a superconducting metal film to achieve the connection between the first lumped capacitor and the SQUID, and the substrate between the second lumped capacitor and the multiple SQUIDs connected in series is covered with a superconducting metal film to achieve the connection between the second lumped capacitor and the SQUID.
  • FIG16 is a schematic diagram of the layout of another amplifier circuit on a chip provided by the present application.
  • the amplifier circuit is taken as an example of the amplifier circuit shown in FIG12 above.
  • the first lumped capacitor is connected to the multiple Josephson junctions connected in series via a superconducting metal film. It can also be understood that the superconducting metal
  • the metal film covers the substrate between the first lumped capacitor and the Josephson junction to achieve the connection between the first lumped capacitor and the Josephson junction.
  • FIG17 is a schematic diagram of the layout of another amplifier circuit on a chip provided by the present application.
  • the amplifier circuit is taken as an example of the amplifier circuit shown in FIG13 above.
  • a superconducting metal film is covered on the substrate between the first lumped capacitor and the lumped linear inductor. It can also be understood that the superconducting metal film is covered on the substrate between the first lumped capacitor and the lumped linear inductor to achieve the connection between the first lumped capacitor and the lumped linear inductor.
  • the chip size can be reduced by at least 80 times compared to the size of an existing parallel circuit, thereby improving the integration of the chip.
  • the above chip needs to work in an extremely low temperature environment, such as less than 30 (mK).
  • the present application can also provide a quantum bit reading system.
  • the quantum bit reading system may include an amplifying circuit or chip in any of the above embodiments.
  • the quantum bit reading system also includes a circulator.
  • the circulator is used to input the signal to be amplified into the chip and output the amplified signal after the chip is amplified.
  • the circulator is a multi-port non-reciprocal device (such as a non-reciprocal optical device or a non-reciprocal electrical device, etc.), and the signal can only propagate in one direction. As shown in Figure 18, it is a structural schematic diagram of a circulator provided by the present application.
  • the loss output from port 2 is small, and the loss output from port 3 is large; if the signal is input from port 2, the loss output from port 3 is small, and the loss output from port 1 is large; if the signal is input from port 3, the loss output from port 1 is small, and the loss output from port 2 is large.
  • the quantum bit reading system includes a chip and a circulator.
  • the chip can be, for example, a superconducting quantum chip.
  • the quantum bit reading system also includes a first isolator and/or a second isolator.
  • the chip includes two ports as an example, namely, port A and port B. Port A is used to input a pump signal. Port B is used to input a signal to be amplified and output an amplified signal. Port B can also be called an input and output port. Port B is connected in series with the circulator.
  • the circulator includes three ports as an example, namely, port 1, port 2 and port 3.
  • Port 1 of the circulator is connected to the first isolator
  • port 3 of the circulator is connected to the second isolator
  • port 2 of the circulator is connected to port B of the chip
  • port A of the chip is connected to the pump source.
  • the signal to be amplified is input from port 1 of the circulator, and is output from port 2 of the circulator to port B of the superconducting quantum chip.
  • the signal to be amplified is amplified by the chip to obtain an amplified signal.
  • the amplified signal is output from port B of the chip to port 2 of the circulator, enters the circulator through port 2 of the circulator, and is output to the second isolator through port 3 of the circulator.
  • the first isolator is used to prevent the reverse transmission of the signal to be amplified and/or the amplified signal, thereby preventing the influence of the signal to be amplified on the quantum bit, and preventing the amplification circuit from interfering with the reaction of the signal to be amplified.
  • the second isolator is used to prevent the reverse transmission of the amplified signal. Further, the second isolator is also used to prevent the reverse transmission of the amplified signal of the next-stage amplification circuit, thereby ensuring the stable operation of the amplification circuit and preventing interference from the circuit outside the port 3 of the circulator. It can be understood that the isolator is a unidirectional signal transmission device that can suppress the back and forth reflection of the signal.
  • the quantum bit reading system also includes a high electron mobility transistor (HEMT) and/or a radio frequency amplification circuit and a reading electronic instrument.
  • the reading electronic instrument includes but is not limited to a network analyzer, a data acquisition card, etc.
  • the high electron mobility transistor is used to further amplify the amplified signal at a temperature of 4 K.
  • the radio frequency amplification circuit is used to further amplify the amplified signal at room temperature.
  • the reading electronic instrument is used to convert the amplified signal into a form that is convenient for computer processing and ultimately obtain useful physical quantities (such as the quantum state of the quantum bit) through computer data processing.
  • the above-mentioned pump source may belong to the quantum bit reading system.
  • At least one of a, b or c can represent: a, b, c, "a and b", “a and c", “b and c", or "a and b and c", where a, b, c can be single or multiple.
  • the character “/” generally indicates that the front and back associated objects are in an “or” relationship.
  • the character “/” indicates that the front and back associated objects are in a "divided” relationship.
  • the symbol “(a, b)" represents an open interval.
  • the range is greater than a and less than b; "[a, b]” represents a closed interval, and the range is greater than or equal to a and less than or equal to b; "(a, b]” represents a half-open and half-closed interval, and the range is greater than a and less than or equal to b; "(a, b]” represents a half-open and half-closed interval, and the range is greater than a and less than or equal to b.
  • the word "exemplary” is used to indicate an example, illustration or description. Any embodiment or design described as an "example” in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Alternatively, it can be understood that the use of the word example is intended to present the concept in a specific way and does not constitute a limitation on this application.

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Abstract

一种放大电路、芯片及量子比特读取系统。应用于量子态读取，量子弱测量领域。放大电路包括N个串联的集总电容电感模块，集总电容电感模块包括串联的集总电容单元和集总电感单元；至少一个集总电容电感模块的集总电感单元包括至少一个超导量子干涉器件SQUID，包括SQUID的集总电容电感模块还包括泵浦信号线，泵浦信号线与SQUID互感耦合。放大电路等效于等效集总电容模块串联等效集总电感模块，这两个等效模块形成非线性谐振器，非线性谐振器与外界环境耦合的Q值为非线性谐振器的阻抗与外界环境的阻抗的比值。为了形成谐振模式，设计非线性谐振器中的电容的值较小，从而可通过平面电容工艺制作电容器，进而简化放大电路的制作工艺。

Description

一种放大电路、芯片及量子比特读取系统
相关申请的交叉引用
本申请要求在2022年09月27日提交中国专利局、申请号为202211183081.4、申请名称为“一种放大电路、芯片及量子比特读取系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及量子计算技术领域，尤其涉及一种放大电路、芯片及量子比特读取系统。
背景技术
随着信息技术的发展，量子计算的应用越来越广泛。例如，量子计算可以解决大数因数分解、量子化学模拟等问题。量子计算可以为这些问题提供指数级的加速优势。量子计算的基本原理是利用量子比特(比如离子)对信息进行编码。单个量子比特的状态(或称为量子态)不仅有0和1两种经典态，还可以是0和1的叠加态，量子比特可以处在一半几率在0态，一半几率在1态。n个量子比特可以同时处于2n个量子态的叠加状态，从而可指数级的提高计算的速度。由于超导量子计算具有较高的可扩展性(如增加量子比特数目)，有望实现通用量子计算。超导量子计算是基于超导电路实现的。超导电路是一种工作在由稀释制冷机提供的超低温环境中的微波电路。超导电路在进行量子计算的时候，需要输入微波信号，输入的微波信号与超导量子比特相互作用完成计算过程。量子比特计算的结果也用微波信号进行读取。读取的微波信号的功率在10-16瓦(W)或更低(几个光子的功率)。
然而，微波信号的读取是在室温中进行的，从而导致引入的热噪音远高于读取的微波信号。为了有效读取微波信号，需要对待读取的微波信号进行放大，放大待读取的微波信号的过程中还需要保持较高的信噪比(即信号强度与噪音强度的比值)。而且，读取一个量子比特需要占用一定中心频率的带宽，当同时读取量子比特数目较多时需要的总带宽也较大。目前采用阻抗变换器型并联式约瑟夫森参量放大器对待读取信号进行大带宽的量子极限放大，请参阅图1。阻抗变换器型并联式约瑟夫森参量放大器包括阻抗变换器和非线性谐振器。其中，阻抗变换器可由带跨线电容桥的共面波导构成，非线性谐振器由平行板电容与非线性可调电感并联形成的。
由于平行板电容器的工艺需要制作多层膜、且带跨线电容桥的波导也需要多层工艺，因此，阻抗变换器型并联式约瑟夫森参量放大器的制作复杂度较高且周期较长。而且，阻抗变换器在参量放大器中会引入额外的电磁波模式，从而导致参量放大器的增益不平坦，进而会影响参量放大器的工作性能。
发明内容
本申请提供一种放大电路、芯片及量子比特读取系统，用于简化放大电路的制作工艺。
第一方面，本申请提供一种放大电路，该放大电路包括N个串联的集总电容电感模块，N为正整数，集总电容电感模块包括集总电容单元集总电感单元，集总电容单元与集总电感单元串联；N个集总电容电感模块中的至少一个集总电容电感模块的集总电感单元包括至少一个超导量子干涉器件(superconducting quantum interference device，SQUID)，包括SQUID的集总电容电感模块还包括泵浦信号线，泵浦信号线与SQUID互感耦合。
基于上述方案，N个串联的集总电容电感模块可以等效于一个等效集总电容模块串联一个等效集总电感模块的电路，等效集总电容模块与串联的等效集总电感模块形成非线性谐振器，该非线性谐振器与外界环境耦合的Q值等于非线性谐振器的阻抗与外界环境的阻抗的比值。为了形成谐振模式，Q值需要大于1/2，因此，可以设计非线性谐振器中的电容的值较小，较小电容值的电容器可以通过平面电容工艺制作，由于平面电容工艺由一步光刻即可完成，从而可以降低制作放大电路的工艺复杂度。
在一种可能的实现方式中，集总电容单元包括一个或多个第一集总电容器，多个第一集总电容器的连接方式为串联和/或并联。
在一种可能的实现方式中，第一集总电容器通过平面电容工艺成型。
通过平面电容工艺成型的第一集总电容器的制作工艺简单。
示例性的，第一集总电容器包括叉指电容器。
在一种可能的实现方式中，N个串联的集总电容电感模块的等效电容Cc与N个串联的集总电容电 感模块的等效对地寄生电容Cs满足关系：Cc/(Cc+Cs)>0.3，其中，N个串联的集总电容电感模块的等效对地寄生电容与N个串联的集总电容电感模块的等效集总电感模块并联，且等效集总电感模块接地。
由于放大电路的带宽取决于放大电路中的非线性谐振器与外界环境的耦合强度(用Q值表征)，Q值越小耦合强度越大，放大电路的带宽越大，又由于等效电容Cc和等效对地寄生电容Cs可以影响Q值，通过设置Cc/(Cc+Cs)>0.3，使得Q值小于10，从而可以使得放大电路具有较大的带宽。
在一种可能的实现方式中，放大电路还包括第二集总电容器，第二集总电容器与N个串联的集总电容电感模块的等效集总电感模块并联，等效集总电感模块接地。
通过在放大电路中增加第二集总电容器，可以使得放大电路的带宽实现从窄带到宽带的变化，即有助于增大放大电路的带宽的可调范围。
在一种可能的实现方式中，N个串联的集总电容电感模块的等效电容Cc与第二集总电容器的电容Cc2满足关系：Cc/(Cc+Cc2)>0.3。
通过设置Cc/(Cc+Cc2)>0.3，使得Q值小于10，从而可以使得放大电路具有较大的带宽。
在一种可能的实现方式中，集总电感单元还可包括一个或多个约瑟夫森结；多个约瑟夫森结的连接方式包括串联和/或并联。
在一种可能的实现方式中，集总电感单元还包括一个或多个第一集总电感器，第一集总电感器为除约瑟夫森结和SQUID外的电感器；多个第一集总电感器的连接方式包括串联和/或并联。
在一种可能的实现方式中，第一集总电感器包括线性集总电感器。
在一种可能的实现方式中，若集总电感单元包括一个或多个SQUID、一个或多个约瑟夫森结、以及一个或多个第一集总电感器，这一个或多个SQUID可以串联也可以并联，一个或多个约瑟夫森结可以串联也可以并联，一个或多个第一集总电感器可以串联也可以并联，SQUID、约瑟夫森结和第一集总电感器之间可以串联也可以并联。
在一种可能的实现方式中，泵浦信号线的一端用于连接泵浦源，另一段用于接地；泵浦信号线传输的来自泵浦源的射频信号用于为待放大信号提供能量。
通过泵浦信号线中传输的射频信号，可以实现对待放大信号进行放大。
在一种可能的实现方式中，泵浦信号线包括共面波导。
通过将共面波导作为泵浦信号线，有助于进一步简化放大电路的制备工艺。而且，若共面波导与SQUID共面还可以增强泵浦信号线与SQUID之间的互感。
第二方面，本申请提供一种芯片，该芯片包括基底以及上述第一方面或第一方面中的任意一种放大电路，放大电路设置于基底。
在一种可能的实现方式中，集总电容单元与集总电感单元位于基底的不同位置；集总电容单元与集总电感单元之间的基底上覆盖有超导金属膜。
第三方面，本申请提供一种量子比特读取系统，该量子比特读取系统包括环形器、以及上述第二方面或第二方面中的任意一种芯片；环形器用于将待放大信号输入芯片，并将经芯片放大后的已放大信号输出。
在一种可能的实现方式中，量子比特读取系统还包括第一隔离器和/或第二隔离器；第一隔离器用于阻止待放大信号和/或已放大信号的反向传输；第二隔离器用于阻止已放大信号的反向传输。
通过第一隔离器阻止待放大信号和/或已放大信号的反向传输，从而可以防止待放大信号对量子比特的影响，以及可以防止放大电路对待放大信号的反作用干扰。通过第二隔离器用于阻止已放大信号的反向传输从而可以保证放大电路的稳定工作，而且可以防止环形器之外的电路的干扰。
上述第二方面至第三方面中任一方面可以达到的技术效果可以参照上述第一方面中有益效果的描述，此处不再重复赘述。
附图说明
图1为现有技术的一种阻抗变换器型并联式约瑟夫森参量放大器的结构示意图；
图2为本申请提供的一种放大电路的结构示意图；
图3为本申请提供的一种放大电路的等效电路示意图；
图4为本申请提供的一种SQUID的结构示意图；
图5为本申请提供的一种约瑟夫森结的结构示意图；
图6为本申请提供的集总电容单元的可能的结构示意图；
图7为本申请提供的又一种放大电路的等效电路示意图；
图8为本申请提供的集总电感的可能的结构示意图；
图9为本申请提供的一种共面波导的结构示意图；
图10a为本申请提供的又一种放大电路的结构示意图；
图10b为本申请提供的又一种放大电路的结构示意图；
图10c为本申请提供的又一种放大电路的结构示意图；
图10d为本申请提供的又一种放大电路的结构示意图；
图11为本申请提供的又一种放大电路的结构示意图；
图12为本申请提供的又一种放大电路的结构示意图；
图13为本申请提供的又一种放大电路的结构示意图；
图14为本申请提供的一种放大电路在芯片上的布局示意图；
图15为本申请提供的一种放大电路在芯片上的布局示意图；
图16为本申请提供的一种放大电路在芯片上的布局示意图；
图17为本申请提供的一种放大电路在芯片上的布局示意图；
图18为本申请提供的一种环形器的结构示意图；
图19为本申请提供的一种量子比特读取系统的架构示意图。
具体实施方式
下面将结合附图，对本申请实施例进行详细描述。
以下，对本申请中的部分用语进行解释说明。需要说明的是，这些解释是为了便于本领域技术人员理解，并不是对本申请所要求的保护范围构成限定。
一、磁通
设在磁感应强度为B的匀强磁场中，有一个有效面积(垂直通过磁场线的面积)为S且与磁场方向垂直的平面，磁感应强度B与有效面积S的乘积，叫做穿过这个平面的磁通量，简称磁通(magnetic flux)。磁通为标量，符号“Φ”，单位韦伯(Wb)。在一般情况下，磁通量是通过磁场在曲面面积上的积分定义的。其中，Φ为磁通量，B为磁感应强度，S为曲面，B·dS为点积，dS为无穷小矢量(见曲面积分)。
二、放大电路的带宽
放大电路的带宽指放大电路能够起到足够放大作用的频率范围。以人耳朵为例，人的耳朵相当于一个振动信号的放大电路，只能响应20-20千赫兹(KHz)的振动，这就是耳朵的带宽。
三、放大电路的动态范围
放大电路的动态范围指放大电路能够合理放大的信号能量上下限。以人耳朵为例，低于0分贝(dB)的声音，耳朵听不见，因为信号能量与自身噪音相当，耳朵已无法分辨。高于100dB的声音会使耳朵极为难受甚至发生物理损伤，这是耳朵所能承受的上限。因此，耳朵的动态范围大约为100dB。
四、量子极限
由量子力学决定的噪声极限。在光学测量中噪声的标准量子极限是指在不采用压缩态光的情况下能得到的最小的量子噪声。
五、电感
电感是闭合回路的一种属性，是一个物理量。当电流通过线圈后，在线圈中形成磁场感应，感应磁场又会产生感应电流来抵制通过线圈中的电流。它是描述由于线圈电流变化，在本线圈中或在另一线圈中引起感应电动势效应的电路参数。电感是自感和互感的总称。提供电感的器件称为电感器。电感器具有一定的电感，它只阻碍电流的变化。如果电感器在没有电流通过的状态下，电路接通时它将试图阻碍电流流过；如果电感器在有电流通过的状态下，电路断开时将试图维持电流不变。
六、互感
当一线圈中的电流发生变化时，在临近的另一线圈中产生感应电动势，叫做互感现象。互感现象是一种常见的电磁感应现象，不仅发生于绕在同一铁芯上的两个线圈之间，而且也可以发生于任何两个相互靠近的电路之间。例如，电感可调的SQUID与泵浦信号线之间也会发生互感。
七、阻抗
在具有电阻、电感和电容的电路里，对电路中的电流所起的阻碍作用叫做阻抗。
八、集总元件
集总元件是指元件大小远小于电路工作频率对应的波长。对于信号而言，集总元件特性始终保持固定、与频率无关。换言之，当信号通过集总元件时，信号在集总元件内部每点的变化相当小，可视为没变化。由集总元件所组成的电路可称为集总式电路。
九、横电磁波(transverse electromagnetic wave，TEM)
横电磁波是指电场分量和磁场分量相互垂直，且都垂直于传播方向的电磁波。
十、品质因子(quality factor)，
品质因子也称为品质因数或Q值，用于表征电路中谐振回路特性的基本参数，具体的可表示一个储能器件(如电感器、电容器等)、谐振电路中所储能量同每周期损耗能量之比的一种质量指标。
十一、谐振频率
由电感L和电容C组成的，可以在一个或若干个频率上发生谐振现象的电路，统称为谐振电路。由电感L和电容C串联而组成的谐振电路称为串联谐振电路。谐振频率是指谐振电路产生谐振(或称为共振)时的频率。此时，谐振电路的感抗与容抗相等，谐振电路对外呈纯电阻性质，即为谐振。发生谐振时，谐振电路将输入信号放大一定的倍数。谐振的实质是电容中的电场能与电感中的磁场能相互转换，此增彼减，完全补偿。电场能和磁场能的总和保持不变，电源不必与电容或电感往返转换能量，只需供给电路中电阻所消耗的电能。
十二、寄生电容
寄生电容或称为杂散电容，是一种不可避免的电容，它存在于电子元件或电路的各个部分之间。例如，当两个电压不同的电导体靠在一起时，它们之间的电场会使电荷储存在它们上面，这种效应就是寄生电容。对地寄生电容是指信号线路上的各电子元件与地之间由于寄生效应产生的电容。
在量子计算领域中，为了获得量子比特的状态信息，需要对量子比特的状态信息进行采集和分析，采集的量子比特的状态信息可以称为读取信号。由于量子比特读取信号极其微弱，以超导量子比特体系为例，量子比特读取信号通常在4-8吉赫兹(GHz)频段，功率在10-16瓦(W)或更低(几个光子的功率)。如此微弱的读取信号，在经过后续的传输中还会受到损失。因此，若量子比特读取信号直接传输出来，会被淹没在噪声(如热噪声、电噪声)中。基于此，需要对量子比特读取信号进行放大。目前对量子比特读取信号进行放大通常采用的是阻抗变换器型并联式约瑟夫森参量放大器进行放大，阻抗变换器型并联式约瑟夫森参量放大器包括阻抗变换器和非线性谐振器，请参阅上述图1。由于平行板电容器需要制作多层膜、且带跨线电容桥的波导也需要多层工艺，因此，阻抗变换器型并联式约瑟夫森参量放大器的制作复杂度较高且周期较长。而且，阻抗变换器在参量放大器中会引入额外的电磁波模式，从而导致参量放大器中的增益不平坦，进而会影响参量放大器的工作性能。
鉴于上述问题，本申请提出一种放大电路。该放大电路可以通过简单的制作工艺制作。需要说明的是，本申请提供的放大电路可以应用于高保真度量子态读取，制备纠缠态微波光子、量子弱测量、量子反馈等场景。
基于上述内容，下面结合附图2至附图13，对本申请提出的放大电路进行具体阐述。
如图2所示，为本申请提供的一种放大电路的结构示意图。该放大电路包括N个集总电容电感模块，N为正整数。集总电容电感模块包括集总电容单元和集总电感单元，集总电容单元与集总电感单元串联。N个集总电容电感模块中的至少一个集总电容电感模块包括的集总电感单元包括至少一个SQUID。包括SQUID的集总电容电感模块还包括泵浦信号线，泵浦信号线与SQUID互感耦合，SQUID的具体结构可参见下述图4的介绍。具体的，SQUID的电感可调，泵浦信号线与SQUID近邻，通过近邻的泵浦信号线中传输的泵浦信号与SQUID的互感，可以改变SQUID环路中的磁通，从而可以调节SQUID的电感。
上述图2的放大电路可以等效为一个等效集总电容模块串联一个等效集总电感模块的电路，其中，等效集总电感模块包括至少一个SQUID。在一种可能的实现方式中，等效集总电感模块的一端与等效集总电容模块连接，等效集总电感模块的另一端接地，请参阅图3。可以理解的是，图3的等效放大电 路不考虑寄生电容的影响，基于此，等效集总电感模块也可以不接地、等效集总电容模块接地。
等效集总电容模块与等效集总电感模块串联形成非线性谐振器(或称为非线性谐振腔或非线性谐振电路)。该非线性谐振器与外界环境耦合的Q值等于非线性谐振器的阻抗与外界环境的阻抗的比值。其中，对于不考虑对地寄生电容的非线性谐振器的阻抗等于C为非线性谐振器的电容，即为等效集总电容模块的电容，L为非线性谐振器的电感，即为等效集总电感模块的电感。外界环境是指与放大电路通过输入输出线连接的放大电路以外的部分统称为放大电路的外界环境，具体可参见下述图19处的相关介绍，此处不再赘述。由于非线性谐振器的系统存在能量耗散，基于带有耗散特性的非谐振系统的动力学特征，为了形成谐振模式，Q值需要大于1/2。因此，需要设计非线性谐振器的阻抗大于外界环境的阻抗(如外界环境的阻抗为50欧姆(Ω)左右)。为了实现这一要求，非线性谐振器中的电容的值低于现有电感与电容并联的电路中的电容的值。例如，非线性谐振器的电容可以小于2皮法(pF)。较小电容值的电容器可以通过平面电容工艺制作出。由于平面电容工艺由一步光刻即可完成，从而可以降低制作放大电路的工艺复杂度。可以理解的是，现有技术中电感与电容并联的电路中非线性谐振器的Q值等于外界环境的阻抗与非线性谐振器的阻抗的比值。而且，基于上述放大电路，可以减小电路中引入额外的电磁波模式，从而有利于平缓增益区域，可以防止出现双峰增益。
其中，SQUID是由两个约瑟夫森结并联形成的环路器件，请参阅图4。两个约瑟夫森结并联形成的SQUID也可以称为直流(direct current，DC)SQUID，SQUID会产生宏观超导量子干涉效应。约瑟夫森结是由两层超导体(如超导金属层)中间夹一层绝缘体(或称为非超导体)构成的S-I-S结构，请参见图5。非超导层对于电子来说就是‘势垒’，温度足够低的时候，超导体快速通过势垒交换成对电子，产生量子隧道效应。其中，约瑟夫森结和SQUID均为非线性电感。通常，约瑟夫森结的电感是固定的，不能调节。例如，约瑟夫森结的电感在[0.1nH，10nH]。超导体是指在某一温度下，电阻为零的导体。超导体不仅具有零电阻的特性，还具有完全抗磁性的特性。完全抗磁性又称迈斯纳效应，“抗磁性”指在磁场强度低于临界值的情况下，磁力线无法穿过超导体，超导体内部磁场为零的现象。
示例性的，本申请中的放大电路可以包括但不限于量子极限放大器，量子极限放大器包括但不限于约瑟夫森参量放大器(Josephson Parametric Amplifier，JPA)。其中，量子极限放大器是指引入噪音为量子极限的放大器。进一步，量子极限放大器包括宽带量子极限放大器。
下面对图2所示的各个功能组件和结构分别进行介绍说明，以给出示例性的具体实现方案。
一、集总电容单元
在一种可能的实现方式中，集总电容单元包括一个第一集总电容器；或者，集总电容单元包括多个串联和/或并联的第一集总电容器。换言之，集总电容单元可以由任意多个第一集总电容器串联和/或并联组成。也可以理解为，若集总电容单元包括多个第一集总电容器，这多个第一集总电容器的连接方式可以是串联和/或并联。
可以理解的是，n个串联电容器的总电容C与n个电容器的电容满足下述公式1，n个并联电容器的总电容C与n个电容器的电容满足下述公式2。

C＝C1+C2…+Cn   公式2
请参阅图6，为本申请提供的集总电容单元的可能的结构示例。图6中的(a)给出了一种集总电容单元包括一个第一集总电容器的示意图。基于此，集总电容单元的总电容C等于第一集总电容器的电容C1，即C＝C1。图6中的(b)给出了一种集总电容单元包括两个串联的第一集总电容器的示意图。该示例中以集总电容单元包括串联的第一集总电容器C1和第一集总电容器C2，基于此，集总电容单元的总电容C等于1/(1/C1+1/C2)＝C1×C1/(C1+C2)。图6中的(c)给出了一种集总电容单元包括两个并联的第一集总电容器的示意图。该示例中以集总电容单元包括并联的第一集总电容器C1和第一集总电容器C2，基于此，集总电容单元的总电容C等于C1+C2。图6中的(d)给出了一种集总电容单元包括两个第一集总电容器并联后与另外一个第一集总电容器串联的示意图。该示例中以集总电容单元包括第一集总电容器C1和第一集总电容器C2并联后，再与第一集总电容器C3串联，基于此，集总电容单元的总电容C等于1/(1/(C1+C2)+1/C3)。
可以理解的是，上述图6给出的集总电容单元包括的第一集总电容器的数量和连接方式仅是示例， 集总电容单元可以包括比上述图6中的(d)更多的第一集总电容器，多个第一集总电容器可以是串联、或者也可以是并列、或者也可以是部分串联部分并联，本申请对此不作限定。集总电容单元包括的第一集总电容器的数量与电容工艺、放大电路的大小以及集总电容单元的总电容相关。
在一种可能的实现方式中，第一集总电容器可以通过平面电容工艺制作。也可以理解为，集总电容单元包括的各个第一集总电容器均可以通过平面电容工艺制作得到。平面电容工艺包括但不限于刻蚀工艺或剥离工艺。对于刻蚀工艺是指在基底上先镀一层超导金属薄膜，然后在超导金属薄膜上匀一层光刻胶，将需要刻蚀的区域(芯片设计中仅有基底没有金属薄膜覆盖的区域)曝光显影后通过湿法将显影后的超导金属刻蚀掉即形成了所需的结构。对于剥离工艺是指在基底上匀一层光刻涂胶，将需要涂覆超导金属膜的区域的曝光显影出来，并在曝光显影后的基底上镀制超导金属膜，再放在溶液中将光刻胶剥离形成所需的结构。其中，第一集总电容器例如可以是叉指电容。
在一种可能的实现方式中，放大电路的带宽取决于放大电路中的非线性谐振器与外界环境的耦合强度(用Q值表征)。Q值越大耦合强度越小，放大电路的带宽越小；Q值越小耦合强度越大，放大电路的带宽越大。因此，放大电路为了实现较大的带宽，需要增加非线性谐振器与外界环境的耦合强度从而减小Q值。具体的，Q值小于10，放大器可以实现大带宽(或称为大带宽)。
进一步，Q值与放大电路中的电容相关。为了使得放大电路可以实现宽带，N个串联的集总电容电感模块的等效电容Cc与N个串联的集总电容电感模块的等效对地寄生电容Cs满足关系1：Cc/(Cc+Cs)>0.3。N个串联的集总电容电感模块的等效电容Cc即为图3中的等效集总电容模块的电容，N个串联的集总电容电感模块的等效对地寄生电容Cs即为图3中的等效集总电容模块的对地寄生电容，请参阅图7。对于需要考虑对地寄生电容的情况下，N个串联的集总电容电感模块的等效对地寄生电容与N个串联的集总电容电感模块的等效集总电感模块并联，且等效集总电感模块接地。可以理解的是，上述关系是通过电路模拟得到的。
下面分情形分别介绍N个串联的集总电容电感模块的等效电容Cc及N个串联的集总电容电感模块的等效对地寄生电容Cs。
情形1，放大电路包括一个集总电容电感模块，N＝1。
下面基于集总电容电感模块中的集总电容单元包括的第一集总电容器的数量，分两种情形介绍。
情形1.1，集总电容单元包括一个第一集总电容器。
基于此，N个串联的集总电容电感模块的等效电容Cc等于第一集总电容器的电容Cc11，N个串联的集总电容电感模块的等效对地寄生电容Cs等于该集总电容电感模块的对地寄生电容的电容Cs11。因此，上述关系1可以表示为：
Cc11/(Cc11+Cs11)>0.3
情形1.2，集总电容单元包括多个串联和/或并联的第一集总电容器。
基于此，N个串联的集总电容电感模块的等效电容Cc等于多个第一集总电容器的总电容Cc12，多个第一集总电容器的总电容可结合上述公式1和/或公式2的介绍确定，此处不再赘述。N个串联的集总电容电感模块的等效对地寄生电容Cs等于该集总电容电感模块的对地寄生电容的总电容Cs12。因此，上述关系1可以表示为：
Cc12/(Cc12+Cs12)>0.3
需要说明的是，不同的第一集总电容器的电容可以相同也可以不同，本申请对此不作限定。此外，对于该情形1.2一种可能的情况是多个第一集总电容器中的每个第一集总电容器的对地寄生电容Cs12较小。可以理解的是，集总电容单元包括的第一集总电容器的个数越多，每个第一集总电容器的对地寄生电容的数值就要越小。
基于上述情形1，在一种可能的实现方式中，该放大电路还包括第二集总电容器，第二集总电容器与集总电容电感模块的等效集总电感模块并联，该等效集总电感模块接地。集总电容电感模块的等效对地寄生电容Cs相较于第二集总电容器的总电容可以忽略不计。基于此，集总电容电感模块的等效电容Cc与第二集总电容器的电容Cc2满足关系2：Cc/(Cc+Cc2)>0.3。通过在放大电路中增加第二集总电容器，可以使得放大电路实现从窄带到宽带的变化，即有助于增大放大电路的带宽的可调范围。
在一种可能的实现方式中，集总电容电感模块的等效对地寄生电容Cs相较于第二集总电容器的总电容不能忽略不计时，集总电容电感模块的等效电容Cc、第二集总电容器的电容Cc2及集总电容电感模块的等效对地寄生电容Cs之间满足关系3：Cc/(Cc+Cc2+Cs)>0.3。
情形2，放大电路包括多个串联集总电容电感模块，N＞1。
基于此，N个串联的集总电容电感模块的等效电容Cc等于各个集总电容电感模块的总电容Ccc，各个集总电容电感模块的总电容可参见上述情形1.1或情形1.2的介绍，此处不再赘述。
基于上述情形2，在一种可能的实现方式中，该放大电路还包括第二集总电容器，第二集总电容器与这N个串联的集总电容电感模块的等效集总电感模块并联，等效集总电感模块接地。进一步，N个串联的集总电容电感模块的等效对地寄生电容Cs相较于第二集总电容器的总电容可以忽略不计。也可以理解为，N个串联的集总电容电感模块的等效对地寄生电容Cs较小。基于此，N个串联的集总电容电感模块的等效电容Cc与第二集总电容器的电容Cc2满足关系2：Cc/(Cc+Cc2)>0.3。通过在放大电路增加第二集总电容器，可以控制放大电路的各个参数(比如Q值，带宽，谐振频率等)，且放大电路的带宽可以实现从窄带到宽大的变化，即有助于增大参数(如带宽)的可调范围。
在一种可能的实现方式中，N个串联的集总电容电感模块的等效对地寄生电容Cs相较于第二集总电容器的总电容不能忽略不计时，集总电容电感模块的等效电容Cc、第二集总电容器的电容Cc2及N个串联的集总电容电感模块的等效对地寄生电容Cs之间满足关系4：Cc/(Cc+Cc2+Cs)>0.3。
可以理解的是，每个集总电容电感模块的对地寄生电容较小时，放大电路可以等效为图7所示的等效放大电路。每个集总电容电感模块的对地寄生电容忽略不计时，放大电路可以等效为图3所示的等效放大电路。
二、集总电感单元
在一种可能的实现方式中，N个集总电容电感模块中的至少一个集总电容电感模块包括的集总电感单元包括至少一个SQUID，包括SQUID的集总电容电感模块还包括泵浦信号线。
如下以包括至少一个SQUID的集总电感单元为例介绍。若集总电感单元包括多个SQUID，这多个SQUID可以是串联的，或者也可以是并联的，或者也可以是部分为串联的部分为并联的。可以理解的是，为了便于放大电路的制作，通常包括的SQUID的数量不大于100。
在一种可能的实现方式中，集总电感单元还可以包括至少一个约瑟夫森结。也可以理解为，集总电感单元包括至少一个SQUID和至少一个约瑟夫森结。
在另一种可能的实现方式中，集总电感单元还可以包括至少一个集总线性电感器。也可以理解为，集总电感单元包括至少一个SQUID和至少一个集总线性电感器。通常，集总线性电感器的电感不能调节。
在又一种可能的实现方式中，集总电感单元还可以包括至少一个约瑟夫森结和至少一个集总线性电感器。也可以理解为，集总电感单元包括至少一个SQUID、至少一个约瑟夫森结和至少一个集总线性电感器。
需要说明的是，N个集总电容电感模块中不包括SQUID的集总电容电感模块中的集总电感单元包括至少一个约瑟夫森结和/或至少一个集总线性电感器。
可以理解的是，n个串联电感器的总电感L与n个电感器的电感满足下述公式3，n个并联电感器的总电感L与n个电感器的电感满足下述公式4。
L＝L1+L2+…Ln   公式3
请参阅图8，为本申请提供的集总电感的可能的结构示例。图8中的(a)给出了一种集总电感单元包括三个串联的SQUID的示意图。基于此，集总电感单元的总电感L等于三个串联的SQUID的电感之和，SQUID的电感用L1表示，L＝L1+L1+L1。图8中的(b)给出了一种集总电感单元包括集总线性电感器和SQUID串联的结构示意图。基于此，集总电感单元的总电感L等于集总线性电感器的电感和SQUID的电感之和，SQUID的电感用L1表示，集总线性电感器的电感用L2表示，即L＝L1+L2。图8中的(c)给出了一种集总电感单元包括一个集总线性电感器、一个约瑟夫森结和一个SQUID的串联结构示意图。基于此，集总电感单元的总电感L等于集总线性电感器的电感、约瑟夫森结的电感和SQUID的电感之和，SQUID的电感用L1表示，集总线性电感器的电感用L2表示，约瑟夫森结的电感用L3表示，即L＝L1+L2+L3。图8中的(d)给出了一种集总电感单元包括约瑟夫森结与集总线性电感器并联后再串联一个集总线性电感器和一个SQUID的示意图。基于此，集总电感单元的总电感L等于1/(1/L3+1/L2)+L2+L1。
可以理解的是，上述8给出的集总电感单元包括的SQUID、约瑟夫森结和集总线性电感器的数量和连接方式仅是示例，本申请对此不作限定。集总电感单元包括的SQUID、约瑟夫森结和集总线性电感器的数量与集总电感单元的总电感、制作工艺等相关。
三、泵浦信号线
在一种可能的实现方式中，泵浦信号线的一端与泵浦源连接，另一端接地(例如芯片的地)。泵浦信号线用于传输泵浦信号。其中，泵浦源包括直流信号源和射频信号源。相应的，泵浦信号包括直流信号和射频信号。射频信号主要用于放大量子比特读取信号，量子比特读取信号可以称为待放大信号。直流信号用于调节放大电路中的非线性谐振器的工作频率。
具体的，直流信号源提供的直流信号用于调节放大电路中的非线性谐振器的工作频率。由于泵浦信号线与SQUID近邻，泵浦信号线中传输的直流信号与SQUID互感，可以改变SQUID的磁通，从而可以改变SQUID的电感，进而可以改变非线性谐振器的工作频率。射频信号源提供的射频信号用于放大待放大的信号。换言之，射频信号源提供的射频信号为量子比特读取信号(待放大信号)供能。例如，射频信号与待放大信号同频。基于此，泵浦信号利用非线性谐振器非线性的特点构造出等效的参量调制动力学方程，以参量调制的方式给系统供能，从而实现对待放大信号的放大。再比如，射频信号的频率是待放大信号的频率的2倍。基于此，泵浦信号可以直接调制非线性谐振器动力学方程中的参数，为系统供能，从而实现对待放大信号进行放大。可以理解的是，射频信号与待放大信号同频的放大过程也可以理解为四波混频过程，射频信号的频率是待放大信号的频率的2倍的放大过程也可以理解为三波混频过程。
示例性的，泵浦信号线包括共面波导(或称为共面微带传输线)，请参阅图9。共面波导是一种共面的双导体系统。共面波导是制作在介质层表面的三条平行的导带层(如金属薄膜)。位于中心的导带层称为中心导带层，中心导带层的宽度为S，用于传输微波信号(即泵浦信号)。两侧的导带层均用于接地。中心导带层与两侧的导带层之间的宽度为w，中心导体与两侧的平板导体之间为空气。共面波导是一种分布式电路元件，其电容、电感、导抗和阻抗均匀地沿着共面波导信号传播方向分布，共面波导传播的是TEM波(或准TEM波)，沿着信号传播方向，波导的阻抗处处相等，因而不存在信号反射，信号能够几乎无损地通过。而且，共面波导没有截止频率，对于一段均匀的共面波导来说，绝大部分频段的微波信号都能畅通无阻地传输，因而又称为传输线，即共面波导传输线。可以理解的是，泵浦信号线也可以是其它可能传输线，本申请对此不作限定。
在一种可能的实现方式中，泵浦信号线与SQUID共面；或者，泵浦信号线也可以位于SQUID所在平面的上方或下方。当泵浦信号线为共面波导且与SQUID共面，可以简化放大电路的制备，增强互感。
基于上述内容，下面结合具体结构，给出上述放大电路的四种具体实现方式，以便于进一步理解上述放大电路的结构。需要说明的是，上述给出各个模块和单元中，如果没有特殊说明以及逻辑冲突，根据其内在的逻辑关系可以组合形成其它可能的放大电路。
如图10a所示，为本申请提供的又一种放大电路的结构示意图。该放大电路包括一个集总电容电感模块，该集总电容电感模块包括集总电容单元、集总电感单元和泵浦信号线，集总电感单元接地。其中，集总电容单元以包括一个第一集总电容器为例，集总电感单元以包括串联的多个SQUID为例，组成SQUID的每个约瑟夫森结的电感在[0.1nH，10nH]范围。第一集总电容器的电容小于2pF，集总电容电感模块的对地寄生电容小于2pF。第一集总电容器的电容与集总电容电感模块的对地寄生电容的比大于3:7。第一集总电容器、集总电容电感模块的对地寄生电容和串联的多个SQUID构成放大电路的非线性谐振器。该非线性谐振器的谐振频率通常在4～10GHz之间，非线性谐振器的Q值小于10，基于此，该放大电路的带宽较大。
如图10b所示，为本申请提供的又一种放大电路的结构示意图。该放大电路包括一个集总电容电感模块，该集总电容电感模块包括集总电容单元、集总电感单元和泵浦信号线，集总电感单元接地。其中，集总电容单元以包括两个第一集总电容器为例，其余可参见上述图10a的介绍，此处不再赘述。
如图10c和图10d所示，为本申请提供的两种可能的放大电路的结构示意图。放大电路包括两个集总电容电感模块，分别为集总电容电感模块A和集总电容电感模块B。其中，集总电容电感模块A和集总电容电感模块B中至少一个包括泵浦信号线。该示例中以集总电容电感模块B包括泵浦信号线示 例。集总电容电感模块A包括集总电容单元和集总电感单元。集总电容电感模块B包括集总电容单元、集总电感单元和泵浦信号线，集总电容电感模块B包括的集总电感单元接地。其中，集总电容电感模块B包括的集总电容单元、集总电感单元和泵浦信号线可参见上述图10a的介绍，集总电容电感模块A包括的集总电容单元和集总电感单元可参见上述图10a的介绍，此处不再赘述。基于上述图10c或图10d，两个第一集总电容器的总电容与集总电容电感模块A和集总电容电感模块B两个模块的对地寄生电容的比大于3:7。换言之，两个第一集总电容器的总电容/(集总电容电感模块A和集总电容电感模块B两个模块的对地寄生电容)大于3:7。
如图11所示，为本申请提供的又一种放大电路的结构示意图。该放大电路包括一个集总电容电感模块和第二集总电容器，该集总电容电感模块包括集总电容单元、集总电感单元和泵浦信号线，集总电感单元接地。其中，集总电容单元以包括一个第一集总电容器为例，集总电感单元以包括串联的多个SQUID为例，组成SQUID的每个约瑟夫森结的电感在[0.1nH，10nH]范围。第一集总电容器的电容小于2pF，第二集总电容器的电容小于2pF。集总电容电感模块的对地寄生电容相较于第二集总电容器的电容可以忽略不计。第一集总电容器的电容与和第二集总电容器的电容的比大于3:7。第一集总电容器、第二集总电容器和串联的多个SQUID构成放大电路的非线性谐振器。关于非线性谐振器的介绍可参见前述相关介绍，此处不再赘述。
如图12所示，为本申请提供的又一种放大电路的结构示意图。该放大电路包括一个集总电容电感模块，该集总电容电感模块包括集总电容单元、集总电感单元和泵浦信号线，该示例中以集总电感单元接地为例。其中，集总电容单元以包括第一集总电容器为例、集总电感单元以包括串联的多个约瑟夫森结和一个SQUID为例，串联的约瑟夫森结与SQUID串联。组成SQUID的每个约瑟夫森结的电感在[0.1nH，10nH]范围，串联的约瑟夫森结的电感在[0.1nH，10nH]范围。第一集总电容器的电容小于2pF，集总电容电感模块的对地寄生电容的电容小于2pF。第一集总电容器的电容与集总电容电感模块的对地寄生电容的比大于3:7。第一集总电容器、集总电容电感模块的对地寄生电容、串联的多个约瑟夫森结和SQUID构成放大电路的非线性谐振器。关于非线性谐振器的介绍可参见前述相关介绍，此处不再赘述。
如图13所示，为本申请提供的又一种放大电路的结构示意图。该放大电路包括一个集总电容电感模块，该集总电容电感模块包括集总电容单元、集总电感单元和泵浦信号线，该示例中以集总电感单元接地为例。其中，集总电容单元以包括第一集总电容器为例、集总电感单元以包括集总线性电感器和一个SQUID为例，集总线性电感器与SQUID串联。组成SQUID的每个约瑟夫森结的电感在[0.1nH，10nH]范围，集总线性电感器的电感小于1000nH。第一集总电容器的电容小于2pF，集总电容电感模块的对地寄生电容的电容小于2pF。第一集总电容器的电容与集总电容电感模块的对地寄生电容的比大于3:7。第一集总电容器、集总电容电感模块的对地寄生电容、SQUID和集总线性电感器构成放大电路的非线性谐振器。关于非线性谐振器的介绍可参见前述相关介绍，此处不再赘述。
需要说明的是，对量子比特读取信号进行放大时，可以是级联的多级放大电路依次进行放大。由于级联的多级放大电路中的第一级放大电路对信号的最终信噪比影响较大。因此，上述示例中的放大电路可以作为第一级放大电路，第一级放大器引入的噪声为量子极限。
基于上述描述的放大电路的结构和功能原理，本申请还可以提供一种芯片。该芯片可以包括上述任一实施例中的放大电路。进一步，可选地，芯片还包括基底，放大电路设置于基底上。如下，以放大电路包括一个电容电感模块为例介绍。
图14为本申请提供的一种放大电路在芯片上的布局示意图。该放大电路以上述图10a所示的放大电路为例。第一集总电容器与SQUID之间通过超导金属膜连接。也可以理解为，超导金属膜覆盖在第一集总电容器与SQUID之间的基底上，以实现集总电容单元和集总电感单元的连接。
图15为本申请提供的又一种放大电路在芯片上的布局示意图。该放大电路以上述图11所示的放大电路为例。第一集总电容器与第二集总电容器近邻，第一集总电容器与串联的多个SQUID之间的基底上覆盖有超导金属膜，以实现第一集总电容器与SQUID连接，以及第二集总电容器与串联的多个SQUID之间的基底上覆盖有超导金属膜，以实现第二集总电容器与SQUID的连接。
图16为本申请提供的又一种放大电路在芯片上的布局示意图。该放大电路以上述图12所示的放大电路为例。第一集总电容器与串联的多个约瑟夫森结之间通过超导金属膜连接。也可以理解为，超导金 属膜覆盖在第一集总电容器与约瑟夫森结之间的基底上，以实现第一集总电容器与约瑟夫森结的连接。
图17为本申请提供的又一种放大电路在芯片上的布局示意图。该放大电路以上述图13所示的放大电路为例。第一集总电容器与集总线性电感器之间的基底上覆盖有超导金属膜。也可以理解为，超导金属膜覆盖在第一集总电容器与集总线性电感器之间的基底上，以实现第一集总电容器与集总线性电感器的连接。
通过集总式电路，可以使得芯片尺寸相对现有并联式的电路的尺寸减小至少80倍从而可以提高芯片的集成度。
在一种可能的实现方式中，上述芯片需要工作在极低温环境中，如低于30(毫开)mK。
基于上述描述的芯片的结构和功能原理，本申请还可以提供一种量子比特读取系统。该量子比特读取系统可以包括上述任一实施例中的放大电路或芯片。进一步，可选地，量子比特读取系统还包括环形器。环形器用于将待放大信号输入芯片，并将经芯片放大后的已放大信号输出。环形器是一种多端口非互易器件(如非互易光学器件或非互易电学器件等)，信号只能沿一个方向传播。如图18所示，为本申请提供的一种环形器的结构示意图。若信号从端口1输入，则从端口2输出的损耗较小，从端口3输出的损耗较大；若信号从端口2输入，则将从端口3输出的损耗较小，从端口1的输出损耗较大；若信号从端口3输入时，则从端口1输出的损耗较小，从端口2输出的损耗较大。
请参阅图19，为本申请提供的一种量子比特读取系统的架构示意图。该量子比特读取系统包括芯片和环形器。该芯片例如可以是超导量子芯片。进一步，量子比特读取系统还包括第一隔离器和/或第二隔离器。该芯片以包括两个端口为例，分别为端口A和端口B。端口A用于输入泵浦信号。端口B用于输入待放大信号和输出已放大信号。端口B也可称为输入输出端。端口B与环形器串联。环形器以包括三个端口为例，分别为端口1、端口2和端口3。环形器的端口1与第一隔离器连接，环形器的端口3与第二隔离器连接，环形器的端口2与芯片的端口B连接，芯片的端口A与泵浦源连接。待放大信号从环形器的端口1输入，经过环形器从端口2输出至超到量子芯片的端口B，待放大信号经芯片放大后得到已放大信号，已放大信号从芯片的端口B输出至环形器的端口2，经环形器的端口2进入环形器，并通过环形器的端口3输出至第二隔离器。
其中，第一隔离器用于阻止待放大信号和/或已放大信号的反向传输，从而可以防止待放大信号对量子比特的影响，以及可以防止放大电路对待放大信号的反作用干扰。第二隔离器用于阻止已放大信号的反向传输，进一步，第二隔离器还用于阻止下一级放大电路的已放大信号的反向传输，从而可以保证放大电路的稳定工作，而且可以防止环形器的端口3之外的电路的干扰。可以理解的是，隔离器是一种单向信号传输器件，可以抑制信号的来回反射。
在一种可能的实现方式中，量子比特读取系统还包括高电子迁移率晶体管(high electron mobility transistor，HEMT)和/或射频放大电路以及读取电子仪器等。其中，读取电子仪器包括但不限于网络分析仪，数据采集卡等。高电子迁移率晶体管用于在4开(K)的温度下进一步放大已放大信号。射频放大电路用于在室温下进一步放大已放大信号。读取电子仪器用于将已放大信号转化为便于计算机处理的形式并最终通过计算机数据处理得到有用的物理量(例如量子比特的量子态)。
可以理解的是，上述泵浦源可以属于量子比特读取系统。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
本申请中，“均匀”不是指绝对的均匀，可以允许有一定工程上的误差。“垂直”不是指绝对的垂直，可以允许有一定工程上的误差。“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。在本申请的文字描述中，字符“/”，一般表示前后关联对象是一种“或”的关系。在本申请的公式中，字符“/”，表示前后关联对象是一种“相除”的关系。本申请中，符号“(a，b)”表示开区间， 范围为大于a且小于b；“[a，b]”表示闭区间，范围为大于或等于a且小于或等于b；“(a，b]”表示半开半闭区间，范围为大于a且小于或等于b；“(a，b]”表示半开半闭区间，范围为大于a且小于或等于b。另外，在本申请中，“示例性的”一词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。或者可理解为，使用示例的一词旨在以具体方式呈现概念，并不对本申请构成限定。
可以理解的是，在本申请中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。术语“第一”、“第二”等类似表述，是用于分区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种放大电路，其特征在于，包括N个串联的集总电容电感模块，所述N为正整数，所述集总电容电感模块包括集总电容单元和集总电感单元，所述集总电容单元与所述集总电感单元串联；
    所述N个集总电容电感模块中的至少一个集总电容电感模块的集总电感单元包括至少一个超导量子干涉器件SQUID，包括所述SQUID的集总电容电感模块还包括泵浦信号线，所述泵浦信号线与所述SQUID互感耦合。
  2. 如权利要求1所述的电路，其特征在于，所述集总电容单元包括一个或多个第一集总电容器，多个所述第一集总电容器的连接方式为串联和/或并联。
  3. 如权利要求2所述的电路，其特征在于，所述第一集总电容器通过平面电容工艺成型。
  4. 如权利要求2或3所述的电路，其特征在于，所述第一集总电容器包括叉指电容器。
  5. 如权利要求1～4任一项所述的电路，其特征在于，所述N个串联的集总电容电感模块的等效电容Cc与所述N个串联的集总电容电感模块的等效对地寄生电容Cs满足关系：Cc/(Cc+Cs)>0.3；
    所述N个串联的集总电容电感模块的等效对地寄生电容与所述N个串联的集总电容电感模块的等效集总电感模块并联，所述等效集总电感模块接地。
  6. 如权利要求2～4任一项所述的电路，其特征在于，所述放大电路还包括第二集总电容器；
    所述第二集总电容器与所述N个串联的集总电容电感模块的等效集总电感模块并联，所述等效集总电感模块接地。
  7. 如权利要求6所述的电路，其特征在于，所述N个串联的集总电容电感模块的等效电容Cc与所述第二集总电容器的电容Cc2满足关系：Cc/(Cc+Cc2)>0.3。
  8. 如权利要求1～7任一项所述的电路，其特征在于，所述集总电感单元还可包括一个或多个约瑟夫森结；
    多个约瑟夫森结的连接方式包括串联和/或并联。
  9. 如权利要求1～8任一项所述的电路，其特征在于，所述集总电感单元还包括一个或多个第一集总电感器，所述第一集总电感器为除约瑟夫森结和所述SQUID外的电感器；
    多个第一集总电感器的连接方式包括串联和/或并联。
  10. 如权利要求9所述的电路，其特征在于，所述第一集总电感器包括线性集总电感器。
  11. 如权利要求1～10任一项所述的电路，其特征在于，所述泵浦信号线的一端用于连接泵浦源，另一段用于接地；
    所述泵浦信号线传输的来自所述泵浦源的射频信号用于为待放大信号提供能量。
  12. 如权利要求1～11任一项所述的电路，其特征在于，所述泵浦信号线包括共面波导。
  13. 一种芯片，其特征在于，包括基底、以及如权利要求1～12任一项所述的放大电路，所述放大电路设置于所述基底。
  14. 如权利要求13所述的芯片，其特征在于，所述集总电容单元与所述集总电感单元位于所述基底的不同位置；
    所述集总电容单元与所述集总电感单元之间的所述基底上覆盖有超导金属膜。
  15. 一种量子比特读取系统，其特征在于，包括环形器、以及如权利要求13或14所述的芯片；
    所述环形器用于将待放大信号输入所述芯片，并将经所述芯片放大后的已放大信号输出。
  16. 如权利要求15所述的系统，其特征在于，所述系统还包括第一隔离器和/或第二隔离器；
    所述第一隔离器，用于阻止所述待放大信号和/或所述已放大信号的反向传输；
    所述第二隔离器，用于阻止所述已放大信号的反向传输。
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CN110120792A (zh) * 2019-06-17 2019-08-13 合肥本源量子计算科技有限责任公司 一种量子参量放大器
CN110138352A (zh) * 2019-06-17 2019-08-16 合肥本源量子计算科技有限责任公司 一种量子参量放大器
CN110277969A (zh) * 2019-06-17 2019-09-24 合肥本源量子计算科技有限责任公司 一种量子参量放大器
CN113242027A (zh) * 2021-02-24 2021-08-10 南京大学 基于多个超导约瑟夫森结串联的阻抗匹配约瑟夫森参量放大器

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* Cited by examiner, † Cited by third party
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CN110120792A (zh) * 2019-06-17 2019-08-13 合肥本源量子计算科技有限责任公司 一种量子参量放大器
CN110138352A (zh) * 2019-06-17 2019-08-16 合肥本源量子计算科技有限责任公司 一种量子参量放大器
CN110277969A (zh) * 2019-06-17 2019-09-24 合肥本源量子计算科技有限责任公司 一种量子参量放大器
CN113242027A (zh) * 2021-02-24 2021-08-10 南京大学 基于多个超导约瑟夫森结串联的阻抗匹配约瑟夫森参量放大器

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