WO2024021177A1 - 一种动态存储器操作方法 - Google Patents

一种动态存储器操作方法 Download PDF

Info

Publication number
WO2024021177A1
WO2024021177A1 PCT/CN2022/112132 CN2022112132W WO2024021177A1 WO 2024021177 A1 WO2024021177 A1 WO 2024021177A1 CN 2022112132 W CN2022112132 W CN 2022112132W WO 2024021177 A1 WO2024021177 A1 WO 2024021177A1
Authority
WO
WIPO (PCT)
Prior art keywords
read
state
voltage
memory cell
write
Prior art date
Application number
PCT/CN2022/112132
Other languages
English (en)
French (fr)
Inventor
童浩
汪宾浩
缪向水
Original Assignee
华中科技大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华中科技大学 filed Critical 华中科技大学
Priority to US18/021,177 priority Critical patent/US12057158B1/en
Publication of WO2024021177A1 publication Critical patent/WO2024021177A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4068—Voltage or leakage in refresh operations

Definitions

  • the present invention belongs to the field of memory technology, and more specifically, relates to a dynamic memory operating method.
  • DRAM Dynamic Random Access Memory
  • 1T1C 1T1C structure
  • the transistor is a three-port device, its peripheral control circuit needs to consume a large area, and the three-port device is not suitable for three-dimensional stacking, making it difficult for DRAM to pass Three-dimensional integration to achieve high-density storage is currently the most critical factor restricting DRAM performance.
  • the purpose of the present invention is to provide a dynamic memory operation method that can effectively ensure the normal operation of the memory unit for read and write operations even when the capacitor in the selected memory unit leaks.
  • the present invention provides a dynamic memory operating method.
  • the dynamic memory includes word lines and bit lines arranged perpendicularly to each other and memory cells arranged in an array between the word lines and the bit lines.
  • the unit includes a capacitor connected in series and a two-terminal gate device.
  • the two-terminal gate device has bidirectional conduction characteristics and has a conduction threshold voltage V TH and a holding voltage Vhold.
  • the method includes the following steps:
  • step (3) Perform corresponding operations on the selected storage unit according to the operation instruction type information in the operation instruction. If the received operation instruction type is a read operation, output the temporarily stored data to the corresponding I/O port, and then execute the steps (3); If the type of operation command received is a refresh operation, perform step (3); if the type of operation command received is a write operation, perform step (4);
  • the dynamic memory operation method provided by the present invention is set to perform a refresh operation on the selected memory unit according to the interval time T, and the interval time T is less than the voltage value of the capacitor in the memory unit during the write operation and the read operation correctly reads out the state of the memory unit.
  • the time t required for the critical capacitance voltage value of the data can effectively ensure that the read operation can always correctly read the status data of the storage unit; in addition, the setting is selected immediately when receiving the operation command.
  • the storage unit performs read operations and temporarily stores status data, and a refresh operation step is performed after each read operation (rewriting the temporarily stored data to the storage unit), which can effectively ensure that subsequent write operations are correctly written. Stores the status data of the unit.
  • step (1) the step of performing a read operation on the selected memory unit and temporarily storing the status data read in the read operation is specifically:
  • step (a) the read voltage V read satisfies the following relationship: V read -V C1 >V TH , V read -V C0 ⁇ V TH , where V C1 is the memory unit The capacitor voltage when it is in state 1, and V C0 is the capacitor voltage when the memory cell is in state 0.
  • writing state 1 to the selected memory cell is performed by applying voltage V WL1 on the word line connected to the selected memory cell, and applying voltage V on the bit line connected to the selected memory cell.
  • BL1 thereby forming a voltage difference of V IN1 at both ends of the selected memory cell
  • writing state 0 to the selected memory cell is accomplished by applying voltage V WL0 to the word line connected to the selected memory cell. This is achieved by applying voltage V BL0 to the bit line connected to the selected memory cell, thereby forming a voltage difference of V IN0 across both ends of the selected memory cell;
  • V IN1 V BL1 –V WL1
  • V IN0 V BL0 –V WL0
  • the interval time T is less than the time t required for the capacitor voltage in the memory cell to drop from
  • step (4) is specifically:
  • the write state 1 operation is directly performed on the selected memory unit; when the operation information of the write operation is write state 0, the write state 1 operation is performed first.
  • the selected storage unit performs a write operation of state 1, and then performs a write operation of state 0 on the selected storage unit.
  • the location information of the selected memory unit in the operation instruction includes bitwise, entire row, entire column or matrix location information.
  • Figure 1 is a schematic flowchart of a dynamic memory operating method provided by an embodiment of the present invention.
  • Figures 2 and 3 correspond to schematic block diagrams of a dynamic memory bitwise operation method and a dynamic memory entire row operation method provided by an embodiment of the present invention
  • Figure 4 and Figure 5 correspond to a diagram of applying a 4.5V read voltage to the selected memory cell in state 1 and state 0 according to a specific embodiment of the present invention
  • Figure 6 is a diagram of applying -4.5V write 1 voltage to the selected memory cell in state 0 provided by a specific embodiment of the present invention.
  • Figure 7 is a diagram of applying a 4.5V write 0 voltage to a selected memory cell in state 1 provided by a specific embodiment of the present invention.
  • FIG. 8 is a voltage diagram of a refresh operation for a selected memory cell in state 0 provided by a specific embodiment of the present invention.
  • the present invention provides a dynamic memory operating method.
  • the applicable dynamic memory includes word lines, bit lines and words arranged vertically.
  • Memory cells arranged in an array between lines and bit lines.
  • the memory cells include series-connected capacitors and a two-terminal gate device.
  • the two-terminal gate device has bidirectional conduction characteristics and has a conduction threshold voltage V TH and a holding voltage Vhold. .
  • Figure 1 is a flow chart of a dynamic memory operating method provided by an embodiment of the present invention. As shown in Figure 1, the method includes steps S10 to S40, which are detailed as follows:
  • the selected storage unit is read according to the location information of the selected storage unit in the operation instruction. And temporarily store the read status data. Specifically, it can be temporarily stored in a read buffer (read buffer).
  • step S10 the interval time T is less than the time t required for the voltage value of the capacitor in the memory cell to drop to the critical capacitance voltage value for the read operation to correctly read the state data of the memory cell during the write operation. Since the voltage of the capacitor in the memory cell will gradually decrease due to the leakage effect, when the voltage value of the capacitor drops to the critical capacitor voltage value for correctly reading the status data during the read operation, it will cause reading and writing errors in subsequent read operations. For example, the current write status of the memory unit is 1, and the voltage value of the capacitor in the memory unit is V 1 at this time.
  • the operation instructions provided by this embodiment include the location information of the selected storage unit and the operation instruction type.
  • the operation instruction types include read operations, write operations, and refresh operations.
  • the location information of the selected memory unit includes bit-wise, entire row, entire column or matrix location information, that is, the word line and bit line location information where the selected memory unit is located, which is used to correspond to the bit-wise, entire row, entire column or matrix pair dynamic memory. Read and write operations are performed on the memory cells in the For example, when it is necessary to perform bit-by-bit read or write operations on memory cells in dynamic memory, one only needs to obtain the information of the memory cell that needs to be operated, that is, the word line and bit line information where the memory cell is located, and then use this information according to this information.
  • the operating methods provided in the embodiment are used to perform corresponding operations; when it is necessary to perform read and write operations on the storage cells in the dynamic memory in a whole row, only the word line and bit line information of the storage unit in the row is needed, and then according to this information, the Perform corresponding operations using the operating methods provided in the embodiments.
  • the implementation method of reading and writing operations on entire columns and matrices will not be described in detail in this embodiment.
  • the dynamic memory will only work after receiving the operation command, and after receiving the operation command, it will immediately perform a read operation on the selected storage unit, and then send the current status data of the selected storage unit to the read
  • the buffer is temporarily stored, so that during subsequent write operations, the storage unit can be correctly written by reading the status data temporarily stored in the buffer.
  • the next operation is performed according to the operation instruction type in the operation instruction, as shown in step S20.
  • step S20 perform corresponding operations on the selected storage unit according to the operation instruction type information in the operation instruction. If the received operation instruction type is a read operation, output the temporarily stored data in the read buffer to the corresponding I/O port. Then step S30 is executed; if the received operation instruction type is a refresh operation, step S30 is executed; if the received operation instruction type is a write operation, step S40 is executed.
  • S30 Write status 1 to the selected storage unit, and then determine the data of the selected storage unit temporarily stored in the read buffer. If the temporarily stored data is status 1, the operation ends. If the temporarily stored data is status 1, the operation is ended. 0, then write state 0 to the selected storage unit.
  • steps S20 and S30 after each read operation, a refresh operation step is performed, because the refresh operation step is essentially to rewrite the data of the selected storage unit temporarily stored in the read buffer. , which facilitates correct writing of the storage unit by reading the temporarily stored status data in the buffer during subsequent write operations.
  • the operation information of the write operation includes write state 1 operation and write state 0 operation.
  • the write state 1 operation can be directly performed on the selected storage unit; when the write operation When the operation information is write state 0, you can first write state 1 to the selected memory unit, and then write state 0 to the selected memory unit.
  • the dynamic memory operation method provided by this embodiment is set to perform an interval refresh operation on the selected memory cell according to time T, and the interval time T is less than the voltage value of the capacitor in the memory cell during the write operation.
  • the time t required for the critical capacitance voltage value of the status data can effectively ensure that the read operation can always correctly read the status data of the storage unit; in addition, it is set to immediately read the status data of the storage unit when receiving the operation command. Select the storage unit for read operation and temporarily store the status data, and perform a refresh operation step after each read operation (rewrite the temporary data to the storage unit), which can effectively ensure that subsequent write operations are correctly written. Status data into the storage unit.
  • the read operation provided in this embodiment can be implemented by applying specific voltages to the word lines and bit lines connected to the selected memory cells.
  • the specific steps are as follows:
  • Step 1 Apply a bit line voltage V BLread to the bit line connected to the selected memory cell, and apply a word line voltage V Wlread to the word line connected to the selected memory cell, so that both ends of the memory cell to be read are Generate a read voltage of V read , which is used to keep the two-terminal strobe device in the selected memory cell in state 0 open, so that both ends of the selected memory cell in state 1
  • the gate device is turned on, changing it from state 1 to state 0, and generating a read current, that is, the read voltage V read must satisfy the following relationship: V read -V C1 > V TH , V read -V C0 ⁇ V TH , where , V C1 is the capacitor voltage when the memory cell is in state 1, and V C0 is the capacitor voltage when the memory cell is in state 0.
  • Step 2 Detect whether there is a read current on the bit line connected to the selected memory cell. If there is a read current, it is judged that the selected memory cell is in state 1 and a state 1 signal is output. Otherwise, it is judged that the selected memory cell is in state 0. And output status 0 signal. After the read operation, the selected memory cells are all in state 0, and then the next operation is performed according to the received operation instruction type, such as the above step S20.
  • Step 3 Send the output status signal to the read buffer for temporary data storage.
  • V IN1 and V IN0 are two voltage pulses with the same amplitude and opposite polarity, that is,
  • the principle is as follows: When an operating voltage pulse V IN1 with an amplitude between V TH and V TH + V Hold is applied to both ends of the memory cell, the initial resistance state of the strobe tube is a high resistance state, and the voltage on the capacitor is 0V, the applied voltage pulse V IN1 is completely applied to the strobe tube, and the amplitude is greater than V TH , causing the strobe tube to switch from a high resistance state to a low resistance state, charging the capacitor quickly. As the capacitor voltage rises, the selected The voltage at both ends of the pass tube drops. When the voltage at both ends of the strobe tube drops to less than V Hold , the strobe tube switches from a low resistance state to a high resistance state.
  • the capacitor voltage is maintained at V IN1 -V Hold , and the operating voltage V IN1 acts After that, the capacitor voltage V IN1 -V Hold is less than V TH , the strobe tube remains in a high-impedance state, the capacitor voltage remains at V IN1 -V Hold , and the writing of the logic state "1" is completed.
  • the writing principle of logic state 0 can refer to the writing principle of logic state "1" mentioned above. This embodiment will not go into details.
  • the operating voltage pulses V IN0 and V IN1 have the same amplitude and opposite polarity, and the capacitor voltage It is also the same as the capacitor voltage amplitude of logic state "0", but the polarity is opposite, which is -
  • the refresh operation interval T provided by the present invention should be less than the time t required for the capacitor voltage in the memory cell to drop from
  • V BL1 , V WL1 , V BL0 , and V WL0 need to meet the following requirements: relation:
  • V TH represents the conduction threshold voltage of the strobe device at both ends in the dynamic memory
  • V Hold represents the holding voltage of the strobe device at both ends in the dynamic memory
  • V BL1 represents the voltage applied to the selected memory cell when writing state 1
  • V WL1 represents the voltage applied on the word line connected to the selected memory cell when writing state 1
  • V BL0 represents the voltage applied on the bit line connected to the selected memory cell when writing state 0 voltage
  • V WL0 represents the voltage applied on the word line connected to the selected memory cell when writing state 0
  • V BLread represents the voltage applied on the bit line connected to the selected memory cell during read operation
  • V WLread represents the read operation The voltage applied on the word line connected to the selected memory cell; the capacitor voltage fluctuation range in the selected memory cell in state 1: -
  • the capacitor voltage of the selected memory cell is: V read –V TH
  • the capacitor voltage amplitude after completing the status writing is the capacitor voltage amplitude after completing the status writing. Because the capacitor has leakage, the capacitor voltage after completing the status writing will gradually decrease over time, so the maximum voltage across the capacitor is
  • -V Hold is less than V TH .
  • V IN1 -4.5V
  • V BL1 -2.5V
  • V WL1 2V
  • V IN0 4.5V
  • V BL0 2.5V
  • V WL0 -2V
  • V read 4.5V
  • V BLread 2.5V
  • V WLread -2V
  • the capacitor voltage in state 1 is: -1.5V ⁇ 0.5V; the capacitor voltage in state 0 is: 0.5V ⁇ 1.5V.
  • V read 4.5V is applied to the selected memory cell.
  • the bit line voltage is applied (see number 31 in Figure 4) is 2.5V
  • the word line voltage is -2V, so that the voltage at both ends of the strobe device in the memory unit is greater than 4V, and the strobe device is turned on.
  • a read current (see number 34 in Figure 4) is generated, and the capacitor voltage (see number 33 in Figure 4) will change from -1V to 1.5V, that is, it is in state 0.
  • the applied bit line voltage (see reference number 41 in Figure 5) is 2.5V
  • the word line voltage (see reference number 42 in Figure 5) is -2V, so that the selected
  • the strobe is closed and no read current will be generated (see number 44 in Figure 5).
  • the capacitor voltage (see number 43 in Figure 5) is maintained at 1.4V.
  • V IN1 -4.5V is applied to the memory cell, as shown in Figure 6.
  • the applied bit line voltage (see number 52 in Figure 6) is -2.5V, and the word line voltage ( (see number 51 in Figure 6) is 2V, because the current memory cell is in state 0 and the voltage at both ends of the strobe tube is greater than 4V, the strobe will open, and the capacitor voltage (see number 53 in Figure 6) in the memory unit becomes -1.5V, the writing of state 1 is completed.
  • the applied bit line voltage (see number 61 in Figure 7) is 2.5V
  • the word line voltage (see number 62 in Figure 7) is -2V
  • the strobe tube will open, the memory cell capacitor voltage (see number 63 in Figure 7) becomes 1.5V, the writing of state 0 is completed, and the operation ends.
  • the received operation command is a read operation
  • the data temporarily stored in the read buffer is output to the I/O port, and then a refresh operation is performed to complete the write-back of the storage unit data.
  • V IN1 -4.5V is applied to the memory cell, as shown in Figure 6.
  • the applied bit line voltage (see number 52 in Figure 6) is -2.5V, and the word line voltage ( (see number 51 in Figure 6) is 2V, because the current memory cell is in state 0, and the voltage at both ends of the strobe tube is greater than 4V, the strobe will open, and the memory unit capacitor voltage (see number 53 in Figure 6) becomes -1.5V , the writing of status 1 is completed.
  • V IN1 -4.5V to the memory cell
  • bit line voltage see number 52 in Figure 6
  • word line voltage see number 51 in Figure 6
  • the bit line voltage is 2V
  • the word line voltage see number 51 in Figure 6
  • the applied bit line voltage is 2.5V
  • the word line voltage see reference number 62 in Figure 7
  • V BLread 2.5V.
  • the voltage at both ends of the strobe is greater than 4V, the strobe is opened, and a read current is generated (see number 34 in Figure 4).
  • the capacitor voltage See number 33 in Figure 4) will become 1.5V, that is, it is in state 0.
  • the voltage at both ends of the strobe tube is less than 4V, the strobe tube is closed, and it will not A read current (see number 44 in Figure 5) is generated, and the capacitor voltage (see number 43 in Figure 5) remains stable.
  • a read current see number 44 in Figure 5
  • the capacitor voltage see number 43 in Figure 5
  • the interval time T is less than the time t required for the capacitor voltage in the storage unit to drop from the highest value to the lowest value due to leakage. That is, it is less than the time t required for the capacitor voltage in the storage unit to drop from the highest value to the lowest value during the write operation until the read operation is correct.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

一种动态存储器操作方法，包括如下步骤：按照预先设定的间隔时间T对动态存储器进行刷新操作，同时实时接收操作指令，当接收到操作指令时，根据操作指令中被选中存储单元的位置信息对被选中存储单元进行读操作，并将读操作中读取的状态数据暂存在读缓冲器中，其中，间隔时间T小于写操作时存储单元中电容的电压值下降到读操作正确读出该存储单元状态数据的临界电容电压值所需的时间t；然后再根据操作指令中操作指令类型信息对被选中存储单元进行相应操作，其中，在每次读操作后需进行一次刷新操作的执行步骤。该方法即使在被选中存储单元中电容发生漏电时，也能有效确保该存储单元进行读、写操作的正常操作。

Description

一种动态存储器操作方法 【技术领域】
本发明属于存储器技术领域，更具体地，涉及一种动态存储器操作方法。
【背景技术】
在冯诺依曼体系计算机结构中，DRAM(动态随机存储器)在外存与CPU之间起到衔接的作用，对计算机系统的稳定性起着非常重要的作用。DRAM采取1T1C结构，即由1个晶体管和1个存储单元串联组成，由于晶体管作为三端口器件，其外围控制电路需要造成较大的面积消耗，且三端口器件不宜实现三维堆叠，使得DRAM难以通过三维集成来实现高密度存储，这也是目前制约DRAM性能最关键的因素。
为了解决DRAM存储密度低的问题，目前存储器领域的学术界和产业界已经探索了很多种可能取代DRAM的新型存储器，其中中国发明专利CN202111280349.1提到的由OTS选通管和电容串联在一起构成存储单元(1S1C单元)，在读、写速度与功耗方面均可以和DRAM相媲美，是非常有希望取代DRAM的一种新型存储技术，但是目前尚未有研究针对其阵列的读写方案进行详细的阐述，且该种存储器为动态存储器，其电容中存储的电荷会因为漏电效应逐渐丢失，影响该存储单元的读写操作。
【发明内容】
针对现有技术的缺陷，本发明的目的在于提供一种动态存储器操作方法，即使在被选中存储单元中电容发生漏电时，也能有效确保该存储单元进行读写操作的正常操作。
为实现上述目的，本发明提供了一种动态存储器操作方法，所述动态存储器包括相互垂直排布的字线、位线及位于字线与位线之间阵列排布的存储单元，所述存储单元包括串联的电容和两端选通器件，该两端选通器 件具有双向导通特性以及具有导通阈值电压V TH和保持电压Vhold，所述方法包括如下步骤：
(1)按照预先设定的间隔时间T对动态存储器进行刷新操作，同时实时接收操作指令，当接收到操作指令时根据操作指令中被选中存储单元的位置信息对被选中存储单元进行读操作，并将读操作中读取的状态数据进行暂存；其中，间隔时间T小于写操作时存储单元中电容的电压值下降到读操作正确读取该存储单元状态数据的临界电容电压值所需的时间t；
(2)根据操作指令中操作指令类型信息对被选中存储单元进行相应操作，若接收到的操作指令类型为读操作时，则将暂存的数据输出至对应的I/O口，然后执行步骤(3)；若接收到的操作指令类型为刷新操作时，执行步骤(3)；若接收到的操作指令类型为写操作时，执行步骤(4)；
(3)对被选中存储单元进行写入状态1操作，然后判断暂存的被选中存储单元的数据，若暂存的数据是状态1，则结束操作，若暂存的数据是状态0，则再对被选中存储单元写入状态0操作；
(4)获取并根据所述写操作的操作信息，对应对所述被选中存储单元进行写入状态1或状态0操作。
本发明提供的动态存储器操作方法，设定按照间隔时间T对被选中存储单元进行刷新操作，且间隔时间T小于写操作时存储单元中电容的电压值下降到读操作正确读出该存储单元状态数据的临界电容电压值所需的时间t，即使在存储单元中电容发生漏电，也可有效确保读操作始终可以正确读出存储单元的状态数据；此外，设置接收到操作指令时立刻对被选中存储单元进行读操作并进行状态数据暂存，且每次读操作后都要执行一次刷新操作的执行步骤(将暂存的数据重新写入存储单元)，可有效确保后续写操作时正确写入存储单元的状态数据。
在其中一个实施例中，步骤(1)中，所述对被选中存储单元进行读操作，并将读操作中读取的状态数据进行暂存的步骤，具体为：
(a)在与被选中存储单元相连的位线上施加一位线电压V BLread，在与被选中存储单元相连的字线上施加一字线电压V Wlread，从而在待读取存储单元的两端产生大小为V read的读电压，该读电压V read用于使处于状态0的被选中存储单元中的两端选通器件继续保持断开，使处于状态1的被选中存储单元中的两端选通器件打开，使其从状态1变成状态0，并产生读电流；
(b)检测与被选中存储单元相连的位线上是否有读电流，若有读电流，则判断被选中存储单元处于状态1，并输出状态1信号，否则判断被选中存储单元处于状态0，并输出状态0信号；
(c)将输出的状态信号发送至读缓冲器进行数据暂存。
在其中一个实施例中，在步骤(a)中，所述读电压V read满足如下关系：V read-V C1＞V TH，V read-V C0＜V TH，式中，V C1为存储单元处于状态1时电容电压，V C0为存储单元处于状态0时电容电压。
在其中一个实施例中，对被选中存储单元进行写入状态1操作是通过在与被选中存储单元相连的字线上施加电压V WL1，在与被选中存储单元相连的位线上施加电压V BL1，从而在被选中存储单元的两端形成V IN1的压差来实现；对被选中存储单元进行写入状态0操作是通过在与被选中存储单元相连的字线上施加电压V WL0，在与被选中存储单元相连的位线上施加电压V BL0，从而在被选中存储单元的两端形成V IN0的压差来实现；
压差V IN1和压差V IN0满足如下关系：
V IN1＝V BL1–V WL1，V IN0＝V BL0–V WL0
|V IN1|＝|V IN0|
V TH＜|V IN1|＝|V IN0|＜V TH+V Hold
|V IN1|-V Hold+|V BL1|＜V TH
|V IN1|-V Hold+|V WL1|＜V TH
|V IN1|-V Hold+|V BL0|＜V TH
|V IN1|-V Hold+|V WL0|＜V TH
|V IN1|-V Hold+|V BLread|＜V TH
|V IN1|-V Hold+|V WLread|＜V TH。
在其中一个实施例中，所述间隔时间T小于存储单元中电容电压从||V IN|-V Hold|下降到V read–V TH所需的时间t，|V IN|＝|V IN1|＝|V IN0|。
在其中一个实施例中，步骤(4)具体为：
当所述写操作的操作信息为写入状态1时，直接对所述被选中存储单元进行写入状态1操作；当所述写操作的操作信息为写入状态0时，则先对所述被选中存储单元进行写入状态1操作，再对所述被选中存储单元进行写入状态0操作。
在其中一个实施例中，所述操作指令中被选中存储单元的位置信息包括按位、整行、整列或矩阵位置信息。
【附图说明】
图1是本发明一实施例提供的动态存储器操作方法的流程示意图
图2和图3对应是本发明一实施例提供的动态存储器按位操作方法和动态存储器整行操作方法的原理框图；
图4和图5对应是本发明一具体实施例提供的向处于状态1和状态0的被选中存储单元施加4.5V读电压图；
图6是本发明一具体实施例提供的向处于状态0的被选中存储单元施加-4.5V写1电压图；
图7是本发明一具体实施例提供的向处于状态1的被选中存储单元施加4.5V写0电压图；
图8是本发明一具体实施例提供的向处于状态0的被选中存储单元刷新操作的电压图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体 实施例仅仅用以解释本发明，并不用于限定本发明。
为确保因存储单元中电容漏电对该存储单元的读、写操作造成影响，本发明提供了一种动态存储器操作方法，适用的动态存储器为包括相互垂直排布的字线、位线及位于字线与位线之间阵列排布的存储单元，其中，存储单元包括串联的电容和两端选通器件，两端选通器件具有双向导通特性以及具有导通阈值电压V TH和保持电压Vhold。
图1是本发明一实施例提供的动态存储器操作方法的流程图，如图1所示，该方法包括步骤S10～S40，详述如下：
S10，按照预先设定的间隔时间T对动态存储器进行刷新操作，同时实时接收操作指令，当接收到操作指令时，根据操作指令中被选中存储单元的位置信息对被选中存储单元进行读操作，并将读取的状态数据进行暂存。具体地，可暂存在读缓冲器(读buffer)中。
在步骤S10中，间隔时间T小于写操作时存储单元中电容的电压值下降到读操作正确读取该存储单元状态数据的临界电容电压值所需的时间t。由于存储单元中电容会因漏电效应电压会逐渐下降，当电容的电压值下降至读操作时正确读出此时状态数据的临界电容电压值时，会导致后续读操作读写错误。比如当前存储单元的写入状态为1，此时该存储单元中的电容的电压值为V 1，如果此时该存储单元中的电容发生漏电，会使得该电容的电压从V 1快开始逐渐下降，而读操作正确读出状态1时电容的电压需在V 2～V 3(V 3大于V 2)之间，则需要在电容电压从V 1下降至V 2之前对该存储单元进行刷新操作，确保后续读操作读状态数据错误，同理可知存储单元写入状态0时的情况，本实施例不再赘述。
本实施例提供的操作指令包括被选中存储单元的位置信息和操作指令类型，操作指令类型包括读操作、写操作和刷新操作。被选中存储单元的位置信息包括按位、整行、整列或矩阵位置信息，即被选中存储单元所在的字线和位线位置信息，用于对应按位、整行、整列或矩阵对动态存储器 中的存储单元进行读和写操作。例如，当需进行按位对动态存储器中的存储单元进行读、写操作时，只需获取需要操作的存储单元的信息，即该存储单元所在字线和位线信息，然后根据该信息按照本实施例提供的操作方法进行相应操作；当需进行整行对动态存储器中的存储单元进行读、写操作时，只需该行存储单元所在的字线和位线信息，然后根据该信息按照本实施例提供的操作方法进行相应操作。同理，可知整列和矩阵进行读、写操作的实现方式，本实施例不再赘述。
在本实施例中，动态存储器只有在接收到操作指令之后才会工作，且接收到操作指令后，会立刻对被选中存储单元进行读操作，然后将被选中存储单元当前的状态数据发送至读buffer进行暂存，便于后续写操作时，通过读buffer暂存的状态数据对存储单元进行正确写入操作。数据暂存后，然后再根据操作指令中的操作指令类型进行下一步操作，如下步骤S20。
S20，根据操作指令中操作指令类型信息对被选中存储单元进行相应操作，若接收到的操作指令类型为读操作时，则将读缓冲器中暂存的数据输出至对应的I/O口，然后执行步骤S30；若接收到的操作指令类型为刷新操作时，则执行步骤S30；若接收到的操作指令类型为写操作时，则执行步骤S40。
S30，对被选中存储单元进行写入状态1操作，然后判断读缓冲器中暂存的被选中存储单元的数据，若暂存的数据是状态1，则结束操作，若暂存的数据是状态0，则再对被选中存储单元写入状态0操作。
在步骤S20和S30中，每次读操作后，都要执行一次刷新操作的执行步骤，由于刷新操作的执行步骤实质上是将读缓冲器中暂存的被选中存储单元的数据进行重新写入，便于后续写操作时，通过读buffer暂存的状态数据对存储单元进行正确写入操作。
S40，获取并根据写操作的操作信息，对应对被选中存储单元进行写入状态1或状态0操作。其中，写操作的操作信息包括写入状态1操作和写 入状态0操作，当写操作的操作信息为写入状态1时，可直接对被选中存储单元进行写入状态1操作；当写操作的操作信息为写入状态0时，可先对被选中存储单元进行写入状态1操作，再对被选中存储单元进行写入状态0操作。
本实施例提供的动态存储器操作方法，设定按照时间T对被选中存储单元进行间隔刷新操作，且间隔时间T小于写操作时存储单元中电容的电压值下降到读操作正确读出该存储单元状态数据的临界电容电压值所需的时间t，即使在存储单元中电容发生漏电，也可有效确保读操作始终可以正确读出存储单元的状态数据；此外，设置接收到操作指令时立刻对被选中存储单元进行读操作并进行状态数据暂存，且每次读操作后都要执行一次刷新操作的执行步骤(将暂存的数据重新写入存储单元)，可有效确保后续写操作时正确写入存储单元的状态数据。
在一个实施例中，本实施例提供的读操作的实现方式可通过在与被选中存储单元相连的字线和位线上分别施加特定电压来完成，具体步骤如下：
步骤1：在与被选中存储单元相连的位线施加一位线电压V BLread，在与被选中存储单元相连的字线上施加一字线电压V Wlread，从而在待读取存储单元的两端产生大小为V read的读电压，该读电压V read用于使处于状态0的被选中存储单元中的两端选通器件继续保持断开，使处于状态1的被选中存储单元中的两端选通器件打开，使其从状态1变成状态0，并产生读电流，即读电压V read需满足如下关系：V read-V C1＞V TH，V read-V C0＜V TH，式中，V C1为存储单元处于状态1时电容电压，V C0为存储单元处于状态0时电容电压。
步骤2：检测与被选中存储单元相连的位线上是否有读电流，若有读电流，则判断被选中存储单元处于状态1，并输出状态1信号，否则判断被选中存储单元处于状态0，并输出状态0信号。经过读操作之后，被选中存储单元均处于状态0，然后再根据接收到的操作指令类型再进行下一步操作，如上述步骤S20。
步骤3：将输出的状态信号发送至读缓冲器进行数据暂存。
在一个实施例中，对被选中存储单元进行写入状态1操作可通过在与被选中存储单元相连的字线上施加电压V WL1，在与被选中存储单元相连的位线上施加电压V BL1，从而在被选中存储单元的两端形成V IN1＝V BL1–V WL1的压差来实现；对被选中存储单元进行写入状态0操作可通过在与被选中存储单元相连的字线上施加电压V WL0，在与被选中存储单元相连的位线上施加电压V BL0，从而在被选中存储单元的两端形成V IN0＝V BL0–V WL0的压差来实现。
其中，V IN1和V IN0为幅值相同、极性相反的两个电压脉冲，即|V IN1|＝|V IN0|，为了能正常写入数据，需要满足这样的关系：V TH＜|V IN1|＝|V IN0|＜V TH+V Hold。其原理如下：在存储单元两端施加了一个幅值在V TH与V TH+V Hold之间的操作电压脉冲V IN1时，选通管的初始阻态为高阻态，电容上的电压为0V，施加的电压脉冲V IN1完全加在选通管上，且幅值大于V TH，使得选通管打开由高阻态切换到低阻态，对电容快速充电，随着电容电压上升，选通管两端的电压下降，当选通管两端电压下降到小于V Hold时，选通管由低阻态切换到高阻态，此时电容电压维持在V IN1-V Hold，操作电压V IN1作用之后，电容电压V IN1-V Hold小于V TH，选通管维持在高阻态，电容电压维持在V IN1-V Hold，完成了逻辑状态“1”的写入。逻辑状态0的写入原理可参考上述逻辑状态“1”的写入原理，本实施例不再详细赘述，两者区别为操作电压脉冲V IN0与V IN1幅值相同，极性相反，电容电压也与逻辑状态“0”的电容电压幅值相同，极性相反，为-||V IN0|-V Hold|。
根据本实施例提供的存储单元写入状态1和写入状态0的原理可知，无论是写入状态1还是写入状态0，此时该存储单元中电容两端的电压值均为||V IN|-V Hold|，|V IN|＝|V IN1|＝|V IN0|。因此，在此种写操作的方式下，本发明提供的刷新操作的间隔时间T应小于存储单元中电容电压从||V IN|-V Hold|下降到V read–V TH所需的时间t。
与此同时，为确保对被选中存储单元进行读、写操作时，在字线和位线上施加的电压不会对半选中单元(与被选中存储单元共用同一字线或者位线的存储单元)和未选中存储单元(与被选中存储单元既不共用一条字线也不共用一条位线的存储单元)的存储状态造成影响，需要求V BL1、V WL1、V BL0、V WL0需要满足如下关系：
|V IN1|-V Hold+|V BL1|＜V TH
|V IN1|-V Hold+|V WL1|＜V TH
|V IN1|-V Hold+|V BL0|＜V TH
|V IN1|-V Hold+|V WL0|＜V TH
|V IN1|-V Hold+|V BLread|＜V TH
|V IN1|-V Hold+|V WLread|＜V TH
其中，V TH表示动态存储器中两端选通管器件的导通阈值电压；V Hold表示动态存储器中两端选通管器件的保持电压；V BL1表示写入状态1时施加在被选中存储单元相连的位线上施加的电压；V WL1表示写入状态1时在被选中存储单元相连的字线上施加的电压；V BL0表示写入状态0时在被选中存储单元相连的位线上施加的电压；V WL0表示写入状态0时在被选中存储单元相连的字线上施加的电压；V BLread表示读操作时在被选中存储单元相连的位线上施加的电压；V WLread表示读操作时在被选中存储单元相连的字线上施加的电压；处于状态1的被选中存储单元中的电容电压波动范围：-||V IN1|-V Hold|～V read–V TH；处于状态0的被选中存储单元中的电容电压的电容电压为：V read–V TH～||V IN1|-V Hold|。
|V IN1|-V Hold为完成状态写入之后的电容电压幅值，因为电容存在漏电，完成状态写入之后的电容电压会随着时间推移逐渐降低，所以电容两端最大电压为|V IN1|-V Hold，因此只需要保证对存储单元进行读、写操作时，电容电压为|V IN1|-V Hold的半选单元不受影响，即半选单元对应的选通管两端电压始终小于阈值电压V TH，即V BL1、V WL1、V BL0、V WL0、V BLread、V WLread加上 |V IN1|-V Hold小于V TH。
为更清楚地说明本发明，以下结合具体实施例对本发明进行说明：
一种1S1C存储器，其中选用的选通管阈值电压Vth为4V，保持电压Vhold为3V。
V IN1＝-4.5V，V BL1＝﹣2.5V，V WL1＝2V
V IN0＝4.5V，V BL0＝2.5V，V WL0＝﹣2V
V read＝4.5V，V BLread＝2.5V，V WLread＝﹣2V
状态1的电容电压为：﹣1.5V～0.5V；状态0的电容电压为：0.5V～1.5V。
如图2所示，对于一种动态存储器按位操作方法：
当接收到操作指令时，立刻对被选中存储单元进行读操作，即对被选中存储单元施加V read＝4.5V，对于处于状态1的被选中存储单元，如图4所示，施加位线电压(见图4中标号31)为2.5V，字线电压(见图4中标号32)为﹣2V，使得该存储单元中的选通管器件的两端电压大于4V，选通管器件打开，产生读电流(见图4中标号34)，电容电压(见图4中标号33)会由﹣1V变为1.5V，即处于状态0。而对于处于状态0的被选中存储单元，如图5所示，施加位线电压(见图5中标号41)为2.5V，字线电压(见图5中标号42)为﹣2V，使得选通管器件两端电压小于4V，选通管关闭，不会产生读电流(见图5中标号44)，电容电压(见图5中标号43)维持在1.4V，通过监测在位线中是否有读电流产生即可判断被选中存储单元的状态，读取后得到的数据会被暂存到读buffer中，经过读取操作之后，存储单元处于状态0。
若接收到的操作指令类型为刷新操作，则对存储单元施加V IN1＝﹣4.5V，如图6所示，施加位线电压(见图6中标号52)为﹣2.5V，字线电压(见图6中标号51)为2V，因为当前存储单元处于状态0，选通管两端电压大于4V，选通管会打开，该存储单元中的电容电压(见图6中标号53)变为﹣1.5V，完成了状态1的写入，此时再判断读buffer中的数据状态，若为 状态1，则操作结束，若为状态0，再对存储单元施加V IN0＝4.5V，如图7所示，施加位线电压(见图7中标号61)为2.5V，字线电压(见图7中标号62)为﹣2V，因为当前存储单元处于状态1，选通管两端电压大于4V，选通管会打开，存储单元电容电压(见图7中标号63)变为1.5V，完成了状态0的写入，操作结束。
若接收到的操作指令为读操作，则将暂存在读buffer中的数据输出至I/O口，然后再执行刷新操作，完成对存储单元数据的回写。
若接收到的操作指令为写1操作，则对存储单元施加V IN1＝﹣4.5V，如图6所示，施加位线电压(见图6中标号52)为﹣2.5V，字线电压(见图6中标号51)为2V，因为当前存储单元处于状态0，选通管两端电压大于4V，选通管会打开，存储单元电容电压(见图6中标号53)变为﹣1.5V，完成了状态1的写入。
若接收到的操作指令为写0操作，则先对存储单元施加V IN1＝﹣4.5V，如图6所示，施加位线电压(见图6中标号52)为﹣2.5V，字线电压(见图6中标号51)为2V，因为当前存储单元处于状态0，选通管两端电压大于4V，选通管会打开，存储单元电容电压53变为﹣1.5V，完成了状态1的写入，再对存储单元施加V IN0＝4.5V，如图7所示，施加位线电压(见图7中标号61)为2.5V，字线电压(见图7中标号62)为﹣2V，因为当前存储单元处于状态1，选通管两端电压大于4V，选通管会打开，存储单元电容电压(见图7中标号63)变为1.5V，完成了状态0的写入，操作结束。
如图3所示，一种动态存储器整行操作方法：
当接收到操作指令时，对整行存储单元施加V read＝4.5V，即在整行存储单元共用的字线上施加电压V WLread＝﹣2V，和在与每个存储单元相连的位线上施加电压V BLread＝2.5V，对于处于状态1的存储单元，如图4所示，选通管两端电压大于4V，选通管打开，产生读电流(见图4中标号34)，电容电压(见图4中标号33)会变为1.5V，即处于状态0，而对于处于状态0 的存储单元，如图5所示，选通管两端电压小于4V，选通管关闭，不会产生读电流(见图5中标号44)，电容电压(见图5中标号43)维持稳定，通过监测位线中是否有读电流产生即可判断对应的存储单元的状态，读取后得到的数据会被暂存到整行读buffer中，经过读取操作之后，整行存储单元均处于状态0。
若接收到的操作指令为刷新操作，则对整行存储单元施加V IN1＝﹣4.5V，如图6所示，即在整行存储单元共用的字线上施加电压V WL1＝2V，和在与每个存储单元相连的位线上施加电压V BL1＝﹣2.5V，因为当前整行存储单元均处于状态0，所以选通管两端电压大于4V，选通管会打开，使整行存储单元均处于状态1，再判断行读buffer中每位暂存的数据是状态1还是状态0，若是状态1，则可以结束操作，若是状态0，则再对相应的存储单元施加V IN0＝4.5V，如图7所示，即在整行存储单元共用的字线上施加电压V WL0＝﹣2V，在需要进行写0操作的存储单元相连的位线上施加电压V BL0＝2.5V，对应的存储单元的选通管两端电压大于4V，选通管会打开，完成状态0的写入。
若接收到的操作指令为写操作，则对整行存储单元施加V IN1＝﹣4.5V，如图6所示，即在整行存储单元共用的字线上施加电压V WL1＝2V，和在与每个存储单元相连的位线上施加电压V BL1＝﹣2.5V，因为当前整行存储单元均处于状态0，所以选通管两端电压大于4V，选通管会打开，使整行存储单元均处于状态1，再根据操作指令判断哪些存储单元需要写入状态0，再对相应的存储单元施加V IN0＝4.5V，如图7所示，即在整行存储单元共用的字线上施加电压V WL0＝﹣2V，在需要进行写0操作的存储单元相连的位线上施加电压V BL0＝2.5V，对应的存储单元的选通管两端电压大于4V，选通管会打开，完成状态0的写入。
如图8所示，对存储单元进行写入逻辑状态“0”操作，施加写入脉冲V IN0＝4.5V，可以看见写入完成后电容电压维持在1.5V附近，此后因为电容 存在漏电现象，电容电压随着时间推移由1.5V开始逐渐下降，到时间t时下降到0.5V，而逻辑状态“0”对应的电容电压为：0.5V～1.5V，如果继续下降，该存储单元存储的逻辑状态将从“0”变为“1”，即存储数据发生错误，因此需要在电容电压下降到0.5V之前对存储单元进行刷新操作重新写入数据，因此需要每隔间隔时间T对存储单元存储的数据进行刷新操作，间隔时间T小于存储单元中电容因漏电导致电容电压从最高值下降为最低值所需的时间t，即小于写操作时存储单元中电容的电压值下降到读操作正确读出该存储单元状态数据的临界电容电压值所需的时间t。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 一种动态存储器操作方法，其特征在于，所述动态存储器包括相互垂直排布的字线、位线及位于字线与位线之间阵列排布的存储单元，所述存储单元包括串联的电容和两端选通器件，该两端选通器件具有双向导通特性以及具有导通阈值电压V TH和保持电压V hold，所述方法包括如下步骤：
    (1)按照预先设定的间隔时间T对动态存储器进行刷新操作，同时实时接收操作指令，当接收到操作指令时根据操作指令中被选中存储单元的位置信息对被选中存储单元进行读操作，并将读操作中读取的状态数据进行暂存；其中，间隔时间T小于写操作时存储单元中电容的电压值下降到读操作正确读取该存储单元状态数据的临界电容电压值所需的时间t；
    (2)根据操作指令中操作指令类型信息对被选中存储单元进行相应操作，若接收到的操作指令类型为读操作时，则将暂存的数据输出至对应的I/O口，然后执行步骤(3)；若接收到的操作指令类型为刷新操作时，执行步骤(3)；若接收到的操作指令类型为写操作时，执行步骤(4)；
    (3)对被选中存储单元进行写入状态1操作，然后判断暂存的被选中存储单元的数据，若暂存的数据是状态1，则结束操作，若暂存的数据是状态0，则再对被选中存储单元写入状态0操作；
    (4)获取并根据所述写操作的操作信息，对应对所述被选中存储单元进行写入状态1或状态0操作。
  2. 根据权利要求1所述的动态存储器操作方法，其特征在于，步骤(1)中，所述对被选中存储单元进行读操作，并将读操作中读取的状态数据进行暂存的步骤，具体为：
    (a)在与被选中存储单元相连的位线上施加一位线电压V BLread，在与被选中存储单元相连的字线上施加一字线电压V Wlread，从而在待读取存储单元的两端产生大小为V read的读电压，该读电压V read用于使处于状态0的被 选中存储单元中的两端选通器件继续保持断开，使处于状态1的被选中存储单元中的两端选通器件打开，使其从状态1变成状态0，并产生读电流；
    (b)检测与被选中存储单元相连的位线上是否有读电流，若有读电流，则判断被选中存储单元处于状态1，并输出状态1信号，否则判断被选中存储单元处于状态0，并输出状态0信号；
    (c)将输出的状态信号发送至读缓冲器进行数据暂存。
  3. 根据权利要求2所述的动态存储器操作方法，其特征在于，在步骤(a)中，所述读电压V read满足如下关系：V read-V C1＞V TH，V read-V C0＜V TH，式中，V C1为存储单元处于状态1时电容电压，V C0为存储单元处于状态0时电容电压。
  4. 根据权利要求1所述的动态存储器操作方法，其特征在于，对被选中存储单元进行写入状态1操作是通过在与被选中存储单元相连的字线上施加电压V WL1，在与被选中存储单元相连的位线上施加电压V BL1，从而在被选中存储单元的两端形成V IN1的压差来实现；对被选中存储单元进行写入状态0操作是通过在与被选中存储单元相连的字线上施加电压V WL0，在与被选中存储单元相连的位线上施加电压V BL0，从而在被选中存储单元的两端形成V IN0的压差来实现；
    压差V IN1和压差V IN0满足如下关系：
    V IN1＝V BL1–V WL1，V IN0＝V BL0–V WL0
    |V IN1|＝|V IN0|
    V TH＜|V IN1|＝|V IN0|＜V TH+V Hold
    |V IN1|-V Hold+|V BL1|＜V TH
    |V IN1|-V Hold+|V WL1|＜V TH
    |V IN1|-V Hold+|V BL0|＜V TH
    |V IN1|-V Hold+|V WL0|＜V TH
    |V IN1|-V Hold+|V BLread|＜V TH
    |V IN1|-V Hold+|V WLread|＜V TH。
  5. 根据权利要求4所述的动态存储器操作方法，其特征在于，所述间隔时间T小于存储单元中电容电压从||V IN|-V Hold|下降到V read–V TH所需的时间t，|V IN|＝|V IN1|＝|V IN0|。
  6. 根据权利要求1所述的动态存储器操作方法，其特征在于，步骤(4)具体为：
    当所述写操作的操作信息为写入状态1时，直接对所述被选中存储单元进行写入状态1操作；当所述写操作的操作信息为写入状态0时，则先对所述被选中存储单元进行写入状态1操作，再对所述被选中存储单元进行写入状态0操作。
  7. 根据权利要求1所述的动态存储器操作方法，其特征在于，所述操作指令中被选中存储单元的位置信息包括按位、整行、整列或矩阵位置信息。
PCT/CN2022/112132 2022-07-29 2022-08-12 一种动态存储器操作方法 WO2024021177A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/021,177 US12057158B1 (en) 2022-07-29 2022-08-12 Method for operating dynamic memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210909473.8 2022-07-29
CN202210909473.8A CN115240728A (zh) 2022-07-29 2022-07-29 一种动态存储器操作方法

Publications (1)

Publication Number Publication Date
WO2024021177A1 true WO2024021177A1 (zh) 2024-02-01

Family

ID=83677327

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/112132 WO2024021177A1 (zh) 2022-07-29 2022-08-12 一种动态存储器操作方法

Country Status (3)

Country Link
US (1) US12057158B1 (zh)
CN (1) CN115240728A (zh)
WO (1) WO2024021177A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170053698A1 (en) * 2015-06-17 2017-02-23 Intel Corporation Provision of holding current in non-volatile random access memory
CN109542839A (zh) * 2019-01-18 2019-03-29 清华大学 融合非易失多值存储与逻辑运算功能的动态可控器件单元
CN113990368A (zh) * 2021-10-29 2022-01-28 华中科技大学 一种基于ots的动态存储结构及其操作方法
CN114360596A (zh) * 2021-12-30 2022-04-15 浙江大学 一种非易失性的动态存储器单元
CN114709211A (zh) * 2022-04-02 2022-07-05 北京超弦存储器研究院 动态存储器及其制作、读写方法、电子设备、存储电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW514920B (en) * 2001-07-20 2002-12-21 United Microelectronics Corp Selective memory refreshing circuit and refreshing method
US9891974B2 (en) * 2014-09-10 2018-02-13 Toshiba Memory Corporation Memory system
KR20200138305A (ko) * 2018-03-29 2020-12-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 기억 장치 및 전자 기기

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170053698A1 (en) * 2015-06-17 2017-02-23 Intel Corporation Provision of holding current in non-volatile random access memory
CN109542839A (zh) * 2019-01-18 2019-03-29 清华大学 融合非易失多值存储与逻辑运算功能的动态可控器件单元
CN113990368A (zh) * 2021-10-29 2022-01-28 华中科技大学 一种基于ots的动态存储结构及其操作方法
CN114360596A (zh) * 2021-12-30 2022-04-15 浙江大学 一种非易失性的动态存储器单元
CN114709211A (zh) * 2022-04-02 2022-07-05 北京超弦存储器研究院 动态存储器及其制作、读写方法、电子设备、存储电路

Also Published As

Publication number Publication date
US12057158B1 (en) 2024-08-06
CN115240728A (zh) 2022-10-25
US20240265962A1 (en) 2024-08-08

Similar Documents

Publication Publication Date Title
JP6886501B2 (ja) メモリを動作させる方法
US5297077A (en) Memory having ferroelectric capacitors polarized in nonvolatile mode
US7391643B2 (en) Semiconductor memory device and writing method thereof
US6388915B1 (en) Method for driving semiconductor memory
US7583546B2 (en) Apparatus and method of operating an integrated circuit
EP3142121B1 (en) Static random access memory (sram) with programmable resistive elements
US11790971B2 (en) Ferroelectric random access memory device and method for operating read and write thereof
WO2024021176A1 (zh) 一种1s1c存储器数据读取方法及系统
US6108233A (en) Ultra low voltage static RAM memory cell
WO2024021177A1 (zh) 一种动态存储器操作方法
CN105632546A (zh) 一种mram芯片及其自刷新操作方法
CN110993001B (zh) 一种stt-mram的双端自检写电路及数据写入方法
JP2003007051A (ja) メモリおよびその動作方法
WO2021039215A1 (ja) メモリチップ及びメモリチップの制御方法
US6992913B2 (en) Ferroelectric storage device
CN110600065B (zh) 具有对称特性的存储器单元及其构成的阵列电路
US20190378554A1 (en) High-Speed Data Transfer Periods for Thyristor Memory Cell Arrays
CN115954028A (zh) 一种存储器的操作方法
WO2023169075A1 (zh) 读写电路、读写方法以及铁电存储器
WO2024198549A1 (zh) 存储器和存储器的控制方法、存储系统、电子设备
WO2022127930A1 (zh) 一种存储单元、存储阵列以及数据存储方法
TWI709962B (zh) 具高存取速度之７ｔ雙埠靜態隨機存取記憶體
US20240079074A1 (en) Memory device included in memory system and method for detecting fail memory cell thereof
CN108665926B (zh) 一种交叉开关结构的阻变存储器写干扰优化方法
TW202341142A (zh) 記憶體裝置、其寫入電路及記憶體寫入方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22952620

Country of ref document: EP

Kind code of ref document: A1