WO2024020869A1 - 显示面板、显示装置及可穿戴设备 - Google Patents

显示面板、显示装置及可穿戴设备 Download PDF

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Publication number
WO2024020869A1
WO2024020869A1 PCT/CN2022/108292 CN2022108292W WO2024020869A1 WO 2024020869 A1 WO2024020869 A1 WO 2024020869A1 CN 2022108292 W CN2022108292 W CN 2022108292W WO 2024020869 A1 WO2024020869 A1 WO 2024020869A1
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WIPO (PCT)
Prior art keywords
test unit
area
unit group
display
display panel
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Application number
PCT/CN2022/108292
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English (en)
French (fr)
Inventor
浦超
杨盛际
陈小川
黄冠达
卢鹏程
杨俊彦
李大超
施蓉蓉
魏俊波
白枭
杨波
吴斌
朱胜迪
丁雁强
郭致成
朱云
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/108292 priority Critical patent/WO2024020869A1/zh
Priority to CN202280002430.XA priority patent/CN117980817A/zh
Publication of WO2024020869A1 publication Critical patent/WO2024020869A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a display device and a wearable device.
  • silicon-based OLED Organic Light Emitting Diode
  • advantages such as high resolution, low power consumption, small size, and light weight. It has good application prospects in high-resolution near-eye display industries such as wearable devices, industrial security, and medical care.
  • embodiments of the present application provide a display panel, including a display area and a peripheral area surrounding the display area, where the peripheral area includes a binding sub-area located on one side of the display area;
  • the area in the peripheral area except the binding sub-area includes a first test unit group and a second test unit group, and the first test unit group and the second test unit group respectively include at least one circuit test Unit;
  • the display area includes a first side and a second side extending along a first direction and arranged oppositely; the first direction is the direction in which the binding sub-area points to the display area;
  • the maximum distance from the first test unit group perpendicular to the first direction to the first side is equal to the maximum distance from the second test unit group perpendicular to the first direction to the second side. the maximum distance.
  • the minimum distance from the first test unit group perpendicular to the first direction to the first side is equal to the minimum distance of the second test unit group perpendicular to the first direction. The minimum distance to the second side.
  • the area in the peripheral area except the binding sub-area includes a light-shielding layer; the inner contour of the orthographic projection of the light-shielding layer on the substrate of the display panel is consistent with the The edge contact of the display area;
  • the first test unit group and the second test unit group are both located on a side of the light shielding layer away from the display area, and the first test unit group and the second test unit group are on the lining.
  • the orthographic projection on the bottom does not overlap with the orthographic projection of the light shielding layer on the substrate.
  • the peripheral area includes a first peripheral sub-area, and the first peripheral sub-area is located on a side of the display area away from the binding sub-area;
  • circuit test units in the first test unit group are located in the first peripheral sub-area, and another part of the circuit test units in the first test unit group are located in the peripheral area close to the first side area;
  • circuit test units in the second test unit group are located in the first peripheral sub-area, and another part of the circuit test units in the second test unit group are located in the peripheral area close to the second Side area.
  • connection line between the geometric center of each circuit test unit in the first test unit group and the connection line between the geometric center of each circuit test unit in the second test unit group Two intersecting line segments are formed respectively;
  • the line connecting the geometric centers of each circuit test unit in the first test unit group and the line connecting the geometric centers of each circuit test unit in the second test unit group are arcs respectively.
  • the geometric center of each circuit test unit in the first test unit group is located in the same line segment, and the geometric center of each circuit test unit in the second test unit group is located in the same line segment. within the line segment.
  • each of the circuit test units in the first test unit group is located in an area of the peripheral area close to the first side, and each of the circuit test units in the second test unit group The circuit test units are all located in the peripheral area close to the second side.
  • the first test unit group and the second test unit group respectively include a first end close to the binding sub-region and a second end far away from the binding sub-region;
  • the minimum distance from the first end perpendicular to the first direction to the display area is greater than or equal to the minimum distance from the second end perpendicular to the first direction to the display area. distance.
  • each circuit test unit in the first test unit group and the second test unit group is located in the first peripheral sub-area, and the circuit test units in the same group are arranged perpendicular to the first direction;
  • the first test unit group and the second test unit group are arranged along the first direction;
  • the first test unit group and the second test unit group are arranged perpendicular to the first direction.
  • each of the circuit test units is arranged in mirror symmetry.
  • the minimum distance from the circuit test unit in the first test unit group and the second test unit group to the light shielding layer is The distance is less than the minimum distance from the binding terminal in the binding sub-region to the light-shielding layer.
  • the display panel includes at least one third test unit group, the third test unit group includes a plurality of transistor test units, and the third test unit group is located in the first peripheral sub-unit. district;
  • the distance between the transistor testing unit and the light-shielding layer is greater than or equal to the distance between the circuit testing unit and the light-shielding layer.
  • the third test unit group is located on a side of all the circuit test units away from the display area, and there is a gap between the third test unit group and the light shielding layer, so The first test unit group and the second test unit group are both located in the gap.
  • the display panel includes two third test unit groups, the two third test unit groups are arranged perpendicular to the first direction, and the first peripheral sub-group
  • the area includes a coding pattern, and the coding pattern is located between two third test unit groups; the minimum distance between the coding pattern and the light-shielding layer is greater than or equal to the distance between the transistor test unit and the light-shielding layer. the minimum distance between them.
  • the peripheral area further includes a second peripheral sub-area, the second peripheral sub-area is located between the binding sub-area and the display area, and the light-shielding layer is located between the binding sub-area and the display area.
  • the orthographic projection on the substrate falls within the area in the peripheral area except the binding sub-area;
  • the distance between the outer contour of the light-shielding layer located in the first peripheral sub-region and the edge of the display area along the first direction is smaller than the outer contour of the light-shielding layer located in the second peripheral sub-area. The distance between a portion of the sub-area along the first direction and an edge of the display area.
  • the shape of the orthographic projection of the light-shielding layer on the substrate includes a rectangle with four rounded corners;
  • the curvature radius of the two rounded corners of the rectangle close to the binding sub-area is greater than the curvature radius of the two rounded corners of the rectangle close to the first peripheral sub-area.
  • the display panel includes a cover plate, the cover plate covers a partial area of the light shielding layer and the display area, and the orthographic projection of the cover plate on the substrate The outer contour falls within the orthographic projection of the light-shielding layer on the substrate;
  • the four vertex corners of the outer contour of the orthographic projection of the cover plate on the substrate are respectively located at the four rounded corners.
  • the area of the portion of the light-shielding layer located in the first peripheral sub-region that does not overlap with the cover plate is smaller than the area of the portion of the light-shielding layer located in the second peripheral sub-region. The area of the area that does not overlap the cover.
  • the number of circuit test units is greater than the number of binding terminals.
  • the size of the area where the cover plate overlaps with the light shielding layer in the direction from the display area to the peripheral area is greater than The size of the circuit test unit along the first direction.
  • the area of the orthographic projection pattern of the circuit test unit on the substrate is less than or equal to the area of the orthographic projection pattern of the binding terminal on the substrate.
  • the display panel further includes a detection unit, the detection unit includes a plurality of auxiliary sub-pixels, the auxiliary sub-pixels are located in an area of the peripheral area close to the first side, and /Or, the auxiliary sub-pixel is located in an area of the peripheral area close to the second side;
  • the structure of the auxiliary sub-pixel is the same as that of the sub-pixel in the display area; the light-shielding layer covers the detection unit.
  • the display panel further includes four marking patterns, the marking patterns are located on a side of the light-shielding layer away from the substrate, and the top corner of the cover plate is on the side of the substrate.
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the marking pattern on the substrate.
  • embodiments of the present application provide a display device, including the display panel as described in the first aspect,
  • the display device also includes a flexible circuit board and a driver chip
  • the display panel includes a display control unit, and the display device further includes a flexible circuit board.
  • embodiments of the present application provide a wearable device, including two display devices as described in the second aspect, and further including two annular first brackets, and the display devices are fixed on the first brackets.
  • the first bracket covers the area in the peripheral area of the display panel that is not provided with a light-shielding layer; wherein, each circuit test unit in one of the display devices is in a state with each circuit test unit in the other display device.
  • an orthographic projection of the first bracket on the substrate of the display panel overlaps with an orthographic projection of the light-shielding layer on the substrate.
  • the inner contour of the orthographic projection of the first bracket on the substrate is at least partially connected with the outer contour of the orthographic projection of the cover plate on the substrate.
  • the second bracket is configured to be wearable, the second bracket includes a main body part and two temples, the main part of the second bracket is fixed with a driving plate and two said A first bracket, the drive board is electrically connected to the flexible circuit boards of the two display devices respectively;
  • the two display panels are arranged in mirror symmetry, and the geometric center of the display area of the two display panels and the geometric center of the main part of the second bracket are located in the same straight line, and the two flexible circuit boards are arranged in such a way that The geometric center of the second bracket is the symmetry point and is arranged centrally symmetrically.
  • Figures 1-7 are schematic structural diagrams of seven display panels provided by embodiments of the present application.
  • FIGS 8-11 are schematic structural diagrams of four types of wearable devices provided by embodiments of the present application.
  • Figure 12 is a schematic structural diagram of a first bracket in a wearable device provided by an embodiment of the present application.
  • Figure 13 is a schematic structural diagram of the main body part of a second bracket in the wearable device provided by an embodiment of the present application;
  • FIGS 14 and 15 are schematic structural diagrams of two wearable devices provided by embodiments of the present application.
  • FIG. 16 is an intermediate structural schematic diagram of a wearable device in related technology provided by an embodiment of the present application.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • the polygons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, fillets, arc edges and deformations. wait.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • CMOS Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor
  • Silicon-based OLED display products are widely used in near-eye displays and virtual reality (Virtual Reality, referred to as VR) or augmented reality (Augmented Reality, referred to as AR), especially in AR/VR head-mounted display devices.
  • VR Virtual Reality
  • AR Augmented Reality
  • silicon-based OLED display products used in AR/VR devices need to have high PPI (Pixels Per Inch, pixel density unit), which places high requirements on the pixel arrangement and pixel area design of silicon-based OLED display products. .
  • PPI Process Per Inch, pixel density unit
  • the designs in related technologies can no longer meet the needs.
  • embodiments of the present application provide a newly designed display panel to expand the use scenarios of silicon-based display products and enable them to have more in-depth capabilities in high-resolution near-eye display industries such as wearable devices, industrial security, and medical care.
  • the application can also improve the display effect and user experience.
  • Embodiments of the present application provide a display panel, as shown in Figures 1 to 7, including a display area AA and a peripheral area surrounding the display area.
  • the peripheral area includes binding sub-areas B-D located on one side of the display area;
  • the area in the peripheral area except the binding sub-areas B-D includes the first test unit group T1 and the second test unit group T2.
  • the first test unit group T1 and the second test unit group T2 each include at least one circuit test unit CP pad.
  • the display area AA includes a first side L1 and a second side L2 extending and oppositely arranged along a first direction, such as the OA1 direction; the first direction, such as the OA1 direction, is the binding sub-area B-D pointing to the display area AA direction;
  • the maximum distance d3 of the first test unit group T1 perpendicular to the first direction to the first side L1 is equal to the maximum distance d3 of the second test unit group T2 perpendicular to the first direction to the second side L2.
  • the specific type of the above display panel is not limited here. The details can be determined according to the actual situation.
  • the above display panel may be an OLED (Organic Light Emitting Diode, organic light emitting diode) display panel.
  • the OLED display panel includes an OLED display panel with a silicon substrate (Si Substrate) and an OLED display panel with a glass substrate.
  • the above display panel may be Micro-OLED (Micro-Organic Light Emitting Diode, micro-organic light-emitting diode).
  • the above display panel may be Mini-OLED (Mini-Organic Light Emitting Diode, sub-millimeter organic light-emitting diode).
  • Micro-OLED display panels and Mini-OLED display panels also include glass substrates and silicon substrates respectively.
  • the silicon substrate can be a P-type single crystal silicon substrate, or it can also be an N-type single crystal silicon substrate, and the details can be determined according to the actual product. It should be noted that the embodiments of the present application are explained by taking the display panel in which the above-mentioned display panel is a silicon substrate as an example.
  • the planar shape of the display area AA is not limited here.
  • the plan shape of the display area AA may be a rectangle as shown in FIGS. 1 to 7; or, the plan shape of the display area AA may also be other polygons, such as pentagons, hexagons, etc., specifically Determine based on usage scenarios and usage requirements.
  • the plane pattern of the peripheral area may be annular.
  • the plane pattern of the peripheral area is different depending on the plane pattern of the display area AA.
  • the plane pattern of the peripheral area is determined according to the plane pattern of the display area AA.
  • planar graphics refer to orthographic projection graphics on the substrate of the display panel.
  • the above-mentioned bonding sub-areas B-D refer to areas in the peripheral area used for bonding with the driver chip (IC) and the flexible circuit board (FPC).
  • the relevant circuits and modules in the driver chip IC are integrated into the driver substrate of the display panel. At this time, the driver chip does not need to be installed in the display panel.
  • the stator areas B-D refer to areas in the peripheral area used for bonding with the flexible circuit board (FPC).
  • the above-mentioned binding sub-regions B-D refer to the peripheral areas respectively used for connecting the driver chip (IC) and the flexible circuit board (FPC).
  • the above-mentioned first test unit group T1 and the second test unit group T2 respectively include at least one circuit test unit CP pad.
  • the above-mentioned first test unit group T1 and the second test unit group T2 respectively include multiple circuits.
  • the test unit CP pad is used as an example for explanation.
  • first test unit group T1 and the second test unit group T2 respectively include multiple circuit test unit CP pads
  • the specific number of circuit test unit CP pads in each group is not limited here, and the number can be determined according to the display The design of the drive circuit in the panel's drive substrate is determined.
  • the circuit test unit CP pad can be used to test the overall electrical performance of the drive circuit in the drive substrate after the preparation of the drive substrate in the display panel is completed or after the display panel is prepared, to check whether there are abnormalities in the drive circuit. If there are Abnormalities can be repaired or adjusted according to the situation. It should be noted that when the display panel is prepared into a display device and used by the user, the circuit test unit CP pad will not be used.
  • the shape of the orthographic projection of the circuit test unit CP pad on the substrate of the display panel is not limited here.
  • the orthographic shape of the circuit test unit CP pad on the substrate of the display panel is
  • the shape of the projection can be rectangular.
  • the shape of the orthographic projection of the circuit test unit CP pad on the substrate of the display panel can also be a circle or a polygon other than a rectangle, which can be determined based on the actual product design.
  • circuit test unit CP pad There is no limit on the size of the circuit test unit CP pad here.
  • the number of circuit test unit CP pads in the first test unit group T1 and the number of circuit test unit CP pads in the second test unit group T2 can be set to be the same.
  • the first side L1 and the second side L2 of the above-mentioned display area AA are two opposite sides extending along the first direction in the display area AA, where the display area AA may also include those shown in Figures 1-7
  • the third side L3 and the fourth side L4 are shown; alternatively, the display area AA may also include a third side, a fourth side, a fifth side and a sixth side.
  • the extension directions of the other sides except the first side L1 and the second side L2 are not limited here.
  • the planar shape of the display area AA cannot be a triangle.
  • the maximum distance d3 from the first test unit group T1 to the first side L1 along the first direction perpendicular to the first direction refers to the maximum distance d3 along the circuit test unit CP pad of the first test unit group T1 The distance from the circuit test unit CP pad that is farthest perpendicular to the first direction to the first side L1 and the first side L1.
  • the maximum distance d4 from the second test unit group T2 to the second side L2 along the first direction perpendicular to the first direction refers to the maximum distance d4 along the circuit test unit CP pad of the second test unit group T2.
  • the maximum distance d4 of the side L2 is equal, which can make the arrangement of the first test unit group T1 in the peripheral area and the arrangement of the second test unit group T2 in the peripheral area as close as possible.
  • each circuit test unit CP pad can be electrically connected to the corresponding interface of the external test equipment, reducing the probability of chaotic connections or signal transmission, and also shortening the product preparation cycle; another
  • the arrangement of the first test unit group T1 in the peripheral area and the arrangement of the second test unit group T2 in the peripheral area can be made as symmetrical as possible to improve their distribution regularity and reduce design difficulty.
  • the minimum distance d1 of the first test unit group T1 along the perpendicular to the first direction to the first side L1 is equal to the minimum distance d1 of the second test unit group T2 along the perpendicular to the first direction.
  • the minimum distance d1 of the first test unit group T1 along the perpendicular to the first direction to the first side L1 refers to the distance d1 in each circuit test unit CP pad of the first test unit group T1 along the perpendicular to the first direction to the first side.
  • the minimum distance d2 of the second test unit group T2 along the perpendicular to the first direction to the second side L2 refers to the distance perpendicular to the first direction to the second side L2 in each circuit test unit CP pad of the second test unit group T2.
  • the minimum distance d1 from the first test unit group T1 to the first side L1 along the perpendicular to the first direction is different from the minimum distance d1 from the first test unit group T1 to the first side along the perpendicular to the first direction.
  • the maximum distance d3 of the side L1 is equal; the minimum distance d2 of the second test unit group T2 perpendicular to the first direction to the second side L2 is the same as the minimum distance d2 of the second test unit group T2 perpendicular to the first direction to the second side L2.
  • the maximum distance d4 is equal.
  • the minimum distance d1 of the first test unit group T1 to the first side L1 is along the perpendicular to the first direction
  • the minimum distance d1 of the second test unit group T2 is perpendicular to the first direction to the second side.
  • the minimum distance d2 of L2 the maximum distance d3 of the first test unit group T1 perpendicular to the first direction to the first side L1
  • the maximum distance d3 of the above-mentioned first test unit group T1 perpendicular to the first direction to the first side L1 and the maximum distance d3 of the second test unit group T2 perpendicular to the first direction to the second side is equal, and the minimum distance d1 of the first test unit group T1 perpendicular to the first direction to the first side L1 is the same as the minimum distance d1 of the second test unit group T2 perpendicular to the first direction to the second side L2.
  • the minimum distance d2 is equal.
  • each circuit test unit CP pad can be electrically connected to the external test equipment conveniently, reducing the probability of chaotic connections. It can also The arrangement of the first test unit group T1 in the peripheral area is as symmetrical as possible with the second test unit group T2, so as to further improve the regularity of its distribution and reduce the design difficulty.
  • the area in the peripheral area except the binding sub-areas B-D includes a light-shielding layer ZG; the orthographic projection of the light-shielding layer ZG on the substrate of the display panel The inner contour of is in contact with the edge of the display area AA;
  • the first test unit group T1 and the second test unit group T2 are both located on the side of the light shielding layer ZG away from the display area AA, and the orthographic projections of the first test unit group T1 and the second test unit group T2 on the substrate are both consistent with the light shielding layer ZG.
  • the orthographic projections of layers ZG on the substrate do not overlap each other.
  • the light-shielding layer ZG located in the peripheral area surrounds the display area AA.
  • the shape of the projection of the light-shielding layer ZG may be annular.
  • the specific shape of the above-mentioned annular shape is not limited here.
  • the annular shape may include a circular annular shape, an elliptical annular shape, a polygonal annular shape, etc.
  • the above-mentioned "contact” means that the projected inner contour of the light-shielding layer ZG is tangent to the projected outer contour of the display area AA, and the light-shielding layer ZG does not cover the display area AA.
  • the first test unit group T1 and the second test unit group T2 are both located on the side of the light-shielding layer ZG away from the display area AA, which means: the first test unit group T1 and the second test unit group T2 are both located on the side of the light-shielding layer ZG.
  • the outside refers to the area outside the outer contour of the light-shielding layer ZG.
  • other circuits and multiple traces may also be provided in the peripheral area, such as a cascaded shift register (GOA). ), light emitting control circuit (EOA), etc.
  • GOA cascaded shift register
  • EOA light emitting control circuit
  • At least a part of a shift register (GOA), an emission control circuit (EOA), and a plurality of traces may be disposed between the substrate of the display panel and the light-shielding layer ZG, that is, the light-shielding layer ZG covers at least part of the shift register (GOA), the light emission control circuit (EOA) and multiple traces to avoid reflection of the circuits and traces and reduce the display effect.
  • GOA shift register
  • EOA emission control circuit
  • a plurality of traces may be disposed between the substrate of the display panel and the light-shielding layer ZG, that is, the light-shielding layer ZG covers at least part of the shift register (GOA), the light emission control circuit (EOA) and multiple traces to avoid reflection of the circuits and traces and reduce the display effect.
  • the light-shielding layer ZG covers as many circuits and traces located in the peripheral area except the binding sub-area as possible.
  • the material of the light-shielding layer ZG includes an insulating material with a light-shielding function.
  • the light-shielding layer ZG can be prepared simultaneously using the same material as the black matrix layer BM in one patterning process.
  • the light-shielding layer ZG may include multiple sub-layers.
  • the light-shielding layer ZG may include: a first sub-layer made of the same material as the red color film pattern, a second sub-layer made of the same material as the green color film pattern, and a second sub-layer made of the same material as the blue color film pattern.
  • the prepared third sub-layer is obtained by arranging the stacked layers; wherein, the arrangement order of the first sub-layer, the second sub-layer and the third sub-layer is not limited here.
  • the first sub-layer can be arranged sequentially in the direction away from the substrate.
  • the first sub-layer, the third sub-layer and the second sub-layer may be disposed in sequence in the direction away from the substrate; for another example, the first sub-layer, the third sub-layer and the second sub-layer may be disposed in sequence in the direction away from the substrate.
  • the second sub-layer, the first sub-layer and the third sub-layer can be arranged in sequence in the direction of Sure.
  • the light-shielding layer ZG can block at least part of the circuits and wiring in the peripheral area to avoid reflection and reducing the display effect, so that the first test unit group T1 and the second test unit group T2 are located on the side of the light-shielding layer ZG away from the display area AA, and the orthographic projections of the first test unit group T1 and the second test unit group T2 on the substrate are both on the same side as the light-shielding layer ZG on the substrate.
  • the orthographic projections do not overlap with each other.
  • the light-shielding layer ZG exposes each circuit test unit CP pad in the first test unit group T1 and the second test unit group T2 to facilitate electrical connection with external test equipment and reduce connection confusion. The probability.
  • the peripheral area includes a first peripheral sub-area B1, and the first peripheral sub-area B1 is located on the side of the display area AA away from the binding sub-areas B-D;
  • the first peripheral sub-area B1 is located on the side of the display area AA away from the binding sub-areas B-D. This means that because the first side The side L1 and the second side L2 are two opposite sides.
  • the first side L1 and the second side L2 also include the opposite third side L3 and the fourth side L4 to form a closed Graphic, in which the first peripheral sub-area B1 and the binding sub-area B-D are respectively located outside the two opposite sides of the display area AA; for example, the first peripheral sub-area B1 is located outside the third side L3 of the display area AA , the binding sub-areas B-D are located outside the fourth side L4 of the display area AA.
  • part of the circuit test unit CP pad in the first test unit group T1 is located in the first peripheral sub-area B1, and another part of the circuit test unit CP pad in the first test unit group T1 is located in the peripheral area close to the first peripheral sub-area B1.
  • circuit test unit CP pads in the second test unit group T2 are located in the first peripheral sub-area B1, and another part of the circuit test unit CP pads in the second test unit group T2 are located in the peripheral area close to the second side L2.
  • one part, another part does not mean that it only includes two parts, but may also include a third part and a fourth part, which are specifically determined according to the design, as explained here.
  • the number of circuit test unit CP pads located in the first peripheral sub-area B1 in the first test unit group T1 is equal to the number of circuit test units CP pad located in the peripheral area close to the first side in the first test unit group T1.
  • the number of circuit test unit CP pads in the L1 area is the same.
  • the number of circuit test unit CP pads located in the first peripheral sub-area B1 in the second test unit group T2 is the same as the number of circuit test unit CP pads located in the peripheral area close to the second side L2 in the second test unit group T2. .
  • the number of circuit test unit CP pads located in the first peripheral sub-area B1 in the first test unit group T1 can be set to be greater than the area in the first test unit group T1 located in the peripheral area close to the first side L1
  • the number of circuit test unit CP pads, the number of circuit test unit CP pads located in the first peripheral sub-area B1 in the second test unit group T2 is greater than the area in the second test unit group T2 located in the peripheral area close to the second side L2
  • the number of circuit test units CP pad so that the left area of the display area AA (the area of the peripheral area close to the first side L1) and the right side of the display area AA (the area of the peripheral area close to the second side L2 ) reserves more design space for arranging GOA circuits, EOA circuits and various signal lines.
  • the signal lines may include power lines, ground lines, clock signal lines, etc.
  • each circuit test unit CP pad in the first test unit group T1 is arranged in an L shape
  • each circuit test unit CP pad in the second test unit group T2 is arranged in an L shape.
  • the line connecting the geometric centers of each circuit test unit CP pad in the first test unit group T1 may be two intersecting line segments, and the angle formed by the two intersecting line segments is not limited here. , for example, the included angle may range from 0° to 180°, such as 90°, 85° or 80°.
  • connection line between the geometric centers of each circuit test unit CP pad in the second test unit group T2 can be two intersecting line segments, and the angle formed by these two intersecting line segments is similar to the above-mentioned angle.
  • the angle formed by the connection between the geometric center of each circuit test unit CP pad in the first test unit group T1 and the connection between the geometric center of each circuit test unit CP pad in the second test unit group T2 can be set.
  • the included angles are the same.
  • connection line between the geometric centers of each circuit test unit CP pad in the first test unit group T1 and the connection line between the geometric centers of each circuit test unit CP pad in the second test unit group T2 may both be arcs.
  • the radian of the above arc is not limited here.
  • the arc formed by the connection line between the geometric center of each circuit test unit CP pad in the first test unit group T1 and the arc formed by the connection line between the geometric center of each circuit test unit CP pad in the second test unit group T2 Lines can be distributed mirror-symmetrically.
  • the circuit test unit CP pad located in the first peripheral sub-area B1 in the first test unit group T1 and the circuit test unit CP pad located in the peripheral area close to the first side in the first test unit group T1 At the position between the circuit test unit CP pads in the area of L1, an island pattern for alignment in the preparation circuit test unit CP pad can also be set, which is located in the first peripheral sub-area B1 in the second test unit group T2 At the position between the circuit test unit CP pad and the circuit test unit CP pad located in the peripheral area close to the second side L2 in the second test unit group T2, an island pattern for alignment marking can also be set .
  • an island pattern used for alignment marking is set between the two areas. On the one hand, one less island pattern can be set, saving design space; On the other hand, it is more conducive to improving alignment accuracy and reducing the difficulty of the preparation process.
  • the first test unit group T1 when preparing the circuit test unit CP pad in practical applications, can also use the second test unit when using its corresponding island pattern.
  • the island decoration pattern of the unit group T2 is used as an alignment reference; similarly, when the second test unit group T2 uses its corresponding island decoration pattern, it can also borrow the island decoration pattern of the first test unit group T1 as an alignment reference. Reference, while saving design space, improve alignment accuracy.
  • the island-shaped patterns used for alignment marking can also be set at both ends of the same test unit group. It can be understood that at this time, one test unit group is provided with two island-shaped patterns used for alignment marking. pattern.
  • each circuit test unit CP pad in the first test unit group T1 is located in the same line segment
  • the second test unit group The geometric center of each circuit test unit CP pad in T2 is located in the same line segment.
  • connection between the geometric center of each circuit test unit CP pad in the first test unit group T1 and the connection between the geometric center of each circuit test unit CP pad in the second test unit group T2 are collinear and intersected. Or whether they are parallel or not is not limited.
  • connection between the geometric center of each circuit test unit CP pad in the first test unit group T1 and the connection between the geometric center of each circuit test unit CP pad in the second test unit group T2 Lines are collinear.
  • connection between the geometric center of each circuit test unit CP pad in the first test unit group T1 and the connection between the geometric center of each circuit test unit CP pad in the second test unit group T2 The lines connecting the geometric centers are parallel.
  • connection between the geometric center of each circuit test unit CP pad in the first test unit group T1 and the connection between the geometric center of each circuit test unit CP pad in the second test unit group T2 Lines connecting geometric centers can intersect.
  • each circuit test unit CP pad in the first test unit group T1 is located in the peripheral area close to the first side L1, and the second test unit CP pad is located in the peripheral area close to the first side L1.
  • Each circuit test unit CP pad in unit group T2 is located in the peripheral area close to the second side L2.
  • the first test unit group T1 and the second test unit group T2 respectively include a first end close to the binding sub-region B-D and a first end far away from the binding sub-region B-D.
  • the second end of sub-area B-D wherein, the minimum distance between the first end perpendicular to the first direction (such as OA1 direction) and the display area AA is greater than or equal to the distance between the second end perpendicular to the first direction and the display area AA. the minimum distance between them.
  • the minimum distance between each circuit test unit CP pad and the edge of the display area AA is the same.
  • the minimum distance between each circuit test unit CP pad and the edge of the display area AA gradually increases.
  • the orthographic projection pattern of the circuit test unit CP pad on the substrate of the display panel includes a first edge, and the first edge is close to the first side of the display area AA
  • the side L1 is set, or the first edge is set close to the second side L2 of the display area AA.
  • the first edge of each circuit test unit CP pad extends along the first direction (for example, the OA1 direction).
  • the first edges of each circuit test unit CP pad in the same circuit test unit group extend in the same direction and the first edges can be collinear.
  • the extension direction of the first edge of each circuit test unit CP pad intersects with the first direction (for example, the OA1 direction). At this time, each first edge in the same circuit test unit group can intersect.
  • each circuit test unit CP that is beneficial to saving space can be determined according to the arrangement of circuits and wiring provided in the area where the peripheral area is located on the first side L1 and the area where the peripheral area is located on the second side L2 The setting position of the pad.
  • each circuit test unit CP pad in the first test unit group T1 and the second test unit group T2 is located in the first peripheral sub-area B1, within the same group
  • the circuit test unit CP pads are arranged perpendicular to the first direction (such as the OA1 direction);
  • the first test unit group T1 and the second test unit group T2 are arranged along the first direction (for example, the OA1 direction);
  • the first test unit group and the second test unit group are arranged perpendicular to the first direction.
  • each circuit test unit CP pad is arranged in mirror symmetry.
  • each circuit test unit CP pad when each circuit test unit CP pad is arranged in mirror symmetry, its symmetry axis (a virtual concept, which does not actually exist) extends along the first direction (for example, the OA1 direction).
  • the display panel has a symmetrically arranged circuit test unit CP pad, which can simplify the design and reduce the design difficulty, and also improve the aesthetics of the display panel.
  • the circuit test unit CP pad in the first test unit group T1 and the second test unit group T1 is shielded from light.
  • the minimum distance of the layer ZG is smaller than the minimum distance from the bonding terminal (not drawn in the figure) in the bonding sub-region B-D to the light shielding layer ZG.
  • the size of the portion of the light-shielding layer ZG located outside the third side L3 of the display area AA along the first direction is smaller than the size of the portion of the light-shielding layer ZG located outside the fourth side L3 of the display area AA along the first direction (such as the OA1 direction).
  • the size of OA1 direction is smaller than the size of the portion of the light-shielding layer ZG located outside the fourth side L3 of the display area AA along the first direction (such as the OA1 direction).
  • the display panel includes at least one third test unit group T3.
  • the third test unit group T3 includes a plurality of transistor test units TEG.
  • the third test unit group T3 Located in the first peripheral sub-area B1;
  • the distance between the transistor test unit TEG and the light shielding layer ZG is greater than or equal to the distance between the circuit test unit CP pad and the light shielding layer ZG.
  • the distance between the transistor test unit TEG and the light shielding layer ZG is greater than the distance between the circuit test unit CP pad and the light shielding layer ZG.
  • the distance between the transistor test unit TEG and the light shielding layer ZG is equal to the distance between the circuit test unit CP pad and the light shielding layer ZG.
  • a plurality of transistor test units TEG in a third test unit group T3 are divided into two parts, one part is set on the left side of each circuit test unit CP pad as shown in Figure 2, and the other part is set as shown in Figure 2 The right side of each circuit test unit CP pad shown in Figure 2; and the multiple transistor test units TEG in the third test unit group T3 are all arranged in the same row as the first test unit group T1.
  • the multiple transistor test units TEG in another third test unit group T3 are divided into two parts. One part is set on the left side of each circuit test unit CP pad as shown in Figure 2, and the other part is set on the left side of each circuit test unit CP pad as shown in Figure 2.
  • the right side of each circuit test unit CP pad shown in 2; and the multiple transistor test units TEG in the third test unit group T3 are all arranged in the same row as the second test unit group T2.
  • the above-mentioned transistor testing unit TEG is used to test the electrical properties of each transistor in the drive circuit of the display panel to ensure that after the preparation of each transistor, its electrical properties are stable. If individual transistors have electrical abnormalities or instability, According to the situation, the transistor can be electrically adjusted or repaired as needed.
  • the third test unit group T3 is located on the side of all circuit test units CP pad away from the display area AA, between the third test unit group T3 and the light shielding layer ZG There is a gap between them, and both the first test unit group T1 and the second test unit group T2 are located in the gap.
  • the display panel includes two third test unit groups T3, and the two third test unit groups T3 are along a direction perpendicular to the first direction, such as OA1 Directionally arranged, the first peripheral sub-area B1 includes a coding pattern, and the coding pattern is located between the two third test unit groups T3;
  • the minimum distance d5 between the coding pattern and the light-shielding layer ZG is greater than or equal to the minimum distance d6 between the transistor test unit TEG and the light-shielding layer ZG.
  • a coding pattern such as an ID
  • the coding pattern may include at least one of numbers, letters, symbols, and patterns.
  • the minimum distance d5 between the encoding pattern and the light shielding layer ZG is greater than the minimum distance d6 between the transistor test unit TEG and the light shielding layer ZG. Due to the limited mark space, in Figure 1 and 2 are not marked d5 and d6, you can refer to the markings in Figure 7.
  • the minimum distance d5 between the encoding pattern and the light-shielding layer ZG is greater than the minimum distance d6 between the transistor test unit TEG and the light-shielding layer ZG.
  • the encoding pattern is as far away from the circuit test unit CP as possible pad to avoid the negative impact of the heat generated by the laser on the circuit test unit CP pad when preparing the encoding pattern, thereby improving the stability of the circuit test unit CP pad.
  • the peripheral area also includes a second peripheral sub-area B-F.
  • the second peripheral sub-area B-F is located between the binding sub-area B-D and the display area AA.
  • the light shielding layer The orthographic projection of ZG on the substrate falls into the area in the peripheral area except for the binding sub-areas B-D;
  • the distance d7 between the outer contour of the light-shielding layer ZG located in the first peripheral sub-region B1 and the edge of the display area AA along the first direction, such as the OA1 direction, is smaller than the outer contour of the light-shielding layer ZG.
  • the distance d8 is between the portion located in the second peripheral sub-region B-F along the first direction, such as the OA1 direction, and the edge of the display area AA.
  • the second peripheral sub-regions B-F may be fan-out sub-regions, where fan-out traces are provided in the fan-out sub-regions, and the fan-out traces are used to connect the data lines (Data) in the display area AA to the The bonding terminals in stator zones B-D are electrically connected together.
  • the second peripheral sub-regions B-F may not be provided with fan-out traces (not fan-out sub-regions), but may be provided through metal holes, such as tungsten, between multi-layer conductive layers in the array substrate of the display panel. holes, which will electrically connect the data line (Data) in the display area AA with the binding terminals in the binding sub-areas B-D. In this way, the size of the peripheral area can be further reduced, thereby facilitating the preparation of narrow-frame display products. .
  • the light-shielding layer ZG covers the second peripheral sub-region B-F and extends to the edge of the binding sub-region B-D.
  • the orthographic projection of the light-shielding layer ZG on the substrate is the same as the orthogonal projection of the binding sub-region on the substrate. The projections do not overlap each other.
  • the light-shielding layer ZG is made to cover as much of the peripheral area as possible, except for the binding terminals (bonding sub-area), the circuit test unit CP pad and the transistor test unit TEG. area, thereby reducing the reflection of light from the wiring in the peripheral area and improving the display effect.
  • the binding terminal (binding sub-area), circuit test unit CP pad and transistor test unit TEG need to be electrically connected to other components in subsequent applications, they need to be exposed and cannot be covered by the light shielding layer ZG.
  • the shape of the orthographic projection of the light shielding layer ZG on the substrate includes a rectangle with four rounded corners;
  • the curvature radius of the two rounded corners of the rectangle close to the binding sub-area B-D is greater than the curvature radius of the two rounded corners of the rectangle close to the first peripheral sub-area B1.
  • the light-shielding layer ZG can cover More areas in the second peripheral sub-region B-F are used to block the traces in the second peripheral sub-region B-F as much as possible, thereby avoiding the reflection of light by the traces and improving the display effect of the display panel.
  • the display panel includes a cover plate CG, which covers part of the light-shielding layer ZG and the display area AA, and the cover plate CG is positioned directly on the substrate.
  • the projected outer contour falls within the orthographic projection of the light-shielding layer ZG on the substrate;
  • the four vertex corners of the outer contour of the orthographic projection of the cover plate CG on the substrate are respectively located at the four rounded corners.
  • the cover plate CG may be made of a light-transmitting material, such as glass or light-transmitting resin.
  • the area of the portion of the light-shielding layer ZG located in the first peripheral sub-region B1 that does not overlap with the cover plate CG is smaller than the area of the portion of the light-shielding layer ZG located in the second peripheral sub-region B1.
  • the portion of the light-shielding layer ZG located in the first peripheral sub-region B1 that does not overlap with the cover plate CG may be the area marked Area1, and the light-shielding layer ZG is located in the second peripheral sub-region B1.
  • the portion of areas B-F that does not overlap with the cover plate CG may be the area marked Area2.
  • the area where the cover plate CG overlaps with the light shielding layer ZG has a dimension d9 in the direction from the display area AA to the peripheral area that is greater than Dimension d10 of the circuit test unit CP pad along the first direction (for example, OA1 direction).
  • the size of the partially overlapping area of the first binding sub-region B1 between the cover plate CG and the light-shielding layer ZG is along the direction of the display area AA toward the peripheral area.
  • the cover plate CG and the light-shielding layer ZG are located at The size of the partially overlapping area of the second peripheral sub-region B-F in the direction of the display area AA pointing to the peripheral area, the partially overlapping area of the cover plate CG and the light shielding layer ZG located in the peripheral area close to the first side L1 along the display area
  • the size of AA in the direction pointing to the peripheral area and the size of the overlapping area of the cover plate CG and the light-shielding layer ZG located near the second side L2 of the peripheral area along the direction of the display area AA pointing to the peripheral area are equal.
  • the area of the orthographic projection pattern of the circuit test unit CP pad on the substrate is less than or equal to the area of the orthographic projection pattern of the binding sub-region B-D binding terminals (not drawn in the figure) on the substrate. area.
  • the size of the orthographic projection pattern of the binding terminal on the substrate pointing toward the peripheral area along the display area AA is larger than that of the circuit test unit CP pad.
  • the orthographic projection pattern on the substrate along the display area AA points toward the periphery. Dimensions in area direction.
  • the size of the orthographic projection pattern of the binding terminal on the substrate along the direction of the display area AA pointing to the peripheral area can be the size of the orthographic projection pattern of the circuit test unit CP pad on the substrate along the direction of the display area AA pointing toward the peripheral area. 5 times to 20 times.
  • circuit test unit CP pad is not used when the display panel is applied to display products and used by users after completing the test, when setting up the circuit test unit CP pad, you can test the process and Within the scope allowed by the preparation process, the size of the circuit test unit CP pad should be reduced as much as possible, thereby reducing the space it occupies and improving the utilization of the design space in the peripheral area, which is beneficial to the preparation of narrow-frame products.
  • the number of circuit test unit CP pads is greater than the number of binding terminals.
  • the number of circuit test unit CP pads is twice or more than twice the number of bound terminals.
  • the circuit test unit CP pad by setting the number of circuit test units CP pad to be greater than the number of bound terminals, when the circuit test unit CP pad is used to detect the drive circuit in the array substrate, it can more accurately detect whether the circuit is If there is an abnormality, it can even accurately detect the area and position of the abnormal device in the driving circuit, which is more conducive to repairing the abnormality before the display panel is prepared into a display device, thereby improving the production yield and production of display products. quality.
  • the display panel further includes a detection unit.
  • the detection unit includes a plurality of auxiliary sub-pixels.
  • the detection unit is located in the peripheral area close to the first side L1, and/or the detection unit is located in the peripheral area close to the first side L1.
  • the area of the two sides L2; the structure of the auxiliary sub-pixel is the same as the structure of the sub-pixel in the display area AA; the light-shielding layer ZG covers the detection unit.
  • the auxiliary sub-pixel is located in the area of the peripheral area close to the first side L1, and/or the auxiliary sub-pixel is located in the area of the peripheral area close to the second side L2, including the following situations:
  • auxiliary sub-pixels are located in the peripheral area close to the first side L1;
  • auxiliary sub-pixels are located in the area of the peripheral area close to the first side L1, and some auxiliary sub-pixels are located in the area of the peripheral area close to the second side L2.
  • the emitting color of each auxiliary sub-pixel may be the same, for example, the emitting color may be white, or the emitting color may be blue.
  • the luminescent colors of each auxiliary sub-pixel may not be exactly the same. For example, the luminescent color of some auxiliary sub-pixels is red, the luminescent color of some auxiliary sub-pixels is green, and the luminescent color of some auxiliary sub-pixels is green. is blue.
  • the auxiliary sub-pixels in the monitoring detection unit can be state to determine the lighting status of the sub-pixels in the display area.
  • the temperature difference between the auxiliary sub-pixels of different colors is determined by monitoring the temperature of the auxiliary sub-pixels in the detection unit. Since the luminous efficiency of the OLED sub-pixels is sensitive to temperature, the temperature difference can be determined based on the temperature difference. Adjust the driving voltage and other related parameters to improve the display effect of the display panel.
  • the display panel also includes four marking patterns BJ.
  • the marking patterns BJ are located on the side of the light-shielding layer ZG away from the substrate.
  • the top corners of the cover plate CG are on the substrate.
  • the orthographic projection at least partially overlaps the orthographic projection of the marking pattern BJ on the substrate.
  • the mark pattern BJ is used as an alignment mark when laminating the cover plate CG to improve the alignment accuracy of the cover plate CG.
  • the mark pattern BJ mentioned in the embodiment of the present application is the alignment mark when fitting the cover plate CG
  • the island pattern mentioned in the embodiment of the present application is the alignment mark when preparing the circuit test unit CP pad. mark.
  • the orthographic projection of the top corner of the cover plate CG on the substrate and the orthographic projection of the marking pattern BJ on the substrate at least partially overlap include but are not limited to the following situations:
  • the orthographic projection of the top corner of the cover plate CG on the substrate partially overlaps with the orthographic projection of the marking pattern BJ on the substrate;
  • the orthographic projection of the top corner of the cover plate CG on the substrate completely overlaps with the orthographic projection of the marking pattern BJ on the substrate.
  • the design space of the marking pattern BJ can be saved, thereby optimizing Display panel design.
  • An embodiment of the present application provides a display device, including the display panel as mentioned above,
  • the display device also includes a flexible circuit board FPC and a driver chip IC;
  • the display panel includes a display control unit, and the display device further includes a flexible circuit board FPC.
  • the array substrate of the silicon substrate in the display device can integrate the pixel driving circuit array, Source Driver (source driver), Gate Driver (gate driver) pole driver), Emission Control Driver (light-emitting control driver), OSC (oscillator, oscillator), Gamma Register (Gamma register) and display control unit integrated circuit are integrated on the same chip. At this time, there is no need to set up additional driver chips.
  • the display panel is directly electrically connected to the flexible circuit board FPC, which is called One Chip technology.
  • the display device prepared by One Chip technology is more integrated, but smaller in size, and can be suitable for high-resolution display products, such as virtual reality (Virtual Reality, referred to as VR) or augmented reality (Augmented Reality, referred to as AR) near-eye display in the field.
  • VR Virtual Reality
  • AR Augmented Reality
  • the array substrate of the silicon substrate can also include a pixel driving circuit array, a Source driver, a Gate driver, and an Emission driver (ie, the EOA of this application).
  • Emission driver ie, the EOA of this application.
  • Unit and other analog circuit parts are separated from the OSC, Gamma register, Interface and display control unit, changing from One Chip technology to Two Chip technology.
  • the display panel needs to be electrically connected to the flexible circuit board FPC and driver chip IC respectively. Compared with One Chip technology products, these products have lower manufacturing process requirements and can use low-tech processes to reduce production costs.
  • the display device may be a flexible display device (also called a flexible screen) or a rigid display device (that is, a display device that cannot be bent), which is not limited here.
  • the display device may be an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device, or may be any product or component with a display function such as a TV, digital camera, mobile phone, tablet computer, etc. including OLED.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the display device has the advantages of good display effect, long life, and high stability.
  • An embodiment of the present application provides a wearable device, as shown in Figures 8-11 and 13-14, which includes two display devices as described above, and also includes two annular first display devices as shown in Figure 12 Bracket ZJ1, the display device is fixed on the first bracket ZJ1, and the first bracket ZJ1 covers the area where the light shielding layer ZG is not provided in the peripheral area of the display panel; among them, each circuit test unit CP pad in one display device is connected to another display device Each circuit test unit CP pad in the circuit is set up in mirror symmetry.
  • the circuit test unit CP pad and the transistor test unit TEG need to be electrically connected to other components in the subsequent process of display panel preparation, in order to perform circuit or For the performance test of the transistor, it needs to be exposed and cannot be covered by the light shielding layer ZG.
  • the display panel is prepared into a display device (at this time, the flexible circuit board has been set on the binding terminal and is not exposed), the circuit or transistor has been completed. Performance test, but the exposed circuit test unit CP pad and transistor test unit TEG will reflect light, reduce the display effect, and reduce the user experience. Therefore, when installing the first bracket ZJ1, the first bracket ZJ1 is blocked
  • the exposed circuit test unit CP pad and transistor test unit TEG can avoid reflection and improve the display effect and user experience.
  • the front projection of the first bracket ZJ1 on the substrate of the display panel and the light-shielding layer ZG are set The orthographic projection on the substrate overlaps, so that the exposed circuit test unit CP pad and transistor test unit TEG can be further blocked, thereby avoiding reflection and improving the display effect and user experience.
  • each circuit test unit CP pad in one display device is mirror symmetrically arranged with each circuit test unit CP pad in another display device, the display areas of the two display devices can be arranged as symmetrically as possible, thereby It can, to a certain extent, improve the problem of image ghosting caused by the unequal center points of the left and right eyes of the wearable device, thus improving the user experience.
  • each circuit test unit CP pad in one display device can also be arranged mirror-symmetrically with each circuit test unit CP pad in another display device, and the display area in one display device and The display areas in the other display device are arranged in mirror symmetry. This can avoid the problem of ghosting images caused by the unequal center points of the left and right eyes of the wearable device, thereby improving the user experience.
  • the inner contour of the orthographic projection of the first bracket ZJ1 on the substrate is at least partially connected with the outer contour of the orthographic projection of the cover plate CG on the substrate. In this way, at least a part of the outer edge of the cover plate CG is stuck on the inner contour of the first bracket ZJ1, thereby playing a fixed role.
  • the first bracket ZJ1 further includes a blocking portion 206 , which contacts the back of the display device to prevent the display device in the wearable device from moving along a direction perpendicular to the substrate. Movement or looseness in the direction of the plane.
  • the above-mentioned back side refers to the side opposite to the light-emitting surface.
  • the first bracket ZJ1 further includes two first mounting parts 204 and two second mounting parts 205 .
  • a second bracket is further included, and the second bracket is configured to be wearable.
  • the second bracket includes a main body portion ZJ2-1 as shown in Figure 13 and Two temples connected to the main part ZJ2-1; wherein, a driving board and two first brackets ZJ1 are respectively fixed on the main part ZJ2-1 of the second bracket, and the driving board is connected to the flexible circuit board of the two display devices respectively. FPC electrical connection;
  • the main part ZJ2-1 of the second bracket as shown in Figure 13 includes a connecting piece 209, two third mounting pieces 207 and two fourth mounting pieces 208, wherein the second mounting piece on the first bracket ZI1 205 is installed and fixed with the third installation part 207 on the second bracket, and the first installation part 204 on the first bracket ZI1 is installed and fixed with the fourth installation part 208 on the second bracket.
  • the above-mentioned driving board is used to provide information such as image signals to the display device.
  • first mounting part 204 and the third mounting part 207 shown in Figures 12 and 13 can both be annular structures, as shown in Figures 12 and 13
  • the second mounting member 205 and the fourth mounting member 208 shown may both be in a columnar structure.
  • the two display panels are arranged in mirror symmetry, and the geometric center of the display area AA of the two display panels is located at the same geometric center as the main body part ZJ2-1 of the second bracket.
  • a display device it is called a display device.
  • the shape and size of the flexible circuit board 201 are not limited here, and can be determined based on the actual design.
  • the shape of the flexible circuit board 201 may be rectangular or L-shaped.
  • the two display panels in the wearable device are arranged in mirror symmetry, and the geometric center of the display area AA of the two display panels and the geometric center of the main body part ZJ2-1 of the second bracket are located at Within the same straight line, when the user uses the device, the center of the field of view of the user's left eye and the center of the field of view of the user's right eye are located in the same straight line.
  • the center of the field of view of the user's left eye and the center of the field of view of the user's right eye are located in the same straight line.
  • two display devices are arranged in mirror symmetry, where the display devices include a display panel and a flexible circuit board 201.
  • the flexible circuit board 201 is provided with a connection interface 202 (also called a connector) for electrically connecting the connection interface with external circuits.
  • a connection interface 202 also called a connector
  • the two flexible circuit boards 201 are centrally symmetrically arranged with the geometric center of the main body part of the second bracket as the symmetry point.
  • Figures 8 to 11 are all schematic diagrams of the intermediate structure of the wearable device.
  • Figures 14 and 15 show schematic structural diagrams of two wearable devices.
  • the wearable device also includes a drive board.
  • the drive board can be disposed at the position marked 1, mark 2 or mark 3.
  • the drive board is connected to the two wearable devices respectively.
  • the flexible circuit boards 201 are electrically connected.
  • the driving board is placed at the position marked 1 in the wearable device to maintain the balance of the device.
  • the two flexible circuit boards 201 can be bent in the direction marked by the arrow as shown in Figure 10 or Figure 11 , and is electrically connected to the drive board set at the position marked 1.
  • the two flexible circuit boards 201 are centrally symmetrical with the geometric center of the second bracket as the symmetry point.
  • the wearable device further includes a first lens and a second lens disposed on the light exit side of the display device.
  • first lens and the second lens disposed on the light exit side of the display device.
  • the light-emitting sides of the two display devices are both facing the human eye position.
  • the temple positions of the wearable device are respectively provided with two traces electrically connected to the two flexible circuit boards, wherein the component 4 is used to connect the two traces together in parallel. , and is electrically connected to an external device, which is used to provide control signals to the wearable device.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板、显示装置及可穿戴设备。显示面板包括显示区（AA）和围绕显示区（AA）的周边区，周边区中除绑定子区（B-D）之外的区域包括第一测试单元组（T1）和第二测试单元组（T2），第一测试单元组（T1）和第二测试单元组（T2）分别包括至少一个电路测试单元（CP pad）；显示区（AA）包括沿第一方向（OA1）延伸且相对设置的第一侧边（L1）和第二侧边（L2）；第一方向（OA1）为绑定子区（B-D）指向显示区（AA）的方向；第一测试单元组（T1）沿垂直于第一方向（OA1）到第一侧边（L1）的最大距离（d3）等于第二测试单元组（T2）沿垂直于第一方向（OA1）到第二侧边（L2）的最大距离（d4）。显示面板的设计难度低、显示效果好。

Description

显示面板、显示装置及可穿戴设备 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、显示装置及可穿戴设备。
背景技术
随着显示技术的不断发展，硅基OLED(Organic Light Emitting Diode，有机发光二极管)显示产品由于其具有高分辨率、低功耗、体积小、重量轻等优势，引起人们的广泛关注。其在可穿戴设备、工业安防、医疗等高分辨率的近眼显示行业具有很好的应用前景。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种显示面板，包括显示区和围绕所述显示区的周边区，所述周边区包括位于所述显示区一侧的绑定子区；
所述周边区中除所述绑定子区之外的区域包括第一测试单元组和第二测试单元组，所述第一测试单元组和所述第二测试单元组分别包括至少一个电路测试单元；所述显示区包括沿第一方向延伸且相对设置的第一侧边和第二侧边；所述第一方向为所述绑定子区指向所述显示区的方向；
其中，所述第一测试单元组沿垂直于所述第一方向到所述第一侧边的最大距离等于所述第二测试单元组沿垂直于所述第一方向到所述第二侧边的最大距离。
在本申请的一些实施例中，所述第一测试单元组沿垂直于所述第一方向到所述第一侧边的最小距离等于所述第二测试单元组沿垂直于所述第一方向到所述第二侧边的最小距离。
在本申请的一些实施例中，所述周边区中除所述绑定子区之外的区域包括遮光层；所述遮光层在所述显示面板的衬底上的正投影的内轮廓 与所述显示区的边缘接触；
所述第一测试单元组和所述第二测试单元组均位于所述遮光层远离所述显示区的一侧，且所述第一测试单元组和所述第二测试单元组在所述衬底上的正投影均与所述遮光层在所述衬底上的正投影互不交叠。
在本申请的一些实施例中，所述周边区包括第一周边子区，所述第一周边子区位于所述显示区远离所述绑定子区的一侧；
所述第一测试单元组中的部分所述电路测试单元位于所述第一周边子区，所述第一测试单元组中的另一部分所述电路测试单元位于所述周边区靠近所述第一侧边的区域；
所述第二测试单元组中的部分所述电路测试单元位于所述第一周边子区，所述第二测试单元组中的另一部分所述电路测试单元位于所述周边区靠近所述第二侧边的区域。
在本申请的一些实施例中，所述第一测试单元组中各所述电路测试单元的几何中心的连线以及所述第二测试单元组中各所述电路测试单元的几何中心的连线分别形成两条相交的线段；
或者，所述第一测试单元组中各所述电路测试单元的几何中心的连线以及所述第二测试单元组中各所述电路测试单元的几何中心的连线分别为弧线。
在本申请的一些实施例中，所述第一测试单元组中各所述电路测试单元的几何中心位于同一线段内，所述第二测试单元组中各所述电路测试单元的几何中心位于同一线段内。
在本申请的一些实施例中，所述第一测试单元组中各所述电路测试单元均位于所述周边区靠近所述第一侧边的区域，所述第二测试单元组中各所述电路测试单元均位于所述周边区靠近所述第二侧边的区域。
在本申请的一些实施例中，所述第一测试单元组和所述第二测试单元组分别包括靠近所述绑定子区的第一端和远离所述绑定子区的第二端；
其中，所述第一端沿垂直于所述第一方向到所述显示区之间的最小距离大于或等于所述第二端沿垂直于所述第一方向到所述显示区之间 的最小距离。
在本申请的一些实施例中，所述第一测试单元组和所述第二测试单元组中各所述电路测试单元均位于所述第一周边子区，同一组内的所述电路测试单元均沿垂直于所述第一方向排布；
所述第一测试单元组和所述第二测试单元组沿所述第一方向排布；
或者，所述第一测试单元组和所述第二测试单元组沿垂直于所述第一方向排布。
在本申请的一些实施例中，各所述电路测试单元呈镜面对称排布。
在本申请的一些实施例中，在平行于所述衬底所在的平面上，所述第一测试单元组和所述第二测试单元组中的所述电路测试单元到所述遮光层的最小距离小于所述绑定子区中的绑定端子到所述遮光层的最小距离。
在本申请的一些实施例中，所述显示面板包括至少一个第三测试单元组，所述第三测试单元组包括多个晶体管测试单元，所述第三测试单元组位于所述第一周边子区；
所述晶体管测试单元到所述遮光层之间的距离大于或等于所述电路测试单元到所述遮光层之间的距离。
在本申请的一些实施例中，所述第三测试单元组位于所有所述电路测试单元远离所述显示区的一侧，所述第三测试单元组与所述遮光层之间具有间隙，所述第一测试单元组和所述第二测试单元组均位于所述间隙中。
在本申请的一些实施例中，所述显示面板包括两个所述第三测试单元组，两个所述第三测试单元组沿垂直于所述第一方向排布，所述第一周边子区包括编码图案，所述编码图案位于两个所述第三测试单元组之间；所述编码图案到所述遮光层之间的最小距离大于或等于所述晶体管测试单元到所述遮光层之间的最小距离。
在本申请的一些实施例中，所述周边区还包括第二周边子区，所述第二周边子区位于所述绑定子区和所述显示区之间，所述遮光层在所述衬底上的正投影落入所述周边区中除所述绑定子区之外的区域内；
其中，所述遮光层的外轮廓位于所述第一周边子区的部分沿所述第一方向到所述显示区的边缘之间的距离小于所述遮光层的外轮廓位于所述第二周边子区的部分沿所述第一方向到所述显示区的边缘之间的距离。
在本申请的一些实施例中，所述遮光层在所述衬底上的正投影的形状包括具有四个圆角的矩形；
其中，所述矩形靠近所述绑定子区的两个所述圆角的曲率半径大于所述矩形靠近所述第一周边子区的两个所述圆角的曲率半径。
在本申请的一些实施例中，所述显示面板包括盖板，所述盖板覆盖所述遮光层的部分区域以及所述显示区，且所述盖板在所述衬底上的正投影的外轮廓落入所述遮光层在所述衬底上的正投影以内；
所述盖板在所述衬底上的正投影的外轮廓的四个顶角分别位于四个所述圆角处。
在本申请的一些实施例中，所述遮光层位于所述第一周边子区的部分未与所述盖板交叠的区域的面积小于所述遮光层位于所述第二周边子区的部分未与所述盖板交叠的区域的面积。
在本申请的一些实施例中，所述电路测试单元的数量大于所述绑定端子的数量。
在本申请的一些实施例中，在平行于所述衬底所在的平面上，所述盖板与所述遮光层交叠的区域沿所述显示区指向所述周边区的方向上的尺寸大于所述电路测试单元沿所述第一方向上的尺寸。
在本申请的一些实施例中，所述电路测试单元在所述衬底上的正投影图形的面积小于或等于所述绑定端子在所述衬底上的正投影图形的面积。
在本申请的一些实施例中，所述显示面板还包括检测单元，所述检测单元包括多个辅助子像素，所述辅助子像素位于所述周边区靠近所述第一侧边的区域，和/或，所述辅助子像素位于所述周边区靠近所述第二侧边的区域；
所述辅助子像素的结构与所述显示区中的子像素的结构相同；所述 遮光层覆盖所述检测单元。
在本申请的一些实施例中，所述显示面板还包括四个标记图案，所述标记图案位于所述遮光层远离所述衬底的一侧，所述盖板的所述顶角在所述衬底上的正投影与所述标记图案在所述衬底上的正投影至少部分交叠。
第二方面，本申请的实施例提供了一种显示装置，包括如第一方面中所述的显示面板，
所述显示装置还包括柔性电路板和驱动芯片；
或者，所述显示面板包括显示控制单元，所述显示装置还包括柔性电路板。
第三方面，本申请的实施例提供了一种可穿戴设备，包括两个如第二方面所述的显示装置，还包括两个环形第一支架，所述显示装置固定在所述第一支架上，所述第一支架覆盖所述显示面板的周边区中未设置遮光层的区域；其中，一个所述显示装置中的各电路测试单元与另一个所述显示装置中的各电路测试单元呈镜面对称设置。
在本申请的一些实施例中，所述第一支架在所述显示面板的衬底上的正投影与所述遮光层在所述衬底上的正投影交叠。
在本申请的一些实施例中，所述第一支架在所述衬底上的正投影的内轮廓与所述盖板在所述衬底上的正投影的外轮廓至少部分相接。
在本申请的一些实施例中，
还包括第二支架，所述第二支架被配置为能够穿戴，所述第二支架包括主体部分和两个镜腿，所述第二支架的主体部分上分别固定有驱动板和两个所述第一支架，所述驱动板分别与两个所述显示装置的柔性电路板电连接；
两个所述显示面板呈镜面对称设置，且两个所述显示面板的显示区的几何中心与所述第二支架的主体部分的几何中心位于同一直线内，两个所述柔性电路板以所述第二支架的几何中心为对称点呈中心对称设 置。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1-图7为本申请的实施例提供的七种显示面板的结构示意图；
图8-图11为本申请的实施例提供的四种可穿戴设备的中间结构示意图；
图12为本申请的实施例提供的可穿戴设备中的一种第一支架的结构示意图；
图13为本申请的实施例提供的可穿戴设备中的一种第二支架的主体部分结构示意图；
图14和图15为本申请的实施例提供的两种可穿戴设备的结构示意图；
图16为本申请的实施例提供的一种相关技术中的可穿戴设备的中间结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
本说明书中多边形并非严格意义上的，可以是近似的三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在倒角、圆角、弧边以及变形等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
现将参照附图更全面地描述示例性的实施例。
随着显示技术的不断发展，硅基OLED(Organic Light Emitting Diode，有机发光二极管)显示产品由于其具有体积小，分辨率高的特点。其背板采用成熟的集成电路CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)工艺制成，实现了像素的有源寻址，包括TCON(Timer Control Register，计数器控制寄存器)、OCP(Over Current Protection，过流保护)等多种电路，能够实现轻量化。
硅基OLED显示产品广泛应用于近眼显示与虚拟现实(Virtual Reality，简称VR)或增强现实(Augmented Reality，简称AR)中，特别是AR/VR头戴显示装置中。目前，应用在AR/VR装置中的硅基OLED显示产品，需要具有较高的PPI(Pixels Per Inch，像素密度单位)，这对硅基OLED显示产品的像素排布与像素面积设计要求较高。另外，在高度集成和小型化的硅基OLED显示产品中，为了兼具较好的显示效果并能够节省设计空间，相关技术中的设计已经不能满足需求。
为此，本申请的实施例提供了一种新设计的显示面板，以扩大硅基显示产品的使用场景，使其能够可穿戴设备、工业安防、医疗等高分辨率的近眼显示行业具有更深入的应用，还能够提高显示效果和用户的使用体验。
本申请的实施例采用如下技术方案：
本申请的实施例提供了一种显示面板，如图1-图7所示，包括显示区AA和围绕显示区的周边区，周边区包括位于显示区一侧的绑定子区B-D；
周边区中除绑定子区B-D之外的区域包括第一测试单元组T1和第二测试单元组T2，第一测试单元组T1和第二测试单元组T2分别包括至少一个电路测试单元CP pad；显示区AA包括沿第一方向，例如OA1方向，延伸且相对设置的第一侧边L1和第二侧边L2；第一方向，例如OA1方向，为绑定子区B-D指向显示区AA的方向；
其中，第一测试单元组T1沿垂直于第一方向到第一侧边L1的最大距离d3等于第二测试单元组T2沿垂直于第一方向到第二侧边L2的 最大距离d3。
这里对于上述显示面板的具体类型不进行限定。具体可以根据实际情况决定。
示例性的，上述显示面板可以为OLED(Organic Light Emitting Diode，有机发光二极管)显示面板，OLED显示面板包括具有硅衬底(Si Substrate)的OLED显示面板以及具有玻璃衬底的OLED显示面板。
示例性的，上述显示面板可以为Micro-OLED(Micro-Organic Light Emitting Diode，微型有机发光二极管)。或者，上述显示面板可以为Mini-OLED(Mini-Organic Light Emitting Diode，次毫米有机发光二极管)。Micro-OLED显示面板和Mini-OLED显示面板也分别包括玻璃衬底和硅衬底两种类型。
其中，硅衬底可以为P型单晶硅衬底，或者，也可以为N型单晶硅衬底，具体可以根据实际产品进行确定。需要说明的是，本申请的实施例以上述显示面板为硅衬底的显示面板为例进行说明。
这里对于上述显示区AA的平面图形不进行限定。
示例性的，显示区AA的平面图形可以为如图1-图7中示例性的矩形；或者，显示区AA的平面图形也可以为其它多边形，例如，五边形、六边形等，具体根据使用场景和使用需求确定。
其中，周边区的平面图形可为环形，显示区AA的平面图形的不同，周边区的平面图形也不同，周边区的平面图形根据显示区AA的平面图形确定。
上述平面图形指的是在显示面板的衬底上的正投影的图形。
上述绑定子区B-D指的是周边区中用于与驱动芯片(IC)和柔性电路板(FPC)进行绑定(Bonding)的区域。
在一些实施例中，为了节省设计空间，提高产品的分辨率，将驱动芯片IC中相关的电路和模块集成在显示面板的驱动基板中，此时，显示面板中可以不设置驱动芯片，则绑定子区B-D指的是周边区中用于与柔性电路板(FPC)进行绑定(Bonding)的区域。
在一些实施例中，为了降低成本，显示面板中同时包括驱动芯片(IC)和柔性电路板(FPC)的情况下，上述绑定子区B-D指的是周边区中分别用于与驱动芯片(IC)和柔性电路板(FPC)进行绑定(Bonding)的区域。
上述第一测试单元组T1和第二测试单元组T2分别包括至少一个电路测试单元CP pad，本申请的实施例均以上述第一测试单元组T1和第二测试单元组T2分别包括多个电路测试单元CP pad为例进行说明。
在上述第一测试单元组T1和第二测试单元组T2分别包括多个电路测试单元CP pad的情况下，这里对各组中电路测试单元CP pad的具体数量不进行限定，其数量可以根据显示面板的驱动基板中的驱动电路的设计确定。
其中，电路测试单元CP pad可以用于在显示面板中的驱动基板制备完成或者显示面板制备完成之后，对驱动基板中驱动电路的整体电性能进行测试，以检查其驱动电路是否存在异常，若存在异常，可根据情况对异常处进行修补或调节。需要说明的是，在显示面板制备成显示装置，且用户使用的过程中，电路测试单元CP pad并不会被使用到。
这里对于电路测试单元CP pad在显示面板的衬底上的正投影的形状不进行限定，示例性的，如图1-图7所示，电路测试单元CP pad在显示面板的衬底上的正投影的形状可以为矩形。当然，电路测试单元CP pad在显示面板的衬底上的正投影的形状还可以为圆形或除矩形之外的其它多边形，具体可以根据实际产品设计确定。
这里对于电路测试单元CP pad的尺寸大小不进行限定。
这里对于同一测试单元组中各电路测试单元CP pad的尺寸是否相同不进行限定。其中，本申请的实施例提供的附图以所有电路测试单元CP pad的尺寸相同为例进行说明。
这里对于第一测试单元组T1中电路测试单元CP pad的数量和第二测试单元组T2中电路测试单元CP pad的数量是否相同不进行限定。
在一些实施例中，为了简化设计，可以设置第一测试单元组T1中电路测试单元CP pad的数量和第二测试单元组T2中电路测试单元CP  pad的数量相同。
上述显示区AA的第一侧边L1和第二侧边L2为显示区AA中沿第一方向延伸的两个相对的侧边，其中，显示区AA还可以包括如图1-图7中所示的第三侧边L3、第四侧边L4；或者，显示区AA还可以包括第三侧边、第四侧边、第五侧边和第六侧边。这里对于除第一侧边L1和第二侧边L2之外的其它侧边的延伸方向不进行限定。
其中，需要说明的是，由于显示区AA的第一侧边L1和第二侧边L2的延伸方向相同(即平行)，故而，显示区AA的平面图形不能为三角形。
在示例性的实施例中，第一测试单元组T1沿垂直于第一方向到第一侧边L1的最大距离d3指的是在第一测试单元组T1的各电路测试单元CP pad中，沿垂直于第一方向到第一侧边L1最远的电路测试单元CP pad到第一侧边L1之间的距离。
在示例性的实施例中，第二测试单元组T2沿垂直于第一方向到第二侧边L2的最大距离d4指的是在第二测试单元组T2的各电路测试单元CP pad中，沿垂直于第一方向到第二侧边L2最远的电路测试单元CP pad到第二侧边L2之间的距离。
在本申请的实施例中，通过设置上述第一测试单元组T1沿垂直于第一方向到第一侧边L1的最大距离d3与第二测试单元组T2沿垂直于第一方向到第二侧边L2的最大距离d4相等，能够使得第一测试单元组T1在周边区中的排布与第二测试单元组T2在周边区中的排布方式尽可能接近，一方面，能够在后续对驱动基板中驱动电路的整体电性能进行测试时，便于各电路测试单元CP pad与外部的测试设备对应的接口电连接，降低连接混乱或信号传输混乱的概率，还能缩短产品的制备周期；另一方面，能够使得第一测试单元组T1在周边区中的排布与第二测试单元组T2在周边区中的排布尽可能对称分布，以提高其分布规律性，降低设计难度。
在本申请的一些实施例中，如图1-图7所示，第一测试单元组T1沿垂直于第一方向到第一侧边L1的最小距离d1等于第二测试单元组 T2沿垂直于第一方向到第二侧边L2的最小距离d2。
其中，第一测试单元组T1沿垂直于第一方向到第一侧边L1的最小距离d1指的是第一测试单元组T1的各电路测试单元CP pad中，沿垂直于第一方向到第一侧边L1最近的电路测试单元CP pad到第一侧边L1之间的距离。
第二测试单元组T2沿垂直于第一方向到第二侧边L2的最小距离d2指的是在第二测试单元组T2的各电路测试单元CP pad中，沿垂直于第一方向到第二侧边L2最近的电路测试单元CP pad到第二侧边L2之间的距离。
在一些实施例中，如图4所示，第一测试单元组T1沿垂直于第一方向到第一侧边L1的最小距离d1与第一测试单元组T1沿垂直于第一方向到第一侧边L1的最大距离d3相等；第二测试单元组T2沿垂直于第一方向到第二侧边L2的最小距离d2与第二测试单元组T2沿垂直于第一方向到第二侧边L2的最大距离d4相等。
示例性的，如图4所示，第一测试单元组T1沿垂直于第一方向到第一侧边L1的最小距离d1、第二测试单元组T2沿垂直于第一方向到第二侧边L2的最小距离d2、第一测试单元组T1沿垂直于第一方向到第一侧边L1的最大距离d3以及第二测试单元组T2沿垂直于第一方向到第二侧边L2的最大距离d4四者均相等。
在本申请的实施例中，通过设置上述第一测试单元组T1沿垂直于第一方向到第一侧边L1的最大距离d3与第二测试单元组T2沿垂直于第一方向到第二侧边L2的最大距离d4相等，且第一测试单元组T1沿垂直于第一方向到第一侧边L1的最小距离d1与第二测试单元组T2沿垂直于第一方向到第二侧边L2的最小距离d2相等，这样，能够在后续对驱动基板中驱动电路的整体电性能进行测试时，进一步使得各电路测试单元CP pad便于与外部的测试设备电连接，降低连接混乱的概率，还能够得第一测试单元组T1在周边区中的排布与第二测试单元组T2尽可能对称分布，以进一步提高其分布规律性，降低设计难度。
在本申请的一些实施例中，如图1-图7所示，周边区中除绑定子区 B-D之外的区域中包括遮光层ZG；遮光层ZG在显示面板的衬底上的正投影的内轮廓与显示区AA的边缘接触；
第一测试单元组T1和第二测试单元组T2均位于遮光层ZG远离显示区AA的一侧，且第一测试单元组T1和第二测试单元组T2在衬底上的正投影均与遮光层ZG在衬底上的正投影互不交叠。
在示例性的实施例中，位于周边区的遮光层ZG围绕显示区AA，可以理解，遮光层ZG的投影的形状可以为环形。这里对于上述环形的具体形状不进行限定，示例性的，环形可以包括圆环形、椭圆环形、多边环形等。
另外，上述“接触”指的是遮光层ZG的投影的内轮廓与显示区AA的投影的外轮廓相切，且遮光层ZG不覆盖显示区AA。
其中，第一测试单元组T1和第二测试单元组T2均位于遮光层ZG远离显示区AA的一侧指的是：第一测试单元组T1和第二测试单元组T2均位于遮光层ZG的外侧。其中，外侧指的是遮光层ZG的外轮廓之外的区域。
在本申请的实施例中，周边区中除第一测试单元组T1和第二测试单元组T2之外，还可以设置有其它电路和多条走线，例如级联设置的移位寄存器(GOA)、发光控制电路(EOA)等。
在一些实施例中，诸如移位寄存器(GOA)、发光控制电路(EOA)和多条走线中的至少一部分可以设置在显示面板的衬底和遮光层ZG之间，也就是说，遮光层ZG覆盖移位寄存器(GOA)、发光控制电路(EOA)和多条走线的至少一部分，以避免电路和走线的反光而降低了显示效果。
示例性的，在制备工艺条件允许的情况下，遮光层ZG覆盖尽可能多的位于周边区中除绑定子区之外的区域中的电路和走线。
在示例性的实施例中，遮光层ZG的材料包括具有遮光功能的绝缘材料。
示例性的，遮光层ZG可以采用与黑色矩阵层BM相同的材料在一次构图工艺中同时制备。
示例性的，遮光层ZG可以包括多个子层。例如，遮光层ZG可以 包括：采用与红色彩膜图案相同的材料制备的第一子层，采用与绿色彩膜图案相同的材料制备的第二子层，以及采用与蓝色彩膜图案相同的材料制备的第三子层叠层设置得到；其中，这里对于第一子层、第二子层和第三子层的设置顺序不进行限定，例如，在沿远离衬底的方向上可以依次设置第一子层、第二子层和第三子层；再例如，在沿远离衬底的方向上可以依次设置第一子层、第三子层和第二子层；又例如，在沿远离衬底的方向上可以依次设置第二子层、第一子层和第三子层；当然，还可以包括其它情况，具体可以根据红色彩膜图案、绿色彩膜图案与蓝色彩膜图案的制备工艺顺序确定。
在本申请的实施例中，通过设置遮光层ZG，这样，在遮光层ZG能够遮挡周边区的至少部分电路和走线，避免其产生反光降低显示效果的情况下，使得第一测试单元组T1和第二测试单元组T2均位于遮光层ZG远离显示区AA的一侧，且第一测试单元组T1和第二测试单元组T2在衬底上的正投影均与遮光层ZG在衬底上的正投影互不交叠，这样，遮光层ZG暴露出第一测试单元组T1和第二测试单元组T2中的各电路测试单元CP pad，以便于与外部的测试设备电连接，降低连接混乱的概率。
在本申请的一些实施例中，如图1-图7所示，周边区包括第一周边子区B1，第一周边子区B1位于显示区AA远离绑定子区B-D的一侧；
以本申请的实施例提供的显示面板的显示区AA的平面图形为矩形为例，说明第一周边子区B1位于显示区AA远离绑定子区B-D的一侧指的是：由于第一侧边L1和第二侧边L2为相对的两个侧边，在第一侧边L1和第二侧边L2之间还包括相对的第三侧边L3和第四侧边L4，以构成封闭的图形，其中，第一周边子区B1和绑定子区B-D分别位于显示区AA相对的两个侧边的外侧；例如，第一周边子区B1位于显示区AA的第三侧边L3的外侧，绑定子区B-D位于显示区AA的第四侧边L4的外侧。
其中，如图3所示，第一测试单元组T1中的部分电路测试单元CP pad位于第一周边子区B1，第一测试单元组T1中的另一部分电路测试 单元CP pad位于周边区靠近第一侧边L1的区域；
第二测试单元组T2中的部分电路测试单元CP pad位于第一周边子区B1，第二测试单元组T2中的另一部分电路测试单元CP pad位于周边区靠近第二侧边L2的区域。
在本申请的实施例中，“部分，另一部分”相关的描述并不代表只包括两个部分，还可以包括第三部分、第四部分，具体根据设计确定，这里做出说明。
在一些实施例中，如图3所示，第一测试单元组T1中位于第一周边子区B1的电路测试单元CP pad的数量与第一测试单元组T1中位于周边区靠近第一侧边L1的区域的电路测试单元CP pad的数量相同。第二测试单元组T2中位于第一周边子区B1的电路测试单元CP pad的数量与第二测试单元组T2中位于周边区靠近第二侧边L2的区域的电路测试单元CP pad的数量相同。
在另一些实施例中，可以设置第一测试单元组T1中位于第一周边子区B1的电路测试单元CP pad的数量大于第一测试单元组T1中位于周边区靠近第一侧边L1的区域的电路测试单元CP pad的数量，第二测试单元组T2中位于第一周边子区B1的电路测试单元CP pad的数量大于第二测试单元组T2中位于周边区靠近第二侧边L2的区域的电路测试单元CP pad的数量，这样，可以在显示区AA的左侧区域(周边区靠近第一侧边L1的区域)以及显示区AA的右侧(周边区靠近第二侧边L2的区域)预留出更多的设计空间用以排布GOA电路、EOA电路和各类信号线。其中，信号线可以包括电源线、接地线、时钟信号线等。
在本申请的一些实施例中，第一测试单元组T1中各电路测试单元CP pad呈L型排布，第二测试单元组T2中各所述电路测试单元CP pad呈L型排布。
在一些实施例中，第一测试单元组T1中各电路测试单元CP pad的几何中心的连线可以为两条相交的线段，这里对于这俩条相交的线段形成的夹角的角度不进行限定，示例性的，其夹角的角度范围可以为0°～180°，例如90°、85°或80°。
其中，第二测试单元组T2中各电路测试单元CP pad的几何中心的连线可以为两条相交的线段，这俩条相交的线段形成的夹角与上述夹角类似。
示例性的，可以设置第一测试单元组T1中各电路测试单元CP pad的几何中心的连线形成的夹角与第二测试单元组T2中各电路测试单元CP pad的几何中心的连线形成的夹角的角度相同。
在一些实施例中，第一测试单元组T1中各电路测试单元CP pad的几何中心的连线以及第二测试单元组T2中各电路测试单元CP pad的几何中心的连线可以均为弧线，这里对于上述弧线的弧度不进行限定。
示例性的，第一测试单元组T1中各电路测试单元CP pad的几何中心的连线形成的弧线与第二测试单元组T2中各电路测试单元CP pad的几何中心的连线形成的弧线可以呈镜面对称分布。
在示例性的实施例中，如图3所示，第一测试单元组T1中位于第一周边子区B1的电路测试单元CP pad以及第一测试单元组T1中位于周边区靠近第一侧边L1的区域的电路测试单元CP pad之间的位置处，还可以设置用于在制备电路测试单元CP pad进行对位的岛状图案，在第二测试单元组T2中位于第一周边子区B1的电路测试单元CP pad以及第二测试单元组T2中位于周边区靠近第二侧边L2的区域的电路测试单元CP pad之间的位置处，还可以设置用于进行对位标记的岛状图案。
由于同一组测试单元组分别位于两个不同的区域内，将用于进行对位标记的一个岛状图案设置在两个区域之间，一方面，可以少设置一个岛装图案，节省设计空间；另一方面，更有利于提高对位精度，降低制备工艺难度。
需要说明的是，对于如图3所示的结构，在实际应用中制备电路测试单元CP pad时，第一测试单元组T1在使用其对应的岛装图案的情况下，还可以借用第二测试单元组T2的岛装图案作为对位参考；同样的，在第二测试单元组T2在使用其对应的岛装图案的情况下，还可以借用第一测试单元组T1的岛装图案作为对位参考，节省设计空间的同时， 提高对位精度。
当然，用于进行对位标记的岛状图案还可以设置在同一组测试单元组的两端，可以理解，此时，一组测试单元组对应设置有两个用于进行对位标记的岛状图案。
在本申请的一些实施例中，如图1、图2、图4-图6所示，第一测试单元组T1中各电路测试单元CP pad的几何中心位于同一线段内，第二测试单元组T2中各电路测试单元CP pad的几何中心位于同一线段内。
这里对于第一测试单元组T1中各电路测试单元CP pad的几何中心的连线与第二测试单元组T2中各电路测试单元CP pad的几何中心的连线之间的是否共线、是否相交或是否平行均不进行限定。
在一些实施例中，如图1所示，第一测试单元组T1中各电路测试单元CP pad的几何中心的连线与第二测试单元组T2中各电路测试单元CP pad的几何中心的连线共线。
在另一些实施例中，如图2和图4所示，第一测试单元组T1中各电路测试单元CP pad的几何中心的连线与第二测试单元组T2中各电路测试单元CP pad的几何中心的连线平行。
在又一些实施例中，如图5和图6所示，第一测试单元组T1中各电路测试单元CP pad的几何中心的连线与第二测试单元组T2中各电路测试单元CP pad的几何中心的连线能够相交。
在本申请的一些实施例中，如图4、图5和图6所示，第一测试单元组T1中各电路测试单元CP pad均位于周边区靠近第一侧边L1的区域，第二测试单元组T2中各电路测试单元CP pad均位于周边区靠近第二侧边L2的区域。
在本申请的一些实施例中，如图4、图5和图6所示，第一测试单元组T1和第二测试单元组T2分别包括靠近绑定子区B-D的第一端和远离绑定子区B-D的第二端；其中，第一端沿垂直于第一方向(例如OA1方向)到显示区AA之间的最小距离大于或等于第二端沿垂直于第一方向到显示区AA之间的最小距离。
在一些实施例中，如图4所示，各电路测试单元CP pad到显示区 AA的边缘之间的最小距离均相等。
在另一些实施例中，如图5和图6所示，沿第一方向(例如OA1方向)上，各电路测试单元CP pad到显示区AA的边缘之间的最小距离逐渐减小。
在又一些实施例中，沿第一方向(例如OA1方向)上，各电路测试单元CP pad到显示区AA的边缘之间的最小距离逐渐增大。
在本申请的一些实施例中，如图5和图6所示，电路测试单元CP pad在显示面板的衬底上的正投影图形包括第一边缘，第一边缘靠近显示区AA的第一侧边L1设置，或第一边缘靠近显示区AA的第二侧边L2设置。
示例性的，如图6所示，各电路测试单元CP pad的第一边缘均沿第一方向(例如OA1方向)延伸。此时，同一电路测试单元组内的各电路测试单元CP pad的第一边缘的延伸方向相同且各第一边缘能够共线。
示例性的，如图5所示，各电路测试单元CP pad的第一边缘的延伸方向均与第一方向(例如OA1方向)相交。此时，同一电路测试单元组内的各第一边缘能够相交。
在实际应用中，可以根据周边区位于第一侧边L1的区域以及周边区位于第二侧边L2的区域中设置的电路和走线的排布，确定有利于节省空间的各电路测试单元CP pad的设置位置。
在本申请的一些实施例中，如图1和图2所示，第一测试单元组T1和第二测试单元组T2中各电路测试单元CP pad均位于第一周边子区B1，同一组内的电路测试单元CP pad均垂直于第一方向(例如OA1方向)排布；
如图2所示，第一测试单元组T1和第二测试单元组T2沿第一方向(例如OA1方向)排布；
或者，如图1所示，第一测试单元组和第二测试单元组沿垂直于第一方向排布。
在本申请的一些实施例中，各电路测试单元CP pad呈镜面对称排 布。
在示例性的实施例中，各电路测试单元CP pad呈镜面对称排布的情况下，其对称轴(虚拟概念，实际并不存在)沿第一方向(例如OA1方向)延伸。
这样，使得显示面板具有对称设置的电路测试单元CP pad，能够简化设计并降低设计难度，还能够提高显示面板的美观度。
在本申请的一些实施例中，如图1和图2所示，在平行于衬底所在的平面上，第一测试单元组T1和第二测试单元组T1中的电路测试单元CP pad到遮光层ZG的最小距离小于绑定子区B-D中的绑定端子(图中未绘制)到遮光层ZG的最小距离。此时，遮光层ZG位于显示区AA第三侧边L3外侧的部分沿第一方向(例如OA1方向)的尺寸小于遮光层ZG位于显示区AA第四侧边L3外侧的部分沿第一方向(例如OA1方向)的尺寸。
需要说明的是，在本申请的实施例中，诸如“平行于衬底所在的平面”相关的描述的含义为：由于衬底的厚度较薄，将其厚度忽略，并将三维立体结构的衬底近似看作一个二维的平面，用于辅助描述，在实际应用中，衬底并不是二维的平面，仅以说明。前后文中相关的描述的含义与此处类似，不再赘述。
在本申请的一些实施例中，如图1-图7所示，显示面板包括至少一个第三测试单元组T3，第三测试单元组T3包括多个晶体管测试单元TEG，第三测试单元组T3位于第一周边子区B1；
晶体管测试单元TEG到遮光层ZG之间的距离大于或等于电路测试单元CP pad到遮光层ZG之间的距离。
在一些实施例中，如图1和图2所示，晶体管测试单元TEG到遮光层ZG之间的距离大于电路测试单元CP pad到遮光层ZG之间的距离。
在另一些实施例中，晶体管测试单元TEG到遮光层ZG之间的距离等于电路测试单元CP pad到遮光层ZG之间的距离。
示例性的，将一组第三测试单元组T3中的多个晶体管测试单元TEG分为两部分，一部分设置在如图2所示的各电路测试单元CP pad 的左侧，另一部分设置在如图2所示的各电路测试单元CP pad的右侧；且该组第三测试单元组T3中的多个晶体管测试单元TEG均与第一测试单元组T1同排设置。
另外，将另一组第三测试单元组T3中的多个晶体管测试单元TEG分为两部分，一部分设置在如图2所示的各电路测试单元CP pad的左侧，另一部分设置在如图2所示的各电路测试单元CP pad的右侧；且该组第三测试单元组T3中的多个晶体管测试单元TEG均与第二测试单元组T2同排设置。这里仅参考如图2中各电路测试单元CP pad的设置位置，且不考虑现有图2中的第三测试单元组T3。
需要说明的是，上述晶体管测试单元TEG用于测试显示面板的驱动电路中各晶体管的电性，以确保在各晶体管制备完成后，其电性能稳定，若个别晶体管出现电性异常或不稳定的情况，根据需求对晶体管进行电性调节或修补。
在本申请的一些实施例中，如图1和图2所示，第三测试单元组T3位于所有电路测试单元CP pad远离显示区AA的一侧，第三测试单元组T3与遮光层ZG之间具有间隙，第一测试单元组T1和第二测试单元组T2均位于间隙中。
在本申请的一些实施例中，如图1、图2和图7所示，显示面板包括两个第三测试单元组T3，两个第三测试单元组T3沿垂直于第一方向，例如OA1方向排布，第一周边子区B1包括编码图案，编码图案位于两个第三测试单元组T3之间；
其中，编码图案到遮光层ZG之间的最小距离d5大于或等于晶体管测试单元TEG到遮光层ZG之间的最小距离d6。
示例性的，编码图案，例如ID，用于区分同一批次生产的不同的显示面板，类似于显示面板的身份标识。编码图案可以包括数字、字母、符号和图案中的至少一种。
在一些实施例中，如图1和图2所示，编码图案到遮光层ZG之间的最小距离d5大于晶体管测试单元TEG到遮光层ZG之间的最小距离d6，由于标记空间有限，在图1和图2中并未标记d5和d6，可以参考 图7的标记。
在一些实施例中，如图7所示，编码图案到遮光层ZG之间的最小距离d5大于晶体管测试单元TEG到遮光层ZG之间的最小距离d6。
在本申请的实施例中，通过设置编码图案到遮光层ZG之间的最小距离d5大于或等于晶体管测试单元TEG到遮光层ZG之间的最小距离d6，使得编码图案尽可能远离电路测试单元CP pad，以避免在制备编码图案时，激光产生的热量对电路测试单元CP pad造成负面影响，从而提高电路测试单元CP pad的稳定性。
在本申请的一些实施例中，如图1-图7所示，周边区还包括第二周边子区B-F，第二周边子区B-F位于绑定子区B-D和显示区AA之间，遮光层ZG在衬底上的正投影落入周边区中除绑定子区B-D之外的区域内；
其中，如图6所示，遮光层ZG的外轮廓位于第一周边子区B1的部分沿第一方向，例如OA1方向，到显示区AA的边缘之间的距离d7小于遮光层ZG的外轮廓位于第二周边子区B-F的部分沿第一方向，例如OA1方向，到显示区AA的边缘之间的距离d8。
在一些实施例中，第二周边子区B-F可以为扇出子区，其中，扇出子区中设置有扇出走线，扇出走线用于将显示区AA中的数据线(Data)与绑定子区B-D中的绑定端子电连接在一起。
在另一些实施例中，第二周边子区B-F可以不设置扇出走线(不是扇出子区)，而是通过位于显示面板的阵列基板中的多层导电层之间的金属孔，例如钨孔，将将显示区AA中的数据线(Data)与绑定子区B-D中的绑定端子电连接在一起，这样，能够进一步减小周边区的尺寸，从而有利于窄边框显示产品的制备。
在本申请的实施例中，遮光层ZG覆盖第二周边子区B-F并延伸至绑定子区B-D的边缘，遮光层ZG在衬底上的正投影与绑定子区在衬底上的正投影互不交叠。
在本申请的实施例中，在制备工艺允许的情况下，使得遮光层ZG尽可能多的覆盖周边区中除设置绑定端子(绑定子区)、电路测试单元 CP pad和晶体管测试单元TEG的区域，从而降低周边区中走线对光线的反射，提高显示效果。另外，由于绑定端子(绑定子区)、电路测试单元CP pad和晶体管测试单元TEG在后续应用中需要与其它部件电连接，故而需要裸露出来，不能被遮光层ZG覆盖。
在本申请的一些实施例中，如图1-7所示，遮光层ZG在衬底上的正投影的形状包括具有四个圆角的矩形；
其中，矩形靠近绑定子区B-D的两个圆角的曲率半径大于矩形靠近第一周边子区B1的两个圆角的曲率半径。
在本申请的实施例中，通过设置矩形靠近绑定子区B-D的两个圆角的曲率半径大于矩形靠近第一周边子区B1的两个圆角的曲率半径，这样，遮光层ZG能够覆盖第二周边子区B-F中更多的区域，以尽可能的遮挡住第二周边子区B-F中的走线，从而避免走线对光线的反射作用，提高显示面板的显示效果。
在本申请的一些实施例中，如图1-图7所示，显示面板包括盖板CG，盖板CG覆盖遮光层ZG的部分区域以及显示区AA，且盖板CG在衬底上的正投影的外轮廓落入遮光层ZG在衬底上的正投影以内；
盖板CG在衬底上的正投影的外轮廓的四个顶角分别位于四个圆角处。
需要说明的是，在本申请的实施例中，为了便于看到显示面板中除盖板CG之外的其它结构，在附图中的盖板CG只绘制出了盖板CG的外轮廓。
在示例性的实施例中，盖板CG的材料可以为透光材料，例如玻璃或透光树脂。
在本申请的一些实施例中，如图1-7所示，遮光层ZG位于第一周边子区B1的部分未与盖板CG交叠的区域的面积小于遮光层ZG位于第二周边子区B-F的部分未与盖板CG交叠的区域的面积。
在示例性的实施例中，如图6所示，遮光层ZG位于第一周边子区B1的部分未与盖板CG交叠的区域可以为标记Area1的区域，遮光层ZG位于第二周边子区B-F的部分未与盖板CG交叠的区域可以为标记 Area2的区域。
在本申请的一些实施例中，如图6所示，在平行于衬底所在的平面上，盖板CG与遮光层ZG交叠的区域沿显示区AA指向周边区的方向上的尺寸d9大于电路测试单元CP pad沿第一方向(例如OA1方向)上的尺寸d10。
在示例性的实施例中，盖板CG与遮光层ZG位于第一绑定子区B1的部分交叠的区域沿显示区AA指向周边区的方向上的尺寸、盖板CG与遮光层ZG位于第二周边子区B-F的部分交叠的区域沿显示区AA指向周边区的方向上的尺寸、盖板CG与遮光层ZG位于周边区靠近第一侧边L1的部分交叠的区域沿显示区AA指向周边区的方向上的尺寸、以及盖板CG与遮光层ZG位于周边区靠近第二侧边L2的部分交叠的区域沿显示区AA指向周边区的方向上的尺寸均相等。
在本申请的一些实施例中，电路测试单元CP pad在衬底上的正投影图形的面积小于或等于绑定子区B-D绑定端子(图中未绘制)在衬底上的正投影图形的面积。
在示例性的实施例中，绑定端子在衬底上的正投影图形沿显示区AA指向周边区方向上的尺寸大于电路测试单元CP pad在衬底上的正投影图形沿显示区AA指向周边区方向上的尺寸。
例如，绑定端子在衬底上的正投影图形沿显示区AA指向周边区方向上的尺寸可以为电路测试单元CP pad在衬底上的正投影图形沿显示区AA指向周边区方向上的尺寸的5倍到20倍。
在实际应用中，由于显示面板在完成测试之后，应用到显示产品时以及用户在使用过程中，电路测试单元CP pad并没有用到，故而在设置电路测试单元CP pad时，可以在测试工艺和制备工艺允许范围内，尽可能缩小电路测试单元CP pad的尺寸，从而减小其占据的空间，提高周边区的设计空间利用率，进而有利于窄边框产品的制备。
在本申请的一些实施例中，电路测试单元CP pad的数量大于绑定端子的数量。
示例性的，电路测试单元CP pad的数量为绑定端子的数量的两倍 以及两倍以上。
在本申请的实施例中，通过设置电路测试单元CP pad的数量大于绑定端子的数量，在通过电路测试单元CP pad对阵列基板中的驱动电路进行检测时，能够更精确的检测出电路是否存在异常，甚至能够精准的检测出驱动电路中的出现异常的器件的区域和位置，从而更有利于在显示面板制备成显示装置之前，对异常处进行修补，从而提高显示产品的制备良率和品质。
在本申请的一些实施例中，显示面板还包括检测单元，检测单元包括多个辅助子像素，检测单元位于周边区靠近第一侧边L1的区域，和/或，检测单元位于周边区靠近第二侧边L2的区域；辅助子像素的结构与显示区AA中的子像素的结构相同；遮光层ZG覆盖检测单元。
辅助子像素位于周边区靠近第一侧边L1的区域，和/或，辅助子像素位于周边区靠近第二侧边L2的区域包括如下情况：
第一、所有辅助子像素位于周边区靠近第一侧边L1的区域；
第二、所有辅助子像素位于周边区靠近第二侧边L2的区域；
第三、部分辅助子像素位于周边区靠近第一侧边L1的区域，部分辅助子像素位于周边区靠近第二侧边L2的区域。
在一些实施例中，各辅助子像素的发光颜色可以均相同，例如，发光颜色均为白色，或者发光颜色均为蓝色。在另一些实施例中，各辅助子像素的发光颜色可以不完全相同，例如，一部分辅助子像素的发光颜色为红色，一部分的辅助子像素的发光颜色为绿色，一部分的辅助子像素的发光颜色为蓝色。
在本申请的实施例中，通过在周边区中设置多个辅助子像素，且辅助子像素的结构与显示区AA中的子像素的结构相同，这样，可以通过监控检测单元中的辅助子像素的状态，以确定显示区中的子像素的发光状况。具体的，对于OLED显示面板，通过监控检测单元中的辅助子像素的温度，确定不同颜色的辅助子像素之间的温度差异，由于OLED子像素的发光效率对温度具有敏感性，可以根据温度差异对驱动电压等相关参数进行调整，从而提高显示面板的显示效果。
在本申请的一些实施例中，如图7所示，显示面板还包括四个标记图案BJ，标记图案BJ位于遮光层ZG远离衬底的一侧，盖板CG的顶角在衬底上的正投影与标记图案BJ在衬底上的正投影至少部分交叠。
需要说明的是，标记图案BJ是用作贴合盖板CG时的对位标记，用以提高盖板CG的对位精度。
为了进行区分，本申请的实施例中提到的标记图案BJ为贴合盖板CG时的对位标记，本申请的实施例提到的岛状图案为制备电路测试单元CP pad时的对位标记。
盖板CG的顶角在衬底上的正投影与标记图案BJ在衬底上的正投影至少部分交叠包括但不限于以下情况：
第一、盖板CG的顶角在衬底上的正投影与标记图案BJ在衬底上的正投影部分交叠；
第二、盖板CG的顶角在衬底上的正投影与标记图案BJ在衬底上的正投影完全交叠。
在本申请的实施例中，通过设置盖板CG的顶角在衬底上的正投影与标记图案BJ在衬底上的正投影至少部分交叠，可以节省标记图案BJ的设计空间，从而优化显示面板的设计。
本申请的实施例提供了一种显示装置，包括如前文所述的显示面板，
显示装置还包括柔性电路板FPC和驱动芯片IC；
或者，显示面板包括显示控制单元，显示装置还包括柔性电路板FPC。
在示例性的实施例中，在显示面板的衬底为硅衬底的情况下，显示装置中硅衬底的阵列基板能够将像素驱动电路阵列、Source Driver(源极驱动)、Gate Driver(栅极驱动)、Emission Control Driver(发光控制驱动)、OSC(oscillator，振荡器)、Gamma Register(Gamma寄存器)以及显示控制单元集成电路集成在同一芯片上，此时，不需要设置额外的驱动芯片，将显示面板直接与柔性电路板FPC进行电连接，这称作One Chip技术。One Chip技术制备的显示装置的集成度更高，然而尺 寸较小，可以适用于高分辨率的显示产品，例如虚拟现实(Virtual Reality，简称VR)或增强现实(Augmented Reality，简称AR)近眼显示领域中。
在示例性的实施例中，在显示面板的衬底为硅衬底的情况下，硅衬底的阵列基板还能够将像素驱动电路阵列、Source driver、Gate driver、Emission driver(即本申请的EOA单元)等模拟电路部分与OSC、Gamma register、Interface以及显示控制单元分开，由One Chip技术变为Two Chip技术，此时，显示面板需要分别与柔性电路板FPC和驱动芯片IC进行电连接，相较于One Chip技术的产品，这类产品制造工艺要求低，可使用低工艺制程以降低生产成本。
该显示装置可以是柔性显示装置(又称柔性屏)，也可以是刚性显示装置(即不能折弯的显示装置)，这里不做限定。该显示装置可以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置，还可以是包括OLED的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。该显示装置具有显示效果好、寿命长、稳定性高等优点。
本申请的实施例提供了一种可穿戴设备，如图8-11、图13-图14所示，包括两个如前文所述显示装置，还包括两个如图12所示的环形第一支架ZJ1，显示装置固定在第一支架ZJ1上，第一支架ZJ1覆盖显示面板的周边区中未设置遮光层ZG的区域；其中，一个显示装置中的各电路测试单元CP pad与另一个显示装置中的各电路测试单元CP pad呈镜面对称设置。
在示例性的实施例中，由于绑定端子(绑定子区B-D)、电路测试单元CP pad和晶体管测试单元TEG在显示面板制备完成的后续工艺中需要与其它部件电连接，以便进行电路或晶体管的性能测试，故而需要裸露出来，不能被遮光层ZG覆盖，在显示面板制备成为显示装置时(此时，绑定端子上已经设置有柔性电路板并未裸露)，已经完成电路或晶体管的性能测试，但是这部分裸露出的电路测试单元CP pad和晶体管测试单元TEG会反射光线，降低显示效果，并降低用户的使用体验， 故而在安装第一支架ZJ1时，使得第一支架ZJ1遮挡住裸露出的电路测试单元CP pad和晶体管测试单元TEG，从而避免反光，提高显示效果以及用户的使用体验。
在本申请的一些实施例中，为了提高遮挡效果，避免第一支架ZJ1与遮光层ZG之间留有缝隙产生反光，设置第一支架ZJ1在显示面板的衬底上的正投影与遮光层ZG在衬底上的正投影交叠，这样，可以进一步遮挡住裸露出的电路测试单元CP pad和晶体管测试单元TEG，从而避免反光，提高显示效果以及用户的使用体验。
另外，通过设置一个显示装置中的各电路测试单元CP pad与另一个显示装置中的各电路测试单元CP pad呈镜面对称设置，从而能够使得两个显示装置的显示区尽可能能够对称设置，从而能够一定程度上改善可穿戴装置左右眼视场中心点不等高导致的用户观测到画面重影的问题，从而提高用户的使用体验。
在本申请的一些实施例中，还可以设置一个显示装置中的各电路测试单元CP pad与另一个显示装置中的各电路测试单元CP pad呈镜面对称设置，且一个显示装置中的显示区与另一个显示装置中的显示区呈镜面对称设置。从而能够避免可穿戴装置左右眼视场中心点不等高导致的用户观测到画面重影的问题，从而提高用户的使用体验。
在本申请的一些实施例中，第一支架ZJ1在衬底上的正投影的内轮廓与盖板CG在衬底上的正投影的外轮廓至少部分相接。这样，使得盖板CG的外边缘的至少一部分卡在第一支架ZJ1的内轮廓上，从而起到固定的作用。
在一些实施例中，如图12所示，第一支架ZJ1上还包括阻挡部206，阻挡部206与显示装置的背面接触，以避免可穿戴设备中的显示装置在沿垂直于衬底所在的平面的方向上移动或松动。
上述背面指的是与出光面相对的一面。
在一些实施例中，如图12所示，第一支架ZJ1上还包括两个第一安装件204和两个第二安装件205。
在本申请的一些实施例中，还包括第二支架，第二支架被配置为能 够穿戴，在可穿戴设备为眼镜的情况下，第二支架包括如图13所示的主体部分ZJ2-1以及与主体部分ZJ2-1连接的两个镜腿；其中，第二支架的主体部分ZJ2-1上分别固定有驱动板和两个第一支架ZJ1，驱动板分别与两个显示装置的柔性电路板FPC电连接；
其中，如图13所示的第二支架的主体部分ZJ2-1包括连接件209、两个第三安装件207和两个第四安装件208，其中，第一支架ZI1上的第二安装件205与第二支架上的第三安装件207安装固定，第一支架ZI1上的第一安装件204与第二支架上的第四安装件208安装固定。
上述驱动板用于向显示装置提供图像信号等信息。
这里对于上述安装件的具体结构不进行限定，示例性的，如图12和图13所示的第一安装件204和第三安装件207可以均为环状结构，如图12和图13所示的第二安装件205和第四安装件208可以均在柱状结构。
在一些实施例中，如图8-11所示，两个显示面板呈镜面对称设置，且两个显示面板的显示区AA的几何中心与第二支架的主体部分ZJ2-1的几何中心位于同一直线内；需要说明的是，显示面板上绑定柔性电路板201之后，称作显示装置。
这里对于上述柔性电路板201的形状和尺寸不进行限定，具体可以根据实际设计确定。示例性的，柔性电路板201的形状可以为矩形或L形。
在本申请的实施例中，通过设置可穿戴设备中的两个显示面板呈镜面对称设置，且两个显示面板的显示区AA的几何中心与第二支架的主体部分ZJ2-1的几何中心位于同一直线内，在用户使用该设备时，用户左眼的视场中心与用户右眼的视场中心位于同一直线内，相较于如图16中所示的相关技术中的设备，能够显著避免左右眼视场中心点不等高导致的用户观测到重影的问题，从而提高用户的使用体验。
在一些实施例中，如图8-9所示，两个显示装置，呈镜面对称设置，其中显示装置包括显示面板和柔性电路板201。
在示例性的实施例中柔性电路板201上设置有连接接口202(又称 作连接器)，用以将连接接口与外界电路电连接。
在一些实施例中，如图10-11所示，两个柔性电路板201以第二支架的主体部分的几何中心为对称点呈中心对称设置。
需要说明的是，图8-图11均为可穿戴设备的中间结构示意图。
图14和图15示出了两种可穿戴设备的结构示意图，其中，该可穿戴设备还包括驱动板，驱动板可以设置在标记1、标记2或标记3的位置处，驱动板分别与两个柔性电路板201电连接。
示例性的，将驱动板设置在可穿戴设备中标记1的位置处，以保持设备平衡，此时，两个柔性电路板201可以如图10或如图11中所示沿箭头标记方向弯折，并与设置在标记1的位置处的驱动板电连接。此时，两个柔性电路板201以第二支架的几何中心为对称点呈中心对称设置。
在示例性的实施例中，可穿戴设备还包括设置在显示装置的出光侧的第一透镜和第二透镜，第一透镜和第二透镜的相关内容可以参考相关技术，这里不再赘述。
需要说明的是，对于如图14和图15所示的可穿戴设备，两个显示装置的出光侧均朝向人眼位置处。另外，如图14和图15所示的可穿戴设备的镜腿位置处分别设置有与两个柔性电路板电连接的两条走线，其中，组件4用于将两条走线并联在一起，并与外界设备电连接，外界设备用于向可穿戴设备提供控制信号。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种显示面板，其中，包括显示区和围绕所述显示区的周边区，所述周边区包括位于所述显示区一侧的绑定子区；
    所述周边区中除所述绑定子区之外的区域包括第一测试单元组和第二测试单元组，所述第一测试单元组和所述第二测试单元组分别包括至少一个电路测试单元；所述显示区包括沿第一方向延伸且相对设置的第一侧边和第二侧边；所述第一方向为所述绑定子区指向所述显示区的方向；
    其中，所述第一测试单元组沿垂直于所述第一方向到所述第一侧边的最大距离等于所述第二测试单元组沿垂直于所述第一方向到所述第二侧边的最大距离。
  2. 根据权利要求1所述的显示面板，其中，所述第一测试单元组沿垂直于所述第一方向到所述第一侧边的最小距离等于所述第二测试单元组沿垂直于所述第一方向到所述第二侧边的最小距离。
  3. 根据权利要求2所述的显示面板，其中，所述周边区中除所述绑定子区之外的区域包括遮光层；所述遮光层在所述显示面板的衬底上的正投影的内轮廓与所述显示区的边缘接触；
    所述第一测试单元组和所述第二测试单元组均位于所述遮光层远离所述显示区的一侧，且所述第一测试单元组和所述第二测试单元组在所述衬底上的正投影均与所述遮光层在所述衬底上的正投影互不交叠。
  4. 根据权利要求3所述的显示面板，其中，所述周边区包括第一周边子区，所述第一周边子区位于所述显示区远离所述绑定子区的一侧；
    所述第一测试单元组中的部分所述电路测试单元位于所述第一周边子区，所述第一测试单元组中的另一部分所述电路测试单元位于所述周边区靠近所述第一侧边的区域；
    所述第二测试单元组中的部分所述电路测试单元位于所述第一周边子区，所述第二测试单元组中的另一部分所述电路测试单元位于所述周边区靠近所述第二侧边的区域。
  5. 根据权利要求4所述的显示面板，其中，所述第一测试单元组 中各所述电路测试单元的几何中心的连线以及所述第二测试单元组中各所述电路测试单元的几何中心的连线分别形成两条相交的线段；
    或者，所述第一测试单元组中各所述电路测试单元的几何中心的连线以及所述第二测试单元组中各所述电路测试单元的几何中心的连线分别为弧线。
  6. 根据权利要求3所述的显示面板，其中，所述第一测试单元组中各所述电路测试单元的几何中心位于同一线段内，所述第二测试单元组中各所述电路测试单元的几何中心位于同一线段内。
  7. 根据权利要求6所述的显示面板，其中，所述第一测试单元组中各所述电路测试单元均位于所述周边区靠近所述第一侧边的区域，所述第二测试单元组中各所述电路测试单元均位于所述周边区靠近所述第二侧边的区域。
  8. 根据权利要求7所述的显示面板，其中，所述第一测试单元组和所述第二测试单元组分别包括靠近所述绑定子区的第一端和远离所述绑定子区的第二端；
    其中，所述第一端沿垂直于所述第一方向到所述显示区之间的最小距离大于或等于所述第二端沿垂直于所述第一方向到所述显示区之间的最小距离。
  9. 根据权利要求6所述的显示面板，其中，所述第一测试单元组和所述第二测试单元组中各所述电路测试单元均位于所述第一周边子区，同一组内的所述电路测试单元均沿垂直于所述第一方向排布；
    所述第一测试单元组和所述第二测试单元组沿所述第一方向排布；
    或者，所述第一测试单元组和所述第二测试单元组沿垂直于所述第一方向排布。
  10. 根据权利要求4-9中任一项所述的显示面板，其中，各所述电路测试单元呈镜面对称排布。
  11. 根据权利要求9所述的显示面板，其中，在平行于所述衬底所在的平面上，所述第一测试单元组和所述第二测试单元组中的所述电路测试单元到所述遮光层的最小距离小于所述绑定子区中的绑定端子到 所述遮光层的最小距离。
  12. 根据权利要求9所述的显示面板，其中，所述显示面板包括至少一个第三测试单元组，所述第三测试单元组包括多个晶体管测试单元，所述第三测试单元组位于所述第一周边子区；
    所述晶体管测试单元到所述遮光层之间的距离大于或等于所述电路测试单元到所述遮光层之间的距离。
  13. 根据权利要求12所述的显示面板，其中，所述第三测试单元组位于所有所述电路测试单元远离所述显示区的一侧，所述第三测试单元组与所述遮光层之间具有间隙，所述第一测试单元组和所述第二测试单元组均位于所述间隙中。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板包括两个所述第三测试单元组，两个所述第三测试单元组沿垂直于所述第一方向排布，所述第一周边子区包括编码图案，所述编码图案位于两个所述第三测试单元组之间；所述编码图案到所述遮光层之间的最小距离大于或等于所述晶体管测试单元到所述遮光层之间的最小距离。
  15. 根据权利要求10所述的显示面板，其中，所述周边区还包括第二周边子区，所述第二周边子区位于所述绑定子区和所述显示区之间，所述遮光层在所述衬底上的正投影落入所述周边区中除所述绑定子区之外的区域内；
    其中，所述遮光层的外轮廓位于所述第一周边子区的部分沿所述第一方向到所述显示区的边缘之间的距离小于所述遮光层的外轮廓位于所述第二周边子区的部分沿所述第一方向到所述显示区的边缘之间的距离。
  16. 根据权利要求15所述的显示面板，其中，所述遮光层在所述衬底上的正投影的形状包括具有四个圆角的矩形；
    其中，所述矩形靠近所述绑定子区的两个所述圆角的曲率半径大于所述矩形靠近所述第一周边子区的两个所述圆角的曲率半径。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板包括盖板，所述盖板覆盖所述遮光层的部分区域以及所述显示区，且所述盖 板在所述衬底上的正投影的外轮廓落入所述遮光层在所述衬底上的正投影以内；
    所述盖板在所述衬底上的正投影的外轮廓的四个顶角分别位于四个所述圆角处。
  18. 根据权利要求17所述的显示面板，其中，所述遮光层位于所述第一周边子区的部分未与所述盖板交叠的区域的面积小于所述遮光层位于所述第二周边子区的部分未与所述盖板交叠的区域的面积。
  19. 根据权利要求17所述的显示面板，其中，在平行于所述衬底所在的平面上，所述盖板与所述遮光层交叠的区域沿所述显示区指向所述周边区的方向上的尺寸大于所述电路测试单元沿所述第一方向上的尺寸。
  20. 根据权利要求11所述的显示面板，其中，所述电路测试单元在所述衬底上的正投影图形的面积小于或等于所述绑定端子在所述衬底上的正投影图形的面积。
  21. 根据权利要求20所述的显示面板，其中，所述电路测试单元的数量大于所述绑定端子的数量。
  22. 根据权利要求11-21中任一项所述的显示面板，其中，所述显示面板还包括检测单元，所述检测单元包括多个辅助子像素，所述辅助子像素位于所述周边区靠近所述第一侧边的区域，和/或，所述辅助子像素位于所述周边区靠近所述第二侧边的区域；所述辅助子像素的结构与所述显示区中的子像素的结构相同；所述遮光层覆盖所述检测单元。
  23. 根据权利要求22所述的显示面板，其中，所述显示面板还包括四个标记图案，所述标记图案位于所述遮光层远离所述衬底的一侧，所述盖板的所述顶角在所述衬底上的正投影与所述标记图案在所述衬底上的正投影至少部分交叠。
  24. 一种显示装置，其中，包括如权利要求1-23中任一项所述的显示面板，
    所述显示装置还包括柔性电路板和驱动芯片；
    或者，所述显示面板包括显示控制单元，所述显示装置还包括柔性 电路板。
  25. 一种可穿戴设备，其中，包括两个如权利要求24所述的显示装置，还包括两个环形第一支架，所述显示装置固定在所述第一支架上，所述第一支架覆盖所述显示面板的周边区中未设置遮光层的区域；其中，一个所述显示装置中的各电路测试单元与另一个所述显示装置中的各电路测试单元呈镜面对称设置。
  26. 根据权利要求25所述的可穿戴设备，其中，所述第一支架在所述显示面板的衬底上的正投影与所述遮光层在所述衬底上的正投影交叠。
  27. 根据权利要求26所述的可穿戴设备，其中，所述第一支架在所述衬底上的正投影的内轮廓与所述盖板在所述衬底上的正投影的外轮廓至少部分相接。
  28. 根据权利要求27所述的可穿戴设备，其中，还包括第二支架，所述第二支架被配置为能够穿戴，所述第二支架包括主体部分和两个镜腿，所述第二支架的主体部分上分别固定有驱动板和两个所述第一支架，所述驱动板分别与两个所述显示装置的柔性电路板电连接；
    两个所述显示面板呈镜面对称设置，且两个所述显示面板的显示区的几何中心与所述第二支架的主体部分的几何中心位于同一直线内，两个所述柔性电路板以所述第二支架的几何中心为对称点呈中心对称设置。
PCT/CN2022/108292 2022-07-27 2022-07-27 显示面板、显示装置及可穿戴设备 WO2024020869A1 (zh)

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CN111367125A (zh) * 2020-02-28 2020-07-03 上海中航光电子有限公司 阵列基板及显示面板
CN112466238A (zh) * 2020-12-03 2021-03-09 友达光电（昆山）有限公司 显示装置

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US20190165052A1 (en) * 2017-11-30 2019-05-30 Lg Display Co., Ltd. Display device and eyeglasses-like augmented reality device using the same
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CN112466238A (zh) * 2020-12-03 2021-03-09 友达光电（昆山）有限公司 显示装置

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