Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/87—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of PN-junction gate FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/83—FETs having PN junction gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/213—Channel regions of field-effect devices
  • H10D62/221—Channel regions of field-effect devices of FETs
  • H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/343—Gate regions of field-effect devices having PN junction gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/60—Impurity distributions or concentrations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology

Definitions

• the present invention relates to a SiC junction field effect transistor (hereinafter referred to as "SiCJFET”) formed using a carbon silicon (SiC) substrate, and an SiC junction field effect transistor (hereinafter referred to as "SiCJFET”) that is provided with an n-channel JFET and a p-channel JFET that are constructed using the SiCJFET.
• SiCJFET SiC junction field effect transistor
• SiCJFET SiC junction field effect transistor
• SiC has a bandgap approximately three times higher than that of Si, it is possible to fabricate integrated circuits that operate in high-temperature environments of 500° C. or higher.
• Non-Patent Document 1 discloses an integrated circuit configured with complementary MOSFETs. Further, Patent Document 1 discloses a complementary JFET in which an n-channel JFET and a p-channel JFET are insulated and separated by a semi-insulating SiC layer.
• Non-Patent Document 1 has a high density of defects and charges at the interface between the SiC substrate and the gate oxide film, so the threshold voltage fluctuates greatly depending on the temperature, resulting in stable operation. The problem is that it is not possible. Another problem is that the gate oxide film deteriorates at high temperatures.
• the complementary JFET disclosed in Patent Document 1 has a structure in which an n-channel JFET and a p-channel JFET are insulated and separated by an intrinsic SiC layer formed by a hot wall CVD method, and a fine trench is formed. , since it is necessary to repeat buried growth and surface flattening polishing, there is a problem that the fabrication process becomes very complicated.
• the present invention has been made in view of the above problems, and its main purpose is to provide a SiC junction field effect transistor that can operate stably at high temperatures and is easy to manufacture as a complementary JFET. be.
• the SiC junction field effect transistor according to the present invention includes a SiC substrate, a channel region of a first conductivity type formed on the main surface of the SiC substrate, and a channel region formed below the channel region on the main surface side of the SiC substrate. a buried gate region of a second conductivity type, and a source region and a drain region of a first conductivity type formed on the main surface of the SiC substrate with a channel region sandwiched therebetween.
• the SiC complementary junction field effect transistor according to the present invention is a SiC complementary junction field effect transistor in which an n-channel junction field effect transistor and a p-channel junction field effect transistor are formed on a SiC substrate.
• the n-channel junction field effect transistor and the p-channel junction field effect transistor are each composed of the above-mentioned normally-off type SiC junction field effect transistor, and the n-channel junction field effect transistor and the p-channel junction field effect transistor
• the effect transistors are formed in a SiC substrate so as to be spaced apart from each other and electrically insulated.
• Another SiC junction field effect transistor includes a SiC substrate, a buried channel region of a first conductivity type formed downwardly from the main surface of the SiC substrate, and a buried channel region formed below the buried channel region. a buried gate region of a second conductivity type, and a source region and a drain region of a first conductivity type formed on the main surface of the SiC substrate with the buried channel region sandwiched therebetween.
• FIG. 1A is a plan view schematically showing the configuration of a SiCJFET in a first embodiment of the present invention.
• FIG. 1B is a cross-sectional view taken along line IB-IB in FIG. 1A.
• FIG. 1C is a cross-sectional view taken along the line IC-IC in FIG. 1A.
• FIG. 2A is a graph obtained by simulation of the impurity density profile in the depth direction from the surface of the channel region when the channel region and buried gate region are respectively formed by ion implantation in the n-channel JFET according to the present embodiment. It is.
• FIG. 1A is a plan view schematically showing the configuration of a SiCJFET in a first embodiment of the present invention.
• FIG. 1B is a cross-sectional view taken along line IB-IB in FIG. 1A.
• FIG. 1C is a cross-sectional view taken along the line IC-IC in FIG. 1A.
• FIG. 2A is a
• FIG. 2B is a graph showing the results of measuring the impurity density profile when the channel region and buried gate region are formed using SIMS under the ion implantation conditions determined in FIG. 2A.
• FIG. 3A is a diagram showing the results of measuring drain current-drain voltage characteristics of an n-channel type SiCJFET.
• FIG. 3B is a diagram showing the results of measuring drain current-drain voltage characteristics of a p-channel type SiC JFET.
• FIG. 4 is a circuit diagram in which an inverter circuit is constructed using SiC complementary JFETs constructed using SiC JFETs.
• FIG. 5 is a cross-sectional view schematically showing the structure of a SiC complementary JFET that constitutes an inverter circuit.
• FIG. 6A is a cross-sectional view schematically showing a modification of the SiC complementary JFET that constitutes the inverter circuit.
• FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A.
• FIG. 7A is a plan view schematically showing the configuration of a SiCJFET in the second embodiment of the present invention.
• FIG. 7B is a cross-sectional view taken along line VIIB-VIIB in FIG. 7A.
• FIG. 7C is a cross-sectional view taken along line VIIC-VIIC in FIG. 7A.
• FIG. 8 is a cross-sectional view schematically showing the structure of a SiC complementary JFET that constitutes an inverter circuit.
• FIG. 8 is a cross-sectional view schematically showing the structure of a SiC complementary JFET that constitutes an inverter circuit.
• FIG. 9A is a cross-sectional view schematically showing another configuration of the SiC complementary JFET that constitutes the inverter circuit.
• FIG. 9B is a cross-sectional view taken along line IXB-IXB in FIG. 9A.
• FIG. 10A is a plan view schematically showing the configuration of a SiCJFET in a modification of the second embodiment.
• FIG. 10B is a cross-sectional view taken along the line XB-XB in FIG. 10A.
• FIG. 10C is a cross-sectional view taken along line XC-XC in FIG. 10A.
• FIG. 11 is a cross-sectional view schematically showing the configuration of a SiCJFET in another modification.
• FIG. 11 is a cross-sectional view schematically showing the configuration of a SiCJFET in another modification.
• FIG. 12 is a cross-sectional view showing the structure of the SiCJFET disclosed in the specification of the previous application by the applicant of the present application.
• FIG. 13A shows the profile of impurity density in the depth direction from the surface of the channel region when the channel region and buried gate region are each formed by ion implantation in the n-channel JFET shown in FIG. 12, obtained by simulation. It is a graph.
• FIG. 13B is a graph showing the results of measuring the impurity density profile when the channel region and buried gate region are formed using SIMS under the ion implantation conditions determined in FIG. 13A.
• FIG. 12 is a cross-sectional view showing an example of the structure of the SiCJFET disclosed in that specification. Although an n-channel JFET is shown here, a p-channel JFET also has a similar structure.
• the SiC JFET disclosed in the above specification includes an n-type buried channel region 111 formed on the main surface side of a SiC substrate 110, and a p + type buried channel region 111 formed on this buried channel region 111. It is composed of a type gate region 114 and an n + type source region 112 and drain region 113 formed with the gate region 114 in between.
• the threshold voltage V th of the SiCJFET having such a configuration can be expressed by the following equation (1) using a depletion layer analysis model of a semiconductor pn junction. Note that the threshold voltage V th of a p-channel type SiC JFET can also be expressed by a similar formula.
• k is the Boltzmann constant
• n is the electron density in the buried channel region 111
• p is the hole density in the gate region 114
• n i is the intrinsic carrier density
• q is the electron charge
• ⁇ s is the dielectric constant of SiC
• N is the impurity density of the buried channel region 111
• a is the thickness of the buried channel region 111 directly under the gate region 114.
• the threshold voltage V th of the SiCJFET can be controlled by adjusting the impurity density N and thickness a of the buried channel region 111 directly under the gate region 114. Furthermore, by setting the impurity density N and thickness a of the buried channel region 111 to predetermined values so that the threshold voltage V th is positive, a normally-off SiC JFET can be realized.
• a SiC complementary JFET including an n-channel SiC JFET and a p-channel SiC JFET that operate normally off has a buried channel region 111, a gate region 114, a source region 112, and a drain region 113 of different conductivity types on the same SiC substrate 110, respectively. It can be easily manufactured by forming by ion implantation.
• FIG. 13A shows the impurity density profile in the depth direction from the surface of the gate region 114 when an n-type buried channel region 111 and a p + type gate region 114 are formed by ion implantation in an n-channel SiC JFET.
• FIG. 13A is a graph obtained by simulation.
• the graph shown by arrow A shows the profile of buried channel region 111
• the graph shown by arrow B shows the profile of gate region 114.
• the region indicated by arrow P becomes the buried channel region 111.
• the simulation was performed using simulation software SRIM (Stopping and Range In Matter) that calculates the distribution of implanted ions using the Monte Carlo method.
• simulation software SRIM Simulation software SRIM (Stopping and Range In Matter) that calculates the distribution of implanted ions using the Monte Carlo method.
• the conditions for ion implantation are such that the impurity density N and thickness a of the buried channel region 111 are set to predetermined values so that the target threshold voltage V th is obtained. It was established as follows. Here, P (phosphorus) was used as the impurity for the n-type buried channel region 111, and Al (aluminum) was used for the impurity for the p + type gate region 114.
• FIG. 13B shows the results of measuring the impurity density profile when the buried channel region 111 and gate region 114 are formed using SIMS (Secondary Ion Mass Spectrometry) under the ion implantation conditions determined in FIG. 13A.
• SIMS Secondary Ion Mass Spectrometry
• both the buried channel region 111 and the gate region 114 are formed with their bases expanding to a position deeper than the peak. Therefore, impurities from the base of the high-density gate region 114 enter the low-density buried channel region 111, so that the impurity density N of the buried channel region 111 is greatly reduced from the design value.
• the thickness a of the channel region 111 is significantly increased from the design value.
• the actual impurity density N and thickness a of the buried channel region 111 deviate greatly from the designed values. It becomes difficult to control.
• the inventors of the present application considered a structure in which even if the buried channel region 111 and the gate region 114 are formed by ion implantation, the channeling phenomenon does not affect the impurity density profile in the buried channel region 111. This led to the idea of an invention.
• FIG. 1A to 1C are diagrams schematically showing the configuration of a SiCJFET in the first embodiment of the present invention, where FIG. 1A is a plan view and FIG. 1B is a diagram taken along the IB-IB line in FIG. 1A.
• FIG. 1C is a cross-sectional view taken along the line IC-IC in FIG. 1A. Here, an n-channel type SiCJFET is shown.
• the SiC JFET in this embodiment includes a semi-insulating SiC substrate 10 and an n-type (first conductivity type) channel region 11 formed on the main surface of the semi-insulating SiC substrate 10. , a P + type (second conductivity type) buried gate region 14 formed on the main surface side of the semi-insulating SiC substrate 10 and below the channel region 11; It has an n + type (first conductivity type) source region 12 and drain region 13 formed on both sides of a channel region 11 .
• the "principal surface” refers to the widest surface of the surfaces forming the semi-insulating SiC substrate 10.
• the impurity density of the channel region 11 is set lower than the impurity density of the buried gate region 14. Further, the channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are all composed of ion-implanted layers.
• a p + type (second conductivity type) gate contact is provided on the main surface of the semi-insulating SiC substrate 10 at a position spaced apart from the source region 12 and drain region 13.
• a region 15 is formed, and the buried gate region 14 extends directly below the gate contact region 15 and is connected to the gate contact region 15 .
• a semi-insulating SiC substrate 10 is used as the SiC substrate 10, but a SiC substrate 10 with a p-type epitaxial layer formed on the surface may be used. Good too. In this case, channel region 11, buried gate region 14, source region 12, and drain region 13 are formed in a p-type epitaxial layer.
• the channel region 11 is p-type
• the buried gate region 14 is n + type
• the source region 12 and drain region 13 are p + type
• the gate contact region 15 is n + type. , can be formed by changing each.
• the threshold voltage V th of the SiCJFET in this embodiment is determined by the impurity density of the channel region 11 being N D , the impurity density of the buried gate region 14 being N A , and the thickness of the channel region 11 When is set to a, it can be expressed by the following formula (2).
• k is the Boltzmann constant
• n is the electron density in the channel region 11
• p is the hole density in the buried gate region 14
• n is the intrinsic carrier density
• q is the electron charge
• ⁇ is the dielectric constant of SiC.
• the above formula (2) is a formula that takes into consideration the case where the difference between the impurity density N D of the channel region 11 and the impurity density N A of the buried gate region 14 is not very large .
• the threshold voltage V th can be determined using the above equation (1).
• the threshold voltage V th of the SiC JFET is controlled by adjusting the impurity density N D and thickness a of the channel region 11 and the impurity density N A of the buried gate region 14. can do. Furthermore, by setting the impurity density N D and thickness a of the channel region 11 and the impurity density N A of the buried gate region 14 to predetermined values so that the threshold voltage V th becomes positive, It is possible to realize a SiCJFET that operates normally off.
• FIG. 2A shows the impurity density profile in the depth direction from the surface of the channel region 11 when the n-type channel region 11 and the p + type buried gate region 14 are respectively formed by ion implantation in an n-channel JFET.
• FIG. 2A is a graph obtained by simulation.
• the graph shown by arrow A shows the profile of channel region 11
• the graph shown by arrow B shows the profile of buried gate region 14.
• the region indicated by the arrow P becomes the channel region 11.
• the simulation was performed using simulation software SRIM (Stopping and Range In Matter), which calculates the distribution of implanted ions using the Monte Carlo method.
• the ion implantation conditions are such that the impurity density N D and thickness a of the channel region 11 and the buried gate region 14 are set so that the target threshold voltage V th can be obtained.
• the impurity density N A was determined to be a predetermined value.
• P phosphorus
• Al aluminum
• FIG. 2B shows the results of measuring the impurity density profile when forming the channel region 11 and buried gate region 14 using SIMS (Secondary Ion Mass Spectrometry) under the ion implantation conditions determined in FIG. 2A.
• SIMS Secondary Ion Mass Spectrometry
• both the channel region 11 and the buried gate region 14 are formed with their bases expanding to a position deeper than the peak, but the channel region 11 and the buried gate region 14 are formed at a position shallower than the peak.
• the impurity density profile of is almost unchanged from the profile shown in FIG. 2A. Therefore, the actual impurity density N D and thickness a of the channel region 11 and the impurity density N A of the buried gate region 14 substantially match the design values shown in FIG. 2A. Therefore, when designing the structure of the SiCJFET, the threshold voltage V th of the SiCJFET can be controlled according to the designed value.
• FIGS. 2A and 2B show the case where the impurity density N D of the channel region 11 is set to be lower than the impurity density N A of the buried gate region 14, the magnitude relationship between the impurity densities of the two Regardless, the fact remains that the actual impurity density N D and thickness a of the channel region 11 and the impurity density N A of the buried gate region 14 substantially match the designed values.
• the buried gate region 14 below the channel region 11, even if the channel region 11 and the buried gate region 14 are formed of ion implantation layers, they are not affected by the channeling phenomenon.
• the threshold voltage V th of the SiCJFET can be controlled according to the designed value, it is possible to realize a SiCJFET that can operate stably at high temperatures.
• the channel region 11, buried gate region 14, source region 12, and drain region 13 are all composed of ion-implanted layers, a complementary JFET can be easily manufactured on the same SiC substrate 10. can.
• FIG. 3A is a diagram showing the results of fabricating an n-channel type SiC JFET having the configuration shown in FIGS. 1A to 1C and measuring the drain current-drain voltage characteristics.
• the measurement was performed at a temperature of 300K.
• each ion implantation layer was formed under the following conditions, and annealing after ion implantation was performed at 1650°C. Note that the ion implantation was performed by changing the acceleration energy in multiple stages (multistage implantation). Further, the length of the channel region 11 was set to 50 ⁇ m, and the width of the channel region 11 was set to 100 ⁇ m.
• the impurity density of the channel region 11 is 5 ⁇ 10 17 cm ⁇ 3
• the impurity density of the buried gate region 14 is 1 ⁇ 10 18 cm ⁇ 3
• the impurity density of the channel region 11 is 5 ⁇ 10 17 cm ⁇ 3 .
• the thickness a was 281 nm.
• the manufactured n-channel type SiCJFET exhibited good drain current-drain voltage characteristics. Further, the threshold voltage V th was only 0.1 V different from the design value (-50.6 V).
• FIG. 3B is a diagram showing the results of measuring the drain current-drain voltage characteristics of a p-channel type SiC JFET having the configuration shown in FIGS. 1A to 1C.
• the measurement was performed at a temperature of 300K.
• each ion implantation layer was formed by multistage implantation under the following conditions, and annealing after ion implantation was performed at 1650°C. Further, the length of the channel region 11 was set to 50 ⁇ m, and the width of the channel region 11 was set to 100 ⁇ m.
• the impurity density of the channel region 11 is 5 ⁇ 10 17 cm ⁇ 3
• the impurity density of the buried gate region 14 is 1 ⁇ 10 18 cm ⁇ 3
• the impurity density of the channel region 11 is 5 ⁇ 10 17 cm ⁇ 3 .
• the thickness a was 281 nm.
• FIG. 4 is a circuit diagram showing an example in which an inverter circuit is configured with SiC complementary JFETs configured using SiC JFETs in this embodiment.
• T r1 is a normally-off type n-channel JFET
• T r2 is a normally-off type p-channel JFET.
• the gate electrodes G of the n-channel JFET and the p-channel JFET are connected to the input terminal V in of the inverter circuit.
• the drain electrodes D of the n-channel JFET and the p-channel JFET are connected to the output terminal V out of the inverter circuit.
• the source electrode S of the n-channel JFET is connected to the ground
• the source electrode S of the p-channel JFET is connected to the power supply (V DD ).
• FIG. 5 is a cross-sectional view schematically showing the structure of the SiC complementary JFET that constitutes this inverter circuit.
• an n-type channel region 11 is formed in the n-channel JFET ( Tr1 ) formation region of the semi-insulating SiC substrate 10, and a p-type channel region 11 is formed in the p-channel JFET ( Tr2 ) formation region. Regions 11 are respectively formed. Further, a p + type buried gate region 14 is formed directly under the n type channel region 11, and an n + type source region 12 and a drain region 13 are formed with the channel region 11 in between. Further, an n + type buried gate region 14 is formed directly under the p type channel region 11, and a p + type source region 12 and a p + type drain region 13 are formed with the channel region 11 in between.
• the channel region 11, buried gate region 14, source region 12, and drain region 13 are all formed by ion implantation, a complementary JFET can be easily manufactured on the same SiC substrate 10. be able to. Furthermore, since the n-channel JFET and the p-channel JFET are formed apart from each other in the semi-insulating SiC substrate 10, the n-channel JFET and the p-channel JFET can be electrically separated easily. . In addition, by adjusting the acceleration energy and dose of ion implantation, the impurity density N and thickness a of the channel region 11 can be set, making it easy to make the JFET normally-off.
• the semi-insulating SiC substrate 10 may have a high resistance as long as it can electrically isolate the n-channel JFET and the p-channel JFET from each other.
• a SiC substrate 10 having a resistivity ⁇ of 10 9 ⁇ cm or more can be used.
• FIGS. 6A and 6B are cross-sectional views schematically showing a modification of the SiC complementary JFET constructed using the SiC JFET in this embodiment.
• FIG. 6A is a plan view
• FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A.
• an n-channel JFET and a p-channel JFET having the structures shown in FIGS. 1A to 1C are formed in a p - type low concentration epitaxial layer 20 formed on a SiC substrate 10. ing.
• n-type well regions 21 spaced apart from each other are formed in a p - type low concentration epitaxial layer 20.
• a p-type well region 22 is further formed in one well region 21, and an n-channel JFET is formed within this well region 22.
• a p-channel JFET is formed in the other well region 21.
• the n-channel JFET and the p-channel JFET are electrically isolated from each other by applying a reverse bias to the pn junction between the p - type low concentration epitaxial layer 20 and the n type well region 21. be able to.
• a SiC complementary JFET with a similar configuration can be formed by changing the conductivity types of the well regions 21 and 22. .
• FIG. 7A to 7C are diagrams schematically showing the configuration of a SiC JFET according to the second embodiment of the present invention, where FIG. 7A is a plan view and FIG. 7B is a cross section taken along the line VIIB-VIIB in FIG. 7A. In the figure, FIG. 7C is a cross-sectional view taken along line VIIC-VIIC in FIG. 7A. Here, an n-channel type SiCJFET is shown.
• an n-type (first conductivity type) channel region 11 was formed on the main surface of a semi-insulating SiC substrate 10, as shown in FIGS. 1A to 1C.
• an n-type (first conductivity type) buried channel region 11 is formed at a position downward and away from the main surface of a semi-insulating SiC substrate 10. There is.
• a p + type (second conductivity type) buried gate region 14 is formed below the buried channel region 11, and the semi-insulating SiC substrate 10, an n + type (first conductivity type) source region 12 and drain region 13 are formed with a buried channel region 11 in between.
• a p + type (second conductivity type) gate contact region 15 is formed on the main surface of the semi-insulating SiC substrate 10 at a position spaced apart from the source region 12 and drain region 13, and is buried. Gate region 14 extends directly below gate contact region 15 and is connected to gate contact region 15 .
• the channel region 11 is formed on the main surface of the SiC substrate 10
• the inside of the channel region 11 will be The depletion layer may expand unintentionally, and the threshold voltage V th may not be as designed.
• variations in the threshold voltage V th due to the influence of charges existing on the surface of the SiC substrate 10 are suppressed. can do.
• the depth of the buried channel region 11 from the main surface of the SiC substrate 10 may be determined as appropriate depending on the amount of charge existing on the surface of the SiC substrate 10.
• buried channel region 11 may be formed 3 to 500 nm below the main surface of SiC substrate 10, more preferably 20 to 300 nm below. If buried channel region 11 is formed at a position shallower than 3 nm from the main surface of SiC substrate 10, it becomes difficult to avoid the influence of charges existing on the surface of SiC substrate 10. Furthermore, if the buried channel region 11 is formed at a position deeper than 500 nm from the main surface of the SiC substrate 10, the buried gate region 14 needs to be formed at an even deeper position, which increases the energy of ion implantation. This results in increased costs.
• the buried channel region 11 and the buried gate region 14 are formed with an ion implantation layer. Even if configured, the threshold voltage V th of the SiCJFET can be controlled according to the designed value without being affected by the channeling phenomenon, making it possible to realize a SiCJFET that can operate stably at high temperatures. .
• the impurity density of the buried channel region 11 is preferably set to be lower than the impurity density of the buried gate region 14.
• the buried channel region 11, buried gate region 14, source region 12, and drain region 13 are all composed of ion-implanted layers. Thereby, complementary JFETs can be easily manufactured on the same SiC substrate 10.
• the threshold voltage V th of the SiCJFET can be controlled by adjusting the impurity density N D and thickness a of the buried channel region 11 and the impurity density NA of the buried gate region 14 . Further, the impurity density N D and thickness a of the buried channel region 11 and the impurity density N A of the buried gate region 14 are set to predetermined values so that the threshold voltage V th becomes positive. Accordingly, it is possible to realize a SiCJFET that operates normally off.
• FIG. 8 is a cross-sectional view schematically showing the structure of a SiC complementary JFET that constitutes the inverter circuit shown in FIG. 4 using the SiC JFET in this embodiment.
• an n-type buried channel region 11 is formed in the n-channel JFET ( Tr1 ) formation region of the semi-insulating SiC substrate 10, and a p-type buried channel region 11 is formed in the p-channel JFET ( Tr2 ) formation region.
• buried channel regions 11 are formed respectively.
• a p + type buried gate region 14 is formed directly under the n type buried channel region 11, and an n + type source region 12 and drain region 13 are formed with the buried channel region 11 in between. has been done.
• an n + type buried gate region 14 is formed directly under the p type buried channel region 11, and a p + type source region 12 and a drain region 13 are formed with the buried channel region 11 in between. has been done.
• buried channel region 11, buried gate region 14, source region 12, and drain region 13 are all formed by ion implantation, complementary JFETs can be easily formed on the same SiC substrate 10. It can be made. Furthermore, since the n-channel JFET and the p-channel JFET are formed apart from each other in the semi-insulating SiC substrate 10, the n-channel JFET and the p-channel JFET can be electrically separated easily. . In addition, by adjusting the acceleration energy and dose of ion implantation, it is possible to set the impurity density N and the thickness a of the buried channel region 11, so it is possible to easily make the JFET normally-off. .
• the semi-insulating SiC substrate 10 may have a high resistance as long as it can electrically isolate the n-channel JFET and the p-channel JFET from each other.
• a SiC substrate 10 having a resistivity ⁇ of 10 9 ⁇ cm or more can be used.
• FIG. 9A and 9B are cross-sectional views schematically showing other configurations of the SiC complementary JFET in this embodiment, in which an n-channel JFET and a p-channel JFET are formed on a p - type JFET formed on a SiC substrate 10.
• the structure is formed in the low concentration epitaxial layer 20 of.
• FIG. 9A is a plan view
• FIG. 9B is a sectional view taken along line IXB-IXB in FIG. 9A.
• two n-type well regions 21 spaced apart from each other are formed in a p - type low concentration epitaxial layer 20.
• a p-type well region 22 is further formed in one well region 21, and an n-channel JFET is formed within this well region 22.
• a p-channel JFET is formed in the other well region 21.
• the n-channel JFET and the p-channel JFET are electrically isolated from each other by applying a reverse bias to the pn junction between the p - type low concentration epitaxial layer 20 and the n type well region 21. be able to.
• a SiC complementary JFET with a similar configuration can be formed by changing the conductivity types of the well regions 21 and 22. .
• FIGS. 7A to 7C are diagrams schematically showing modified examples of the SiC JFET shown in FIGS. 7A to 7C, where FIG. 10A is a plan view and FIG. 10B is a cross section taken along the XB-XB line in FIG. 10A. In the figure, FIG. 10C is a cross-sectional view taken along the line XC-XC in FIG. 10A. Here, an n-channel type SiCJFET is shown.
• the SiCJFET in this modification is the same as the SiCJFET shown in FIGS. 7A to 7C, but is located on the main surface of the SiC substrate 10 at a position above the buried channel region 11 and facing the p + type buried gate region 14.
• a p-type (second conductivity type) surface gate region 16 is formed therein. That is, the SiCJFET in this modification has a double gate structure in which a buried channel region 11 is sandwiched between a pair of buried gate regions 14 and a surface gate region 16.
• the depletion layer in the buried channel region 11 is controlled by the pair of buried gate regions 14 and surface gate regions 16 formed on both sides of the buried channel region 11, so that the depletion layer in the buried channel region 11 is controlled by the pair of buried gate regions 14 and surface gate regions 16 formed on both sides of the buried channel region 11.
• the drain current can be increased approximately twice when the threshold voltage V th is the same. This makes it possible to realize a SiC JFET with high current drive capability.
• the surface gate region 16 be connected to the gate contact region 15 by wiring or the like.
• the front gate region 16 may be connected to the gate contact region 15 by extending the front gate region 16 to the gate contact region 15 on the main surface.
• the surface gate region 16 is not connected to the gate contact region 15 by wiring or the like, and the buried gate region 14 and the surface gate region 16 are each provided with separate gate voltages. may be applied to control the depletion layer in the buried channel region 11.
• the impurity density of the surface gate region 16 is set to be lower than the impurity density of the buried gate region 14.
• the impurity density of the buried gate region 14 is set to be lower than the impurity density of the buried gate region 14.
• SiC JFET in this modification, it is possible to form a SiC complementary JFET having a structure as shown in FIG. 8, or FIG. 9A or FIG. 9B.
• FIGS. 6A, 6B, 9A, and 9B can also be applied to a single SiC JFET.
• the SiCJFET in the above embodiment can of course be applied not only to a normally-off type but also to a normally-on type.
• the impurity density N D of the channel region 11 or the buried channel region 11 is set to be lower than the impurity density N A of the buried gate region 14. They may have similar densities.
• SiC substrate 11 Channel region (buried channel region) 12 Source region 13 Drain region 14 Buried gate region 15 Gate contact region 16 Surface gate region 20 P-type epitaxial layer 21 N - type well region 22 P-type well region

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• 2023
  • 2023-07-13 WO PCT/JP2023/025890 patent/WO2024014510A1/ja not_active Ceased
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• 2024
  • 2024-12-10 US US18/976,181 patent/US20250107188A1/en active Pending

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